Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	66	0	66	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	64	0	64	100.00	100	1	1	64

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_cmd_filter_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

14691

1

T1

1

T3

7

T4

36

auto[1]

43166

1

T1

1

T3

7

T4

24

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	64	0	64	100.00

Automatically Generated Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:3]	1265	1			T4	3		T6	2		T7	6
auto[4:7]	23318	1			T4	5		T6	248		T7	32
auto[8:11]	1358	1			T4	2		T6	5		T7	10
auto[12:15]	299	1			T6	3		T7	2		T11	1
auto[16:19]	314	1			T7	5		T11	3		T14	1
auto[20:23]	1703	1			T3	2		T4	3		T6	8
auto[24:27]	312	1			T6	1		T7	1		T11	3
auto[28:31]	326	1			T4	1		T6	2		T7	1
auto[32:35]	329	1			T6	3		T7	1		T8	1
auto[36:39]	355	1			T4	2		T8	1		T14	2
auto[40:43]	317	1			T6	1		T7	1		T8	2
auto[44:47]	359	1			T6	4		T7	1		T9	4
auto[48:51]	316	1			T6	2		T7	1		T8	1
auto[52:55]	1778	1			T3	8		T4	1		T6	8
auto[56:59]	1298	1			T4	2		T6	7		T7	12
auto[60:63]	311	1			T6	2		T7	1		T8	3
auto[64:67]	358	1			T4	1		T6	1		T9	2
auto[68:71]	336	1			T4	4		T6	1		T8	1
auto[72:75]	330	1			T6	4		T7	1		T9	2
auto[76:79]	318	1			T4	1		T6	4		T7	1
auto[80:83]	341	1			T4	1		T8	1		T9	1
auto[84:87]	300	1			T6	2		T7	2		T14	2
auto[88:91]	1747	1			T3	4		T4	5		T6	11
auto[92:95]	293	1			T4	1		T9	2		T11	2
auto[96:99]	321	1			T4	1		T6	1		T7	2
auto[100:103]	330	1			T6	3		T7	1		T9	1
auto[104:107]	1295	1			T4	4		T6	2		T7	5
auto[108:111]	363	1			T4	1		T6	1		T7	2
auto[112:115]	323	1			T6	1		T7	4		T8	2
auto[116:119]	309	1			T7	1		T8	1		T9	3
auto[120:123]	328	1			T9	1		T40	1		T43	3
auto[124:127]	276	1			T6	1		T9	1		T11	2
auto[128:131]	350	1			T6	1		T7	1		T8	1
auto[132:135]	267	1			T4	1		T7	2		T11	3
auto[136:139]	335	1			T8	4		T11	2		T14	1
auto[140:143]	338	1			T6	1		T7	2		T9	1
auto[144:147]	329	1			T6	1		T11	3		T36	1
auto[148:151]	316	1			T4	1		T6	3		T7	1
auto[152:155]	326	1			T6	3		T8	2		T9	2
auto[156:159]	1735	1			T1	2		T4	2		T6	12
auto[160:163]	308	1			T6	4		T7	2		T9	3
auto[164:167]	351	1			T4	1		T6	1		T14	2
auto[168:171]	275	1			T7	1		T8	1		T11	1
auto[172:175]	253	1			T8	2		T11	1		T36	3
auto[176:179]	323	1			T6	3		T8	5		T9	1
auto[180:183]	1778	1			T4	2		T6	8		T7	6
auto[184:187]	1298	1			T4	2		T6	5		T7	9
auto[188:191]	292	1			T7	5		T8	1		T9	1
auto[192:195]	317	1			T6	3		T8	2		T9	3
auto[196:199]	357	1			T6	1		T7	1		T9	3
auto[200:203]	336	1			T6	6		T7	1		T8	2
auto[204:207]	325	1			T7	3		T8	1		T9	1
auto[208:211]	336	1			T4	1		T9	1		T14	1
auto[212:215]	297	1			T4	2		T9	3		T11	3
auto[216:219]	311	1			T4	1		T6	1		T7	2
auto[220:223]	291	1			T4	2		T7	5		T9	2
auto[224:227]	311	1			T6	1		T11	2		T14	1
auto[228:231]	291	1			T4	2		T6	1		T7	1
auto[232:235]	2717	1			T4	4		T6	9		T7	11
auto[236:239]	340	1			T6	1		T7	2		T9	1
auto[240:243]	285	1			T4	1		T6	5		T8	1
auto[244:247]	324	1			T6	4		T7	1		T8	1
auto[248:251]	316	1			T6	3		T7	1		T9	1
auto[252:255]	303	1			T6	1		T9	3		T11	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:3]	auto[0]	472	1			T4	3		T7	2		T24	1
auto[0:3]	auto[1]	793	1			T6	2		T7	4		T8	1
auto[4:7]	auto[0]	5003	1			T4	4		T7	13		T8	10
auto[4:7]	auto[1]	18315	1			T4	1		T6	248		T7	19
auto[8:11]	auto[0]	440	1			T7	4		T8	8		T14	5
auto[8:11]	auto[1]	918	1			T4	2		T6	5		T7	6
auto[12:15]	auto[0]	73	1			T40	2		T159	1		T230	1
auto[12:15]	auto[1]	226	1			T6	3		T7	2		T11	1
auto[16:19]	auto[0]	84	1			T7	2		T14	1		T110	2
auto[16:19]	auto[1]	230	1			T7	3		T11	3		T36	2
auto[20:23]	auto[0]	441	1			T3	1		T4	3		T7	1
auto[20:23]	auto[1]	1262	1			T3	1		T6	8		T7	2
auto[24:27]	auto[0]	88	1			T36	1		T40	1		T41	1
auto[24:27]	auto[1]	224	1			T6	1		T7	1		T11	3
auto[28:31]	auto[0]	80	1			T4	1		T7	1		T8	1
auto[28:31]	auto[1]	246	1			T6	2		T9	2		T11	4
auto[32:35]	auto[0]	88	1			T36	1		T43	1		T242	2
auto[32:35]	auto[1]	241	1			T6	3		T7	1		T8	1
auto[36:39]	auto[0]	107	1			T4	2		T8	1		T44	3
auto[36:39]	auto[1]	248	1			T14	2		T40	2		T41	1
auto[40:43]	auto[0]	81	1			T7	1		T8	2		T43	3
auto[40:43]	auto[1]	236	1			T6	1		T9	2		T14	1
auto[44:47]	auto[0]	77	1			T14	1		T40	1		T44	2
auto[44:47]	auto[1]	282	1			T6	4		T7	1		T9	4
auto[48:51]	auto[0]	92	1			T7	1		T14	2		T43	1
auto[48:51]	auto[1]	224	1			T6	2		T8	1		T9	3
auto[52:55]	auto[0]	451	1			T3	4		T8	3		T14	2
auto[52:55]	auto[1]	1327	1			T3	4		T4	1		T6	8
auto[56:59]	auto[0]	470	1			T7	5		T8	1		T14	1
auto[56:59]	auto[1]	828	1			T4	2		T6	7		T7	7
auto[60:63]	auto[0]	75	1			T7	1		T14	1		T37	1
auto[60:63]	auto[1]	236	1			T6	2		T8	3		T9	2
auto[64:67]	auto[0]	76	1			T44	2		T182	2		T37	1
auto[64:67]	auto[1]	282	1			T4	1		T6	1		T9	2
auto[68:71]	auto[0]	92	1			T4	2		T14	5		T36	1
auto[68:71]	auto[1]	244	1			T4	2		T6	1		T8	1
auto[72:75]	auto[0]	77	1			T37	2		T190	2		T181	1
auto[72:75]	auto[1]	253	1			T6	4		T7	1		T9	2
auto[76:79]	auto[0]	96	1			T4	1		T7	1		T158	1
auto[76:79]	auto[1]	222	1			T6	4		T11	1		T14	3
auto[80:83]	auto[0]	85	1			T4	1		T14	1		T42	1
auto[80:83]	auto[1]	256	1			T8	1		T9	1		T11	1
auto[84:87]	auto[0]	62	1			T7	1		T14	2		T41	2
auto[84:87]	auto[1]	238	1			T6	2		T7	1		T36	1
auto[88:91]	auto[0]	478	1			T3	2		T4	2		T7	5
auto[88:91]	auto[1]	1269	1			T3	2		T4	3		T6	11
auto[92:95]	auto[0]	78	1			T36	2		T43	1		T44	1
auto[92:95]	auto[1]	215	1			T4	1		T9	2		T11	2
auto[96:99]	auto[0]	85	1			T4	1		T36	1		T44	3
auto[96:99]	auto[1]	236	1			T6	1		T7	2		T11	2
auto[100:103]	auto[0]	102	1			T14	1		T36	1		T41	3
auto[100:103]	auto[1]	228	1			T6	3		T7	1		T9	1
auto[104:107]	auto[0]	539	1			T4	2		T7	5		T8	4
auto[104:107]	auto[1]	756	1			T4	2		T6	2		T8	2
auto[108:111]	auto[0]	90	1			T4	1		T7	2		T8	2
auto[108:111]	auto[1]	273	1			T6	1		T9	2		T14	1
auto[112:115]	auto[0]	77	1			T7	1		T8	2		T43	1
auto[112:115]	auto[1]	246	1			T6	1		T7	3		T11	1
auto[116:119]	auto[0]	72	1			T158	1		T41	1		T43	1
auto[116:119]	auto[1]	237	1			T7	1		T8	1		T9	3
auto[120:123]	auto[0]	82	1			T43	3		T44	2		T15	3
auto[120:123]	auto[1]	246	1			T9	1		T40	1		T182	2
auto[124:127]	auto[0]	65	1			T41	2		T182	3		T15	1
auto[124:127]	auto[1]	211	1			T6	1		T9	1		T11	2
auto[128:131]	auto[0]	88	1			T8	1		T40	2		T44	3
auto[128:131]	auto[1]	262	1			T6	1		T7	1		T9	1
auto[132:135]	auto[0]	60	1			T4	1		T7	1		T41	2
auto[132:135]	auto[1]	207	1			T7	1		T11	3		T72	3
auto[136:139]	auto[0]	95	1			T8	4		T158	2		T43	2
auto[136:139]	auto[1]	240	1			T11	2		T14	1		T28	1
auto[140:143]	auto[0]	93	1			T7	2		T36	1		T43	2
auto[140:143]	auto[1]	245	1			T6	1		T9	1		T11	2
auto[144:147]	auto[0]	88	1			T36	1		T40	1		T44	3
auto[144:147]	auto[1]	241	1			T6	1		T11	3		T26	1
auto[148:151]	auto[0]	66	1			T14	1		T36	1		T110	1
auto[148:151]	auto[1]	250	1			T4	1		T6	3		T7	1
auto[152:155]	auto[0]	68	1			T8	2		T36	2		T40	1
auto[152:155]	auto[1]	258	1			T6	3		T9	2		T11	2
auto[156:159]	auto[0]	490	1			T1	1		T7	2		T8	1
auto[156:159]	auto[1]	1245	1			T1	1		T4	2		T6	12
auto[160:163]	auto[0]	58	1			T14	1		T182	1		T126	1
auto[160:163]	auto[1]	250	1			T6	4		T7	2		T9	3
auto[164:167]	auto[0]	93	1			T14	2		T37	2		T172	2
auto[164:167]	auto[1]	258	1			T4	1		T6	1		T28	1
auto[168:171]	auto[0]	73	1			T8	1		T14	2		T42	1
auto[168:171]	auto[1]	202	1			T7	1		T11	1		T14	1
auto[172:175]	auto[0]	66	1			T36	3		T158	2		T43	1
auto[172:175]	auto[1]	187	1			T8	2		T11	1		T28	2
auto[176:179]	auto[0]	76	1			T8	5		T158	1		T44	1
auto[176:179]	auto[1]	247	1			T6	3		T9	1		T11	2
auto[180:183]	auto[0]	480	1			T4	1		T7	2		T8	3
auto[180:183]	auto[1]	1298	1			T4	1		T6	8		T7	4
auto[184:187]	auto[0]	469	1			T4	2		T7	3		T8	1
auto[184:187]	auto[1]	829	1			T6	5		T7	6		T8	1
auto[188:191]	auto[0]	69	1			T36	2		T37	1		T186	2
auto[188:191]	auto[1]	223	1			T7	5		T8	1		T9	1
auto[192:195]	auto[0]	87	1			T8	2		T43	1		T44	1
auto[192:195]	auto[1]	230	1			T6	3		T9	3		T11	1
auto[196:199]	auto[0]	83	1			T43	3		T44	1		T15	1
auto[196:199]	auto[1]	274	1			T6	1		T7	1		T9	3
auto[200:203]	auto[0]	78	1			T8	1		T41	1		T43	1
auto[200:203]	auto[1]	258	1			T6	6		T7	1		T8	1
auto[204:207]	auto[0]	87	1			T7	3		T14	1		T44	1
auto[204:207]	auto[1]	238	1			T8	1		T9	1		T11	1
auto[208:211]	auto[0]	103	1			T4	1		T44	2		T15	1
auto[208:211]	auto[1]	233	1			T9	1		T14	1		T26	1
auto[212:215]	auto[0]	62	1			T44	1		T258	1		T172	1
auto[212:215]	auto[1]	235	1			T4	2		T9	3		T11	3
auto[216:219]	auto[0]	72	1			T8	3		T44	1		T182	1
auto[216:219]	auto[1]	239	1			T4	1		T6	1		T7	2
auto[220:223]	auto[0]	72	1			T4	2		T7	3		T44	1
auto[220:223]	auto[1]	219	1			T7	2		T9	2		T36	1
auto[224:227]	auto[0]	70	1			T40	1		T41	2		T230	1
auto[224:227]	auto[1]	241	1			T6	1		T11	2		T14	1
auto[228:231]	auto[0]	79	1			T4	2		T7	1		T158	1
auto[228:231]	auto[1]	212	1			T6	1		T9	2		T11	1
auto[232:235]	auto[0]	824	1			T4	4		T7	8		T8	3
auto[232:235]	auto[1]	1893	1			T6	9		T7	3		T8	2
auto[236:239]	auto[0]	73	1			T7	1		T14	1		T36	2
auto[236:239]	auto[1]	267	1			T6	1		T7	1		T9	1
auto[240:243]	auto[0]	74	1			T14	2		T43	1		T182	1
auto[240:243]	auto[1]	211	1			T4	1		T6	5		T8	1
auto[244:247]	auto[0]	52	1			T14	1		T198	1		T38	1
auto[244:247]	auto[1]	272	1			T6	4		T7	1		T8	1
auto[248:251]	auto[0]	94	1			T36	3		T41	1		T44	1
auto[248:251]	auto[1]	222	1			T6	3		T7	1		T9	1
auto[252:255]	auto[0]	71	1			T43	2		T44	2		T15	4
auto[252:255]	auto[1]	232	1			T6	1		T9	3		T11	2