Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	426	1			T7	3		T8	1		T14	2
auto[ReadAddrCrossIntoMailbox]	292	1			T4	1		T7	7		T8	2
auto[ReadAddrCrossOutOfMailbox]	327	1			T4	1		T7	4		T8	4
auto[ReadAddrCrossAllMailbox]	215	1			T7	5		T8	1		T14	1
auto[ReadAddrOutsideMailbox]	3625	1			T4	12		T7	19		T8	13

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2381

1

T4

5

T7

19

T8

15

auto[1]

2504

1

T4

9

T7

19

T8

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	803	1			T4	3		T7	6		T8	1
read_ops[0x0b]	846	1			T4	2		T7	6		T8	8
read_ops[0x3b]	776	1			T4	2		T7	11		T8	2
read_ops[0x6b]	820	1			T4	4		T7	5		T8	4
read_ops[0xbb]	827	1			T4	2		T7	6		T8	2
read_ops[0xeb]	813	1			T4	1		T7	4		T8	4

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	21	1			T7	1		T41	1		T44	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	30	1			T40	1		T44	1		T38	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	23	1			T36	1		T15	1		T181	2
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	29	1			T7	2		T43	2		T44	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	20	1			T41	1		T181	1		T259	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	39	1			T40	1		T44	1		T37	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T259	1		T17	1		T229	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T181	1		T259	1		T17	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	315	1			T4	1		T7	1		T24	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	294	1			T4	2		T7	2		T8	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	36	1			T14	1		T88	3		T37	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	46	1			T36	1		T88	3		T158	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	27	1			T8	1		T14	1		T37	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	27	1			T4	1		T7	2		T36	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T66	2		T219	2		T220	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	32	1			T4	1		T7	1		T36	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T14	1		T259	1		T173	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	26	1			T40	1		T157	1		T259	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	273	1			T8	7		T14	2		T41	2
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	340	1			T7	3		T14	2		T40	2
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	37	1			T40	1		T37	2		T181	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	43	1			T7	1		T15	1		T227	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	20	1			T41	1		T43	1		T37	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	22	1			T181	2		T157	1		T205	2
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T41	1		T17	3		T195	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	27	1			T44	1		T205	1		T17	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T7	2		T181	1		T212	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	11	1			T84	1		T212	1		T173	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	276	1			T7	3		T8	1		T14	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	302	1			T4	2		T7	5		T8	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	41	1			T8	1		T15	3		T181	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	27	1			T182	1		T181	1		T201	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	27	1			T36	1		T38	2		T17	2
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	27	1			T15	1		T181	1		T195	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	26	1			T37	2		T17	3		T18	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	25	1			T8	1		T14	1		T182	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	23	1			T7	1		T38	1		T17	2
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	21	1			T8	1		T158	1		T43	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	332	1			T4	1		T7	4		T8	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	271	1			T4	3		T24	1		T14	5
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	38	1			T36	1		T89	1		T227	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	39	1			T89	1		T227	1		T17	2
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	20	1			T7	2		T40	1		T15	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	28	1			T8	1		T41	1		T172	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	24	1			T7	1		T41	1		T172	2
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	26	1			T41	1		T17	1		T84	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	19	1			T15	1		T181	1		T46	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	17	1			T7	2		T158	1		T37	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	310	1			T4	2		T8	1		T24	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	306	1			T7	1		T24	1		T14	3
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	28	1			T7	1		T44	1		T225	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	40	1			T14	1		T36	1		T44	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	20	1			T7	1		T181	1		T157	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	22	1			T44	1		T15	2		T84	2
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	35	1			T7	2		T8	3		T37	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	27	1			T43	1		T157	1		T192	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T37	1		T157	1		T132	2
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	18	1			T41	1		T37	1		T181	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	280	1			T4	1		T24	3		T14	3
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	326	1			T8	1		T24	3		T14	2