Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3105	1			T4	20		T7	21		T88	8
values[1]	4437	1			T4	20		T7	46		T24	16
values[2]	3766	1			T7	22		T8	23		T14	54
values[3]	3957	1			T8	21		T14	22		T40	20
values[4]	3553	1			T1	2		T4	20		T7	42
values[5]	3593	1			T14	25		T44	191		T225	4
values[6]	4256	1			T3	14		T7	21		T8	108
values[7]	3481	1			T7	20		T45	4		T14	21

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3849	1			T4	20		T7	47		T36	20
values[1]	3518	1			T4	20		T7	42		T45	4
values[2]	3386	1			T1	2		T42	8		T44	85
values[3]	3901	1			T4	20		T7	41		T8	53
values[4]	4618	1			T7	42		T14	29		T159	20
values[5]	3360	1			T8	55		T24	16		T14	21
values[6]	4086	1			T3	14		T8	21		T14	70
values[7]	3430	1			T8	44		T14	25		T40	20

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29361

1

T1

2

T3

14

T4

57

auto[1]

787

1

T4

3

T7

11

T8

7

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	497	1			T43	20		T46	23		T173	19
auto[0]	values[0]	values[1]	400	1			T256	16		T205	19		T17	20
auto[0]	values[0]	values[2]	375	1			T44	64		T15	20		T37	21
auto[0]	values[0]	values[3]	397	1			T4	20		T7	21		T43	23
auto[0]	values[0]	values[4]	440	1			T260	4		T173	40		T185	20
auto[0]	values[0]	values[5]	299	1			T88	8		T30	20		T261	20
auto[0]	values[0]	values[6]	331	1			T237	4		T157	43		T221	23
auto[0]	values[0]	values[7]	300	1			T201	20		T46	23		T66	24
auto[0]	values[1]	values[0]	402	1			T7	22		T157	20		T262	20
auto[0]	values[1]	values[1]	574	1			T4	20		T36	40		T43	23
auto[0]	values[1]	values[2]	290	1			T42	6		T15	18		T238	2
auto[0]	values[1]	values[3]	506	1			T205	39		T246	14		T22	18
auto[0]	values[1]	values[4]	895	1			T7	16		T255	4		T15	18
auto[0]	values[1]	values[5]	583	1			T24	16		T43	23		T186	20
auto[0]	values[1]	values[6]	587	1			T263	14		T226	8		T203	24
auto[0]	values[1]	values[7]	482	1			T41	17		T182	18		T203	20
auto[0]	values[2]	values[0]	624	1			T40	19		T128	126		T83	10
auto[0]	values[2]	values[1]	302	1			T7	20		T46	18		T264	6
auto[0]	values[2]	values[2]	492	1			T172	20		T46	20		T84	19
auto[0]	values[2]	values[3]	466	1			T17	50		T22	28		T31	23
auto[0]	values[2]	values[4]	693	1			T14	26		T158	19		T41	20
auto[0]	values[2]	values[5]	328	1			T15	19		T258	2		T18	24
auto[0]	values[2]	values[6]	454	1			T110	16		T41	19		T44	56
auto[0]	values[2]	values[7]	290	1			T8	23		T14	25		T40	19
auto[0]	values[3]	values[0]	485	1			T43	21		T17	43		T30	59
auto[0]	values[3]	values[1]	335	1			T43	31		T182	20		T242	18
auto[0]	values[3]	values[2]	383	1			T30	24		T31	132		T220	36
auto[0]	values[3]	values[3]	742	1			T15	20		T46	24		T51	16
auto[0]	values[3]	values[4]	620	1			T44	17		T265	10		T175	2
auto[0]	values[3]	values[5]	386	1			T40	17		T43	20		T240	2
auto[0]	values[3]	values[6]	534	1			T14	22		T44	50		T248	8
auto[0]	values[3]	values[7]	371	1			T8	21		T44	38		T84	18
auto[0]	values[4]	values[0]	371	1			T4	17		T186	18		T198	4
auto[0]	values[4]	values[1]	440	1			T126	20		T37	20		T46	26
auto[0]	values[4]	values[2]	283	1			T1	2		T157	19		T172	20
auto[0]	values[4]	values[3]	474	1			T7	20		T182	20		T192	64
auto[0]	values[4]	values[4]	599	1			T7	21		T44	69		T15	20
auto[0]	values[4]	values[5]	547	1			T36	33		T181	20		T66	125
auto[0]	values[4]	values[6]	320	1			T8	20		T14	22		T36	20
auto[0]	values[4]	values[7]	406	1			T38	33		T249	18		T18	20
auto[0]	values[5]	values[0]	375	1			T181	20		T38	20		T157	42
auto[0]	values[5]	values[1]	417	1			T44	39		T18	22		T46	20
auto[0]	values[5]	values[2]	452	1			T17	20		T46	20		T247	19
auto[0]	values[5]	values[3]	455	1			T18	22		T213	14		T46	24
auto[0]	values[5]	values[4]	610	1			T44	128		T131	8		T38	20
auto[0]	values[5]	values[5]	316	1			T37	20		T205	20		T206	4
auto[0]	values[5]	values[6]	578	1			T14	24		T156	60		T37	20
auto[0]	values[5]	values[7]	325	1			T44	23		T225	4		T205	20
auto[0]	values[6]	values[0]	449	1			T7	21		T36	20		T41	20
auto[0]	values[6]	values[1]	533	1			T158	20		T38	18		T172	20
auto[0]	values[6]	values[2]	533	1			T44	20		T157	22		T205	18
auto[0]	values[6]	values[3]	448	1			T8	52		T205	17		T192	31
auto[0]	values[6]	values[4]	417	1			T41	19		T186	19		T172	18
auto[0]	values[6]	values[5]	599	1			T8	50		T44	67		T15	21
auto[0]	values[6]	values[6]	643	1			T3	14		T236	10		T17	23
auto[0]	values[6]	values[7]	508	1			T37	21		T157	23		T212	32
auto[0]	values[7]	values[0]	541	1			T182	20		T181	20		T172	20
auto[0]	values[7]	values[1]	411	1			T7	20		T45	4		T37	19
auto[0]	values[7]	values[2]	495	1			T15	20		T157	20		T17	22
auto[0]	values[7]	values[3]	319	1			T40	20		T253	20		T266	14
auto[0]	values[7]	values[4]	230	1			T159	20		T227	6		T205	20
auto[0]	values[7]	values[5]	209	1			T14	21		T43	17		T185	43
auto[0]	values[7]	values[6]	532	1			T89	8		T15	26		T195	19
auto[0]	values[7]	values[7]	663	1			T44	73		T15	21		T37	20
auto[1]	values[0]	values[0]	14	1			T46	2		T173	1		T31	1
auto[1]	values[0]	values[1]	7	1			T256	2		T205	1		T267	2
auto[1]	values[0]	values[2]	11	1			T44	1		T37	1		T195	1
auto[1]	values[0]	values[3]	8	1			T43	3		T84	1		T268	2
auto[1]	values[0]	values[4]	3	1			T269	1		T270	2		-	-
auto[1]	values[0]	values[5]	8	1			T180	1		T197	3		T271	1
auto[1]	values[0]	values[6]	6	1			T157	3		T173	1		T199	1
auto[1]	values[0]	values[7]	9	1			T46	4		T66	2		T132	1
auto[1]	values[1]	values[0]	8	1			T7	4		T66	1		T31	2
auto[1]	values[1]	values[1]	22	1			T130	2		T181	1		T212	3
auto[1]	values[1]	values[2]	8	1			T42	2		T15	2		T272	2
auto[1]	values[1]	values[3]	12	1			T205	1		T22	2		T177	3
auto[1]	values[1]	values[4]	19	1			T7	4		T15	2		T192	1
auto[1]	values[1]	values[5]	7	1			T178	1		T273	2		T274	2
auto[1]	values[1]	values[6]	29	1			T192	3		T199	1		T177	2
auto[1]	values[1]	values[7]	13	1			T41	3		T182	2		T185	3
auto[1]	values[2]	values[0]	14	1			T40	1		T66	5		T233	1
auto[1]	values[2]	values[1]	15	1			T7	2		T46	2		T275	3
auto[1]	values[2]	values[2]	14	1			T84	1		T30	3		T276	2
auto[1]	values[2]	values[3]	12	1			T17	4		T22	1		T219	1
auto[1]	values[2]	values[4]	26	1			T14	3		T158	1		T184	1
auto[1]	values[2]	values[5]	9	1			T15	1		T18	3		T233	1
auto[1]	values[2]	values[6]	17	1			T41	1		T44	3		T157	2
auto[1]	values[2]	values[7]	10	1			T40	1		T15	1		T199	1
auto[1]	values[3]	values[0]	17	1			T43	3		T17	1		T30	1
auto[1]	values[3]	values[1]	6	1			T31	1		T219	1		T277	1
auto[1]	values[3]	values[2]	7	1			T275	2		T155	3		T278	2
auto[1]	values[3]	values[3]	16	1			T30	1		T132	2		T177	1
auto[1]	values[3]	values[4]	19	1			T44	3		T195	1		T185	1
auto[1]	values[3]	values[5]	16	1			T40	3		T203	3		T132	2
auto[1]	values[3]	values[6]	10	1			T44	1		T204	1		T279	1
auto[1]	values[3]	values[7]	10	1			T44	2		T84	2		T280	1
auto[1]	values[4]	values[0]	18	1			T4	3		T186	2		T198	6
auto[1]	values[4]	values[1]	13	1			T37	1		T199	3		T281	1
auto[1]	values[4]	values[2]	6	1			T157	1		T201	3		T195	1
auto[1]	values[4]	values[3]	10	1			T212	3		T276	2		T232	1
auto[1]	values[4]	values[4]	16	1			T7	1		T44	1		T132	4
auto[1]	values[4]	values[5]	27	1			T36	1		T66	4		T253	2
auto[1]	values[4]	values[6]	11	1			T8	1		T14	1		T31	2
auto[1]	values[4]	values[7]	12	1			T38	2		T179	2		T282	3
auto[1]	values[5]	values[0]	12	1			T181	1		T46	1		T280	3
auto[1]	values[5]	values[1]	9	1			T44	1		T18	1		T173	1
auto[1]	values[5]	values[2]	7	1			T247	1		T195	1		T283	4
auto[1]	values[5]	values[3]	4	1			T213	2		T272	2		-	-
auto[1]	values[5]	values[4]	14	1			T38	2		T184	2		T84	1
auto[1]	values[5]	values[5]	5	1			T278	2		T284	2		T285	1
auto[1]	values[5]	values[6]	7	1			T14	1		T17	1		T179	1
auto[1]	values[5]	values[7]	7	1			T286	1		T287	2		T288	4
auto[1]	values[6]	values[0]	14	1			T181	2		T172	2		T220	2
auto[1]	values[6]	values[1]	21	1			T38	2		T17	1		T31	2
auto[1]	values[6]	values[2]	23	1			T157	3		T205	2		T219	4
auto[1]	values[6]	values[3]	21	1			T8	1		T205	3		T192	2
auto[1]	values[6]	values[4]	13	1			T41	1		T186	1		T172	2
auto[1]	values[6]	values[5]	11	1			T8	5		T44	2		T254	1
auto[1]	values[6]	values[6]	15	1			T17	1		T203	2		T46	3
auto[1]	values[6]	values[7]	8	1			T37	1		T157	1		T232	1
auto[1]	values[7]	values[0]	8	1			T287	2		T283	1		T289	1
auto[1]	values[7]	values[1]	13	1			T37	1		T250	2		T205	2
auto[1]	values[7]	values[2]	7	1			T17	1		T290	1		T289	1
auto[1]	values[7]	values[3]	11	1			T274	2		T267	3		T291	2
auto[1]	values[7]	values[4]	4	1			T196	1		T280	3		-	-
auto[1]	values[7]	values[5]	10	1			T43	3		T292	4		T293	2
auto[1]	values[7]	values[6]	12	1			T15	3		T195	1		T66	1
auto[1]	values[7]	values[7]	16	1			T186	2		T155	2		T285	7