Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	849	1			T6	7		T14	4		T15	4
all_values[1]	849	1			T6	7		T14	4		T15	4
all_values[2]	849	1			T6	7		T14	4		T15	4
all_values[3]	849	1			T6	7		T14	4		T15	4
all_values[4]	849	1			T6	7		T14	4		T15	4
all_values[5]	849	1			T6	7		T14	4		T15	4
all_values[6]	849	1			T6	7		T14	4		T15	4
all_values[7]	849	1			T6	7		T14	4		T15	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3678

1

T6

34

T14

22

T15

18

auto[1]

3114

1

T6

22

T14

10

T15

14

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2769

1

T6

17

T14

17

T15

16

auto[1]

4023

1

T6

39

T14

15

T15

16

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3904

1

T6

31

T14

20

T15

22

auto[1]

2888

1

T6

25

T14

12

T15

10

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	154	1			T6	1		T14	3		T15	4
all_values[0]	auto[0]	auto[0]	auto[1]	89	1			T6	1		T18	1		T19	2
all_values[0]	auto[0]	auto[1]	auto[0]	144	1			T18	4		T19	6		T20	4
all_values[0]	auto[0]	auto[1]	auto[1]	83	1			T6	1		T16	1		T18	1
all_values[0]	auto[1]	auto[0]	auto[1]	201	1			T6	2		T14	1		T18	2
all_values[0]	auto[1]	auto[1]	auto[1]	178	1			T6	2		T16	2		T18	3
all_values[1]	auto[0]	auto[0]	auto[0]	208	1			T6	1		T15	1		T16	1
all_values[1]	auto[0]	auto[0]	auto[1]	103	1			T15	2		T18	2		T19	2
all_values[1]	auto[0]	auto[1]	auto[0]	109	1			T6	3		T14	1		T16	1
all_values[1]	auto[0]	auto[1]	auto[1]	68	1			T6	1		T14	1		T16	1
all_values[1]	auto[1]	auto[0]	auto[1]	187	1			T6	1		T14	1		T15	1
all_values[1]	auto[1]	auto[1]	auto[1]	174	1			T6	1		T14	1		T18	3
all_values[2]	auto[0]	auto[0]	auto[0]	175	1			T6	1		T14	1		T16	1
all_values[2]	auto[0]	auto[0]	auto[1]	83	1			T6	3		T15	2		T18	3
all_values[2]	auto[0]	auto[1]	auto[0]	184	1			T14	2		T15	1		T18	1
all_values[2]	auto[0]	auto[1]	auto[1]	78	1			T16	1		T18	3		T20	1
all_values[2]	auto[1]	auto[0]	auto[1]	168	1			T6	3		T14	1		T16	1
all_values[2]	auto[1]	auto[1]	auto[1]	161	1			T15	1		T16	1		T18	1
all_values[3]	auto[0]	auto[0]	auto[0]	174	1			T6	1		T14	1		T18	2
all_values[3]	auto[0]	auto[0]	auto[1]	87	1			T6	1		T16	1		T18	2
all_values[3]	auto[0]	auto[1]	auto[0]	127	1			T15	3		T18	1		T19	4
all_values[3]	auto[0]	auto[1]	auto[1]	80	1			T6	1		T19	2		T20	3
all_values[3]	auto[1]	auto[0]	auto[1]	216	1			T14	3		T16	1		T18	4
all_values[3]	auto[1]	auto[1]	auto[1]	165	1			T6	4		T15	1		T16	2
all_values[4]	auto[0]	auto[0]	auto[0]	189	1			T6	1		T18	4		T19	2
all_values[4]	auto[0]	auto[0]	auto[1]	84	1			T6	3		T15	1		T16	1
all_values[4]	auto[0]	auto[1]	auto[0]	157	1			T15	2		T16	2		T18	1
all_values[4]	auto[0]	auto[1]	auto[1]	75	1			T14	1		T18	1		T19	1
all_values[4]	auto[1]	auto[0]	auto[1]	194	1			T6	3		T14	2		T16	1
all_values[4]	auto[1]	auto[1]	auto[1]	150	1			T14	1		T15	1		T18	1
all_values[5]	auto[0]	auto[0]	auto[0]	251	1			T6	3		T14	2		T16	1
all_values[5]	auto[0]	auto[1]	auto[0]	235	1			T6	2		T14	1		T15	1
all_values[5]	auto[1]	auto[0]	auto[1]	190	1			T6	1		T14	1		T15	2
all_values[5]	auto[1]	auto[1]	auto[1]	173	1			T6	1		T15	1		T18	4
all_values[6]	auto[0]	auto[0]	auto[0]	182	1			T6	3		T14	1		T15	1
all_values[6]	auto[0]	auto[0]	auto[1]	89	1			T14	1		T18	1		T19	5
all_values[6]	auto[0]	auto[1]	auto[0]	134	1			T14	1		T16	1		T18	3
all_values[6]	auto[0]	auto[1]	auto[1]	74	1			T6	1		T15	1		T16	1
all_values[6]	auto[1]	auto[0]	auto[1]	202	1			T6	1		T14	1		T15	1
all_values[6]	auto[1]	auto[1]	auto[1]	168	1			T6	2		T15	1		T18	2
all_values[7]	auto[0]	auto[0]	auto[0]	193	1			T6	1		T14	3		T15	2
all_values[7]	auto[0]	auto[0]	auto[1]	75	1			T6	1		T19	1		T22	1
all_values[7]	auto[0]	auto[1]	auto[0]	153	1			T14	1		T15	1		T16	1
all_values[7]	auto[0]	auto[1]	auto[1]	67	1			T6	1		T18	1		T19	3
all_values[7]	auto[1]	auto[0]	auto[1]	184	1			T6	2		T15	1		T16	1
all_values[7]	auto[1]	auto[1]	auto[1]	177	1			T6	2		T18	2		T19	8

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal