Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1692

1

T7

8

T8

1

T11

10

auto[1]

1667

1

T7

2

T8

4

T11

5

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1730

1

T7

10

T8

3

T11

15

auto[1]

1629

1

T8

2

T25

3

T43

6

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2720

1

T7

9

T8

2

T11

10

auto[1]

639

1

T7

1

T8

3

T11

5

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	720	1			T7	1		T8	2		T11	4
valid[1]	666	1			T7	1		T8	1		T11	3
valid[2]	657	1			T7	2		T8	1		T11	2
valid[3]	656	1			T7	2		T11	2		T14	5
valid[4]	660	1			T7	4		T8	1		T11	4

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	117	1			T11	2		T14	2		T25	1
auto[0]	auto[0]	valid[0]	auto[1]	191	1			T37	1		T78	5		T79	4
auto[0]	auto[0]	valid[1]	auto[0]	105	1			T11	1		T27	2		T28	2
auto[0]	auto[0]	valid[1]	auto[1]	180	1			T25	1		T43	2		T78	1
auto[0]	auto[0]	valid[2]	auto[0]	115	1			T7	2		T11	1		T14	2
auto[0]	auto[0]	valid[2]	auto[1]	144	1			T37	2		T78	1		T79	1
auto[0]	auto[0]	valid[3]	auto[0]	106	1			T7	2		T14	2		T26	2
auto[0]	auto[0]	valid[3]	auto[1]	153	1			T25	1		T43	1		T78	2
auto[0]	auto[0]	valid[4]	auto[0]	107	1			T7	3		T11	2		T14	1
auto[0]	auto[0]	valid[4]	auto[1]	151	1			T78	3		T80	1		T81	1
auto[0]	auto[1]	valid[0]	auto[0]	118	1			T7	1		T11	1		T25	1
auto[0]	auto[1]	valid[0]	auto[1]	141	1			T37	1		T78	3		T79	1
auto[0]	auto[1]	valid[1]	auto[0]	107	1			T7	1		T11	1		T27	2
auto[0]	auto[1]	valid[1]	auto[1]	156	1			T8	1		T43	2		T37	1
auto[0]	auto[1]	valid[2]	auto[0]	93	1			T14	1		T304	1		T43	1
auto[0]	auto[1]	valid[2]	auto[1]	178	1			T8	1		T25	1		T78	5
auto[0]	auto[1]	valid[3]	auto[0]	92	1			T14	3		T27	1		T29	3
auto[0]	auto[1]	valid[3]	auto[1]	186	1			T43	1		T37	1		T78	1
auto[0]	auto[1]	valid[4]	auto[0]	131	1			T11	2		T14	1		T27	1
auto[0]	auto[1]	valid[4]	auto[1]	149	1			T78	2		T73	1		T82	1
auto[1]	auto[0]	valid[0]	auto[0]	70	1			T27	1		T43	1		T37	1
auto[1]	auto[0]	valid[1]	auto[0]	57	1			T11	1		T14	1		T43	2
auto[1]	auto[0]	valid[2]	auto[0]	74	1			T11	1		T26	1		T29	2
auto[1]	auto[0]	valid[3]	auto[0]	58	1			T11	2		T25	1		T26	1
auto[1]	auto[0]	valid[4]	auto[0]	64	1			T7	1		T8	1		T306	1
auto[1]	auto[1]	valid[0]	auto[0]	83	1			T8	2		T11	1		T25	1
auto[1]	auto[1]	valid[1]	auto[0]	61	1			T14	1		T27	2		T29	2
auto[1]	auto[1]	valid[2]	auto[0]	53	1			T25	1		T26	1		T28	1
auto[1]	auto[1]	valid[3]	auto[0]	61	1			T25	1		T29	1		T15	2
auto[1]	auto[1]	valid[4]	auto[0]	58	1			T14	1		T25	2		T28	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal