Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

44351

1

T7

236

T8

46

T11

323

auto[1]

17029

1

T8

35

T25

28

T43

102

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

45216

1

T7

173

T8

52

T11

203

auto[1]

16164

1

T7

63

T8

29

T11

120

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	31463	1			T7	137		T8	38		T11	161
others[1]	5255	1			T7	24		T8	6		T11	30
others[2]	5243	1			T7	18		T8	7		T11	32
others[3]	5848	1			T7	16		T8	12		T11	30
interest[1]	3343	1			T7	14		T8	6		T11	23
interest[4]	20472	1			T7	82		T8	21		T11	95
interest[64]	10228	1			T7	27		T8	12		T11	47

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	14427	1			T7	102		T8	8		T11	102
auto[0]	auto[0]	others[1]	2436	1			T7	16		T8	3		T11	22
auto[0]	auto[0]	others[2]	2502	1			T7	14		T11	20		T13	2
auto[0]	auto[0]	others[3]	2654	1			T7	10		T8	3		T11	18
auto[0]	auto[0]	interest[1]	1548	1			T7	11		T8	1		T11	17
auto[0]	auto[0]	interest[4]	9393	1			T7	62		T8	4		T11	61
auto[0]	auto[0]	interest[64]	4620	1			T7	20		T8	2		T11	24
auto[0]	auto[1]	others[0]	8782	1			T8	16		T25	14		T43	50
auto[0]	auto[1]	others[1]	1472	1			T8	2		T25	3		T43	11
auto[0]	auto[1]	others[2]	1453	1			T8	3		T25	1		T43	8
auto[0]	auto[1]	others[3]	1571	1			T8	4		T25	5		T43	8
auto[0]	auto[1]	interest[1]	850	1			T8	3		T25	1		T43	7
auto[0]	auto[1]	interest[4]	5756	1			T8	10		T25	9		T43	35
auto[0]	auto[1]	interest[64]	2901	1			T8	7		T25	4		T43	18
auto[1]	auto[0]	others[0]	8254	1			T7	35		T8	14		T11	59
auto[1]	auto[0]	others[1]	1347	1			T7	8		T8	1		T11	8
auto[1]	auto[0]	others[2]	1288	1			T7	4		T8	4		T11	12
auto[1]	auto[0]	others[3]	1623	1			T7	6		T8	5		T11	12
auto[1]	auto[0]	interest[1]	945	1			T7	3		T8	2		T11	6
auto[1]	auto[0]	interest[4]	5323	1			T7	20		T8	7		T11	34
auto[1]	auto[0]	interest[64]	2707	1			T7	7		T8	3		T11	23

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal