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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.07 98.44 94.08 98.62 89.36 97.28 95.43 99.26


Total test records in report: 1151
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T1039 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.689058285 Jul 26 04:47:06 PM PDT 24 Jul 26 04:47:07 PM PDT 24 94440922 ps
T1040 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.1552664577 Jul 26 04:46:50 PM PDT 24 Jul 26 04:46:52 PM PDT 24 71755412 ps
T96 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.819619781 Jul 26 04:47:10 PM PDT 24 Jul 26 04:47:12 PM PDT 24 37580517 ps
T1041 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.493455839 Jul 26 04:46:59 PM PDT 24 Jul 26 04:47:00 PM PDT 24 10425145 ps
T1042 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.3574194710 Jul 26 04:47:09 PM PDT 24 Jul 26 04:47:11 PM PDT 24 62126295 ps
T117 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.1741410564 Jul 26 04:46:56 PM PDT 24 Jul 26 04:47:17 PM PDT 24 361788617 ps
T100 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2703686310 Jul 26 04:47:02 PM PDT 24 Jul 26 04:47:07 PM PDT 24 244339438 ps
T97 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1007929932 Jul 26 04:47:05 PM PDT 24 Jul 26 04:47:14 PM PDT 24 743076959 ps
T1043 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.923973937 Jul 26 04:46:51 PM PDT 24 Jul 26 04:46:52 PM PDT 24 30835496 ps
T1044 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.588886485 Jul 26 04:47:04 PM PDT 24 Jul 26 04:47:05 PM PDT 24 30204345 ps
T107 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.994394653 Jul 26 04:46:59 PM PDT 24 Jul 26 04:47:02 PM PDT 24 167038533 ps
T118 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.913940379 Jul 26 04:46:59 PM PDT 24 Jul 26 04:47:01 PM PDT 24 80590519 ps
T108 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.330102713 Jul 26 04:47:13 PM PDT 24 Jul 26 04:47:20 PM PDT 24 38178567 ps
T1045 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.1127068741 Jul 26 04:47:05 PM PDT 24 Jul 26 04:47:06 PM PDT 24 41283626 ps
T119 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.1083047354 Jul 26 04:46:44 PM PDT 24 Jul 26 04:46:46 PM PDT 24 235049785 ps
T1046 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3214975793 Jul 26 04:47:03 PM PDT 24 Jul 26 04:47:04 PM PDT 24 88097551 ps
T120 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.2532193459 Jul 26 04:47:01 PM PDT 24 Jul 26 04:47:03 PM PDT 24 106099188 ps
T1047 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.2654083103 Jul 26 04:47:07 PM PDT 24 Jul 26 04:47:09 PM PDT 24 87507586 ps
T98 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.2623964968 Jul 26 04:46:52 PM PDT 24 Jul 26 04:47:05 PM PDT 24 2336575436 ps
T1048 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.2118073052 Jul 26 04:47:06 PM PDT 24 Jul 26 04:47:07 PM PDT 24 21664620 ps
T1049 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.659381634 Jul 26 04:47:02 PM PDT 24 Jul 26 04:47:06 PM PDT 24 118843934 ps
T101 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.3484955028 Jul 26 04:47:05 PM PDT 24 Jul 26 04:47:10 PM PDT 24 64431324 ps
T75 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.962615549 Jul 26 04:46:54 PM PDT 24 Jul 26 04:47:00 PM PDT 24 30007616 ps
T163 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.3758410474 Jul 26 04:46:55 PM PDT 24 Jul 26 04:47:08 PM PDT 24 1120235006 ps
T121 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1273168268 Jul 26 04:46:32 PM PDT 24 Jul 26 04:46:58 PM PDT 24 6916759935 ps
T103 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.1856320493 Jul 26 04:46:56 PM PDT 24 Jul 26 04:46:58 PM PDT 24 25252362 ps
T1050 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.1118826321 Jul 26 04:47:05 PM PDT 24 Jul 26 04:47:06 PM PDT 24 35929396 ps
T102 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.1236924721 Jul 26 04:47:07 PM PDT 24 Jul 26 04:47:10 PM PDT 24 416064741 ps
T1051 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.328010339 Jul 26 04:46:51 PM PDT 24 Jul 26 04:46:52 PM PDT 24 11742507 ps
T1052 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.845327401 Jul 26 04:47:05 PM PDT 24 Jul 26 04:47:06 PM PDT 24 11075185 ps
T76 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3655255844 Jul 26 04:47:11 PM PDT 24 Jul 26 04:47:13 PM PDT 24 91763885 ps
T104 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1371349139 Jul 26 04:47:02 PM PDT 24 Jul 26 04:47:07 PM PDT 24 670660932 ps
T1053 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.820250604 Jul 26 04:46:54 PM PDT 24 Jul 26 04:46:54 PM PDT 24 43525423 ps
T147 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.4194259671 Jul 26 04:47:12 PM PDT 24 Jul 26 04:47:14 PM PDT 24 71590241 ps
T167 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.643127067 Jul 26 04:47:00 PM PDT 24 Jul 26 04:47:09 PM PDT 24 584529382 ps
T1054 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.4266068417 Jul 26 04:46:43 PM PDT 24 Jul 26 04:46:45 PM PDT 24 97502891 ps
T164 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.3337028754 Jul 26 04:47:03 PM PDT 24 Jul 26 04:47:16 PM PDT 24 844685991 ps
T1055 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.2184097066 Jul 26 04:47:01 PM PDT 24 Jul 26 04:47:01 PM PDT 24 12001440 ps
T1056 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1990785329 Jul 26 04:47:06 PM PDT 24 Jul 26 04:47:10 PM PDT 24 124441487 ps
T1057 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.3499137755 Jul 26 04:47:08 PM PDT 24 Jul 26 04:47:12 PM PDT 24 135319579 ps
T1058 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.3653775499 Jul 26 04:47:13 PM PDT 24 Jul 26 04:47:14 PM PDT 24 44016067 ps
T1059 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1285642873 Jul 26 04:46:58 PM PDT 24 Jul 26 04:46:59 PM PDT 24 80628272 ps
T161 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1049429291 Jul 26 04:47:02 PM PDT 24 Jul 26 04:47:09 PM PDT 24 194811385 ps
T1060 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.200893998 Jul 26 04:47:02 PM PDT 24 Jul 26 04:47:03 PM PDT 24 12901404 ps
T123 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2845463993 Jul 26 04:46:40 PM PDT 24 Jul 26 04:47:06 PM PDT 24 8229956812 ps
T122 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.1783101078 Jul 26 04:47:05 PM PDT 24 Jul 26 04:47:08 PM PDT 24 290872656 ps
T1061 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.1953666149 Jul 26 04:47:04 PM PDT 24 Jul 26 04:47:08 PM PDT 24 101546185 ps
T1062 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.3314437019 Jul 26 04:47:04 PM PDT 24 Jul 26 04:47:05 PM PDT 24 39946293 ps
T165 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.4231032102 Jul 26 04:46:58 PM PDT 24 Jul 26 04:47:17 PM PDT 24 2803408901 ps
T1063 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.3121605724 Jul 26 04:47:00 PM PDT 24 Jul 26 04:47:01 PM PDT 24 82710257 ps
T1064 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.650041768 Jul 26 04:46:58 PM PDT 24 Jul 26 04:46:59 PM PDT 24 155284156 ps
T162 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.1107245983 Jul 26 04:47:08 PM PDT 24 Jul 26 04:47:21 PM PDT 24 507689653 ps
T148 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.158868117 Jul 26 04:46:57 PM PDT 24 Jul 26 04:47:01 PM PDT 24 169555843 ps
T1065 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.4136409836 Jul 26 04:47:19 PM PDT 24 Jul 26 04:47:21 PM PDT 24 99177777 ps
T1066 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.596462852 Jul 26 04:47:08 PM PDT 24 Jul 26 04:47:11 PM PDT 24 69978988 ps
T1067 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.3980450584 Jul 26 04:46:58 PM PDT 24 Jul 26 04:47:05 PM PDT 24 264497599 ps
T1068 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.551943477 Jul 26 04:47:04 PM PDT 24 Jul 26 04:47:07 PM PDT 24 71583629 ps
T77 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.1577126699 Jul 26 04:46:55 PM PDT 24 Jul 26 04:46:56 PM PDT 24 20464761 ps
T1069 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.165937478 Jul 26 04:47:00 PM PDT 24 Jul 26 04:47:01 PM PDT 24 141476532 ps
T1070 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.4171686796 Jul 26 04:47:05 PM PDT 24 Jul 26 04:47:07 PM PDT 24 162914162 ps
T1071 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.1782509592 Jul 26 04:47:25 PM PDT 24 Jul 26 04:47:26 PM PDT 24 12488143 ps
T1072 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.3997844346 Jul 26 04:47:22 PM PDT 24 Jul 26 04:47:23 PM PDT 24 14196385 ps
T1073 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.683724823 Jul 26 04:46:58 PM PDT 24 Jul 26 04:46:59 PM PDT 24 20312731 ps
T105 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.2403698665 Jul 26 04:47:13 PM PDT 24 Jul 26 04:47:15 PM PDT 24 25549671 ps
T1074 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.4043971414 Jul 26 04:47:00 PM PDT 24 Jul 26 04:47:02 PM PDT 24 42221297 ps
T124 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.761656534 Jul 26 04:47:03 PM PDT 24 Jul 26 04:47:25 PM PDT 24 1233596063 ps
T1075 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3809764644 Jul 26 04:47:04 PM PDT 24 Jul 26 04:47:08 PM PDT 24 128419375 ps
T1076 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1073005498 Jul 26 04:46:44 PM PDT 24 Jul 26 04:46:48 PM PDT 24 120244103 ps
T149 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3972109987 Jul 26 04:46:55 PM PDT 24 Jul 26 04:46:59 PM PDT 24 581417233 ps
T1077 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3737551790 Jul 26 04:47:17 PM PDT 24 Jul 26 04:47:20 PM PDT 24 503332915 ps
T125 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.1368175822 Jul 26 04:47:04 PM PDT 24 Jul 26 04:47:05 PM PDT 24 95638878 ps
T1078 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.4085326060 Jul 26 04:46:54 PM PDT 24 Jul 26 04:46:56 PM PDT 24 59385729 ps
T1079 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1845254117 Jul 26 04:46:57 PM PDT 24 Jul 26 04:46:58 PM PDT 24 12405300 ps
T1080 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2160269385 Jul 26 04:47:04 PM PDT 24 Jul 26 04:47:06 PM PDT 24 102381635 ps
T1081 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.3425854091 Jul 26 04:47:15 PM PDT 24 Jul 26 04:47:17 PM PDT 24 61366709 ps
T1082 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1580957641 Jul 26 04:47:13 PM PDT 24 Jul 26 04:47:15 PM PDT 24 13659258 ps
T106 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3390543676 Jul 26 04:46:38 PM PDT 24 Jul 26 04:46:41 PM PDT 24 49476120 ps
T1083 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.714176448 Jul 26 04:47:04 PM PDT 24 Jul 26 04:47:04 PM PDT 24 17585943 ps
T1084 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.536262094 Jul 26 04:47:08 PM PDT 24 Jul 26 04:47:09 PM PDT 24 87893692 ps
T160 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2030990697 Jul 26 04:46:56 PM PDT 24 Jul 26 04:47:01 PM PDT 24 698627754 ps
T1085 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.661482023 Jul 26 04:47:11 PM PDT 24 Jul 26 04:47:14 PM PDT 24 44234638 ps
T1086 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1899922779 Jul 26 04:46:53 PM PDT 24 Jul 26 04:46:56 PM PDT 24 318675870 ps
T1087 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.2210554453 Jul 26 04:46:48 PM PDT 24 Jul 26 04:46:51 PM PDT 24 152644320 ps
T1088 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2624134869 Jul 26 04:47:01 PM PDT 24 Jul 26 04:47:04 PM PDT 24 40270324 ps
T1089 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.4029279981 Jul 26 04:47:17 PM PDT 24 Jul 26 04:47:20 PM PDT 24 312946948 ps
T1090 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.3844275029 Jul 26 04:47:03 PM PDT 24 Jul 26 04:47:11 PM PDT 24 504455766 ps
T1091 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.4111041882 Jul 26 04:47:04 PM PDT 24 Jul 26 04:47:06 PM PDT 24 360045371 ps
T1092 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.2324135324 Jul 26 04:47:14 PM PDT 24 Jul 26 04:47:15 PM PDT 24 33502751 ps
T1093 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.282770322 Jul 26 04:46:50 PM PDT 24 Jul 26 04:47:14 PM PDT 24 1149542716 ps
T1094 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.3326073941 Jul 26 04:46:58 PM PDT 24 Jul 26 04:47:00 PM PDT 24 70326157 ps
T1095 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3059708944 Jul 26 04:47:09 PM PDT 24 Jul 26 04:47:10 PM PDT 24 21828415 ps
T1096 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3217027646 Jul 26 04:46:58 PM PDT 24 Jul 26 04:47:20 PM PDT 24 919280271 ps
T1097 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.593365821 Jul 26 04:46:59 PM PDT 24 Jul 26 04:47:01 PM PDT 24 100034910 ps
T1098 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.3634572132 Jul 26 04:47:13 PM PDT 24 Jul 26 04:47:14 PM PDT 24 14134010 ps
T1099 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.1540023666 Jul 26 04:47:10 PM PDT 24 Jul 26 04:47:14 PM PDT 24 152646251 ps
T1100 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.4018489160 Jul 26 04:46:57 PM PDT 24 Jul 26 04:46:58 PM PDT 24 14411314 ps
T1101 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.2472834464 Jul 26 04:47:08 PM PDT 24 Jul 26 04:47:09 PM PDT 24 21919820 ps
T1102 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.3934617000 Jul 26 04:47:02 PM PDT 24 Jul 26 04:47:04 PM PDT 24 230409335 ps
T1103 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1772793022 Jul 26 04:47:12 PM PDT 24 Jul 26 04:47:16 PM PDT 24 88870262 ps
T166 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2995087514 Jul 26 04:46:57 PM PDT 24 Jul 26 04:47:12 PM PDT 24 548699683 ps
T1104 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.1851765614 Jul 26 04:47:03 PM PDT 24 Jul 26 04:47:20 PM PDT 24 702207927 ps
T1105 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.2162428359 Jul 26 04:47:05 PM PDT 24 Jul 26 04:47:06 PM PDT 24 167346218 ps
T1106 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.3971802480 Jul 26 04:46:58 PM PDT 24 Jul 26 04:46:59 PM PDT 24 15731999 ps
T168 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.2783322549 Jul 26 04:46:51 PM PDT 24 Jul 26 04:46:58 PM PDT 24 261763063 ps
T1107 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.1971043376 Jul 26 04:46:49 PM PDT 24 Jul 26 04:46:50 PM PDT 24 44392328 ps
T1108 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3760924116 Jul 26 04:47:08 PM PDT 24 Jul 26 04:47:11 PM PDT 24 802042723 ps
T1109 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.586554978 Jul 26 04:47:14 PM PDT 24 Jul 26 04:47:15 PM PDT 24 16772223 ps
T1110 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.153342923 Jul 26 04:46:58 PM PDT 24 Jul 26 04:46:59 PM PDT 24 45071362 ps
T1111 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.1615482870 Jul 26 04:47:05 PM PDT 24 Jul 26 04:47:13 PM PDT 24 521282764 ps
T1112 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.681532660 Jul 26 04:46:45 PM PDT 24 Jul 26 04:46:46 PM PDT 24 12861898 ps
T1113 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.253349568 Jul 26 04:47:00 PM PDT 24 Jul 26 04:47:12 PM PDT 24 202008475 ps
T169 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1566842134 Jul 26 04:47:10 PM PDT 24 Jul 26 04:47:28 PM PDT 24 1179604613 ps
T1114 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.3407236745 Jul 26 04:46:59 PM PDT 24 Jul 26 04:47:01 PM PDT 24 71067698 ps
T1115 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3946282408 Jul 26 04:46:57 PM PDT 24 Jul 26 04:46:58 PM PDT 24 11410604 ps
T170 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.840319602 Jul 26 04:47:11 PM PDT 24 Jul 26 04:47:25 PM PDT 24 633039172 ps
T1116 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.791444195 Jul 26 04:46:59 PM PDT 24 Jul 26 04:47:01 PM PDT 24 62813790 ps
T1117 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.2301933238 Jul 26 04:47:21 PM PDT 24 Jul 26 04:47:23 PM PDT 24 139120066 ps
T1118 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.3780393111 Jul 26 04:46:59 PM PDT 24 Jul 26 04:47:00 PM PDT 24 31028112 ps
T1119 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.420146507 Jul 26 04:47:13 PM PDT 24 Jul 26 04:47:13 PM PDT 24 68678156 ps
T1120 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3029967636 Jul 26 04:46:49 PM PDT 24 Jul 26 04:46:49 PM PDT 24 17601574 ps
T1121 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.583129965 Jul 26 04:47:02 PM PDT 24 Jul 26 04:47:05 PM PDT 24 501589540 ps
T1122 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.833362163 Jul 26 04:47:34 PM PDT 24 Jul 26 04:47:45 PM PDT 24 11068380 ps
T1123 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.3274660930 Jul 26 04:47:01 PM PDT 24 Jul 26 04:47:02 PM PDT 24 11992596 ps
T1124 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2116061711 Jul 26 04:47:00 PM PDT 24 Jul 26 04:47:01 PM PDT 24 16097268 ps
T1125 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.527138686 Jul 26 04:47:16 PM PDT 24 Jul 26 04:47:17 PM PDT 24 51321371 ps
T1126 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2678637179 Jul 26 04:46:59 PM PDT 24 Jul 26 04:47:01 PM PDT 24 33912448 ps
T1127 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.3915102902 Jul 26 04:46:55 PM PDT 24 Jul 26 04:47:03 PM PDT 24 473166163 ps
T1128 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.2935347972 Jul 26 04:47:02 PM PDT 24 Jul 26 04:47:03 PM PDT 24 14330507 ps
T1129 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.3836187139 Jul 26 04:47:03 PM PDT 24 Jul 26 04:47:10 PM PDT 24 1096877810 ps
T1130 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.2536160347 Jul 26 04:46:49 PM PDT 24 Jul 26 04:47:04 PM PDT 24 3485065294 ps
T1131 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1951864226 Jul 26 04:46:58 PM PDT 24 Jul 26 04:46:59 PM PDT 24 69248692 ps
T1132 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.917690851 Jul 26 04:47:20 PM PDT 24 Jul 26 04:47:21 PM PDT 24 28263763 ps
T1133 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.1976635501 Jul 26 04:47:22 PM PDT 24 Jul 26 04:47:23 PM PDT 24 12178891 ps
T1134 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.3188358014 Jul 26 04:47:07 PM PDT 24 Jul 26 04:47:09 PM PDT 24 15021672 ps
T1135 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.732259217 Jul 26 04:46:47 PM PDT 24 Jul 26 04:46:48 PM PDT 24 213832152 ps
T1136 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.2955125260 Jul 26 04:47:07 PM PDT 24 Jul 26 04:47:10 PM PDT 24 391474223 ps
T1137 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.4095935321 Jul 26 04:47:07 PM PDT 24 Jul 26 04:47:07 PM PDT 24 17859021 ps
T1138 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3168827602 Jul 26 04:47:01 PM PDT 24 Jul 26 04:47:07 PM PDT 24 240906728 ps
T1139 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.1212903906 Jul 26 04:47:14 PM PDT 24 Jul 26 04:47:15 PM PDT 24 19498508 ps
T1140 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1833421663 Jul 26 04:47:11 PM PDT 24 Jul 26 04:47:31 PM PDT 24 1460534360 ps
T1141 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.4081964931 Jul 26 04:46:54 PM PDT 24 Jul 26 04:46:55 PM PDT 24 52859352 ps
T1142 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1919629142 Jul 26 04:47:14 PM PDT 24 Jul 26 04:47:16 PM PDT 24 72912441 ps
T1143 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.3942034325 Jul 26 04:46:52 PM PDT 24 Jul 26 04:46:53 PM PDT 24 38933143 ps
T1144 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.4268459649 Jul 26 04:46:52 PM PDT 24 Jul 26 04:46:54 PM PDT 24 400169279 ps
T1145 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.1249021640 Jul 26 04:47:05 PM PDT 24 Jul 26 04:47:06 PM PDT 24 47178688 ps
T1146 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3805234618 Jul 26 04:46:59 PM PDT 24 Jul 26 04:47:25 PM PDT 24 6469014740 ps
T1147 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3519008795 Jul 26 04:47:00 PM PDT 24 Jul 26 04:47:02 PM PDT 24 289287955 ps
T1148 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.1265841612 Jul 26 04:47:03 PM PDT 24 Jul 26 04:47:05 PM PDT 24 120828137 ps
T1149 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.1726444673 Jul 26 04:47:04 PM PDT 24 Jul 26 04:47:05 PM PDT 24 14614928 ps
T1150 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2089598938 Jul 26 04:47:10 PM PDT 24 Jul 26 04:47:13 PM PDT 24 180572332 ps
T1151 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3279337968 Jul 26 04:47:20 PM PDT 24 Jul 26 04:47:24 PM PDT 24 574020668 ps

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.4246020818
Short name T8
Test name
Test status
Simulation time 15299878513 ps
CPU time 145.57 seconds
Started Jul 26 04:54:31 PM PDT 24
Finished Jul 26 04:56:57 PM PDT 24
Peak memory 249952 kb
Host smart-5ae4ae55-63a8-4934-b5a9-4ad56474eec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246020818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.4246020818
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.2181742209
Short name T14
Test name
Test status
Simulation time 146925762988 ps
CPU time 344.12 seconds
Started Jul 26 04:54:14 PM PDT 24
Finished Jul 26 04:59:59 PM PDT 24
Peak memory 267228 kb
Host smart-2131fc12-a179-457f-9542-959f850d2c6a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181742209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.2181742209
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.378892910
Short name T17
Test name
Test status
Simulation time 324131415413 ps
CPU time 1038.38 seconds
Started Jul 26 04:53:48 PM PDT 24
Finished Jul 26 05:11:07 PM PDT 24
Peak memory 289688 kb
Host smart-7c1cabeb-2408-46cc-b521-4b7399dc38e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378892910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stres
s_all.378892910
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.229036929
Short name T92
Test name
Test status
Simulation time 113663502 ps
CPU time 1.75 seconds
Started Jul 26 04:46:52 PM PDT 24
Finished Jul 26 04:46:54 PM PDT 24
Peak memory 216992 kb
Host smart-e8153f84-f828-47da-ba1e-9bd859cbf7b6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229036929 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.229036929
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.391935246
Short name T7
Test name
Test status
Simulation time 164790125096 ps
CPU time 393.79 seconds
Started Jul 26 04:52:32 PM PDT 24
Finished Jul 26 04:59:06 PM PDT 24
Peak memory 255884 kb
Host smart-43129b70-1ccd-41bb-bfe0-1c91004ae016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391935246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle.
391935246
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.690943377
Short name T18
Test name
Test status
Simulation time 22288899718 ps
CPU time 142.62 seconds
Started Jul 26 04:53:48 PM PDT 24
Finished Jul 26 04:56:11 PM PDT 24
Peak memory 256476 kb
Host smart-0ca646d0-2b82-4956-b062-1aa9159f2652
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690943377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stres
s_all.690943377
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.3110292217
Short name T59
Test name
Test status
Simulation time 16891720 ps
CPU time 0.79 seconds
Started Jul 26 04:52:00 PM PDT 24
Finished Jul 26 04:52:01 PM PDT 24
Peak memory 216684 kb
Host smart-ac1f4b0b-d3db-45c4-ab49-a81c6e080b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110292217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.3110292217
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.3604778081
Short name T15
Test name
Test status
Simulation time 19232059913 ps
CPU time 158.62 seconds
Started Jul 26 04:51:55 PM PDT 24
Finished Jul 26 04:54:34 PM PDT 24
Peak memory 258148 kb
Host smart-9ac253ad-a4e4-486a-a41c-b8cf3ee67d02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604778081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.3604778081
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.3449149541
Short name T46
Test name
Test status
Simulation time 118095365445 ps
CPU time 614.18 seconds
Started Jul 26 04:54:30 PM PDT 24
Finished Jul 26 05:04:44 PM PDT 24
Peak memory 266020 kb
Host smart-0bf06a1f-f1db-41d7-852b-725a57aa664f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449149541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.3449149541
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.2376399809
Short name T61
Test name
Test status
Simulation time 112281963 ps
CPU time 1.05 seconds
Started Jul 26 04:52:04 PM PDT 24
Finished Jul 26 04:52:05 PM PDT 24
Peak memory 236180 kb
Host smart-c579fccd-4cc0-4842-9f25-25236bc83847
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376399809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.2376399809
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.2339029480
Short name T157
Test name
Test status
Simulation time 122716608163 ps
CPU time 411.98 seconds
Started Jul 26 04:53:37 PM PDT 24
Finished Jul 26 05:00:29 PM PDT 24
Peak memory 257400 kb
Host smart-54803ad4-2f57-46e3-9562-65e2595e3e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339029480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.2339029480
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.4268685753
Short name T73
Test name
Test status
Simulation time 12755381354 ps
CPU time 88.1 seconds
Started Jul 26 04:54:42 PM PDT 24
Finished Jul 26 04:56:11 PM PDT 24
Peak memory 252972 kb
Host smart-d3328a86-b3bf-47f8-986c-ca478b8fea57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268685753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.4268685753
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.397047767
Short name T143
Test name
Test status
Simulation time 750086916 ps
CPU time 8.29 seconds
Started Jul 26 04:53:16 PM PDT 24
Finished Jul 26 04:53:25 PM PDT 24
Peak memory 241600 kb
Host smart-7fa5d044-bf8e-4b50-a282-1e2e71723d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397047767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.397047767
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.1986156735
Short name T155
Test name
Test status
Simulation time 19636408168 ps
CPU time 279.76 seconds
Started Jul 26 04:52:42 PM PDT 24
Finished Jul 26 04:57:23 PM PDT 24
Peak memory 281044 kb
Host smart-8cd8e369-799e-4ed7-bef3-0c3790a68b4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986156735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.1986156735
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2703686310
Short name T100
Test name
Test status
Simulation time 244339438 ps
CPU time 4.77 seconds
Started Jul 26 04:47:02 PM PDT 24
Finished Jul 26 04:47:07 PM PDT 24
Peak memory 216084 kb
Host smart-c68ab88f-d2d5-48d5-88ea-e58272c8096a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703686310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.2
703686310
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.378431598
Short name T43
Test name
Test status
Simulation time 67016140841 ps
CPU time 515.64 seconds
Started Jul 26 04:51:56 PM PDT 24
Finished Jul 26 05:00:31 PM PDT 24
Peak memory 256896 kb
Host smart-ea7426a9-b001-4efd-bc4a-81855a893719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378431598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle.
378431598
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.4231032102
Short name T165
Test name
Test status
Simulation time 2803408901 ps
CPU time 18.45 seconds
Started Jul 26 04:46:58 PM PDT 24
Finished Jul 26 04:47:17 PM PDT 24
Peak memory 216080 kb
Host smart-0cf3468b-c388-4de2-af2f-2fea1625f413
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231032102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.4231032102
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.3769989957
Short name T66
Test name
Test status
Simulation time 103888124694 ps
CPU time 294.77 seconds
Started Jul 26 04:52:06 PM PDT 24
Finished Jul 26 04:57:01 PM PDT 24
Peak memory 257184 kb
Host smart-dba595f5-c5a7-4640-880a-9bd9d95ea344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769989957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.3769989957
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.2772369103
Short name T114
Test name
Test status
Simulation time 808587148 ps
CPU time 13.53 seconds
Started Jul 26 04:46:45 PM PDT 24
Finished Jul 26 04:46:59 PM PDT 24
Peak memory 207668 kb
Host smart-207ad6b5-cb8d-4e94-89e3-65910361e32c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772369103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.2772369103
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.3482410427
Short name T150
Test name
Test status
Simulation time 899420808997 ps
CPU time 823.38 seconds
Started Jul 26 04:53:22 PM PDT 24
Finished Jul 26 05:07:05 PM PDT 24
Peak memory 270744 kb
Host smart-9f89d661-575a-4dea-83e9-8280079cae2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482410427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.3482410427
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.46880563
Short name T44
Test name
Test status
Simulation time 20494982504 ps
CPU time 203.35 seconds
Started Jul 26 04:53:45 PM PDT 24
Finished Jul 26 04:57:08 PM PDT 24
Peak memory 268832 kb
Host smart-f612b154-1288-4dc3-9f3a-8b0acff5584e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46880563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.46880563
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.1391369289
Short name T35
Test name
Test status
Simulation time 15508611 ps
CPU time 1.03 seconds
Started Jul 26 04:51:57 PM PDT 24
Finished Jul 26 04:51:58 PM PDT 24
Peak memory 217268 kb
Host smart-f54919d1-4368-4077-acbf-281f5491d23c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391369289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.spi_device_mem_parity.1391369289
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.2871967622
Short name T37
Test name
Test status
Simulation time 103028198038 ps
CPU time 274.32 seconds
Started Jul 26 04:52:41 PM PDT 24
Finished Jul 26 04:57:16 PM PDT 24
Peak memory 253128 kb
Host smart-2eb2961f-59f7-4d3a-8a8f-f4a1339d70e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871967622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.2871967622
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.3944698148
Short name T30
Test name
Test status
Simulation time 13881244030 ps
CPU time 151.09 seconds
Started Jul 26 04:52:47 PM PDT 24
Finished Jul 26 04:55:18 PM PDT 24
Peak memory 253748 kb
Host smart-d4ea11aa-1ce2-41ae-85b2-5beeddafd217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944698148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.3944698148
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.2206398169
Short name T40
Test name
Test status
Simulation time 8669770467 ps
CPU time 25.61 seconds
Started Jul 26 04:53:24 PM PDT 24
Finished Jul 26 04:53:50 PM PDT 24
Peak memory 249932 kb
Host smart-bf7836e8-7330-4b4d-8fbf-9091fa0dcfd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206398169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmd
s.2206398169
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.2636248609
Short name T11
Test name
Test status
Simulation time 57902097042 ps
CPU time 277.93 seconds
Started Jul 26 04:52:51 PM PDT 24
Finished Jul 26 04:57:29 PM PDT 24
Peak memory 255964 kb
Host smart-79c5aa20-7e55-4a4c-b326-c5ce63fca40b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636248609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.2636248609
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.3426579086
Short name T232
Test name
Test status
Simulation time 46722384200 ps
CPU time 409.34 seconds
Started Jul 26 04:52:23 PM PDT 24
Finished Jul 26 04:59:12 PM PDT 24
Peak memory 256700 kb
Host smart-746eb539-976f-40e0-8f3c-f69ee78d58ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426579086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.3426579086
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.227165772
Short name T404
Test name
Test status
Simulation time 27199832 ps
CPU time 0.69 seconds
Started Jul 26 04:52:40 PM PDT 24
Finished Jul 26 04:52:41 PM PDT 24
Peak memory 205932 kb
Host smart-ae7ebfb8-a017-4382-a126-33c80750cf4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227165772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.227165772
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.4062128718
Short name T199
Test name
Test status
Simulation time 110313999731 ps
CPU time 310.65 seconds
Started Jul 26 04:53:25 PM PDT 24
Finished Jul 26 04:58:36 PM PDT 24
Peak memory 257676 kb
Host smart-cc80bda6-a146-42c6-8b8b-72e7ff483b9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062128718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.4062128718
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.1487924170
Short name T173
Test name
Test status
Simulation time 13854011502 ps
CPU time 63.09 seconds
Started Jul 26 04:54:25 PM PDT 24
Finished Jul 26 04:55:28 PM PDT 24
Peak memory 254132 kb
Host smart-ad09cc7b-cb04-4ea0-8511-e150d8484ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487924170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmd
s.1487924170
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.275070086
Short name T895
Test name
Test status
Simulation time 50175397995 ps
CPU time 185.04 seconds
Started Jul 26 04:53:19 PM PDT 24
Finished Jul 26 04:56:24 PM PDT 24
Peak memory 274632 kb
Host smart-5ab50b1b-2d19-4fca-a0b0-2866751a47cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275070086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idle
.275070086
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1007929932
Short name T97
Test name
Test status
Simulation time 743076959 ps
CPU time 8.97 seconds
Started Jul 26 04:47:05 PM PDT 24
Finished Jul 26 04:47:14 PM PDT 24
Peak memory 216544 kb
Host smart-24d0a4a6-50e6-44fa-824e-84633078aaee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007929932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.1007929932
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.2326320550
Short name T288
Test name
Test status
Simulation time 33811247390 ps
CPU time 299.22 seconds
Started Jul 26 04:53:03 PM PDT 24
Finished Jul 26 04:58:03 PM PDT 24
Peak memory 272444 kb
Host smart-dab7aa6e-257b-43fb-8a6f-9dac470850d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326320550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmd
s.2326320550
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.4065312617
Short name T282
Test name
Test status
Simulation time 18887568778 ps
CPU time 174.49 seconds
Started Jul 26 04:53:37 PM PDT 24
Finished Jul 26 04:56:32 PM PDT 24
Peak memory 249572 kb
Host smart-c61ee4c0-850b-4794-9d19-801295293b7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065312617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.4065312617
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.1956636873
Short name T205
Test name
Test status
Simulation time 65392040184 ps
CPU time 455.97 seconds
Started Jul 26 04:52:12 PM PDT 24
Finished Jul 26 04:59:48 PM PDT 24
Peak memory 272924 kb
Host smart-d9f65424-7548-4036-9f4c-73ff9d87a694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956636873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds
.1956636873
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1566842134
Short name T169
Test name
Test status
Simulation time 1179604613 ps
CPU time 17.84 seconds
Started Jul 26 04:47:10 PM PDT 24
Finished Jul 26 04:47:28 PM PDT 24
Peak memory 215912 kb
Host smart-2b098005-3a7c-4cee-a25c-11a47bbc2adc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566842134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.1566842134
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.2828694389
Short name T340
Test name
Test status
Simulation time 6346395632 ps
CPU time 36.13 seconds
Started Jul 26 04:52:44 PM PDT 24
Finished Jul 26 04:53:20 PM PDT 24
Peak memory 217040 kb
Host smart-d4a2d1bb-0b82-43b0-8cd0-f1d84dcd9297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828694389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.2828694389
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.836793112
Short name T109
Test name
Test status
Simulation time 1632604147 ps
CPU time 13.64 seconds
Started Jul 26 04:53:24 PM PDT 24
Finished Jul 26 04:53:38 PM PDT 24
Peak memory 241700 kb
Host smart-2796797e-5120-4539-a774-ec2157c76a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836793112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.836793112
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.975227404
Short name T285
Test name
Test status
Simulation time 52784374857 ps
CPU time 343.52 seconds
Started Jul 26 04:53:43 PM PDT 24
Finished Jul 26 04:59:27 PM PDT 24
Peak memory 273732 kb
Host smart-d46b3333-0b74-4228-bc31-143b2fdf1179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975227404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idle
.975227404
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.53704291
Short name T307
Test name
Test status
Simulation time 44585825842 ps
CPU time 143.03 seconds
Started Jul 26 04:53:43 PM PDT 24
Finished Jul 26 04:56:07 PM PDT 24
Peak memory 250140 kb
Host smart-71025b63-2da2-4124-842e-85bf5b84b7da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53704291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stress
_all.53704291
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.2799760153
Short name T397
Test name
Test status
Simulation time 175114942 ps
CPU time 5.13 seconds
Started Jul 26 04:54:19 PM PDT 24
Finished Jul 26 04:54:24 PM PDT 24
Peak memory 225284 kb
Host smart-b21ff4aa-623a-4b02-9932-31702ff0684b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799760153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.2799760153
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1371349139
Short name T104
Test name
Test status
Simulation time 670660932 ps
CPU time 4.75 seconds
Started Jul 26 04:47:02 PM PDT 24
Finished Jul 26 04:47:07 PM PDT 24
Peak memory 216376 kb
Host smart-a4b59471-4202-4626-802a-fe3fa1232885
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371349139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
1371349139
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.3758410474
Short name T163
Test name
Test status
Simulation time 1120235006 ps
CPU time 7.41 seconds
Started Jul 26 04:46:55 PM PDT 24
Finished Jul 26 04:47:08 PM PDT 24
Peak memory 216128 kb
Host smart-d16cad1e-ee04-4360-bf09-2ea80a146000
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758410474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.3758410474
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1049429291
Short name T161
Test name
Test status
Simulation time 194811385 ps
CPU time 6.33 seconds
Started Jul 26 04:47:02 PM PDT 24
Finished Jul 26 04:47:09 PM PDT 24
Peak memory 215928 kb
Host smart-3ba5158e-f5e1-4a82-afb9-bf1a1787ac39
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049429291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.1049429291
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.875792864
Short name T269
Test name
Test status
Simulation time 10824062308 ps
CPU time 41.85 seconds
Started Jul 26 04:52:42 PM PDT 24
Finished Jul 26 04:53:24 PM PDT 24
Peak memory 233696 kb
Host smart-55146dc9-51ec-417b-9390-0cc63d1b26b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875792864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.875792864
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.3946511336
Short name T294
Test name
Test status
Simulation time 537221343 ps
CPU time 9.74 seconds
Started Jul 26 04:52:53 PM PDT 24
Finished Jul 26 04:53:03 PM PDT 24
Peak memory 225236 kb
Host smart-953177a4-affe-4a39-89a0-4666199e5c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946511336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.3946511336
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.875075733
Short name T233
Test name
Test status
Simulation time 68120586296 ps
CPU time 80.66 seconds
Started Jul 26 04:53:03 PM PDT 24
Finished Jul 26 04:54:24 PM PDT 24
Peak memory 249988 kb
Host smart-89650d83-f0b5-4be6-9d64-8b1d70d760e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875075733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idle
.875075733
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.1198478859
Short name T196
Test name
Test status
Simulation time 8715717321 ps
CPU time 127.04 seconds
Started Jul 26 04:53:21 PM PDT 24
Finished Jul 26 04:55:28 PM PDT 24
Peak memory 265904 kb
Host smart-6a776fcb-6624-4374-8ea7-402c0d659b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198478859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.1198478859
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.1801875150
Short name T283
Test name
Test status
Simulation time 31172144747 ps
CPU time 76.56 seconds
Started Jul 26 04:53:41 PM PDT 24
Finished Jul 26 04:54:57 PM PDT 24
Peak memory 274240 kb
Host smart-7f1405b5-4f80-423b-a0f6-ed9ac8099be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801875150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.1801875150
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.1282553802
Short name T272
Test name
Test status
Simulation time 26825926833 ps
CPU time 148.26 seconds
Started Jul 26 04:53:47 PM PDT 24
Finished Jul 26 04:56:16 PM PDT 24
Peak memory 274160 kb
Host smart-e5da6ba1-89f2-45b9-847c-607b478997ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282553802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.1282553802
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.2064274008
Short name T709
Test name
Test status
Simulation time 265068868 ps
CPU time 5.3 seconds
Started Jul 26 04:52:46 PM PDT 24
Finished Jul 26 04:52:51 PM PDT 24
Peak memory 225280 kb
Host smart-617a7a58-32a7-4d94-8e84-bf2a18117469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064274008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.2064274008
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.2266137661
Short name T248
Test name
Test status
Simulation time 613791001 ps
CPU time 4.85 seconds
Started Jul 26 04:53:02 PM PDT 24
Finished Jul 26 04:53:07 PM PDT 24
Peak memory 225380 kb
Host smart-f4fbe317-fc3f-49fe-9d16-4d377c3729d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266137661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.2266137661
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.962615549
Short name T75
Test name
Test status
Simulation time 30007616 ps
CPU time 1.19 seconds
Started Jul 26 04:46:54 PM PDT 24
Finished Jul 26 04:47:00 PM PDT 24
Peak memory 216960 kb
Host smart-f09d0532-177d-444a-9d22-38f1299cc8a5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962615549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_hw_reset.962615549
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1273168268
Short name T121
Test name
Test status
Simulation time 6916759935 ps
CPU time 25.87 seconds
Started Jul 26 04:46:32 PM PDT 24
Finished Jul 26 04:46:58 PM PDT 24
Peak memory 216020 kb
Host smart-c64c6fd1-6ace-4278-8aaa-e03d07f4ad67
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273168268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.1273168268
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.732259217
Short name T1135
Test name
Test status
Simulation time 213832152 ps
CPU time 1.59 seconds
Started Jul 26 04:46:47 PM PDT 24
Finished Jul 26 04:46:48 PM PDT 24
Peak memory 216096 kb
Host smart-aa7ce0ab-66b7-471c-93e8-acd8992fee13
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732259217 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.732259217
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2631772145
Short name T111
Test name
Test status
Simulation time 137584328 ps
CPU time 2.26 seconds
Started Jul 26 04:46:47 PM PDT 24
Finished Jul 26 04:46:54 PM PDT 24
Peak memory 215936 kb
Host smart-a6a7074f-7d2b-479d-b0fc-ff2e27d89cbf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631772145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.2
631772145
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2116061711
Short name T1124
Test name
Test status
Simulation time 16097268 ps
CPU time 0.71 seconds
Started Jul 26 04:47:00 PM PDT 24
Finished Jul 26 04:47:01 PM PDT 24
Peak memory 204540 kb
Host smart-1117a543-95f0-4bed-aaa0-fcb09a819fcc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116061711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.2
116061711
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.870806038
Short name T116
Test name
Test status
Simulation time 32290284 ps
CPU time 1.44 seconds
Started Jul 26 04:46:46 PM PDT 24
Finished Jul 26 04:46:47 PM PDT 24
Peak memory 215900 kb
Host smart-f8dd9c08-5298-4103-95f5-47aefe1ccff8
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870806038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_
device_mem_partial_access.870806038
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.681532660
Short name T1112
Test name
Test status
Simulation time 12861898 ps
CPU time 0.72 seconds
Started Jul 26 04:46:45 PM PDT 24
Finished Jul 26 04:46:46 PM PDT 24
Peak memory 203436 kb
Host smart-f47abd7d-cb73-407d-bc7a-78236153bfb7
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681532660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_mem
_walk.681532660
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.2210554453
Short name T1087
Test name
Test status
Simulation time 152644320 ps
CPU time 3.19 seconds
Started Jul 26 04:46:48 PM PDT 24
Finished Jul 26 04:46:51 PM PDT 24
Peak memory 215936 kb
Host smart-e682d95d-ffbe-457e-b1f4-a70b8789c3f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210554453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.2210554453
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.1856320493
Short name T103
Test name
Test status
Simulation time 25252362 ps
CPU time 1.71 seconds
Started Jul 26 04:46:56 PM PDT 24
Finished Jul 26 04:46:58 PM PDT 24
Peak memory 216140 kb
Host smart-7ed4ee01-06cd-4e57-a56f-03e9e0a58bed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856320493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.1
856320493
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.2783322549
Short name T168
Test name
Test status
Simulation time 261763063 ps
CPU time 6.98 seconds
Started Jul 26 04:46:51 PM PDT 24
Finished Jul 26 04:46:58 PM PDT 24
Peak memory 216184 kb
Host smart-74084c3d-b9e0-44b1-96f0-c0e20c88b687
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783322549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.2783322549
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.761656534
Short name T124
Test name
Test status
Simulation time 1233596063 ps
CPU time 21.82 seconds
Started Jul 26 04:47:03 PM PDT 24
Finished Jul 26 04:47:25 PM PDT 24
Peak memory 215908 kb
Host smart-f2d91a0b-9a66-40a2-abe9-95726e883700
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761656534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_aliasing.761656534
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2845463993
Short name T123
Test name
Test status
Simulation time 8229956812 ps
CPU time 25.94 seconds
Started Jul 26 04:46:40 PM PDT 24
Finished Jul 26 04:47:06 PM PDT 24
Peak memory 207840 kb
Host smart-54741d51-765b-4719-9772-8a5c410479ae
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845463993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.2845463993
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.1577126699
Short name T77
Test name
Test status
Simulation time 20464761 ps
CPU time 1.18 seconds
Started Jul 26 04:46:55 PM PDT 24
Finished Jul 26 04:46:56 PM PDT 24
Peak memory 217916 kb
Host smart-c2f0330e-0470-4614-9d05-850eafa7fd6c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577126699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.1577126699
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3972109987
Short name T149
Test name
Test status
Simulation time 581417233 ps
CPU time 3.69 seconds
Started Jul 26 04:46:55 PM PDT 24
Finished Jul 26 04:46:59 PM PDT 24
Peak memory 217624 kb
Host smart-92d66ddd-4d2c-4ec9-86fe-b969b3c1cc14
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972109987 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.3972109987
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.1018447680
Short name T137
Test name
Test status
Simulation time 92931022 ps
CPU time 2.57 seconds
Started Jul 26 04:46:42 PM PDT 24
Finished Jul 26 04:46:45 PM PDT 24
Peak memory 215836 kb
Host smart-7b0e8482-b50a-4395-ba67-fc0f06c22ae4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018447680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.1
018447680
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3029967636
Short name T1120
Test name
Test status
Simulation time 17601574 ps
CPU time 0.71 seconds
Started Jul 26 04:46:49 PM PDT 24
Finished Jul 26 04:46:49 PM PDT 24
Peak memory 204696 kb
Host smart-f5d1acef-ea46-426a-a5b1-4beb92409c80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029967636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.3
029967636
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.1083047354
Short name T119
Test name
Test status
Simulation time 235049785 ps
CPU time 1.77 seconds
Started Jul 26 04:46:44 PM PDT 24
Finished Jul 26 04:46:46 PM PDT 24
Peak memory 215840 kb
Host smart-41374ed8-9f1f-4020-81b3-ceca10163824
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083047354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.1083047354
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.923973937
Short name T1043
Test name
Test status
Simulation time 30835496 ps
CPU time 0.66 seconds
Started Jul 26 04:46:51 PM PDT 24
Finished Jul 26 04:46:52 PM PDT 24
Peak memory 204124 kb
Host smart-e0d7ab02-128e-4b31-afdd-4c141097a69d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923973937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem
_walk.923973937
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.593365821
Short name T1097
Test name
Test status
Simulation time 100034910 ps
CPU time 1.73 seconds
Started Jul 26 04:46:59 PM PDT 24
Finished Jul 26 04:47:01 PM PDT 24
Peak memory 207716 kb
Host smart-56610357-1285-4cb7-aee6-210a16aa66e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593365821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sp
i_device_same_csr_outstanding.593365821
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.2162428359
Short name T1105
Test name
Test status
Simulation time 167346218 ps
CPU time 1.41 seconds
Started Jul 26 04:47:05 PM PDT 24
Finished Jul 26 04:47:06 PM PDT 24
Peak memory 216136 kb
Host smart-87dbe7f7-73d6-4f57-958d-a35c6c54f71f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162428359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.2
162428359
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.3915102902
Short name T1127
Test name
Test status
Simulation time 473166163 ps
CPU time 7.59 seconds
Started Jul 26 04:46:55 PM PDT 24
Finished Jul 26 04:47:03 PM PDT 24
Peak memory 216260 kb
Host smart-8acaf6e8-423d-464f-a2d1-62e58cce14e5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915102902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.3915102902
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2160269385
Short name T1080
Test name
Test status
Simulation time 102381635 ps
CPU time 1.8 seconds
Started Jul 26 04:47:04 PM PDT 24
Finished Jul 26 04:47:06 PM PDT 24
Peak memory 216952 kb
Host smart-e31ebe0f-13f9-4838-ac40-66faac812abc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160269385 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.2160269385
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.1552664577
Short name T1040
Test name
Test status
Simulation time 71755412 ps
CPU time 2.09 seconds
Started Jul 26 04:46:50 PM PDT 24
Finished Jul 26 04:46:52 PM PDT 24
Peak memory 215772 kb
Host smart-5b79391d-b74e-49e0-8674-e752ed5c904e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552664577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
1552664577
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.3780393111
Short name T1118
Test name
Test status
Simulation time 31028112 ps
CPU time 0.72 seconds
Started Jul 26 04:46:59 PM PDT 24
Finished Jul 26 04:47:00 PM PDT 24
Peak memory 204696 kb
Host smart-77570c4f-a4bd-43ef-96df-a9632ca82069
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780393111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
3780393111
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.3574194710
Short name T1042
Test name
Test status
Simulation time 62126295 ps
CPU time 1.85 seconds
Started Jul 26 04:47:09 PM PDT 24
Finished Jul 26 04:47:11 PM PDT 24
Peak memory 215788 kb
Host smart-28fa4320-2b6d-44bf-85e4-376cf9936d33
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574194710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.3574194710
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.330102713
Short name T108
Test name
Test status
Simulation time 38178567 ps
CPU time 1.66 seconds
Started Jul 26 04:47:13 PM PDT 24
Finished Jul 26 04:47:20 PM PDT 24
Peak memory 216000 kb
Host smart-107bc45d-6ea0-4a05-b11b-c2d5a2b06ff1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330102713 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.330102713
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.1160391152
Short name T136
Test name
Test status
Simulation time 42709189 ps
CPU time 1.29 seconds
Started Jul 26 04:47:15 PM PDT 24
Finished Jul 26 04:47:17 PM PDT 24
Peak memory 207728 kb
Host smart-d119dd4a-134f-4d3a-8cfb-7c525e135593
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160391152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
1160391152
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.2857425271
Short name T1036
Test name
Test status
Simulation time 43113686 ps
CPU time 0.67 seconds
Started Jul 26 04:47:20 PM PDT 24
Finished Jul 26 04:47:21 PM PDT 24
Peak memory 204296 kb
Host smart-dd38521d-59f8-4955-b365-c46aefe4f61f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857425271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
2857425271
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.4043971414
Short name T1074
Test name
Test status
Simulation time 42221297 ps
CPU time 2.81 seconds
Started Jul 26 04:47:00 PM PDT 24
Finished Jul 26 04:47:02 PM PDT 24
Peak memory 215824 kb
Host smart-de1ae62a-4841-44a3-9fe2-fd48cbd74a98
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043971414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.4043971414
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.819619781
Short name T96
Test name
Test status
Simulation time 37580517 ps
CPU time 1.37 seconds
Started Jul 26 04:47:10 PM PDT 24
Finished Jul 26 04:47:12 PM PDT 24
Peak memory 216044 kb
Host smart-028208ce-1402-4158-b9df-bf2586ff92f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819619781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.819619781
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2995087514
Short name T166
Test name
Test status
Simulation time 548699683 ps
CPU time 14.43 seconds
Started Jul 26 04:46:57 PM PDT 24
Finished Jul 26 04:47:12 PM PDT 24
Peak memory 215860 kb
Host smart-ae1205da-453a-43e2-b0fc-c605762e91e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995087514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.2995087514
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3885711355
Short name T93
Test name
Test status
Simulation time 24646039 ps
CPU time 1.58 seconds
Started Jul 26 04:46:56 PM PDT 24
Finished Jul 26 04:46:58 PM PDT 24
Peak memory 215968 kb
Host smart-47e556e1-c812-4268-9d97-3d07366ee63a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885711355 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.3885711355
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.1935403232
Short name T112
Test name
Test status
Simulation time 225226981 ps
CPU time 1.93 seconds
Started Jul 26 04:47:03 PM PDT 24
Finished Jul 26 04:47:05 PM PDT 24
Peak memory 207668 kb
Host smart-927c4d83-f684-4779-8e20-39d585b96404
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935403232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
1935403232
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.200893998
Short name T1060
Test name
Test status
Simulation time 12901404 ps
CPU time 0.71 seconds
Started Jul 26 04:47:02 PM PDT 24
Finished Jul 26 04:47:03 PM PDT 24
Peak memory 204464 kb
Host smart-7e4ba7fb-1b2b-4829-a1b7-a6f91932d7ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200893998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.200893998
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1919629142
Short name T1142
Test name
Test status
Simulation time 72912441 ps
CPU time 1.8 seconds
Started Jul 26 04:47:14 PM PDT 24
Finished Jul 26 04:47:16 PM PDT 24
Peak memory 215916 kb
Host smart-91348011-27cf-49d0-a779-8b76aaad587d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919629142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.1919629142
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.2403698665
Short name T105
Test name
Test status
Simulation time 25549671 ps
CPU time 1.6 seconds
Started Jul 26 04:47:13 PM PDT 24
Finished Jul 26 04:47:15 PM PDT 24
Peak memory 216208 kb
Host smart-d7258b36-6b87-4c10-9491-5d88ee0086e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403698665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
2403698665
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.1851765614
Short name T1104
Test name
Test status
Simulation time 702207927 ps
CPU time 16.78 seconds
Started Jul 26 04:47:03 PM PDT 24
Finished Jul 26 04:47:20 PM PDT 24
Peak memory 216000 kb
Host smart-0741a707-1b6a-46c9-ba95-0b96413543f5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851765614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.1851765614
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.596462852
Short name T1066
Test name
Test status
Simulation time 69978988 ps
CPU time 2.53 seconds
Started Jul 26 04:47:08 PM PDT 24
Finished Jul 26 04:47:11 PM PDT 24
Peak memory 217040 kb
Host smart-20729f5f-b783-4085-9235-11cfadcc4e9e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596462852 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.596462852
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.913940379
Short name T118
Test name
Test status
Simulation time 80590519 ps
CPU time 2.04 seconds
Started Jul 26 04:46:59 PM PDT 24
Finished Jul 26 04:47:01 PM PDT 24
Peak memory 207708 kb
Host smart-20fa31b7-a244-4ae5-8a1d-81028081ff73
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913940379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.913940379
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3214975793
Short name T1046
Test name
Test status
Simulation time 88097551 ps
CPU time 0.74 seconds
Started Jul 26 04:47:03 PM PDT 24
Finished Jul 26 04:47:04 PM PDT 24
Peak memory 204368 kb
Host smart-33e67d79-aa8d-4f07-91eb-f1afa341a557
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214975793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
3214975793
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3737551790
Short name T1077
Test name
Test status
Simulation time 503332915 ps
CPU time 2.11 seconds
Started Jul 26 04:47:17 PM PDT 24
Finished Jul 26 04:47:20 PM PDT 24
Peak memory 215788 kb
Host smart-eb2f4ae0-f169-4d20-a9c9-c3410ae52a83
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737551790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.3737551790
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.4136409836
Short name T1065
Test name
Test status
Simulation time 99177777 ps
CPU time 1.67 seconds
Started Jul 26 04:47:19 PM PDT 24
Finished Jul 26 04:47:21 PM PDT 24
Peak memory 216012 kb
Host smart-0080d381-db27-4d8a-a430-a3b923a754bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136409836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
4136409836
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.840319602
Short name T170
Test name
Test status
Simulation time 633039172 ps
CPU time 13.29 seconds
Started Jul 26 04:47:11 PM PDT 24
Finished Jul 26 04:47:25 PM PDT 24
Peak memory 215948 kb
Host smart-6796400a-e47d-454f-a187-647b66c1de8c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840319602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device
_tl_intg_err.840319602
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.1127068741
Short name T1045
Test name
Test status
Simulation time 41283626 ps
CPU time 1.65 seconds
Started Jul 26 04:47:05 PM PDT 24
Finished Jul 26 04:47:06 PM PDT 24
Peak memory 215912 kb
Host smart-918aa598-c47d-421e-bd53-2b3df9b70e98
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127068741 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.1127068741
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1721194209
Short name T115
Test name
Test status
Simulation time 56039411 ps
CPU time 1.88 seconds
Started Jul 26 04:47:10 PM PDT 24
Finished Jul 26 04:47:12 PM PDT 24
Peak memory 215804 kb
Host smart-705dfa2c-41cd-47df-9edd-debc473d7b85
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721194209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
1721194209
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.3274660930
Short name T1123
Test name
Test status
Simulation time 11992596 ps
CPU time 0.73 seconds
Started Jul 26 04:47:01 PM PDT 24
Finished Jul 26 04:47:02 PM PDT 24
Peak memory 204660 kb
Host smart-48767411-d2e7-470e-961e-b352424dbf5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274660930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
3274660930
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2089598938
Short name T1150
Test name
Test status
Simulation time 180572332 ps
CPU time 2.73 seconds
Started Jul 26 04:47:10 PM PDT 24
Finished Jul 26 04:47:13 PM PDT 24
Peak memory 215912 kb
Host smart-c0ac50f0-ae4e-4de7-ac8d-9bbf3bb6d73c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089598938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.2089598938
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.4029279981
Short name T1089
Test name
Test status
Simulation time 312946948 ps
CPU time 2.95 seconds
Started Jul 26 04:47:17 PM PDT 24
Finished Jul 26 04:47:20 PM PDT 24
Peak memory 216140 kb
Host smart-a2e6941b-b6c3-465a-8b52-af520b6def4f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029279981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
4029279981
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.643127067
Short name T167
Test name
Test status
Simulation time 584529382 ps
CPU time 8.44 seconds
Started Jul 26 04:47:00 PM PDT 24
Finished Jul 26 04:47:09 PM PDT 24
Peak memory 215956 kb
Host smart-8d9cac7a-53a8-4d9b-8cba-9f6ab387dc8b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643127067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device
_tl_intg_err.643127067
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1899922779
Short name T1086
Test name
Test status
Simulation time 318675870 ps
CPU time 2.6 seconds
Started Jul 26 04:46:53 PM PDT 24
Finished Jul 26 04:46:56 PM PDT 24
Peak memory 216940 kb
Host smart-80d559c8-be99-4b34-bfb8-1d0881359de3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899922779 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.1899922779
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.1265841612
Short name T1148
Test name
Test status
Simulation time 120828137 ps
CPU time 2.48 seconds
Started Jul 26 04:47:03 PM PDT 24
Finished Jul 26 04:47:05 PM PDT 24
Peak memory 215896 kb
Host smart-15757cbb-ab90-4a2b-9846-c02dea69195c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265841612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
1265841612
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.1976635501
Short name T1133
Test name
Test status
Simulation time 12178891 ps
CPU time 0.76 seconds
Started Jul 26 04:47:22 PM PDT 24
Finished Jul 26 04:47:23 PM PDT 24
Peak memory 204368 kb
Host smart-3d231486-f6f8-4f6e-bfb1-0c10da182a2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976635501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
1976635501
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.4067908606
Short name T1037
Test name
Test status
Simulation time 54866207 ps
CPU time 1.93 seconds
Started Jul 26 04:47:06 PM PDT 24
Finished Jul 26 04:47:08 PM PDT 24
Peak memory 215824 kb
Host smart-c7d3f404-fa31-4ef6-ad57-16cb6142c72e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067908606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.4067908606
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.3425854091
Short name T1081
Test name
Test status
Simulation time 61366709 ps
CPU time 1.76 seconds
Started Jul 26 04:47:15 PM PDT 24
Finished Jul 26 04:47:17 PM PDT 24
Peak memory 216184 kb
Host smart-d16512f0-0961-475e-a5fe-18faa8db0802
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425854091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
3425854091
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3760924116
Short name T1108
Test name
Test status
Simulation time 802042723 ps
CPU time 3.47 seconds
Started Jul 26 04:47:08 PM PDT 24
Finished Jul 26 04:47:11 PM PDT 24
Peak memory 218304 kb
Host smart-bfbe590a-27c0-4999-abf1-8e7df83651cb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760924116 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.3760924116
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.683724823
Short name T1073
Test name
Test status
Simulation time 20312731 ps
CPU time 1.26 seconds
Started Jul 26 04:46:58 PM PDT 24
Finished Jul 26 04:46:59 PM PDT 24
Peak memory 215848 kb
Host smart-396510c0-ea54-4cf0-92c2-32be2a5e6362
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683724823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.683724823
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.689058285
Short name T1039
Test name
Test status
Simulation time 94440922 ps
CPU time 0.76 seconds
Started Jul 26 04:47:06 PM PDT 24
Finished Jul 26 04:47:07 PM PDT 24
Peak memory 204336 kb
Host smart-5ef44561-0462-4516-bfc9-a3a627f87cf5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689058285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.689058285
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.661482023
Short name T1085
Test name
Test status
Simulation time 44234638 ps
CPU time 2.89 seconds
Started Jul 26 04:47:11 PM PDT 24
Finished Jul 26 04:47:14 PM PDT 24
Peak memory 216288 kb
Host smart-85da05e9-0709-455d-86f6-b6e199e57e6a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661482023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.s
pi_device_same_csr_outstanding.661482023
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.2426712611
Short name T95
Test name
Test status
Simulation time 154926111 ps
CPU time 2.69 seconds
Started Jul 26 04:47:02 PM PDT 24
Finished Jul 26 04:47:05 PM PDT 24
Peak memory 217176 kb
Host smart-2960ac5e-98f0-4344-a348-b21655905202
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426712611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
2426712611
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.701422972
Short name T99
Test name
Test status
Simulation time 172660703 ps
CPU time 1.7 seconds
Started Jul 26 04:47:17 PM PDT 24
Finished Jul 26 04:47:19 PM PDT 24
Peak memory 216352 kb
Host smart-4418f1c4-20d1-4433-8c4d-0cf9f742613e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701422972 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.701422972
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.1368175822
Short name T125
Test name
Test status
Simulation time 95638878 ps
CPU time 1.4 seconds
Started Jul 26 04:47:04 PM PDT 24
Finished Jul 26 04:47:05 PM PDT 24
Peak memory 207584 kb
Host smart-b9122a67-17f2-404f-87fd-1eee8864b16a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368175822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
1368175822
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.714176448
Short name T1083
Test name
Test status
Simulation time 17585943 ps
CPU time 0.73 seconds
Started Jul 26 04:47:04 PM PDT 24
Finished Jul 26 04:47:04 PM PDT 24
Peak memory 204252 kb
Host smart-e68da20e-082b-4919-8e9c-b5cdecd66322
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714176448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.714176448
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.4194259671
Short name T147
Test name
Test status
Simulation time 71590241 ps
CPU time 1.85 seconds
Started Jul 26 04:47:12 PM PDT 24
Finished Jul 26 04:47:14 PM PDT 24
Peak memory 207708 kb
Host smart-bbf01b7c-1ceb-425a-8bff-881f5a28e58e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194259671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.4194259671
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3168827602
Short name T1138
Test name
Test status
Simulation time 240906728 ps
CPU time 5.34 seconds
Started Jul 26 04:47:01 PM PDT 24
Finished Jul 26 04:47:07 PM PDT 24
Peak memory 216156 kb
Host smart-42935222-ca3e-4dcb-80c8-54a47f0d6fa7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168827602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
3168827602
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1833421663
Short name T1140
Test name
Test status
Simulation time 1460534360 ps
CPU time 19.86 seconds
Started Jul 26 04:47:11 PM PDT 24
Finished Jul 26 04:47:31 PM PDT 24
Peak memory 215792 kb
Host smart-30d6fe67-9bf9-4afb-a46a-260c6ff9fb4d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833421663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.1833421663
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.1540023666
Short name T1099
Test name
Test status
Simulation time 152646251 ps
CPU time 3.6 seconds
Started Jul 26 04:47:10 PM PDT 24
Finished Jul 26 04:47:14 PM PDT 24
Peak memory 217648 kb
Host smart-37d0e991-924c-459e-8ba4-b0b84abf5a78
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540023666 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.1540023666
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.1783101078
Short name T122
Test name
Test status
Simulation time 290872656 ps
CPU time 2.31 seconds
Started Jul 26 04:47:05 PM PDT 24
Finished Jul 26 04:47:08 PM PDT 24
Peak memory 215920 kb
Host smart-8c394b47-0191-424d-bcb1-58a2ca763053
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783101078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
1783101078
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.2118073052
Short name T1048
Test name
Test status
Simulation time 21664620 ps
CPU time 0.76 seconds
Started Jul 26 04:47:06 PM PDT 24
Finished Jul 26 04:47:07 PM PDT 24
Peak memory 204684 kb
Host smart-a31ad071-314e-4439-9298-48641f0440e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118073052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
2118073052
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1772793022
Short name T1103
Test name
Test status
Simulation time 88870262 ps
CPU time 3.56 seconds
Started Jul 26 04:47:12 PM PDT 24
Finished Jul 26 04:47:16 PM PDT 24
Peak memory 215864 kb
Host smart-e38fc6cb-175c-4367-bfe5-d7c59822c980
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772793022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.1772793022
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.3484955028
Short name T101
Test name
Test status
Simulation time 64431324 ps
CPU time 4.38 seconds
Started Jul 26 04:47:05 PM PDT 24
Finished Jul 26 04:47:10 PM PDT 24
Peak memory 215976 kb
Host smart-9a148419-2ddb-4e1a-bd1c-429f110b78b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484955028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
3484955028
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.3980450584
Short name T1067
Test name
Test status
Simulation time 264497599 ps
CPU time 7.42 seconds
Started Jul 26 04:46:58 PM PDT 24
Finished Jul 26 04:47:05 PM PDT 24
Peak memory 215944 kb
Host smart-f4861fca-7041-4a75-8756-f3bd1601b4f9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980450584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.3980450584
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.4171686796
Short name T1070
Test name
Test status
Simulation time 162914162 ps
CPU time 1.7 seconds
Started Jul 26 04:47:05 PM PDT 24
Finished Jul 26 04:47:07 PM PDT 24
Peak memory 215920 kb
Host smart-228848a2-989c-425e-a3d2-9db6baf1fc11
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171686796 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.4171686796
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.2532193459
Short name T120
Test name
Test status
Simulation time 106099188 ps
CPU time 2.64 seconds
Started Jul 26 04:47:01 PM PDT 24
Finished Jul 26 04:47:03 PM PDT 24
Peak memory 215900 kb
Host smart-45084772-c9a8-4497-9372-58c479dd1853
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532193459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
2532193459
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.4020897803
Short name T1033
Test name
Test status
Simulation time 21091693 ps
CPU time 0.79 seconds
Started Jul 26 04:47:03 PM PDT 24
Finished Jul 26 04:47:05 PM PDT 24
Peak memory 203864 kb
Host smart-c5ac07ac-fc55-45db-8702-93b6cf21d720
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020897803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
4020897803
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.551943477
Short name T1068
Test name
Test status
Simulation time 71583629 ps
CPU time 2.95 seconds
Started Jul 26 04:47:04 PM PDT 24
Finished Jul 26 04:47:07 PM PDT 24
Peak memory 215900 kb
Host smart-1ab2149f-7c1e-4ebf-9424-2ec0f59c1984
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551943477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.s
pi_device_same_csr_outstanding.551943477
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.3934617000
Short name T1102
Test name
Test status
Simulation time 230409335 ps
CPU time 1.86 seconds
Started Jul 26 04:47:02 PM PDT 24
Finished Jul 26 04:47:04 PM PDT 24
Peak memory 215992 kb
Host smart-e1d84523-046d-4284-8832-7b005b524635
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934617000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
3934617000
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.3836187139
Short name T1129
Test name
Test status
Simulation time 1096877810 ps
CPU time 7.57 seconds
Started Jul 26 04:47:03 PM PDT 24
Finished Jul 26 04:47:10 PM PDT 24
Peak memory 217116 kb
Host smart-d806e490-56b9-49d7-aff4-fd986e725c89
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836187139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.3836187139
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3217027646
Short name T1096
Test name
Test status
Simulation time 919280271 ps
CPU time 22.32 seconds
Started Jul 26 04:46:58 PM PDT 24
Finished Jul 26 04:47:20 PM PDT 24
Peak memory 207860 kb
Host smart-809a54ed-a3ff-41a3-94b3-a350a189b3cd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217027646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.3217027646
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3805234618
Short name T1146
Test name
Test status
Simulation time 6469014740 ps
CPU time 26.09 seconds
Started Jul 26 04:46:59 PM PDT 24
Finished Jul 26 04:47:25 PM PDT 24
Peak memory 207796 kb
Host smart-afdd2acd-08b4-4dc6-ad75-291aa2126c57
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805234618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.3805234618
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3655255844
Short name T76
Test name
Test status
Simulation time 91763885 ps
CPU time 1.41 seconds
Started Jul 26 04:47:11 PM PDT 24
Finished Jul 26 04:47:13 PM PDT 24
Peak memory 207660 kb
Host smart-386b34d3-bc6c-4061-b645-fc3acc9ab8b6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655255844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.3655255844
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.994394653
Short name T107
Test name
Test status
Simulation time 167038533 ps
CPU time 2.73 seconds
Started Jul 26 04:46:59 PM PDT 24
Finished Jul 26 04:47:02 PM PDT 24
Peak memory 217772 kb
Host smart-9276f651-1907-4a16-aa6e-f2fa1235573c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994394653 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.994394653
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.791444195
Short name T1116
Test name
Test status
Simulation time 62813790 ps
CPU time 1.86 seconds
Started Jul 26 04:46:59 PM PDT 24
Finished Jul 26 04:47:01 PM PDT 24
Peak memory 215740 kb
Host smart-28aaeefd-8d0c-41cc-98f5-e0eb126a0157
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791444195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.791444195
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.328010339
Short name T1051
Test name
Test status
Simulation time 11742507 ps
CPU time 0.74 seconds
Started Jul 26 04:46:51 PM PDT 24
Finished Jul 26 04:46:52 PM PDT 24
Peak memory 204260 kb
Host smart-37d6135d-224c-4466-82f4-ae09dfbe2dca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328010339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.328010339
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.153342923
Short name T1110
Test name
Test status
Simulation time 45071362 ps
CPU time 1.31 seconds
Started Jul 26 04:46:58 PM PDT 24
Finished Jul 26 04:46:59 PM PDT 24
Peak memory 215900 kb
Host smart-623f0aee-66ab-4d71-836c-0451f37a409c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153342923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_
device_mem_partial_access.153342923
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3946282408
Short name T1115
Test name
Test status
Simulation time 11410604 ps
CPU time 0.67 seconds
Started Jul 26 04:46:57 PM PDT 24
Finished Jul 26 04:46:58 PM PDT 24
Peak memory 204248 kb
Host smart-fd84e789-af3a-4e5d-b546-f775e3d52e6e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946282408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.3946282408
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1951864226
Short name T1131
Test name
Test status
Simulation time 69248692 ps
CPU time 1.75 seconds
Started Jul 26 04:46:58 PM PDT 24
Finished Jul 26 04:46:59 PM PDT 24
Peak memory 215832 kb
Host smart-f2d86abd-1d5c-4b48-a7c4-7772e7ccdb23
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951864226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.1951864226
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3390543676
Short name T106
Test name
Test status
Simulation time 49476120 ps
CPU time 2.96 seconds
Started Jul 26 04:46:38 PM PDT 24
Finished Jul 26 04:46:41 PM PDT 24
Peak memory 216040 kb
Host smart-2997a220-052c-4813-977d-a34785685563
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390543676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.3
390543676
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.2623964968
Short name T98
Test name
Test status
Simulation time 2336575436 ps
CPU time 13.48 seconds
Started Jul 26 04:46:52 PM PDT 24
Finished Jul 26 04:47:05 PM PDT 24
Peak memory 216000 kb
Host smart-d1d0100a-2163-441a-be56-d86f2280f652
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623964968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.2623964968
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.2184097066
Short name T1055
Test name
Test status
Simulation time 12001440 ps
CPU time 0.72 seconds
Started Jul 26 04:47:01 PM PDT 24
Finished Jul 26 04:47:01 PM PDT 24
Peak memory 204588 kb
Host smart-0bcff04d-8591-4875-8fc1-4ef72f81d899
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184097066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
2184097066
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.527138686
Short name T1125
Test name
Test status
Simulation time 51321371 ps
CPU time 0.73 seconds
Started Jul 26 04:47:16 PM PDT 24
Finished Jul 26 04:47:17 PM PDT 24
Peak memory 204332 kb
Host smart-b7b976da-795c-4e22-8485-edaa9cf5dfa1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527138686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.527138686
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.650041768
Short name T1064
Test name
Test status
Simulation time 155284156 ps
CPU time 0.77 seconds
Started Jul 26 04:46:58 PM PDT 24
Finished Jul 26 04:46:59 PM PDT 24
Peak memory 204360 kb
Host smart-b5ca754f-e1a0-4d56-9790-b91cc08d0813
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650041768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.650041768
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.586554978
Short name T1109
Test name
Test status
Simulation time 16772223 ps
CPU time 0.78 seconds
Started Jul 26 04:47:14 PM PDT 24
Finished Jul 26 04:47:15 PM PDT 24
Peak memory 204348 kb
Host smart-cc41e4d4-7672-4423-883a-49fa86266dfc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586554978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.586554978
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.113591284
Short name T1038
Test name
Test status
Simulation time 37600371 ps
CPU time 0.77 seconds
Started Jul 26 04:47:11 PM PDT 24
Finished Jul 26 04:47:13 PM PDT 24
Peak memory 204672 kb
Host smart-103fa116-7b9e-4ca1-b4d9-70569b957a60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113591284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.113591284
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.588886485
Short name T1044
Test name
Test status
Simulation time 30204345 ps
CPU time 0.75 seconds
Started Jul 26 04:47:04 PM PDT 24
Finished Jul 26 04:47:05 PM PDT 24
Peak memory 204360 kb
Host smart-f87715fe-3511-4b42-afd9-a43b737b6bfa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588886485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.588886485
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.3971802480
Short name T1106
Test name
Test status
Simulation time 15731999 ps
CPU time 0.72 seconds
Started Jul 26 04:46:58 PM PDT 24
Finished Jul 26 04:46:59 PM PDT 24
Peak memory 204296 kb
Host smart-0b712438-8e63-4dfb-8692-59ed63133bbd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971802480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
3971802480
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.2324135324
Short name T1092
Test name
Test status
Simulation time 33502751 ps
CPU time 0.7 seconds
Started Jul 26 04:47:14 PM PDT 24
Finished Jul 26 04:47:15 PM PDT 24
Peak memory 204364 kb
Host smart-6cd29b2f-66c3-4403-90b4-1c470d5517cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324135324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
2324135324
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.2654083103
Short name T1047
Test name
Test status
Simulation time 87507586 ps
CPU time 0.74 seconds
Started Jul 26 04:47:07 PM PDT 24
Finished Jul 26 04:47:09 PM PDT 24
Peak memory 204636 kb
Host smart-9488b75d-7050-4ec7-83dc-d80e55e0c94a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654083103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
2654083103
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.1726444673
Short name T1149
Test name
Test status
Simulation time 14614928 ps
CPU time 0.74 seconds
Started Jul 26 04:47:04 PM PDT 24
Finished Jul 26 04:47:05 PM PDT 24
Peak memory 204688 kb
Host smart-263ac76e-0ea9-49be-909a-eba7f479439a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726444673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
1726444673
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.3844275029
Short name T1090
Test name
Test status
Simulation time 504455766 ps
CPU time 7.8 seconds
Started Jul 26 04:47:03 PM PDT 24
Finished Jul 26 04:47:11 PM PDT 24
Peak memory 207756 kb
Host smart-ae042e29-1789-459b-9156-60bddb879065
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844275029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.3844275029
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.2536160347
Short name T1130
Test name
Test status
Simulation time 3485065294 ps
CPU time 14.64 seconds
Started Jul 26 04:46:49 PM PDT 24
Finished Jul 26 04:47:04 PM PDT 24
Peak memory 207848 kb
Host smart-7b5d9b35-b1e2-49fd-821d-0f6fbf7f3e82
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536160347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.2536160347
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2678637179
Short name T1126
Test name
Test status
Simulation time 33912448 ps
CPU time 1.2 seconds
Started Jul 26 04:46:59 PM PDT 24
Finished Jul 26 04:47:01 PM PDT 24
Peak memory 216812 kb
Host smart-d4ff4261-4c5a-4866-a277-331eeb9facc4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678637179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.2678637179
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.158868117
Short name T148
Test name
Test status
Simulation time 169555843 ps
CPU time 3.73 seconds
Started Jul 26 04:46:57 PM PDT 24
Finished Jul 26 04:47:01 PM PDT 24
Peak memory 218428 kb
Host smart-2e6c746f-8149-4c3c-8b4a-bd64f59bed3a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158868117 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.158868117
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.2301933238
Short name T1117
Test name
Test status
Simulation time 139120066 ps
CPU time 1.28 seconds
Started Jul 26 04:47:21 PM PDT 24
Finished Jul 26 04:47:23 PM PDT 24
Peak memory 207672 kb
Host smart-c874efd4-58b4-4cd4-bcca-a8cfc990d68d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301933238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.2
301933238
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.3121605724
Short name T1063
Test name
Test status
Simulation time 82710257 ps
CPU time 0.78 seconds
Started Jul 26 04:47:00 PM PDT 24
Finished Jul 26 04:47:01 PM PDT 24
Peak memory 204288 kb
Host smart-51e99988-207a-4c67-8423-3d887cd689e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121605724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.3
121605724
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.4268459649
Short name T1144
Test name
Test status
Simulation time 400169279 ps
CPU time 1.66 seconds
Started Jul 26 04:46:52 PM PDT 24
Finished Jul 26 04:46:54 PM PDT 24
Peak memory 215936 kb
Host smart-73446a51-577b-41f0-b74c-36a0947e073d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268459649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.4268459649
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1845254117
Short name T1079
Test name
Test status
Simulation time 12405300 ps
CPU time 0.65 seconds
Started Jul 26 04:46:57 PM PDT 24
Finished Jul 26 04:46:58 PM PDT 24
Peak memory 204244 kb
Host smart-7fa38a45-705d-4d22-9e5c-532d02994db1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845254117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.1845254117
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1281936690
Short name T146
Test name
Test status
Simulation time 390413475 ps
CPU time 3.98 seconds
Started Jul 26 04:46:52 PM PDT 24
Finished Jul 26 04:46:56 PM PDT 24
Peak memory 215776 kb
Host smart-e1a68017-2ec2-4728-86e8-38216b587792
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281936690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.1281936690
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.1621401263
Short name T94
Test name
Test status
Simulation time 163470606 ps
CPU time 2.79 seconds
Started Jul 26 04:46:53 PM PDT 24
Finished Jul 26 04:46:56 PM PDT 24
Peak memory 216020 kb
Host smart-787e6b50-ecef-43d8-837d-ab62ef0e873b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621401263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.1
621401263
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.1615482870
Short name T1111
Test name
Test status
Simulation time 521282764 ps
CPU time 7.76 seconds
Started Jul 26 04:47:05 PM PDT 24
Finished Jul 26 04:47:13 PM PDT 24
Peak memory 215800 kb
Host smart-325cc426-aada-4e59-a986-2020fc694ef2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615482870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.1615482870
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.917690851
Short name T1132
Test name
Test status
Simulation time 28263763 ps
CPU time 0.73 seconds
Started Jul 26 04:47:20 PM PDT 24
Finished Jul 26 04:47:21 PM PDT 24
Peak memory 204384 kb
Host smart-fff14923-ddc1-4f79-8892-46e83de85201
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917690851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.917690851
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.2935347972
Short name T1128
Test name
Test status
Simulation time 14330507 ps
CPU time 0.78 seconds
Started Jul 26 04:47:02 PM PDT 24
Finished Jul 26 04:47:03 PM PDT 24
Peak memory 204612 kb
Host smart-a2c282a4-3f21-437a-8645-408858e71354
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935347972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
2935347972
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.3653775499
Short name T1058
Test name
Test status
Simulation time 44016067 ps
CPU time 0.69 seconds
Started Jul 26 04:47:13 PM PDT 24
Finished Jul 26 04:47:14 PM PDT 24
Peak memory 204300 kb
Host smart-0aa4e2b0-7382-451f-bb80-ef05dff659b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653775499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
3653775499
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.420146507
Short name T1119
Test name
Test status
Simulation time 68678156 ps
CPU time 0.7 seconds
Started Jul 26 04:47:13 PM PDT 24
Finished Jul 26 04:47:13 PM PDT 24
Peak memory 204324 kb
Host smart-6480d0a3-7229-494b-b425-fb12cecde3e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420146507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.420146507
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.845327401
Short name T1052
Test name
Test status
Simulation time 11075185 ps
CPU time 0.74 seconds
Started Jul 26 04:47:05 PM PDT 24
Finished Jul 26 04:47:06 PM PDT 24
Peak memory 204656 kb
Host smart-1d7cdad0-b0f9-4173-8eec-b19aa060cc57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845327401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.845327401
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.1249021640
Short name T1145
Test name
Test status
Simulation time 47178688 ps
CPU time 0.72 seconds
Started Jul 26 04:47:05 PM PDT 24
Finished Jul 26 04:47:06 PM PDT 24
Peak memory 204708 kb
Host smart-ad2d5915-0b3e-4157-af1e-ec265d6b73f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249021640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
1249021640
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.3634572132
Short name T1098
Test name
Test status
Simulation time 14134010 ps
CPU time 0.77 seconds
Started Jul 26 04:47:13 PM PDT 24
Finished Jul 26 04:47:14 PM PDT 24
Peak memory 204268 kb
Host smart-f9650638-23a7-4061-a347-8338de0377ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634572132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
3634572132
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.4095935321
Short name T1137
Test name
Test status
Simulation time 17859021 ps
CPU time 0.67 seconds
Started Jul 26 04:47:07 PM PDT 24
Finished Jul 26 04:47:07 PM PDT 24
Peak memory 204336 kb
Host smart-7da3480e-64f9-426a-8905-3b2141827cc4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095935321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
4095935321
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.2514764447
Short name T1032
Test name
Test status
Simulation time 43460908 ps
CPU time 0.72 seconds
Started Jul 26 04:47:10 PM PDT 24
Finished Jul 26 04:47:11 PM PDT 24
Peak memory 204304 kb
Host smart-b5cfe5e5-658f-4054-9d29-ef80e6b5ebfa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514764447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
2514764447
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.3314437019
Short name T1062
Test name
Test status
Simulation time 39946293 ps
CPU time 0.71 seconds
Started Jul 26 04:47:04 PM PDT 24
Finished Jul 26 04:47:05 PM PDT 24
Peak memory 204260 kb
Host smart-af9f5985-fe92-4f2f-bff8-7fb36baa1dad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314437019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
3314437019
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.282770322
Short name T1093
Test name
Test status
Simulation time 1149542716 ps
CPU time 24.1 seconds
Started Jul 26 04:46:50 PM PDT 24
Finished Jul 26 04:47:14 PM PDT 24
Peak memory 215748 kb
Host smart-8f7e1532-9752-44dc-81ad-c5a5f92117fb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282770322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_aliasing.282770322
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.1741410564
Short name T117
Test name
Test status
Simulation time 361788617 ps
CPU time 21.22 seconds
Started Jul 26 04:46:56 PM PDT 24
Finished Jul 26 04:47:17 PM PDT 24
Peak memory 207520 kb
Host smart-7f1ae43e-ef6d-4bc6-b13c-1aba3b083559
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741410564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.1741410564
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.1045625436
Short name T1034
Test name
Test status
Simulation time 35016150 ps
CPU time 0.99 seconds
Started Jul 26 04:47:00 PM PDT 24
Finished Jul 26 04:47:01 PM PDT 24
Peak memory 207460 kb
Host smart-034d481d-c018-4f28-82c4-6889ab3dd44c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045625436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.1045625436
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.2955125260
Short name T1136
Test name
Test status
Simulation time 391474223 ps
CPU time 3.56 seconds
Started Jul 26 04:47:07 PM PDT 24
Finished Jul 26 04:47:10 PM PDT 24
Peak memory 217848 kb
Host smart-44503acf-4627-4580-bbb6-6f7c4be4561d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955125260 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.2955125260
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.583129965
Short name T1121
Test name
Test status
Simulation time 501589540 ps
CPU time 2.69 seconds
Started Jul 26 04:47:02 PM PDT 24
Finished Jul 26 04:47:05 PM PDT 24
Peak memory 216220 kb
Host smart-77efb43a-3c07-491c-a1fd-7ce4bbbfd8ff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583129965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.583129965
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.4081964931
Short name T1141
Test name
Test status
Simulation time 52859352 ps
CPU time 0.78 seconds
Started Jul 26 04:46:54 PM PDT 24
Finished Jul 26 04:46:55 PM PDT 24
Peak memory 203912 kb
Host smart-9d3bf237-dd7e-47b8-af15-b93f59605801
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081964931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.4
081964931
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.2883222473
Short name T113
Test name
Test status
Simulation time 42554763 ps
CPU time 1.74 seconds
Started Jul 26 04:47:11 PM PDT 24
Finished Jul 26 04:47:13 PM PDT 24
Peak memory 215872 kb
Host smart-930a4686-760b-4221-9926-b9737811c4c8
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883222473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.2883222473
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.493455839
Short name T1041
Test name
Test status
Simulation time 10425145 ps
CPU time 0.69 seconds
Started Jul 26 04:46:59 PM PDT 24
Finished Jul 26 04:47:00 PM PDT 24
Peak memory 204184 kb
Host smart-295e7a73-9526-461b-b5ed-efa5a65cd6ca
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493455839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_mem
_walk.493455839
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.659381634
Short name T1049
Test name
Test status
Simulation time 118843934 ps
CPU time 3.11 seconds
Started Jul 26 04:47:02 PM PDT 24
Finished Jul 26 04:47:06 PM PDT 24
Peak memory 215900 kb
Host smart-1c4b38cf-d19d-4997-ab28-7a0bf5a03134
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659381634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sp
i_device_same_csr_outstanding.659381634
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2030990697
Short name T160
Test name
Test status
Simulation time 698627754 ps
CPU time 4.23 seconds
Started Jul 26 04:46:56 PM PDT 24
Finished Jul 26 04:47:01 PM PDT 24
Peak memory 216096 kb
Host smart-b37aa875-31b4-4ecb-986c-585bf13adc5d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030990697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.2
030990697
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.3188358014
Short name T1134
Test name
Test status
Simulation time 15021672 ps
CPU time 0.7 seconds
Started Jul 26 04:47:07 PM PDT 24
Finished Jul 26 04:47:09 PM PDT 24
Peak memory 204364 kb
Host smart-8b5f59bc-7075-42d3-a071-f20d58a71ad0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188358014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
3188358014
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.2472834464
Short name T1101
Test name
Test status
Simulation time 21919820 ps
CPU time 0.72 seconds
Started Jul 26 04:47:08 PM PDT 24
Finished Jul 26 04:47:09 PM PDT 24
Peak memory 204324 kb
Host smart-80ed2feb-f4b8-4a2a-b26d-f1f1b25184ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472834464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
2472834464
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.1782509592
Short name T1071
Test name
Test status
Simulation time 12488143 ps
CPU time 0.77 seconds
Started Jul 26 04:47:25 PM PDT 24
Finished Jul 26 04:47:26 PM PDT 24
Peak memory 204400 kb
Host smart-e37b316c-27f4-40c7-8671-15ef9e904a96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782509592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
1782509592
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.1212903906
Short name T1139
Test name
Test status
Simulation time 19498508 ps
CPU time 0.77 seconds
Started Jul 26 04:47:14 PM PDT 24
Finished Jul 26 04:47:15 PM PDT 24
Peak memory 204288 kb
Host smart-57b2a593-e784-42d4-8ce2-3e7fe94bab07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212903906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
1212903906
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1580957641
Short name T1082
Test name
Test status
Simulation time 13659258 ps
CPU time 0.74 seconds
Started Jul 26 04:47:13 PM PDT 24
Finished Jul 26 04:47:15 PM PDT 24
Peak memory 204684 kb
Host smart-6613d544-bea8-4a34-b1a7-113c85dc3c93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580957641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
1580957641
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3059708944
Short name T1095
Test name
Test status
Simulation time 21828415 ps
CPU time 0.68 seconds
Started Jul 26 04:47:09 PM PDT 24
Finished Jul 26 04:47:10 PM PDT 24
Peak memory 204644 kb
Host smart-85a4e75e-11b1-47e4-9c84-e2d6d514071e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059708944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
3059708944
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.536262094
Short name T1084
Test name
Test status
Simulation time 87893692 ps
CPU time 0.71 seconds
Started Jul 26 04:47:08 PM PDT 24
Finished Jul 26 04:47:09 PM PDT 24
Peak memory 204704 kb
Host smart-73e18ad8-d9d6-4e25-b62d-03540ff06421
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536262094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.536262094
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.3997844346
Short name T1072
Test name
Test status
Simulation time 14196385 ps
CPU time 0.74 seconds
Started Jul 26 04:47:22 PM PDT 24
Finished Jul 26 04:47:23 PM PDT 24
Peak memory 204708 kb
Host smart-5b6b7ef9-f446-42e2-a8aa-29d4fd0e0aac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997844346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
3997844346
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.833362163
Short name T1122
Test name
Test status
Simulation time 11068380 ps
CPU time 0.71 seconds
Started Jul 26 04:47:34 PM PDT 24
Finished Jul 26 04:47:45 PM PDT 24
Peak memory 204336 kb
Host smart-a7e6e44b-7aad-4718-8257-0b01612d1b61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833362163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.833362163
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.3409843865
Short name T1035
Test name
Test status
Simulation time 14141857 ps
CPU time 0.73 seconds
Started Jul 26 04:47:22 PM PDT 24
Finished Jul 26 04:47:23 PM PDT 24
Peak memory 204412 kb
Host smart-92161c04-bbcf-49c8-949a-db520d7506a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409843865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
3409843865
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1073005498
Short name T1076
Test name
Test status
Simulation time 120244103 ps
CPU time 3.97 seconds
Started Jul 26 04:46:44 PM PDT 24
Finished Jul 26 04:46:48 PM PDT 24
Peak memory 218340 kb
Host smart-7b32f748-e017-4d47-8f99-9595e2dc9bdd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073005498 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.1073005498
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.3942034325
Short name T1143
Test name
Test status
Simulation time 38933143 ps
CPU time 1.27 seconds
Started Jul 26 04:46:52 PM PDT 24
Finished Jul 26 04:46:53 PM PDT 24
Peak memory 215928 kb
Host smart-3c136cd2-ea20-4415-bf11-5a0ab0b29348
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942034325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.3
942034325
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.820250604
Short name T1053
Test name
Test status
Simulation time 43525423 ps
CPU time 0.69 seconds
Started Jul 26 04:46:54 PM PDT 24
Finished Jul 26 04:46:54 PM PDT 24
Peak memory 204328 kb
Host smart-348ff3c4-1a8e-4466-a156-0f910b606c17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820250604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.820250604
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2624134869
Short name T1088
Test name
Test status
Simulation time 40270324 ps
CPU time 2.48 seconds
Started Jul 26 04:47:01 PM PDT 24
Finished Jul 26 04:47:04 PM PDT 24
Peak memory 215836 kb
Host smart-6112d830-a216-4569-9a16-d8ae57b61d9c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624134869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.2624134869
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.4111041882
Short name T1091
Test name
Test status
Simulation time 360045371 ps
CPU time 2.58 seconds
Started Jul 26 04:47:04 PM PDT 24
Finished Jul 26 04:47:06 PM PDT 24
Peak memory 216036 kb
Host smart-cd07cbf4-271a-48eb-92b0-fdcf28a6a7e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111041882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.4
111041882
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.3326073941
Short name T1094
Test name
Test status
Simulation time 70326157 ps
CPU time 2.02 seconds
Started Jul 26 04:46:58 PM PDT 24
Finished Jul 26 04:47:00 PM PDT 24
Peak memory 215952 kb
Host smart-edb44783-2bbf-4340-921d-f4e027893f91
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326073941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.3
326073941
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.1971043376
Short name T1107
Test name
Test status
Simulation time 44392328 ps
CPU time 0.73 seconds
Started Jul 26 04:46:49 PM PDT 24
Finished Jul 26 04:46:50 PM PDT 24
Peak memory 204392 kb
Host smart-36e3227d-1ac0-4a90-ba3d-0461b754cd34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971043376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.1
971043376
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3519008795
Short name T1147
Test name
Test status
Simulation time 289287955 ps
CPU time 1.88 seconds
Started Jul 26 04:47:00 PM PDT 24
Finished Jul 26 04:47:02 PM PDT 24
Peak memory 207760 kb
Host smart-ed6c2e25-a4f6-4d45-a45e-b93571aef488
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519008795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.3519008795
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.1236924721
Short name T102
Test name
Test status
Simulation time 416064741 ps
CPU time 2.34 seconds
Started Jul 26 04:47:07 PM PDT 24
Finished Jul 26 04:47:10 PM PDT 24
Peak memory 216192 kb
Host smart-28434f97-88df-423b-b24d-b76fc52b330e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236924721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.1
236924721
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.253349568
Short name T1113
Test name
Test status
Simulation time 202008475 ps
CPU time 11.79 seconds
Started Jul 26 04:47:00 PM PDT 24
Finished Jul 26 04:47:12 PM PDT 24
Peak memory 216396 kb
Host smart-eab40fbe-8e46-4f72-a54f-27d8a762dc18
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253349568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_
tl_intg_err.253349568
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.1953666149
Short name T1061
Test name
Test status
Simulation time 101546185 ps
CPU time 3.81 seconds
Started Jul 26 04:47:04 PM PDT 24
Finished Jul 26 04:47:08 PM PDT 24
Peak memory 218012 kb
Host smart-3a1ee25e-daf1-4265-ae65-78f6bfb77219
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953666149 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.1953666149
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1285642873
Short name T1059
Test name
Test status
Simulation time 80628272 ps
CPU time 1.47 seconds
Started Jul 26 04:46:58 PM PDT 24
Finished Jul 26 04:46:59 PM PDT 24
Peak memory 215828 kb
Host smart-337e8d33-9cab-4780-91cf-40e4269cfc82
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285642873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.1
285642873
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.4018489160
Short name T1100
Test name
Test status
Simulation time 14411314 ps
CPU time 0.76 seconds
Started Jul 26 04:46:57 PM PDT 24
Finished Jul 26 04:46:58 PM PDT 24
Peak memory 204356 kb
Host smart-070ad0a2-629d-406e-bb02-9960a3ef885e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018489160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.4
018489160
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.535637244
Short name T138
Test name
Test status
Simulation time 84491391 ps
CPU time 2.14 seconds
Started Jul 26 04:46:42 PM PDT 24
Finished Jul 26 04:46:45 PM PDT 24
Peak memory 215804 kb
Host smart-769622ed-e21d-4933-adc0-482330734a43
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535637244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sp
i_device_same_csr_outstanding.535637244
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.3337028754
Short name T164
Test name
Test status
Simulation time 844685991 ps
CPU time 12.24 seconds
Started Jul 26 04:47:03 PM PDT 24
Finished Jul 26 04:47:16 PM PDT 24
Peak memory 215912 kb
Host smart-f318bd6c-bf4b-42f0-84d5-a6e2005eb426
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337028754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.3337028754
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3809764644
Short name T1075
Test name
Test status
Simulation time 128419375 ps
CPU time 3.52 seconds
Started Jul 26 04:47:04 PM PDT 24
Finished Jul 26 04:47:08 PM PDT 24
Peak memory 217708 kb
Host smart-f559e535-3af0-4fd4-a90a-ca371ceab5e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809764644 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.3809764644
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.4085326060
Short name T1078
Test name
Test status
Simulation time 59385729 ps
CPU time 1.82 seconds
Started Jul 26 04:46:54 PM PDT 24
Finished Jul 26 04:46:56 PM PDT 24
Peak memory 215876 kb
Host smart-398d8e60-fe7f-480f-9b34-2c6a1806f1ec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085326060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.4
085326060
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.165937478
Short name T1069
Test name
Test status
Simulation time 141476532 ps
CPU time 0.74 seconds
Started Jul 26 04:47:00 PM PDT 24
Finished Jul 26 04:47:01 PM PDT 24
Peak memory 204348 kb
Host smart-21abbb02-2218-4743-b486-30693ea18638
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165937478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.165937478
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.4266068417
Short name T1054
Test name
Test status
Simulation time 97502891 ps
CPU time 1.82 seconds
Started Jul 26 04:46:43 PM PDT 24
Finished Jul 26 04:46:45 PM PDT 24
Peak memory 206904 kb
Host smart-b121db58-9c07-4c12-8606-a2f3b4847e31
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266068417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.4266068417
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.3499137755
Short name T1057
Test name
Test status
Simulation time 135319579 ps
CPU time 3.55 seconds
Started Jul 26 04:47:08 PM PDT 24
Finished Jul 26 04:47:12 PM PDT 24
Peak memory 216556 kb
Host smart-33f37c52-ef77-4b55-b002-6939656eec3c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499137755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.3
499137755
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.1107245983
Short name T162
Test name
Test status
Simulation time 507689653 ps
CPU time 12.74 seconds
Started Jul 26 04:47:08 PM PDT 24
Finished Jul 26 04:47:21 PM PDT 24
Peak memory 223100 kb
Host smart-540792fe-3a42-4272-a07e-7c5d4452e78d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107245983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.1107245983
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1990785329
Short name T1056
Test name
Test status
Simulation time 124441487 ps
CPU time 3.68 seconds
Started Jul 26 04:47:06 PM PDT 24
Finished Jul 26 04:47:10 PM PDT 24
Peak memory 217820 kb
Host smart-984d1667-517f-41bc-a1f4-155b5ca95397
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990785329 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.1990785329
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.3407236745
Short name T1114
Test name
Test status
Simulation time 71067698 ps
CPU time 1.46 seconds
Started Jul 26 04:46:59 PM PDT 24
Finished Jul 26 04:47:01 PM PDT 24
Peak memory 207752 kb
Host smart-8dcaee78-a4d0-4223-9634-ac22ce9f86c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407236745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.3
407236745
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.1118826321
Short name T1050
Test name
Test status
Simulation time 35929396 ps
CPU time 0.71 seconds
Started Jul 26 04:47:05 PM PDT 24
Finished Jul 26 04:47:06 PM PDT 24
Peak memory 204240 kb
Host smart-d30518ec-3f52-4525-80fb-bcba9f680c42
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118826321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.1
118826321
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3279337968
Short name T1151
Test name
Test status
Simulation time 574020668 ps
CPU time 3.81 seconds
Started Jul 26 04:47:20 PM PDT 24
Finished Jul 26 04:47:24 PM PDT 24
Peak memory 215900 kb
Host smart-afedea61-cb3a-48fb-9bb4-dcebe028cb48
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279337968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.3279337968
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.4225087814
Short name T91
Test name
Test status
Simulation time 247756686 ps
CPU time 2.63 seconds
Started Jul 26 04:47:17 PM PDT 24
Finished Jul 26 04:47:20 PM PDT 24
Peak memory 216044 kb
Host smart-fbc9ae04-a396-44bc-b3d3-0700fda80b26
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225087814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.4
225087814
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.4179658532
Short name T90
Test name
Test status
Simulation time 573838569 ps
CPU time 7.77 seconds
Started Jul 26 04:46:58 PM PDT 24
Finished Jul 26 04:47:06 PM PDT 24
Peak memory 215952 kb
Host smart-c2bb7191-4acf-467a-9ebc-552cbe9e07b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179658532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.4179658532
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.1265290989
Short name T730
Test name
Test status
Simulation time 12195272 ps
CPU time 0.69 seconds
Started Jul 26 04:51:59 PM PDT 24
Finished Jul 26 04:52:00 PM PDT 24
Peak memory 206200 kb
Host smart-efe4821c-1cd7-4df7-8291-cfcbf02df4c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265290989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.1
265290989
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.3010963779
Short name T944
Test name
Test status
Simulation time 35905864 ps
CPU time 2.54 seconds
Started Jul 26 04:51:55 PM PDT 24
Finished Jul 26 04:51:58 PM PDT 24
Peak memory 233496 kb
Host smart-f2dbb3f0-d297-43bd-9e14-002a8cd76ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010963779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.3010963779
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.3694701476
Short name T791
Test name
Test status
Simulation time 22593990 ps
CPU time 0.71 seconds
Started Jul 26 04:52:00 PM PDT 24
Finished Jul 26 04:52:00 PM PDT 24
Peak memory 206016 kb
Host smart-54343e10-86b0-4f92-877b-6746c1baba53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694701476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.3694701476
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.3223110895
Short name T275
Test name
Test status
Simulation time 37543751004 ps
CPU time 248.45 seconds
Started Jul 26 04:51:54 PM PDT 24
Finished Jul 26 04:56:03 PM PDT 24
Peak memory 256840 kb
Host smart-fd71cbf3-e942-4f24-88d8-20ac10391dda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223110895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.3223110895
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.1022668526
Short name T866
Test name
Test status
Simulation time 25368122314 ps
CPU time 205.29 seconds
Started Jul 26 04:51:59 PM PDT 24
Finished Jul 26 04:55:24 PM PDT 24
Peak memory 258156 kb
Host smart-1f482895-7485-4dd5-bd8d-384e4924db45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022668526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.1022668526
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.2747589291
Short name T479
Test name
Test status
Simulation time 441554929 ps
CPU time 3.32 seconds
Started Jul 26 04:52:01 PM PDT 24
Finished Jul 26 04:52:05 PM PDT 24
Peak memory 233448 kb
Host smart-fd90d918-bdcb-4a72-bc4e-bfab0802f817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747589291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.2747589291
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.3223591956
Short name T991
Test name
Test status
Simulation time 861339202 ps
CPU time 11.39 seconds
Started Jul 26 04:51:59 PM PDT 24
Finished Jul 26 04:52:10 PM PDT 24
Peak memory 236108 kb
Host smart-1bf0ebfe-ca8c-4a33-a562-a6bee4753340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223591956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds
.3223591956
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_intercept.3535807902
Short name T227
Test name
Test status
Simulation time 1636035596 ps
CPU time 5.24 seconds
Started Jul 26 04:51:57 PM PDT 24
Finished Jul 26 04:52:02 PM PDT 24
Peak memory 225264 kb
Host smart-5ab8c8a2-0f76-4c2c-afdb-21c618892ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535807902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.3535807902
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.3187180587
Short name T910
Test name
Test status
Simulation time 3691345408 ps
CPU time 30.8 seconds
Started Jul 26 04:51:55 PM PDT 24
Finished Jul 26 04:52:26 PM PDT 24
Peak memory 220616 kb
Host smart-6b99b554-2891-470f-b48a-fc8d385b2445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187180587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.3187180587
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.4093976470
Short name T929
Test name
Test status
Simulation time 26007642 ps
CPU time 1.05 seconds
Started Jul 26 04:51:55 PM PDT 24
Finished Jul 26 04:51:57 PM PDT 24
Peak memory 217252 kb
Host smart-85a425b2-9860-4ee3-8b1b-f18c601e4c10
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093976470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.spi_device_mem_parity.4093976470
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.2522578274
Short name T250
Test name
Test status
Simulation time 648221667 ps
CPU time 3.65 seconds
Started Jul 26 04:51:56 PM PDT 24
Finished Jul 26 04:52:00 PM PDT 24
Peak memory 225204 kb
Host smart-ca622311-9281-41a9-ae43-b50a58deb8de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522578274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.2522578274
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.3976091648
Short name T620
Test name
Test status
Simulation time 3011291026 ps
CPU time 7.41 seconds
Started Jul 26 04:52:03 PM PDT 24
Finished Jul 26 04:52:10 PM PDT 24
Peak memory 225264 kb
Host smart-5ea9cd37-90f9-4f61-b1be-b7fb9e3bfc84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976091648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.3976091648
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.4275587474
Short name T985
Test name
Test status
Simulation time 1787106246 ps
CPU time 8.91 seconds
Started Jul 26 04:51:57 PM PDT 24
Finished Jul 26 04:52:06 PM PDT 24
Peak memory 219692 kb
Host smart-61587cd0-5385-4227-bc18-c994e63c45be
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4275587474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.4275587474
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.442019477
Short name T63
Test name
Test status
Simulation time 160461964 ps
CPU time 1.18 seconds
Started Jul 26 04:51:58 PM PDT 24
Finished Jul 26 04:51:59 PM PDT 24
Peak memory 235784 kb
Host smart-6f4ed09d-497f-48b5-9eb8-bc2ae1b7e71b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442019477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.442019477
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.371522114
Short name T504
Test name
Test status
Simulation time 1383434281 ps
CPU time 22.65 seconds
Started Jul 26 04:51:53 PM PDT 24
Finished Jul 26 04:52:16 PM PDT 24
Peak memory 217244 kb
Host smart-b79b6786-f1dc-4e3f-bf1c-dc551749b740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371522114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.371522114
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.3731858045
Short name T712
Test name
Test status
Simulation time 492451681 ps
CPU time 2.46 seconds
Started Jul 26 04:51:57 PM PDT 24
Finished Jul 26 04:51:59 PM PDT 24
Peak memory 217040 kb
Host smart-f6f0e4a0-47fa-4ef0-b29c-880895e2f4f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731858045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.3731858045
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.1058453387
Short name T825
Test name
Test status
Simulation time 170364941 ps
CPU time 1.52 seconds
Started Jul 26 04:51:54 PM PDT 24
Finished Jul 26 04:51:55 PM PDT 24
Peak memory 217080 kb
Host smart-7993d149-df00-4a96-9fe2-7fc6eabee1c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058453387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.1058453387
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.3585590526
Short name T487
Test name
Test status
Simulation time 36227901 ps
CPU time 0.82 seconds
Started Jul 26 04:51:58 PM PDT 24
Finished Jul 26 04:51:59 PM PDT 24
Peak memory 206576 kb
Host smart-bf2a6ffd-e08f-4503-a577-6af54816d93e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585590526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.3585590526
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.1621096477
Short name T621
Test name
Test status
Simulation time 330422290 ps
CPU time 5.42 seconds
Started Jul 26 04:51:58 PM PDT 24
Finished Jul 26 04:52:03 PM PDT 24
Peak memory 233524 kb
Host smart-2917e5d5-d433-45a5-8ae2-352ab992838b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621096477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.1621096477
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.3849333645
Short name T832
Test name
Test status
Simulation time 14394267 ps
CPU time 0.74 seconds
Started Jul 26 04:52:06 PM PDT 24
Finished Jul 26 04:52:07 PM PDT 24
Peak memory 205912 kb
Host smart-f4a454f7-428b-424e-a88d-369ab383758b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849333645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.3
849333645
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.1929725870
Short name T834
Test name
Test status
Simulation time 239093869 ps
CPU time 2.62 seconds
Started Jul 26 04:52:04 PM PDT 24
Finished Jul 26 04:52:07 PM PDT 24
Peak memory 233040 kb
Host smart-ad39abfd-596a-44f3-bf7f-e34af4f6a25d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929725870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.1929725870
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.1212271030
Short name T611
Test name
Test status
Simulation time 43620673 ps
CPU time 0.81 seconds
Started Jul 26 04:52:03 PM PDT 24
Finished Jul 26 04:52:04 PM PDT 24
Peak memory 207352 kb
Host smart-69e5b344-d9d9-44a8-a95b-05281f32a1ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212271030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.1212271030
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.458154127
Short name T972
Test name
Test status
Simulation time 6289915635 ps
CPU time 17.97 seconds
Started Jul 26 04:52:06 PM PDT 24
Finished Jul 26 04:52:24 PM PDT 24
Peak memory 241804 kb
Host smart-b4d64380-7bfd-45c3-a47b-c08c00e80053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458154127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.458154127
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.3888773189
Short name T184
Test name
Test status
Simulation time 17274861249 ps
CPU time 81.35 seconds
Started Jul 26 04:52:04 PM PDT 24
Finished Jul 26 04:53:26 PM PDT 24
Peak memory 256316 kb
Host smart-ad499ea2-0400-47c0-8e34-9a3764a49a24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888773189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.3888773189
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.2149574239
Short name T559
Test name
Test status
Simulation time 3793835451 ps
CPU time 8.87 seconds
Started Jul 26 04:52:05 PM PDT 24
Finished Jul 26 04:52:15 PM PDT 24
Peak memory 241756 kb
Host smart-c4aed273-d7ba-46c1-a75f-78e1b2286cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149574239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.2149574239
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.3214332359
Short name T529
Test name
Test status
Simulation time 21815181 ps
CPU time 0.78 seconds
Started Jul 26 04:52:04 PM PDT 24
Finished Jul 26 04:52:05 PM PDT 24
Peak memory 216420 kb
Host smart-58ffa337-35a6-4c71-93c4-0e07ce7018e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214332359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds
.3214332359
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/1.spi_device_intercept.1312081864
Short name T194
Test name
Test status
Simulation time 1076846685 ps
CPU time 3.72 seconds
Started Jul 26 04:52:04 PM PDT 24
Finished Jul 26 04:52:08 PM PDT 24
Peak memory 225228 kb
Host smart-0ad09191-9c47-401d-b448-7056fc61e3cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312081864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.1312081864
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.919315300
Short name T202
Test name
Test status
Simulation time 2914196464 ps
CPU time 18.99 seconds
Started Jul 26 04:51:55 PM PDT 24
Finished Jul 26 04:52:15 PM PDT 24
Peak memory 241336 kb
Host smart-8fa3068c-3263-4978-8331-827017e2e4fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919315300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.919315300
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.2054339899
Short name T183
Test name
Test status
Simulation time 5527226644 ps
CPU time 18.25 seconds
Started Jul 26 04:52:04 PM PDT 24
Finished Jul 26 04:52:23 PM PDT 24
Peak memory 233444 kb
Host smart-416667f7-becb-4ec1-9d46-77a57c7660ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054339899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.2054339899
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.1928351978
Short name T246
Test name
Test status
Simulation time 417391398 ps
CPU time 6.58 seconds
Started Jul 26 04:51:57 PM PDT 24
Finished Jul 26 04:52:03 PM PDT 24
Peak memory 234576 kb
Host smart-925b7910-0046-4e06-8ff5-6cb308732b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928351978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.1928351978
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.20434222
Short name T312
Test name
Test status
Simulation time 3170808504 ps
CPU time 19.05 seconds
Started Jul 26 04:52:04 PM PDT 24
Finished Jul 26 04:52:24 PM PDT 24
Peak memory 224016 kb
Host smart-f9a4c0ff-20c4-404d-b82a-c65e9e6c4c21
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=20434222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_direct
.20434222
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.856124142
Short name T987
Test name
Test status
Simulation time 36800689023 ps
CPU time 324.1 seconds
Started Jul 26 04:52:07 PM PDT 24
Finished Jul 26 04:57:32 PM PDT 24
Peak memory 256624 kb
Host smart-f528a48d-613f-4b90-8746-2e016fa53c4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856124142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stress
_all.856124142
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.97379464
Short name T651
Test name
Test status
Simulation time 2312193396 ps
CPU time 12.71 seconds
Started Jul 26 04:51:57 PM PDT 24
Finished Jul 26 04:52:10 PM PDT 24
Peak memory 220160 kb
Host smart-529d474d-365b-4e3a-b074-b555aab4aaff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97379464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.97379464
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.1361930901
Short name T598
Test name
Test status
Simulation time 1275858308 ps
CPU time 5.91 seconds
Started Jul 26 04:51:56 PM PDT 24
Finished Jul 26 04:52:02 PM PDT 24
Peak memory 216992 kb
Host smart-3fed9d40-6776-4063-9d68-236eb4c63c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361930901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.1361930901
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.2567803383
Short name T786
Test name
Test status
Simulation time 39991125 ps
CPU time 0.66 seconds
Started Jul 26 04:51:57 PM PDT 24
Finished Jul 26 04:51:58 PM PDT 24
Peak memory 206172 kb
Host smart-48b4cd85-a945-47a5-a530-f71d2f2b8b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567803383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.2567803383
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.4250820723
Short name T1023
Test name
Test status
Simulation time 118626671 ps
CPU time 0.86 seconds
Started Jul 26 04:52:03 PM PDT 24
Finished Jul 26 04:52:04 PM PDT 24
Peak memory 207556 kb
Host smart-1f08c38d-5d20-4fcd-a5de-2d3aec6bfabc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250820723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.4250820723
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.4101496110
Short name T260
Test name
Test status
Simulation time 53331064 ps
CPU time 2.64 seconds
Started Jul 26 04:52:05 PM PDT 24
Finished Jul 26 04:52:08 PM PDT 24
Peak memory 233528 kb
Host smart-134a08b5-7fd9-4e5f-89bf-9492f16cc649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101496110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.4101496110
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.3678092305
Short name T622
Test name
Test status
Simulation time 302003964 ps
CPU time 4.47 seconds
Started Jul 26 04:52:43 PM PDT 24
Finished Jul 26 04:52:48 PM PDT 24
Peak memory 225328 kb
Host smart-5ae8d202-01e6-449e-9121-5de92522018d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678092305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.3678092305
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.4230844152
Short name T383
Test name
Test status
Simulation time 25604052 ps
CPU time 0.72 seconds
Started Jul 26 04:52:31 PM PDT 24
Finished Jul 26 04:52:31 PM PDT 24
Peak memory 206008 kb
Host smart-93fe224c-9d51-4de1-ad41-af4dc7f9df58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230844152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.4230844152
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.821812587
Short name T409
Test name
Test status
Simulation time 11276682271 ps
CPU time 49.47 seconds
Started Jul 26 04:52:47 PM PDT 24
Finished Jul 26 04:53:37 PM PDT 24
Peak memory 249916 kb
Host smart-23c42d72-6729-4580-9387-9af728b6041f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821812587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.821812587
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.3482016035
Short name T276
Test name
Test status
Simulation time 24000734582 ps
CPU time 64.19 seconds
Started Jul 26 04:52:41 PM PDT 24
Finished Jul 26 04:53:46 PM PDT 24
Peak memory 235804 kb
Host smart-6bdd4e18-7f3a-4ba5-8768-7ad19e4d43e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482016035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.3482016035
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.2515008185
Short name T755
Test name
Test status
Simulation time 2637305539 ps
CPU time 52.65 seconds
Started Jul 26 04:52:42 PM PDT 24
Finished Jul 26 04:53:35 PM PDT 24
Peak memory 239628 kb
Host smart-fea86de5-cbc0-4030-a4a7-3392c87207f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515008185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.2515008185
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.3673838222
Short name T736
Test name
Test status
Simulation time 2699033296 ps
CPU time 20.34 seconds
Started Jul 26 04:52:42 PM PDT 24
Finished Jul 26 04:53:02 PM PDT 24
Peak memory 249896 kb
Host smart-5c754b51-edc2-45fe-acf6-84d9818e0168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673838222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.3673838222
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.355485481
Short name T692
Test name
Test status
Simulation time 12346719332 ps
CPU time 83.99 seconds
Started Jul 26 04:52:43 PM PDT 24
Finished Jul 26 04:54:07 PM PDT 24
Peak memory 237588 kb
Host smart-26dc71e2-7326-4208-9754-90685b604ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355485481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmds
.355485481
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/10.spi_device_intercept.211685765
Short name T614
Test name
Test status
Simulation time 270952390 ps
CPU time 3.17 seconds
Started Jul 26 04:52:33 PM PDT 24
Finished Jul 26 04:52:37 PM PDT 24
Peak memory 225340 kb
Host smart-0316f275-76f0-4531-8537-785410fc4143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211685765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.211685765
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.2083766961
Short name T332
Test name
Test status
Simulation time 27441501 ps
CPU time 1.03 seconds
Started Jul 26 04:52:33 PM PDT 24
Finished Jul 26 04:52:34 PM PDT 24
Peak memory 217252 kb
Host smart-d5a13c44-6edd-41d2-9d0c-9269774a99fc
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083766961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.spi_device_mem_parity.2083766961
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.1711967719
Short name T704
Test name
Test status
Simulation time 1412894707 ps
CPU time 5.16 seconds
Started Jul 26 04:52:34 PM PDT 24
Finished Jul 26 04:52:40 PM PDT 24
Peak memory 233556 kb
Host smart-28452b41-6e72-46d7-b100-51403e22bb3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711967719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.1711967719
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.3148659689
Short name T922
Test name
Test status
Simulation time 2092203344 ps
CPU time 6.18 seconds
Started Jul 26 04:52:35 PM PDT 24
Finished Jul 26 04:52:41 PM PDT 24
Peak memory 233524 kb
Host smart-e2d6daa9-249c-4366-bc5d-646bbb73afc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148659689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.3148659689
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.537886116
Short name T579
Test name
Test status
Simulation time 571028519 ps
CPU time 7.91 seconds
Started Jul 26 04:52:43 PM PDT 24
Finished Jul 26 04:52:51 PM PDT 24
Peak memory 220000 kb
Host smart-3c430ae6-040e-4c77-bd53-f17cdc757386
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=537886116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dire
ct.537886116
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.3683302103
Short name T567
Test name
Test status
Simulation time 6495889830 ps
CPU time 33.85 seconds
Started Jul 26 04:52:33 PM PDT 24
Finished Jul 26 04:53:07 PM PDT 24
Peak memory 217060 kb
Host smart-58be0e3b-1f66-46b3-b943-458eef972924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683302103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.3683302103
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.3817487776
Short name T49
Test name
Test status
Simulation time 370210846 ps
CPU time 1.21 seconds
Started Jul 26 04:52:33 PM PDT 24
Finished Jul 26 04:52:34 PM PDT 24
Peak memory 208360 kb
Host smart-97dbbf2e-aac2-4a33-9f86-73082c9ef234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817487776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.3817487776
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.3462244399
Short name T654
Test name
Test status
Simulation time 153988719 ps
CPU time 1.42 seconds
Started Jul 26 04:52:58 PM PDT 24
Finished Jul 26 04:53:00 PM PDT 24
Peak memory 217036 kb
Host smart-a5fdeb97-3331-4ae9-ae43-9bc43234e9ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462244399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.3462244399
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.1654306360
Short name T461
Test name
Test status
Simulation time 87267039 ps
CPU time 0.72 seconds
Started Jul 26 04:52:33 PM PDT 24
Finished Jul 26 04:52:34 PM PDT 24
Peak memory 206592 kb
Host smart-67be7f83-3492-4fbb-b8cc-a87d18877629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654306360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.1654306360
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.746299295
Short name T613
Test name
Test status
Simulation time 1031076204 ps
CPU time 8.68 seconds
Started Jul 26 04:52:44 PM PDT 24
Finished Jul 26 04:52:53 PM PDT 24
Peak memory 233488 kb
Host smart-a996888d-7569-4dcc-894b-ca98bbe7360c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746299295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.746299295
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.2839678397
Short name T318
Test name
Test status
Simulation time 33879851 ps
CPU time 0.69 seconds
Started Jul 26 04:52:45 PM PDT 24
Finished Jul 26 04:52:46 PM PDT 24
Peak memory 206192 kb
Host smart-3d9698d9-2882-41ce-82aa-2ec0b656143d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839678397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
2839678397
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.4084881696
Short name T759
Test name
Test status
Simulation time 303086074 ps
CPU time 1.97 seconds
Started Jul 26 04:52:47 PM PDT 24
Finished Jul 26 04:52:49 PM PDT 24
Peak memory 224272 kb
Host smart-dd674dd3-1ec4-42df-96f8-1bc0c19d8b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084881696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.4084881696
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.1218630600
Short name T541
Test name
Test status
Simulation time 22600511 ps
CPU time 0.79 seconds
Started Jul 26 04:52:43 PM PDT 24
Finished Jul 26 04:52:44 PM PDT 24
Peak memory 206852 kb
Host smart-e47d2454-05d3-49b2-b39e-241d91f9aece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218630600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.1218630600
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.4103359115
Short name T750
Test name
Test status
Simulation time 75351676984 ps
CPU time 292.3 seconds
Started Jul 26 04:52:41 PM PDT 24
Finished Jul 26 04:57:34 PM PDT 24
Peak memory 256020 kb
Host smart-4cce859a-0bce-4409-8df9-67e79300df3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103359115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.4103359115
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.1557426451
Short name T470
Test name
Test status
Simulation time 22660909017 ps
CPU time 48.88 seconds
Started Jul 26 04:52:45 PM PDT 24
Finished Jul 26 04:53:34 PM PDT 24
Peak memory 238752 kb
Host smart-b49b6d2b-9ea9-4c52-ac42-4a29c4beb1a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557426451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.1557426451
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.2301669221
Short name T317
Test name
Test status
Simulation time 132381031 ps
CPU time 4.73 seconds
Started Jul 26 04:52:41 PM PDT 24
Finished Jul 26 04:52:46 PM PDT 24
Peak memory 225360 kb
Host smart-94b1f6be-b281-4c5b-84e0-d2ec2f784ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301669221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.2301669221
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.524691844
Short name T293
Test name
Test status
Simulation time 13919002256 ps
CPU time 94.81 seconds
Started Jul 26 04:52:42 PM PDT 24
Finished Jul 26 04:54:18 PM PDT 24
Peak memory 250016 kb
Host smart-82ac156f-9f71-477b-81c5-8862f35c734d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524691844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmds
.524691844
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_intercept.1369325013
Short name T792
Test name
Test status
Simulation time 1056079473 ps
CPU time 4.22 seconds
Started Jul 26 04:52:43 PM PDT 24
Finished Jul 26 04:52:48 PM PDT 24
Peak memory 225324 kb
Host smart-097e5564-2f60-4f77-94ae-5fc0f81c0a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369325013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.1369325013
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.1761754819
Short name T828
Test name
Test status
Simulation time 129014365 ps
CPU time 4.29 seconds
Started Jul 26 04:52:41 PM PDT 24
Finished Jul 26 04:52:46 PM PDT 24
Peak memory 233448 kb
Host smart-b9a48f9a-a33e-46b3-badd-f461fba0c378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761754819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.1761754819
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.2372556302
Short name T771
Test name
Test status
Simulation time 31471146 ps
CPU time 1.05 seconds
Started Jul 26 04:52:43 PM PDT 24
Finished Jul 26 04:52:45 PM PDT 24
Peak memory 218480 kb
Host smart-8dca614a-29d8-4f54-9fb4-1a3dcd30c4d8
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372556302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.spi_device_mem_parity.2372556302
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.236470092
Short name T411
Test name
Test status
Simulation time 3980753489 ps
CPU time 11.83 seconds
Started Jul 26 04:52:45 PM PDT 24
Finished Jul 26 04:52:57 PM PDT 24
Peak memory 233520 kb
Host smart-0466b97c-34a2-4209-adb9-2fad33fef33e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236470092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swap
.236470092
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.1884645417
Short name T606
Test name
Test status
Simulation time 1035539639 ps
CPU time 2.51 seconds
Started Jul 26 04:52:44 PM PDT 24
Finished Jul 26 04:52:47 PM PDT 24
Peak memory 225324 kb
Host smart-a29c94d9-ad55-4b4e-8264-c2d27b93d2b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884645417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.1884645417
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.1956739204
Short name T145
Test name
Test status
Simulation time 447827337 ps
CPU time 3.78 seconds
Started Jul 26 04:52:41 PM PDT 24
Finished Jul 26 04:52:45 PM PDT 24
Peak memory 219540 kb
Host smart-39c8d3cf-81f0-4c81-a6ad-b6f8f5c23112
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1956739204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.1956739204
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.2440619225
Short name T996
Test name
Test status
Simulation time 273063718 ps
CPU time 0.93 seconds
Started Jul 26 04:52:43 PM PDT 24
Finished Jul 26 04:52:44 PM PDT 24
Peak memory 207492 kb
Host smart-49674ab9-1baa-4e96-b1ce-42178f2e3f22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440619225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.2440619225
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.1238975259
Short name T933
Test name
Test status
Simulation time 647442620 ps
CPU time 1.59 seconds
Started Jul 26 04:52:42 PM PDT 24
Finished Jul 26 04:52:45 PM PDT 24
Peak memory 208628 kb
Host smart-3468b2b2-aef8-43d7-b1ce-ef97efa836d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238975259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.1238975259
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.779554174
Short name T514
Test name
Test status
Simulation time 18681930 ps
CPU time 1.01 seconds
Started Jul 26 04:52:46 PM PDT 24
Finished Jul 26 04:52:47 PM PDT 24
Peak memory 207640 kb
Host smart-2f51c92b-3dce-411a-aad3-1f7371b5c618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779554174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.779554174
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.366370986
Short name T864
Test name
Test status
Simulation time 12889090 ps
CPU time 0.71 seconds
Started Jul 26 04:52:46 PM PDT 24
Finished Jul 26 04:52:46 PM PDT 24
Peak memory 206076 kb
Host smart-a5636914-e844-4b0f-b135-4ad88ff0864e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366370986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.366370986
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.3752325454
Short name T582
Test name
Test status
Simulation time 220005507 ps
CPU time 4.17 seconds
Started Jul 26 04:52:41 PM PDT 24
Finished Jul 26 04:52:46 PM PDT 24
Peak memory 233448 kb
Host smart-0ea60c04-d6cc-4b1c-9bea-9b58f81a0855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752325454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.3752325454
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.4263139750
Short name T633
Test name
Test status
Simulation time 15295351 ps
CPU time 0.73 seconds
Started Jul 26 04:52:43 PM PDT 24
Finished Jul 26 04:52:45 PM PDT 24
Peak memory 205916 kb
Host smart-e3361f02-5fa4-4e5f-8e15-c2d8a61c8d2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263139750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
4263139750
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.1458649064
Short name T604
Test name
Test status
Simulation time 4929934987 ps
CPU time 13.01 seconds
Started Jul 26 04:52:39 PM PDT 24
Finished Jul 26 04:52:52 PM PDT 24
Peak memory 233424 kb
Host smart-d7e6828c-0bdf-453a-995a-c3b316051587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458649064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.1458649064
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.3172804738
Short name T495
Test name
Test status
Simulation time 15635540 ps
CPU time 0.8 seconds
Started Jul 26 04:52:43 PM PDT 24
Finished Jul 26 04:52:44 PM PDT 24
Peak memory 207116 kb
Host smart-b77c6aae-114b-48c0-9062-279df4c22885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172804738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.3172804738
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.810592227
Short name T309
Test name
Test status
Simulation time 18184575 ps
CPU time 0.78 seconds
Started Jul 26 04:52:45 PM PDT 24
Finished Jul 26 04:52:46 PM PDT 24
Peak memory 216544 kb
Host smart-b9a3a4ea-1ce4-4708-acc0-716aa25472a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810592227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.810592227
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.3765740183
Short name T420
Test name
Test status
Simulation time 136401543 ps
CPU time 6.4 seconds
Started Jul 26 04:52:45 PM PDT 24
Finished Jul 26 04:52:52 PM PDT 24
Peak memory 225312 kb
Host smart-bb1cda5e-934f-48d9-ae33-e5c9ae50463b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765740183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.3765740183
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.2801434534
Short name T87
Test name
Test status
Simulation time 184635301548 ps
CPU time 64.97 seconds
Started Jul 26 04:52:43 PM PDT 24
Finished Jul 26 04:53:49 PM PDT 24
Peak memory 250004 kb
Host smart-ed48db0e-8413-4a65-9c06-64941a7286fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801434534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmd
s.2801434534
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_intercept.1406448935
Short name T580
Test name
Test status
Simulation time 1365588965 ps
CPU time 12.72 seconds
Started Jul 26 04:52:41 PM PDT 24
Finished Jul 26 04:52:55 PM PDT 24
Peak memory 233520 kb
Host smart-5aca0fa0-53bb-4d9f-9a6e-6225674a2fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406448935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.1406448935
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.3585788763
Short name T5
Test name
Test status
Simulation time 12205721454 ps
CPU time 32.58 seconds
Started Jul 26 04:52:45 PM PDT 24
Finished Jul 26 04:53:18 PM PDT 24
Peak memory 238152 kb
Host smart-1743b91b-055c-4652-b4dd-1659da2135cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585788763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.3585788763
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.1801250791
Short name T903
Test name
Test status
Simulation time 41038239 ps
CPU time 1.03 seconds
Started Jul 26 04:52:40 PM PDT 24
Finished Jul 26 04:52:41 PM PDT 24
Peak memory 217288 kb
Host smart-fe6a3b0e-a46d-4967-9264-356c7c9e4eba
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801250791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.spi_device_mem_parity.1801250791
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.481866047
Short name T892
Test name
Test status
Simulation time 2501900007 ps
CPU time 7.26 seconds
Started Jul 26 04:52:41 PM PDT 24
Finished Jul 26 04:52:48 PM PDT 24
Peak memory 233600 kb
Host smart-15d2fde5-8ce3-45de-8baf-d8c67ed6f868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481866047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swap
.481866047
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.117319959
Short name T231
Test name
Test status
Simulation time 1549032929 ps
CPU time 2.8 seconds
Started Jul 26 04:52:47 PM PDT 24
Finished Jul 26 04:52:50 PM PDT 24
Peak memory 225212 kb
Host smart-b189e97f-607f-496f-860f-98809f5dc985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117319959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.117319959
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.2740970883
Short name T805
Test name
Test status
Simulation time 153102857 ps
CPU time 4.5 seconds
Started Jul 26 04:52:41 PM PDT 24
Finished Jul 26 04:52:45 PM PDT 24
Peak memory 223724 kb
Host smart-e5a11b4d-def0-4a9c-9a1f-8ef654c8ce06
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2740970883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.2740970883
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.4131460211
Short name T766
Test name
Test status
Simulation time 138538314915 ps
CPU time 242.95 seconds
Started Jul 26 04:52:44 PM PDT 24
Finished Jul 26 04:56:47 PM PDT 24
Peak memory 249888 kb
Host smart-1a1f0926-27c2-48e7-82c6-a72814e189c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131460211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.4131460211
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.3337902295
Short name T894
Test name
Test status
Simulation time 1904629552 ps
CPU time 10.49 seconds
Started Jul 26 04:52:46 PM PDT 24
Finished Jul 26 04:52:57 PM PDT 24
Peak memory 216972 kb
Host smart-0d4af056-014a-42c9-a861-73b8dd31173e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337902295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.3337902295
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.56903716
Short name T525
Test name
Test status
Simulation time 4096221228 ps
CPU time 6.03 seconds
Started Jul 26 04:52:43 PM PDT 24
Finished Jul 26 04:52:49 PM PDT 24
Peak memory 217180 kb
Host smart-70170646-66de-4698-85fe-7f18ff2e4bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56903716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.56903716
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.345352434
Short name T781
Test name
Test status
Simulation time 155003211 ps
CPU time 1.09 seconds
Started Jul 26 04:52:47 PM PDT 24
Finished Jul 26 04:52:48 PM PDT 24
Peak memory 208024 kb
Host smart-171a705d-59d5-4628-8ad9-06685550cf01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345352434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.345352434
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.120114077
Short name T476
Test name
Test status
Simulation time 74488531 ps
CPU time 0.96 seconds
Started Jul 26 04:52:43 PM PDT 24
Finished Jul 26 04:52:44 PM PDT 24
Peak memory 206696 kb
Host smart-fcf403a6-86be-436e-a648-263ee1085f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120114077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.120114077
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.3042283013
Short name T266
Test name
Test status
Simulation time 98921352920 ps
CPU time 17.54 seconds
Started Jul 26 04:52:44 PM PDT 24
Finished Jul 26 04:53:02 PM PDT 24
Peak memory 233624 kb
Host smart-65a7ed67-0502-412b-95f3-07592c3a2789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042283013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.3042283013
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.689091139
Short name T53
Test name
Test status
Simulation time 42684100 ps
CPU time 0.71 seconds
Started Jul 26 04:52:57 PM PDT 24
Finished Jul 26 04:52:58 PM PDT 24
Peak memory 205952 kb
Host smart-cbe327ec-14fb-4489-b8cc-8b222278df7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689091139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.689091139
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.233061007
Short name T901
Test name
Test status
Simulation time 63986002 ps
CPU time 2.96 seconds
Started Jul 26 04:52:52 PM PDT 24
Finished Jul 26 04:52:55 PM PDT 24
Peak memory 233460 kb
Host smart-b7db9ac1-3034-444b-99ce-2a563a9d3adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233061007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.233061007
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.3395019878
Short name T405
Test name
Test status
Simulation time 53606486 ps
CPU time 0.79 seconds
Started Jul 26 04:52:43 PM PDT 24
Finished Jul 26 04:52:45 PM PDT 24
Peak memory 207120 kb
Host smart-be3849e7-3b1b-47e6-9f10-d963d150618d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395019878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.3395019878
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.3973139541
Short name T174
Test name
Test status
Simulation time 58185797546 ps
CPU time 137.45 seconds
Started Jul 26 04:52:52 PM PDT 24
Finished Jul 26 04:55:09 PM PDT 24
Peak memory 258164 kb
Host smart-904c5610-0fc4-4b0c-a62c-400aac1b0c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973139541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.3973139541
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.1677404046
Short name T178
Test name
Test status
Simulation time 147941721399 ps
CPU time 326.64 seconds
Started Jul 26 04:52:52 PM PDT 24
Finished Jul 26 04:58:19 PM PDT 24
Peak memory 266452 kb
Host smart-0c3227f3-6a02-45a4-8377-7a6f233a1fe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677404046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.1677404046
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.33927660
Short name T201
Test name
Test status
Simulation time 17048817890 ps
CPU time 52.79 seconds
Started Jul 26 04:52:52 PM PDT 24
Finished Jul 26 04:53:45 PM PDT 24
Peak memory 233612 kb
Host smart-8b5d6872-f924-4b55-a987-bebae9a160c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33927660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idle.33927660
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.553647922
Short name T297
Test name
Test status
Simulation time 4278841509 ps
CPU time 18.53 seconds
Started Jul 26 04:52:52 PM PDT 24
Finished Jul 26 04:53:10 PM PDT 24
Peak memory 233592 kb
Host smart-3e273dbb-7627-4c84-bf27-ea9016538e50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553647922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.553647922
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.3318380656
Short name T1019
Test name
Test status
Simulation time 15995681997 ps
CPU time 78.52 seconds
Started Jul 26 04:52:56 PM PDT 24
Finished Jul 26 04:54:15 PM PDT 24
Peak memory 257636 kb
Host smart-c0b4b7e4-42d3-4e5b-83cd-b7504bef8485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318380656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmd
s.3318380656
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/13.spi_device_intercept.99670850
Short name T265
Test name
Test status
Simulation time 979644458 ps
CPU time 5 seconds
Started Jul 26 04:52:50 PM PDT 24
Finished Jul 26 04:52:55 PM PDT 24
Peak memory 233520 kb
Host smart-c4f0c5e9-96b3-41bf-b9d2-a2e52dc11eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99670850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.99670850
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.2866873271
Short name T943
Test name
Test status
Simulation time 6126815025 ps
CPU time 56.13 seconds
Started Jul 26 04:52:52 PM PDT 24
Finished Jul 26 04:53:49 PM PDT 24
Peak memory 241248 kb
Host smart-0f17d6eb-a3a5-4391-8964-743109ac3c25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866873271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.2866873271
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.3693788811
Short name T415
Test name
Test status
Simulation time 25918599 ps
CPU time 1.03 seconds
Started Jul 26 04:52:42 PM PDT 24
Finished Jul 26 04:52:43 PM PDT 24
Peak memory 217216 kb
Host smart-60b5212a-8a55-4c82-91df-edcbfa2c1524
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693788811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.spi_device_mem_parity.3693788811
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.3422826157
Short name T268
Test name
Test status
Simulation time 3079529539 ps
CPU time 8.98 seconds
Started Jul 26 04:52:44 PM PDT 24
Finished Jul 26 04:52:53 PM PDT 24
Peak memory 233548 kb
Host smart-6ff26b23-aff9-4519-a81d-d075e51a47ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422826157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.3422826157
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.514881549
Short name T507
Test name
Test status
Simulation time 14870758797 ps
CPU time 11.86 seconds
Started Jul 26 04:52:43 PM PDT 24
Finished Jul 26 04:52:55 PM PDT 24
Peak memory 233312 kb
Host smart-a33714a3-1204-42ca-84a6-2c9b96f24c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514881549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.514881549
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.546479828
Short name T449
Test name
Test status
Simulation time 3563595612 ps
CPU time 9.59 seconds
Started Jul 26 04:52:51 PM PDT 24
Finished Jul 26 04:53:01 PM PDT 24
Peak memory 223600 kb
Host smart-82d8e1b3-7fc1-4fbc-8d14-b1efd675c903
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=546479828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dire
ct.546479828
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.2653810304
Short name T21
Test name
Test status
Simulation time 31636905 ps
CPU time 0.93 seconds
Started Jul 26 04:52:54 PM PDT 24
Finished Jul 26 04:52:55 PM PDT 24
Peak memory 207992 kb
Host smart-ae21b870-1437-4b55-8232-d08852309396
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653810304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.2653810304
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.3792560180
Short name T1029
Test name
Test status
Simulation time 18018612510 ps
CPU time 28.79 seconds
Started Jul 26 04:52:44 PM PDT 24
Finished Jul 26 04:53:14 PM PDT 24
Peak memory 217056 kb
Host smart-8b0240fd-6fb5-4500-8ef2-a555b9f0fb0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792560180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.3792560180
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.3792968552
Short name T900
Test name
Test status
Simulation time 34505350188 ps
CPU time 13.64 seconds
Started Jul 26 04:52:44 PM PDT 24
Finished Jul 26 04:52:58 PM PDT 24
Peak memory 216984 kb
Host smart-baf24315-7c1d-40d1-a523-d4c61ba30645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792968552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.3792968552
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.1045846564
Short name T442
Test name
Test status
Simulation time 127182491 ps
CPU time 1.35 seconds
Started Jul 26 04:52:44 PM PDT 24
Finished Jul 26 04:52:46 PM PDT 24
Peak memory 216988 kb
Host smart-cb2c898c-99a8-409a-b56f-84b90b24fb22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045846564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.1045846564
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.1287265120
Short name T426
Test name
Test status
Simulation time 76142896 ps
CPU time 0.79 seconds
Started Jul 26 04:52:42 PM PDT 24
Finished Jul 26 04:52:43 PM PDT 24
Peak memory 206644 kb
Host smart-29bc3bdb-9681-4bdb-a9b4-f00f3e9dae6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287265120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.1287265120
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.964604016
Short name T599
Test name
Test status
Simulation time 5501023708 ps
CPU time 13.26 seconds
Started Jul 26 04:52:51 PM PDT 24
Finished Jul 26 04:53:05 PM PDT 24
Peak memory 241560 kb
Host smart-9e8786ac-9195-4ae7-a82a-a1b2dfc517b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964604016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.964604016
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.3585568590
Short name T333
Test name
Test status
Simulation time 36395322 ps
CPU time 0.77 seconds
Started Jul 26 04:52:50 PM PDT 24
Finished Jul 26 04:52:51 PM PDT 24
Peak memory 205864 kb
Host smart-d627be2d-3a90-49a5-b26f-c9602de16935
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585568590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
3585568590
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.4154166252
Short name T700
Test name
Test status
Simulation time 210651482 ps
CPU time 3.11 seconds
Started Jul 26 04:52:50 PM PDT 24
Finished Jul 26 04:52:53 PM PDT 24
Peak memory 233520 kb
Host smart-67a75426-16d3-439b-b3b7-dff29faa2266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154166252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.4154166252
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.1692030197
Short name T430
Test name
Test status
Simulation time 21371686 ps
CPU time 0.79 seconds
Started Jul 26 04:52:57 PM PDT 24
Finished Jul 26 04:52:58 PM PDT 24
Peak memory 207148 kb
Host smart-a4c5a44a-b609-4106-997f-4827d9b49c08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692030197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.1692030197
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.1454258092
Short name T648
Test name
Test status
Simulation time 3124637134 ps
CPU time 34.17 seconds
Started Jul 26 04:52:50 PM PDT 24
Finished Jul 26 04:53:24 PM PDT 24
Peak memory 250016 kb
Host smart-8d4b2f0e-3abd-41f1-bb42-9381897729d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454258092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.1454258092
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.2236072861
Short name T872
Test name
Test status
Simulation time 20740825184 ps
CPU time 222.97 seconds
Started Jul 26 04:52:51 PM PDT 24
Finished Jul 26 04:56:35 PM PDT 24
Peak memory 256976 kb
Host smart-3e35f805-7a6c-4d8d-9813-086deb7bd743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236072861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.2236072861
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.2739782381
Short name T41
Test name
Test status
Simulation time 19003804728 ps
CPU time 83.1 seconds
Started Jul 26 04:52:49 PM PDT 24
Finished Jul 26 04:54:12 PM PDT 24
Peak memory 253172 kb
Host smart-266f2f0e-bd04-4a5e-aeb4-3c0aa1a58d42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739782381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmd
s.2739782381
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_intercept.1854229738
Short name T839
Test name
Test status
Simulation time 1092970772 ps
CPU time 11.24 seconds
Started Jul 26 04:52:49 PM PDT 24
Finished Jul 26 04:53:00 PM PDT 24
Peak memory 233420 kb
Host smart-bfe856f0-9c94-4cd3-9083-3e1cda028fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854229738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.1854229738
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.1908023337
Short name T263
Test name
Test status
Simulation time 11797249554 ps
CPU time 100.84 seconds
Started Jul 26 04:52:49 PM PDT 24
Finished Jul 26 04:54:30 PM PDT 24
Peak memory 241440 kb
Host smart-563da67b-c8a9-4a6c-9e4e-0705a3d5aea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908023337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.1908023337
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.1187449412
Short name T935
Test name
Test status
Simulation time 100074217 ps
CPU time 1.1 seconds
Started Jul 26 04:52:53 PM PDT 24
Finished Jul 26 04:52:55 PM PDT 24
Peak memory 217272 kb
Host smart-3b97be91-545e-4443-a383-5973dafc2c8a
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187449412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.spi_device_mem_parity.1187449412
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.1884144370
Short name T545
Test name
Test status
Simulation time 107492127835 ps
CPU time 17.64 seconds
Started Jul 26 04:52:54 PM PDT 24
Finished Jul 26 04:53:12 PM PDT 24
Peak memory 225248 kb
Host smart-f66ffcb0-cd93-40b8-a688-1086b48001a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884144370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.1884144370
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.2621101241
Short name T856
Test name
Test status
Simulation time 59529512 ps
CPU time 2.77 seconds
Started Jul 26 04:52:57 PM PDT 24
Finished Jul 26 04:53:00 PM PDT 24
Peak memory 225216 kb
Host smart-ae7c7997-cda6-4e7e-83c8-766305c0b51b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621101241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.2621101241
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.2305944073
Short name T660
Test name
Test status
Simulation time 1440372751 ps
CPU time 10.69 seconds
Started Jul 26 04:52:51 PM PDT 24
Finished Jul 26 04:53:02 PM PDT 24
Peak memory 223188 kb
Host smart-c36b068f-0d39-4756-bbc8-e3c470baa1c2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2305944073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.2305944073
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.2531365883
Short name T357
Test name
Test status
Simulation time 60361659 ps
CPU time 0.92 seconds
Started Jul 26 04:53:02 PM PDT 24
Finished Jul 26 04:53:04 PM PDT 24
Peak memory 207888 kb
Host smart-59b24c8c-06f4-44e7-b451-83f98ae6e18f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531365883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.2531365883
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.2579201510
Short name T861
Test name
Test status
Simulation time 10352669794 ps
CPU time 16.77 seconds
Started Jul 26 04:52:51 PM PDT 24
Finished Jul 26 04:53:08 PM PDT 24
Peak memory 220592 kb
Host smart-5551c1f0-f991-4d27-8663-8ec26ffcffc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579201510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.2579201510
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.1422505828
Short name T565
Test name
Test status
Simulation time 11128356149 ps
CPU time 18.3 seconds
Started Jul 26 04:52:51 PM PDT 24
Finished Jul 26 04:53:10 PM PDT 24
Peak memory 217100 kb
Host smart-f556e884-1544-46e3-96ca-764def5ea4e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422505828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.1422505828
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.230805482
Short name T976
Test name
Test status
Simulation time 84149813 ps
CPU time 2.24 seconds
Started Jul 26 04:52:51 PM PDT 24
Finished Jul 26 04:52:54 PM PDT 24
Peak memory 217000 kb
Host smart-2f088075-440c-48cb-916f-dc29ac336013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230805482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.230805482
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.151910351
Short name T970
Test name
Test status
Simulation time 206542510 ps
CPU time 1 seconds
Started Jul 26 04:52:52 PM PDT 24
Finished Jul 26 04:52:53 PM PDT 24
Peak memory 207668 kb
Host smart-8d856968-d577-4303-9e28-f86eae2c7097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151910351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.151910351
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.1782564178
Short name T814
Test name
Test status
Simulation time 11657869382 ps
CPU time 20.07 seconds
Started Jul 26 04:53:02 PM PDT 24
Finished Jul 26 04:53:23 PM PDT 24
Peak memory 240012 kb
Host smart-363967bb-0dc1-4e04-8902-f8ac93d5a271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782564178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.1782564178
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.1828902263
Short name T998
Test name
Test status
Simulation time 16179484 ps
CPU time 0.74 seconds
Started Jul 26 04:53:03 PM PDT 24
Finished Jul 26 04:53:04 PM PDT 24
Peak memory 205944 kb
Host smart-7eae857a-2cf9-48ee-8801-d8d7fb910149
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828902263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
1828902263
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.1235512183
Short name T623
Test name
Test status
Simulation time 328571776 ps
CPU time 4.01 seconds
Started Jul 26 04:52:57 PM PDT 24
Finished Jul 26 04:53:01 PM PDT 24
Peak memory 233020 kb
Host smart-6e214a0a-adca-4bdf-a615-683ea4f8eb06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235512183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.1235512183
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.3837700476
Short name T460
Test name
Test status
Simulation time 52501386 ps
CPU time 0.79 seconds
Started Jul 26 04:52:50 PM PDT 24
Finished Jul 26 04:52:51 PM PDT 24
Peak memory 207204 kb
Host smart-8d3cbfc9-8f05-4dda-b53f-992049e50e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837700476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.3837700476
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.982013284
Short name T656
Test name
Test status
Simulation time 23023857028 ps
CPU time 128.17 seconds
Started Jul 26 04:52:49 PM PDT 24
Finished Jul 26 04:54:58 PM PDT 24
Peak memory 265088 kb
Host smart-63260f5d-1002-477b-b822-1cfd100d72cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982013284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.982013284
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.2518337220
Short name T728
Test name
Test status
Simulation time 6336649359 ps
CPU time 85.29 seconds
Started Jul 26 04:52:52 PM PDT 24
Finished Jul 26 04:54:17 PM PDT 24
Peak memory 258240 kb
Host smart-d18c84d6-a610-4bf2-801e-61ed68c942f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518337220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.2518337220
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.1283298677
Short name T67
Test name
Test status
Simulation time 32664371041 ps
CPU time 58 seconds
Started Jul 26 04:53:03 PM PDT 24
Finished Jul 26 04:54:01 PM PDT 24
Peak memory 240700 kb
Host smart-d7e062fc-2101-4c38-9125-354a26a60fef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283298677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.1283298677
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.2582193759
Short name T140
Test name
Test status
Simulation time 463138175 ps
CPU time 9.75 seconds
Started Jul 26 04:52:51 PM PDT 24
Finished Jul 26 04:53:01 PM PDT 24
Peak memory 233504 kb
Host smart-6dad486b-545e-4187-933b-10cd57e95999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582193759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.2582193759
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.3297189388
Short name T463
Test name
Test status
Simulation time 18800211878 ps
CPU time 44.17 seconds
Started Jul 26 04:52:49 PM PDT 24
Finished Jul 26 04:53:33 PM PDT 24
Peak memory 239672 kb
Host smart-c5003041-5631-4aaf-8c76-47c4650e6420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297189388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmd
s.3297189388
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/15.spi_device_intercept.1601590399
Short name T790
Test name
Test status
Simulation time 254402456 ps
CPU time 6.46 seconds
Started Jul 26 04:52:57 PM PDT 24
Finished Jul 26 04:53:03 PM PDT 24
Peak memory 225276 kb
Host smart-1fc28272-bccd-4f93-962a-dc7b620da6cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601590399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.1601590399
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.778478774
Short name T71
Test name
Test status
Simulation time 8539703516 ps
CPU time 80.88 seconds
Started Jul 26 04:52:54 PM PDT 24
Finished Jul 26 04:54:15 PM PDT 24
Peak memory 239932 kb
Host smart-b840823b-411d-4eab-8e8a-34ba2d2981e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778478774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.778478774
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.2702266426
Short name T34
Test name
Test status
Simulation time 55742746 ps
CPU time 0.99 seconds
Started Jul 26 04:52:53 PM PDT 24
Finished Jul 26 04:52:55 PM PDT 24
Peak memory 217220 kb
Host smart-b31059f5-e546-4d3d-bb45-c3c2765c5271
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702266426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.2702266426
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.2733565043
Short name T548
Test name
Test status
Simulation time 417906829 ps
CPU time 7.38 seconds
Started Jul 26 04:53:03 PM PDT 24
Finished Jul 26 04:53:10 PM PDT 24
Peak memory 233492 kb
Host smart-c439c725-ac67-4d6b-8fa2-99d7176bf542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733565043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.2733565043
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.1848944088
Short name T804
Test name
Test status
Simulation time 59603017 ps
CPU time 2.17 seconds
Started Jul 26 04:52:57 PM PDT 24
Finished Jul 26 04:52:59 PM PDT 24
Peak memory 232920 kb
Host smart-c3919d5f-1da4-427a-9cc9-83f3b5eabcf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848944088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.1848944088
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.1336705011
Short name T968
Test name
Test status
Simulation time 1570626620 ps
CPU time 18.68 seconds
Started Jul 26 04:53:02 PM PDT 24
Finished Jul 26 04:53:21 PM PDT 24
Peak memory 222452 kb
Host smart-e4b82ce1-a3f8-45c0-88b2-3fb76b78c126
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1336705011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.1336705011
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.4113346899
Short name T789
Test name
Test status
Simulation time 62891074934 ps
CPU time 625.54 seconds
Started Jul 26 04:52:57 PM PDT 24
Finished Jul 26 05:03:22 PM PDT 24
Peak memory 271092 kb
Host smart-338efe9d-3049-4c57-bcc9-b0a22d5ea3fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113346899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.4113346899
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.803952589
Short name T380
Test name
Test status
Simulation time 94682808 ps
CPU time 0.7 seconds
Started Jul 26 04:52:53 PM PDT 24
Finished Jul 26 04:52:54 PM PDT 24
Peak memory 206144 kb
Host smart-89f404c0-16dd-4c2d-962d-8755240fc42f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803952589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.803952589
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.1536119814
Short name T591
Test name
Test status
Simulation time 56120320312 ps
CPU time 22.78 seconds
Started Jul 26 04:52:51 PM PDT 24
Finished Jul 26 04:53:13 PM PDT 24
Peak memory 217048 kb
Host smart-6a087c04-e4ab-43b5-9a0c-24cf8c1ba729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536119814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.1536119814
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.2979864180
Short name T362
Test name
Test status
Simulation time 53976085 ps
CPU time 1.16 seconds
Started Jul 26 04:52:50 PM PDT 24
Finished Jul 26 04:52:52 PM PDT 24
Peak memory 208624 kb
Host smart-ea094332-ed4c-4f36-bad3-83a4917809cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979864180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.2979864180
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.1509279438
Short name T1018
Test name
Test status
Simulation time 195280184 ps
CPU time 0.98 seconds
Started Jul 26 04:52:53 PM PDT 24
Finished Jul 26 04:52:55 PM PDT 24
Peak memory 207676 kb
Host smart-c9c42d21-c813-4909-a3d2-188b1b88bedf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509279438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.1509279438
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.2012451740
Short name T705
Test name
Test status
Simulation time 2729909369 ps
CPU time 6 seconds
Started Jul 26 04:52:57 PM PDT 24
Finished Jul 26 04:53:03 PM PDT 24
Peak memory 233532 kb
Host smart-1eb30785-f6de-4bd5-9cd0-4e0abd3a0fa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012451740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.2012451740
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.884244622
Short name T58
Test name
Test status
Simulation time 35523927 ps
CPU time 0.68 seconds
Started Jul 26 04:53:03 PM PDT 24
Finished Jul 26 04:53:04 PM PDT 24
Peak memory 205964 kb
Host smart-1e220214-eff4-404a-9579-0bd99381fac5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884244622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.884244622
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.668073510
Short name T454
Test name
Test status
Simulation time 250760080 ps
CPU time 4.82 seconds
Started Jul 26 04:53:02 PM PDT 24
Finished Jul 26 04:53:07 PM PDT 24
Peak memory 225336 kb
Host smart-bc30d1a0-5e9a-4720-8ecc-4015d378a2bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668073510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.668073510
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.278016226
Short name T52
Test name
Test status
Simulation time 17927925 ps
CPU time 0.78 seconds
Started Jul 26 04:52:52 PM PDT 24
Finished Jul 26 04:52:53 PM PDT 24
Peak memory 207476 kb
Host smart-2b0fc75e-2dd4-4ff3-84e4-747da97ecd29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278016226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.278016226
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.2201396337
Short name T200
Test name
Test status
Simulation time 9175359856 ps
CPU time 60.9 seconds
Started Jul 26 04:53:02 PM PDT 24
Finished Jul 26 04:54:03 PM PDT 24
Peak memory 236336 kb
Host smart-3dc7f32c-d407-4afd-ac55-ea0159727741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201396337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.2201396337
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.439300067
Short name T187
Test name
Test status
Simulation time 3069954128 ps
CPU time 61 seconds
Started Jul 26 04:53:04 PM PDT 24
Finished Jul 26 04:54:05 PM PDT 24
Peak memory 255112 kb
Host smart-9e6f3aee-5e08-47bb-b8cc-b8659dc13efb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439300067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.439300067
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.1337717145
Short name T1003
Test name
Test status
Simulation time 8732932271 ps
CPU time 22.98 seconds
Started Jul 26 04:53:03 PM PDT 24
Finished Jul 26 04:53:26 PM PDT 24
Peak memory 250032 kb
Host smart-b7eeb7bb-0eca-4fdb-a370-c00c5452319d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337717145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.1337717145
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.3211805556
Short name T253
Test name
Test status
Simulation time 232028090367 ps
CPU time 170.34 seconds
Started Jul 26 04:53:06 PM PDT 24
Finished Jul 26 04:55:57 PM PDT 24
Peak memory 251212 kb
Host smart-935fc5ba-46f7-4550-9001-08c12f1284cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211805556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmd
s.3211805556
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/16.spi_device_intercept.521066687
Short name T663
Test name
Test status
Simulation time 534629366 ps
CPU time 5.43 seconds
Started Jul 26 04:53:02 PM PDT 24
Finished Jul 26 04:53:07 PM PDT 24
Peak memory 225204 kb
Host smart-0533b949-5be9-431a-8a3a-80d6c4f3d5bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521066687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.521066687
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.4224765549
Short name T366
Test name
Test status
Simulation time 10691874031 ps
CPU time 86.8 seconds
Started Jul 26 04:53:04 PM PDT 24
Finished Jul 26 04:54:31 PM PDT 24
Peak memory 252824 kb
Host smart-65a7e379-6f7e-4f62-9f43-6c886730e13d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224765549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.4224765549
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.872090677
Short name T875
Test name
Test status
Simulation time 146185857 ps
CPU time 1.09 seconds
Started Jul 26 04:52:53 PM PDT 24
Finished Jul 26 04:52:54 PM PDT 24
Peak memory 217288 kb
Host smart-dd7f2b18-f5d2-4d40-82d7-91262377d201
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872090677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.spi_device_mem_parity.872090677
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.2346292934
Short name T739
Test name
Test status
Simulation time 2405455911 ps
CPU time 8.72 seconds
Started Jul 26 04:53:01 PM PDT 24
Finished Jul 26 04:53:10 PM PDT 24
Peak memory 225228 kb
Host smart-07c7a674-0f28-4e86-9aba-9962196bcf55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346292934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.2346292934
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.3710325013
Short name T228
Test name
Test status
Simulation time 2895801017 ps
CPU time 10.75 seconds
Started Jul 26 04:53:01 PM PDT 24
Finished Jul 26 04:53:12 PM PDT 24
Peak memory 238460 kb
Host smart-9be60599-d7db-4502-b576-b212c92d1e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710325013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.3710325013
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.96115740
Short name T659
Test name
Test status
Simulation time 300292512 ps
CPU time 4.4 seconds
Started Jul 26 04:53:03 PM PDT 24
Finished Jul 26 04:53:08 PM PDT 24
Peak memory 219400 kb
Host smart-c98a386c-d412-41fb-8847-786c9876df64
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=96115740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_direc
t.96115740
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.1385311754
Short name T1010
Test name
Test status
Simulation time 84785241139 ps
CPU time 802.58 seconds
Started Jul 26 04:53:02 PM PDT 24
Finished Jul 26 05:06:25 PM PDT 24
Peak memory 272012 kb
Host smart-54189a46-4b01-4ab8-8633-5c1078b40674
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385311754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.1385311754
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.3785474164
Short name T590
Test name
Test status
Simulation time 2470954515 ps
CPU time 27.03 seconds
Started Jul 26 04:53:01 PM PDT 24
Finished Jul 26 04:53:28 PM PDT 24
Peak memory 217116 kb
Host smart-9350bb3b-7cdc-417c-aacc-e5b7498797da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785474164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.3785474164
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.385230489
Short name T372
Test name
Test status
Simulation time 14791375909 ps
CPU time 22.13 seconds
Started Jul 26 04:53:00 PM PDT 24
Finished Jul 26 04:53:22 PM PDT 24
Peak memory 217184 kb
Host smart-b2404ef7-8cca-4554-8ea0-1556722e2030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385230489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.385230489
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.1154506418
Short name T566
Test name
Test status
Simulation time 10249439 ps
CPU time 0.72 seconds
Started Jul 26 04:53:00 PM PDT 24
Finished Jul 26 04:53:01 PM PDT 24
Peak memory 206128 kb
Host smart-ab42abb0-1a54-46d1-b993-768c74317f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154506418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.1154506418
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.820506532
Short name T715
Test name
Test status
Simulation time 27232469 ps
CPU time 0.73 seconds
Started Jul 26 04:53:03 PM PDT 24
Finished Jul 26 04:53:04 PM PDT 24
Peak memory 206676 kb
Host smart-5868ea53-6e16-4510-9d9f-30e5b75ae013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820506532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.820506532
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.1483644891
Short name T513
Test name
Test status
Simulation time 7687951911 ps
CPU time 12.43 seconds
Started Jul 26 04:53:01 PM PDT 24
Finished Jul 26 04:53:14 PM PDT 24
Peak memory 225380 kb
Host smart-8be99e5d-e199-4721-96a7-21b088a6794f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483644891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.1483644891
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.2546949029
Short name T756
Test name
Test status
Simulation time 25708201 ps
CPU time 0.71 seconds
Started Jul 26 04:53:03 PM PDT 24
Finished Jul 26 04:53:04 PM PDT 24
Peak memory 205904 kb
Host smart-ea1e8a75-60b4-45bd-a126-50d61e192c74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546949029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
2546949029
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.3654678911
Short name T683
Test name
Test status
Simulation time 737110035 ps
CPU time 3.27 seconds
Started Jul 26 04:53:05 PM PDT 24
Finished Jul 26 04:53:08 PM PDT 24
Peak memory 225284 kb
Host smart-72540aa4-50b4-492d-90cc-d2924be76591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654678911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.3654678911
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.1264650554
Short name T403
Test name
Test status
Simulation time 56940052 ps
CPU time 0.77 seconds
Started Jul 26 04:53:06 PM PDT 24
Finished Jul 26 04:53:07 PM PDT 24
Peak memory 207144 kb
Host smart-a406442c-9ae7-4184-aeb5-54d6450e585a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264650554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.1264650554
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.3884444844
Short name T185
Test name
Test status
Simulation time 19825927902 ps
CPU time 93.16 seconds
Started Jul 26 04:53:01 PM PDT 24
Finished Jul 26 04:54:34 PM PDT 24
Peak memory 255544 kb
Host smart-54e84fce-59a5-43ac-8dee-090f6721b72a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884444844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.3884444844
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.1464619974
Short name T819
Test name
Test status
Simulation time 10438833924 ps
CPU time 35.73 seconds
Started Jul 26 04:53:05 PM PDT 24
Finished Jul 26 04:53:41 PM PDT 24
Peak memory 250108 kb
Host smart-b76223da-f053-4a6a-9219-5806f559da62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464619974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.1464619974
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.3288402540
Short name T211
Test name
Test status
Simulation time 32334707939 ps
CPU time 58.88 seconds
Started Jul 26 04:53:00 PM PDT 24
Finished Jul 26 04:53:59 PM PDT 24
Peak memory 256196 kb
Host smart-63cfb72f-85c3-420b-8118-93782086f5f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288402540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.3288402540
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.3355613953
Short name T773
Test name
Test status
Simulation time 1332761875 ps
CPU time 10.03 seconds
Started Jul 26 04:53:02 PM PDT 24
Finished Jul 26 04:53:12 PM PDT 24
Peak memory 241680 kb
Host smart-f8843ca2-d9cb-4658-8034-a588ec37565c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355613953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.3355613953
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_intercept.2271722647
Short name T191
Test name
Test status
Simulation time 172591151 ps
CPU time 3.65 seconds
Started Jul 26 04:53:03 PM PDT 24
Finished Jul 26 04:53:07 PM PDT 24
Peak memory 225268 kb
Host smart-2332327b-ac72-48df-ab30-020164cef36f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271722647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.2271722647
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.2626572858
Short name T434
Test name
Test status
Simulation time 1980457824 ps
CPU time 9.67 seconds
Started Jul 26 04:53:01 PM PDT 24
Finished Jul 26 04:53:11 PM PDT 24
Peak memory 233528 kb
Host smart-bdc63555-05bc-485a-ba2a-e0059ec86293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626572858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.2626572858
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.1759563465
Short name T393
Test name
Test status
Simulation time 56301296 ps
CPU time 1.05 seconds
Started Jul 26 04:53:00 PM PDT 24
Finished Jul 26 04:53:01 PM PDT 24
Peak memory 217248 kb
Host smart-4d5f2e47-fea5-4e7a-8611-5f6b7c751566
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759563465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.spi_device_mem_parity.1759563465
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.2111914413
Short name T999
Test name
Test status
Simulation time 5401172066 ps
CPU time 10.57 seconds
Started Jul 26 04:53:02 PM PDT 24
Finished Jul 26 04:53:13 PM PDT 24
Peak memory 233500 kb
Host smart-e61520ee-c37e-472d-9022-7b3393a3c0a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111914413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.2111914413
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.1072786385
Short name T469
Test name
Test status
Simulation time 3678330425 ps
CPU time 14.75 seconds
Started Jul 26 04:53:03 PM PDT 24
Finished Jul 26 04:53:18 PM PDT 24
Peak memory 233592 kb
Host smart-f33f53b4-e666-40ca-92e3-5f8f04a94bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072786385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.1072786385
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.3040264719
Short name T352
Test name
Test status
Simulation time 164954612 ps
CPU time 3.37 seconds
Started Jul 26 04:53:00 PM PDT 24
Finished Jul 26 04:53:04 PM PDT 24
Peak memory 220152 kb
Host smart-edf33d56-5661-4637-be4e-a2218b2e8b86
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3040264719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.3040264719
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.4262148153
Short name T135
Test name
Test status
Simulation time 29494603148 ps
CPU time 358.95 seconds
Started Jul 26 04:53:06 PM PDT 24
Finished Jul 26 04:59:06 PM PDT 24
Peak memory 274360 kb
Host smart-03368c37-bc7a-4dfe-8d42-0982dd6dcce9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262148153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.4262148153
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.1732588237
Short name T56
Test name
Test status
Simulation time 2247241553 ps
CPU time 15.16 seconds
Started Jul 26 04:53:04 PM PDT 24
Finished Jul 26 04:53:19 PM PDT 24
Peak memory 217104 kb
Host smart-74274909-6122-42d2-a0bd-fdf45c88633d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732588237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.1732588237
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.4209343351
Short name T636
Test name
Test status
Simulation time 3944012707 ps
CPU time 11.16 seconds
Started Jul 26 04:53:02 PM PDT 24
Finished Jul 26 04:53:13 PM PDT 24
Peak memory 217108 kb
Host smart-cb33f93e-8865-424d-a71c-3c3db4b5e18b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209343351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.4209343351
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.70177495
Short name T619
Test name
Test status
Simulation time 129389696 ps
CPU time 1.03 seconds
Started Jul 26 04:53:00 PM PDT 24
Finished Jul 26 04:53:01 PM PDT 24
Peak memory 207696 kb
Host smart-f347f81b-dd11-4c46-ba6b-c7b9a98f4dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70177495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.70177495
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.1405968683
Short name T330
Test name
Test status
Simulation time 199298243 ps
CPU time 0.97 seconds
Started Jul 26 04:53:02 PM PDT 24
Finished Jul 26 04:53:03 PM PDT 24
Peak memory 206696 kb
Host smart-2aace56c-35e2-49d9-b005-d3d0f89f1521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405968683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.1405968683
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.3672483698
Short name T940
Test name
Test status
Simulation time 39352864 ps
CPU time 2.49 seconds
Started Jul 26 04:53:06 PM PDT 24
Finished Jul 26 04:53:08 PM PDT 24
Peak memory 225012 kb
Host smart-d9564138-412e-49bc-83a9-e6a4b51b9c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672483698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.3672483698
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.1959855619
Short name T368
Test name
Test status
Simulation time 11945101 ps
CPU time 0.72 seconds
Started Jul 26 04:53:12 PM PDT 24
Finished Jul 26 04:53:13 PM PDT 24
Peak memory 205344 kb
Host smart-47b79872-19d7-4332-a585-0136c6cbecc9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959855619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
1959855619
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.341088300
Short name T763
Test name
Test status
Simulation time 1774830849 ps
CPU time 8.81 seconds
Started Jul 26 04:53:06 PM PDT 24
Finished Jul 26 04:53:15 PM PDT 24
Peak memory 233608 kb
Host smart-55d2a9c9-73c0-4afd-9501-c74665bc8567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341088300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.341088300
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.751357350
Short name T319
Test name
Test status
Simulation time 16598149 ps
CPU time 0.79 seconds
Started Jul 26 04:53:02 PM PDT 24
Finished Jul 26 04:53:04 PM PDT 24
Peak memory 205992 kb
Host smart-8b0195ca-12de-467b-8907-07b82aea5e87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751357350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.751357350
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.2515646310
Short name T526
Test name
Test status
Simulation time 2966658129 ps
CPU time 57.39 seconds
Started Jul 26 04:53:04 PM PDT 24
Finished Jul 26 04:54:02 PM PDT 24
Peak memory 253912 kb
Host smart-f02d311e-5642-48db-83db-7552b1303afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515646310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.2515646310
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.532059851
Short name T65
Test name
Test status
Simulation time 3140425943 ps
CPU time 46.75 seconds
Started Jul 26 04:53:11 PM PDT 24
Finished Jul 26 04:53:58 PM PDT 24
Peak memory 250672 kb
Host smart-37d93842-ceaf-47ea-9e50-4e2733a319b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532059851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.532059851
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.2014525599
Short name T274
Test name
Test status
Simulation time 24598753422 ps
CPU time 121.51 seconds
Started Jul 26 04:53:11 PM PDT 24
Finished Jul 26 04:55:13 PM PDT 24
Peak memory 266416 kb
Host smart-73277118-cf5e-44bc-aeed-a563d337a8a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014525599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.2014525599
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.2999475613
Short name T1026
Test name
Test status
Simulation time 1534114704 ps
CPU time 24.24 seconds
Started Jul 26 04:53:04 PM PDT 24
Finished Jul 26 04:53:28 PM PDT 24
Peak memory 249900 kb
Host smart-d0aff591-c9cc-4f25-ac12-f0f45b1eeb6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999475613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.2999475613
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.2294915764
Short name T645
Test name
Test status
Simulation time 12857212997 ps
CPU time 66.47 seconds
Started Jul 26 04:53:04 PM PDT 24
Finished Jul 26 04:54:11 PM PDT 24
Peak memory 252536 kb
Host smart-d14a5fcb-2c73-46bc-bbb3-fa7ff4af9d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294915764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmd
s.2294915764
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/18.spi_device_intercept.2248689151
Short name T860
Test name
Test status
Simulation time 161718834 ps
CPU time 2.33 seconds
Started Jul 26 04:53:02 PM PDT 24
Finished Jul 26 04:53:05 PM PDT 24
Peak memory 225392 kb
Host smart-3e8a477c-151d-4842-af93-4b358a73fd22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248689151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.2248689151
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.3737008610
Short name T680
Test name
Test status
Simulation time 183916233425 ps
CPU time 117.4 seconds
Started Jul 26 04:53:02 PM PDT 24
Finished Jul 26 04:54:59 PM PDT 24
Peak memory 233640 kb
Host smart-c04f9553-4c9f-4585-a80e-71dcb5c2bc31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737008610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.3737008610
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.3982457158
Short name T978
Test name
Test status
Simulation time 173096239 ps
CPU time 1.05 seconds
Started Jul 26 04:53:02 PM PDT 24
Finished Jul 26 04:53:04 PM PDT 24
Peak memory 217284 kb
Host smart-1f33257d-d812-4eae-a368-7c1dc7bb8873
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982457158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.spi_device_mem_parity.3982457158
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.160131593
Short name T262
Test name
Test status
Simulation time 68273705314 ps
CPU time 46.42 seconds
Started Jul 26 04:53:02 PM PDT 24
Finished Jul 26 04:53:49 PM PDT 24
Peak memory 241640 kb
Host smart-ece77548-dc6f-43c8-b93d-9220b1d46a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160131593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.160131593
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.2662884916
Short name T412
Test name
Test status
Simulation time 784151217 ps
CPU time 4.49 seconds
Started Jul 26 04:53:02 PM PDT 24
Finished Jul 26 04:53:07 PM PDT 24
Peak memory 221540 kb
Host smart-ed203845-5311-4ca9-b417-e03410ee7468
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2662884916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.2662884916
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.4210664749
Short name T151
Test name
Test status
Simulation time 7655212337 ps
CPU time 28.29 seconds
Started Jul 26 04:53:14 PM PDT 24
Finished Jul 26 04:53:42 PM PDT 24
Peak memory 225460 kb
Host smart-8ff7a6ae-2576-4939-918e-c046b88431a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210664749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.4210664749
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.3717185159
Short name T355
Test name
Test status
Simulation time 1926228020 ps
CPU time 12.04 seconds
Started Jul 26 04:53:02 PM PDT 24
Finished Jul 26 04:53:14 PM PDT 24
Peak memory 217192 kb
Host smart-aaa92c7c-d11e-4c72-bb03-a7124f058b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717185159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.3717185159
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.2112834996
Short name T601
Test name
Test status
Simulation time 531018154 ps
CPU time 4.4 seconds
Started Jul 26 04:53:01 PM PDT 24
Finished Jul 26 04:53:06 PM PDT 24
Peak memory 216908 kb
Host smart-9a71548b-e081-49a1-a2a4-3eee9b7bd7ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112834996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.2112834996
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.3444410984
Short name T646
Test name
Test status
Simulation time 150331891 ps
CPU time 1.24 seconds
Started Jul 26 04:53:05 PM PDT 24
Finished Jul 26 04:53:06 PM PDT 24
Peak memory 208756 kb
Host smart-417c9415-497d-45a7-a97d-7602f0c8a17f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444410984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.3444410984
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.2007051827
Short name T831
Test name
Test status
Simulation time 870957665 ps
CPU time 0.94 seconds
Started Jul 26 04:53:02 PM PDT 24
Finished Jul 26 04:53:04 PM PDT 24
Peak memory 206688 kb
Host smart-dec52d74-c985-4d4d-8c54-5fe5af412daf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007051827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.2007051827
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.400174573
Short name T770
Test name
Test status
Simulation time 321006285 ps
CPU time 7.61 seconds
Started Jul 26 04:53:02 PM PDT 24
Finished Jul 26 04:53:10 PM PDT 24
Peak memory 252656 kb
Host smart-6db807e2-f2f7-45aa-8f16-de45281688f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400174573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.400174573
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.521913996
Short name T631
Test name
Test status
Simulation time 27615671 ps
CPU time 0.69 seconds
Started Jul 26 04:53:15 PM PDT 24
Finished Jul 26 04:53:16 PM PDT 24
Peak memory 205984 kb
Host smart-575893eb-1910-4bc8-b949-79cad37127f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521913996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.521913996
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.2735585506
Short name T51
Test name
Test status
Simulation time 597111434 ps
CPU time 4.08 seconds
Started Jul 26 04:53:13 PM PDT 24
Finished Jul 26 04:53:17 PM PDT 24
Peak memory 233492 kb
Host smart-bbebb2f9-a960-4cf6-956a-e8c1188f589c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735585506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.2735585506
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.1350844605
Short name T387
Test name
Test status
Simulation time 56111120 ps
CPU time 0.78 seconds
Started Jul 26 04:53:11 PM PDT 24
Finished Jul 26 04:53:12 PM PDT 24
Peak memory 207424 kb
Host smart-b69d44cf-495c-428f-884b-304b02139dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350844605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.1350844605
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.44932916
Short name T783
Test name
Test status
Simulation time 5772345237 ps
CPU time 50.26 seconds
Started Jul 26 04:53:13 PM PDT 24
Finished Jul 26 04:54:03 PM PDT 24
Peak memory 251348 kb
Host smart-d7834509-71d1-4a85-aee5-4ef525b99a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44932916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.44932916
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.1467512625
Short name T899
Test name
Test status
Simulation time 29865992710 ps
CPU time 243.04 seconds
Started Jul 26 04:53:14 PM PDT 24
Finished Jul 26 04:57:17 PM PDT 24
Peak memory 258208 kb
Host smart-70ca43fe-2357-404b-b732-3d9c3c890948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467512625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.1467512625
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.2925187738
Short name T72
Test name
Test status
Simulation time 14439498396 ps
CPU time 134.79 seconds
Started Jul 26 04:53:12 PM PDT 24
Finished Jul 26 04:55:27 PM PDT 24
Peak memory 253136 kb
Host smart-ddfa11ce-79df-48da-b650-e0222d24fbce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925187738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.2925187738
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.2499949082
Short name T931
Test name
Test status
Simulation time 393631148 ps
CPU time 6.6 seconds
Started Jul 26 04:53:13 PM PDT 24
Finished Jul 26 04:53:19 PM PDT 24
Peak memory 225252 kb
Host smart-a7a2c8f9-0821-413d-8427-2d35d08c5f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499949082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.2499949082
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.2514161217
Short name T687
Test name
Test status
Simulation time 83314101101 ps
CPU time 145.42 seconds
Started Jul 26 04:53:13 PM PDT 24
Finished Jul 26 04:55:39 PM PDT 24
Peak memory 249748 kb
Host smart-32df4b60-5d12-431c-b4da-b8e3e915ea67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514161217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmd
s.2514161217
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_intercept.3794776457
Short name T689
Test name
Test status
Simulation time 191680399 ps
CPU time 5.49 seconds
Started Jul 26 04:53:16 PM PDT 24
Finished Jul 26 04:53:22 PM PDT 24
Peak memory 233520 kb
Host smart-c5b4b769-f166-4866-abf0-78e2bfc2dd03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794776457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.3794776457
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.3395160789
Short name T833
Test name
Test status
Simulation time 11815424630 ps
CPU time 29.27 seconds
Started Jul 26 04:53:10 PM PDT 24
Finished Jul 26 04:53:40 PM PDT 24
Peak memory 241404 kb
Host smart-51139053-d445-4ef3-a853-034e2da5d85d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395160789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.3395160789
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.1886727490
Short name T522
Test name
Test status
Simulation time 27440396 ps
CPU time 1.08 seconds
Started Jul 26 04:53:12 PM PDT 24
Finished Jul 26 04:53:13 PM PDT 24
Peak memory 217248 kb
Host smart-266575a9-528f-4ffd-ad77-0aee649cb58d
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886727490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.spi_device_mem_parity.1886727490
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.2427573841
Short name T1000
Test name
Test status
Simulation time 182195006 ps
CPU time 3.29 seconds
Started Jul 26 04:53:12 PM PDT 24
Finished Jul 26 04:53:15 PM PDT 24
Peak memory 225332 kb
Host smart-f53a3e67-97ff-4814-bfb0-317a3c002f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427573841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.2427573841
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.3291433886
Short name T334
Test name
Test status
Simulation time 351369082 ps
CPU time 3.43 seconds
Started Jul 26 04:53:11 PM PDT 24
Finished Jul 26 04:53:15 PM PDT 24
Peak memory 233636 kb
Host smart-203083f5-648f-4f2e-bab8-06a4fcf37f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291433886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.3291433886
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.2404009624
Short name T570
Test name
Test status
Simulation time 454256367 ps
CPU time 4.92 seconds
Started Jul 26 04:53:16 PM PDT 24
Finished Jul 26 04:53:21 PM PDT 24
Peak memory 223720 kb
Host smart-d47f29fe-8fc5-4c65-86a6-08251a8b0ad1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2404009624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.2404009624
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.3614005026
Short name T153
Test name
Test status
Simulation time 7006686598 ps
CPU time 109.71 seconds
Started Jul 26 04:53:16 PM PDT 24
Finished Jul 26 04:55:06 PM PDT 24
Peak memory 267004 kb
Host smart-e70fa4ec-baed-47f1-aca0-97872a8cd4d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614005026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.3614005026
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.262023527
Short name T467
Test name
Test status
Simulation time 36067015146 ps
CPU time 43.71 seconds
Started Jul 26 04:53:12 PM PDT 24
Finished Jul 26 04:53:56 PM PDT 24
Peak memory 217176 kb
Host smart-f6b5245e-9da1-4e3c-af89-01a5f48b0e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262023527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.262023527
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.2135962312
Short name T554
Test name
Test status
Simulation time 826508524 ps
CPU time 2.9 seconds
Started Jul 26 04:53:13 PM PDT 24
Finished Jul 26 04:53:16 PM PDT 24
Peak memory 217084 kb
Host smart-4e604798-c8aa-4443-9eff-c979dd85dc0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135962312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.2135962312
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.3463474822
Short name T490
Test name
Test status
Simulation time 235963786 ps
CPU time 4.19 seconds
Started Jul 26 04:53:12 PM PDT 24
Finished Jul 26 04:53:16 PM PDT 24
Peak memory 216932 kb
Host smart-8ab077fa-828a-4788-bb42-514b2fc3f9ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463474822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.3463474822
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.3258482461
Short name T661
Test name
Test status
Simulation time 88351681 ps
CPU time 0.9 seconds
Started Jul 26 04:53:14 PM PDT 24
Finished Jul 26 04:53:15 PM PDT 24
Peak memory 206632 kb
Host smart-a977e32e-f4c3-42c2-8fb0-b6889f86a67a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258482461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.3258482461
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.403710214
Short name T128
Test name
Test status
Simulation time 799424986 ps
CPU time 6.33 seconds
Started Jul 26 04:53:16 PM PDT 24
Finished Jul 26 04:53:23 PM PDT 24
Peak memory 225364 kb
Host smart-dc9415b1-9f07-4636-9068-76e8be27b09b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403710214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.403710214
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.2226102341
Short name T612
Test name
Test status
Simulation time 24641991 ps
CPU time 0.75 seconds
Started Jul 26 04:52:07 PM PDT 24
Finished Jul 26 04:52:08 PM PDT 24
Peak memory 205964 kb
Host smart-0a86b9d8-c872-4d08-b699-5495593603f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226102341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.2
226102341
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.3044984084
Short name T370
Test name
Test status
Simulation time 459939187 ps
CPU time 6.62 seconds
Started Jul 26 04:52:05 PM PDT 24
Finished Jul 26 04:52:12 PM PDT 24
Peak memory 233476 kb
Host smart-30c33f51-ddce-4a5e-90c3-70dd6f42da7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044984084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.3044984084
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.1948879157
Short name T928
Test name
Test status
Simulation time 41175003 ps
CPU time 0.78 seconds
Started Jul 26 04:52:06 PM PDT 24
Finished Jul 26 04:52:07 PM PDT 24
Peak memory 207116 kb
Host smart-22088327-dd95-4039-9cab-6720c36bfc2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948879157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.1948879157
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.3566569248
Short name T625
Test name
Test status
Simulation time 1495045148 ps
CPU time 20.43 seconds
Started Jul 26 04:52:09 PM PDT 24
Finished Jul 26 04:52:29 PM PDT 24
Peak memory 241608 kb
Host smart-b2106b9b-c59d-4243-b9c8-558bcbb099b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566569248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.3566569248
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.2531050780
Short name T28
Test name
Test status
Simulation time 94228653854 ps
CPU time 92.97 seconds
Started Jul 26 04:52:06 PM PDT 24
Finished Jul 26 04:53:39 PM PDT 24
Peak memory 250100 kb
Host smart-779304ed-2198-40f6-9431-891544503dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531050780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.2531050780
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.1291609710
Short name T587
Test name
Test status
Simulation time 15568184161 ps
CPU time 36.72 seconds
Started Jul 26 04:52:08 PM PDT 24
Finished Jul 26 04:52:45 PM PDT 24
Peak memory 240028 kb
Host smart-1934172a-f6c4-44fa-8e03-a1f55bca4a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291609710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.1291609710
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.2183288695
Short name T693
Test name
Test status
Simulation time 328544149 ps
CPU time 10.96 seconds
Started Jul 26 04:52:07 PM PDT 24
Finished Jul 26 04:52:18 PM PDT 24
Peak memory 233512 kb
Host smart-d22659aa-0b37-4ef4-9757-4976d51fbd2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183288695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.2183288695
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.3924585014
Short name T84
Test name
Test status
Simulation time 3348341846 ps
CPU time 84.73 seconds
Started Jul 26 04:52:05 PM PDT 24
Finished Jul 26 04:53:30 PM PDT 24
Peak memory 267320 kb
Host smart-a16c947e-4ff1-4274-ae9d-ecf90920bfc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924585014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds
.3924585014
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_intercept.77137149
Short name T965
Test name
Test status
Simulation time 7004487074 ps
CPU time 17.31 seconds
Started Jul 26 04:52:06 PM PDT 24
Finished Jul 26 04:52:24 PM PDT 24
Peak memory 225412 kb
Host smart-5ca59fec-bd37-434d-a5f1-049c757ac73a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77137149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.77137149
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.3208595989
Short name T724
Test name
Test status
Simulation time 29903370673 ps
CPU time 106.19 seconds
Started Jul 26 04:52:16 PM PDT 24
Finished Jul 26 04:54:03 PM PDT 24
Peak memory 241476 kb
Host smart-a3079f27-f58a-4b27-86a0-a0644e9aa463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208595989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.3208595989
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.3867224779
Short name T521
Test name
Test status
Simulation time 85808527 ps
CPU time 1.1 seconds
Started Jul 26 04:52:05 PM PDT 24
Finished Jul 26 04:52:06 PM PDT 24
Peak memory 218548 kb
Host smart-916fa704-618f-44d0-a219-63b54401e406
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867224779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.spi_device_mem_parity.3867224779
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.2970000379
Short name T735
Test name
Test status
Simulation time 869623918 ps
CPU time 4.58 seconds
Started Jul 26 04:52:05 PM PDT 24
Finished Jul 26 04:52:10 PM PDT 24
Peak memory 225332 kb
Host smart-40cf2b4b-b8f7-4e98-8c8a-e735681f3661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970000379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.2970000379
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.2438707809
Short name T775
Test name
Test status
Simulation time 8143394210 ps
CPU time 26.63 seconds
Started Jul 26 04:52:24 PM PDT 24
Finished Jul 26 04:52:51 PM PDT 24
Peak memory 249820 kb
Host smart-6ebedf6c-eae2-476c-bafb-f23a37c53b6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438707809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.2438707809
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.3339858422
Short name T869
Test name
Test status
Simulation time 4600680863 ps
CPU time 14.97 seconds
Started Jul 26 04:52:04 PM PDT 24
Finished Jul 26 04:52:20 PM PDT 24
Peak memory 221000 kb
Host smart-a01eb607-c1e6-4079-a089-17caad8ce38e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3339858422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.3339858422
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.4118309501
Short name T62
Test name
Test status
Simulation time 582912666 ps
CPU time 1.26 seconds
Started Jul 26 04:52:23 PM PDT 24
Finished Jul 26 04:52:24 PM PDT 24
Peak memory 235780 kb
Host smart-0f16cee5-5704-4672-ad91-1bd728e4f5d3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118309501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.4118309501
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.3050227396
Short name T997
Test name
Test status
Simulation time 3000015212 ps
CPU time 75.95 seconds
Started Jul 26 04:52:23 PM PDT 24
Finished Jul 26 04:53:39 PM PDT 24
Peak memory 253848 kb
Host smart-84b8b0e6-b777-4a99-b8ae-0735faddbc52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050227396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.3050227396
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.1691667160
Short name T376
Test name
Test status
Simulation time 1379332287 ps
CPU time 3.08 seconds
Started Jul 26 04:52:32 PM PDT 24
Finished Jul 26 04:52:36 PM PDT 24
Peak memory 217060 kb
Host smart-f3e7bed0-015e-4d9c-b234-e9f118619b78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691667160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.1691667160
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.3556374578
Short name T424
Test name
Test status
Simulation time 3109746882 ps
CPU time 4.72 seconds
Started Jul 26 04:52:09 PM PDT 24
Finished Jul 26 04:52:14 PM PDT 24
Peak memory 217008 kb
Host smart-026faf5d-d831-45f4-a870-651e8e68dffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556374578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.3556374578
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.3946585763
Short name T980
Test name
Test status
Simulation time 623140526 ps
CPU time 3.79 seconds
Started Jul 26 04:52:06 PM PDT 24
Finished Jul 26 04:52:10 PM PDT 24
Peak memory 217040 kb
Host smart-02380290-6143-42fa-9553-82704905c01a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946585763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.3946585763
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.3917939295
Short name T718
Test name
Test status
Simulation time 274644219 ps
CPU time 0.8 seconds
Started Jul 26 04:52:05 PM PDT 24
Finished Jul 26 04:52:06 PM PDT 24
Peak memory 206636 kb
Host smart-90a2e760-9b3b-43f5-9bbc-1f8bc0334398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917939295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.3917939295
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.1835802883
Short name T664
Test name
Test status
Simulation time 13487414025 ps
CPU time 13.37 seconds
Started Jul 26 04:52:04 PM PDT 24
Finished Jul 26 04:52:18 PM PDT 24
Peak memory 225448 kb
Host smart-b4166a48-7979-42c2-90c5-df1033b2bd83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835802883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.1835802883
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.1936953090
Short name T696
Test name
Test status
Simulation time 15573974 ps
CPU time 0.73 seconds
Started Jul 26 04:53:14 PM PDT 24
Finished Jul 26 04:53:14 PM PDT 24
Peak memory 205344 kb
Host smart-633c2fb8-c21b-43ba-b8a8-0b4df0eaf5b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936953090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
1936953090
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.4132056719
Short name T753
Test name
Test status
Simulation time 334598414 ps
CPU time 2.13 seconds
Started Jul 26 04:53:16 PM PDT 24
Finished Jul 26 04:53:19 PM PDT 24
Peak memory 224552 kb
Host smart-6e33b8c7-5927-4c1f-9ba2-83398eb923ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132056719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.4132056719
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.672420623
Short name T374
Test name
Test status
Simulation time 15890144 ps
CPU time 0.84 seconds
Started Jul 26 04:53:11 PM PDT 24
Finished Jul 26 04:53:12 PM PDT 24
Peak memory 207356 kb
Host smart-a31418b6-89f6-44be-948f-09286ead5f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672420623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.672420623
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.1943079100
Short name T492
Test name
Test status
Simulation time 27063405180 ps
CPU time 194.89 seconds
Started Jul 26 04:53:16 PM PDT 24
Finished Jul 26 04:56:32 PM PDT 24
Peak memory 253156 kb
Host smart-96bf74b1-9f83-47f6-947a-1a7fa49a3921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943079100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.1943079100
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.1147698768
Short name T273
Test name
Test status
Simulation time 87064360265 ps
CPU time 219.84 seconds
Started Jul 26 04:53:15 PM PDT 24
Finished Jul 26 04:56:55 PM PDT 24
Peak memory 256684 kb
Host smart-1f898918-22cc-49ec-8b14-401c1f053923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147698768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.1147698768
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.1068847789
Short name T531
Test name
Test status
Simulation time 1379915134 ps
CPU time 9.77 seconds
Started Jul 26 04:53:14 PM PDT 24
Finished Jul 26 04:53:24 PM PDT 24
Peak memory 234512 kb
Host smart-491bc4cb-3f89-49c3-b482-581a6343f1fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068847789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.1068847789
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.2305730972
Short name T945
Test name
Test status
Simulation time 58974838954 ps
CPU time 413.52 seconds
Started Jul 26 04:53:15 PM PDT 24
Finished Jul 26 05:00:08 PM PDT 24
Peak memory 274556 kb
Host smart-41fde9ca-7e23-496b-84f1-5ea7d66dea45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305730972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmd
s.2305730972
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/20.spi_device_intercept.4024566926
Short name T714
Test name
Test status
Simulation time 169261790 ps
CPU time 4.29 seconds
Started Jul 26 04:53:11 PM PDT 24
Finished Jul 26 04:53:16 PM PDT 24
Peak memory 225244 kb
Host smart-0e6238f5-6735-463a-8eaa-60d086831d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024566926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.4024566926
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.3776502528
Short name T245
Test name
Test status
Simulation time 37752506365 ps
CPU time 103.15 seconds
Started Jul 26 04:53:10 PM PDT 24
Finished Jul 26 04:54:53 PM PDT 24
Peak memory 234708 kb
Host smart-28768769-8b67-40cb-8bd8-4c03db9f0057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776502528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.3776502528
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.2212491901
Short name T206
Test name
Test status
Simulation time 10519830060 ps
CPU time 9.11 seconds
Started Jul 26 04:53:17 PM PDT 24
Finished Jul 26 04:53:26 PM PDT 24
Peak memory 233572 kb
Host smart-d5713ca7-f5b6-4e8f-9a88-ce286b7fbfb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212491901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.2212491901
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.926099074
Short name T635
Test name
Test status
Simulation time 27531716817 ps
CPU time 24.24 seconds
Started Jul 26 04:53:18 PM PDT 24
Finished Jul 26 04:53:42 PM PDT 24
Peak memory 249964 kb
Host smart-de16dc6a-4da0-4d88-84c8-222bd9418d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926099074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.926099074
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.2283470627
Short name T351
Test name
Test status
Simulation time 163448471 ps
CPU time 4.22 seconds
Started Jul 26 04:53:16 PM PDT 24
Finished Jul 26 04:53:20 PM PDT 24
Peak memory 220644 kb
Host smart-5ff25c26-84e0-4406-912b-0c0bbae9527e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2283470627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.2283470627
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.3563451886
Short name T20
Test name
Test status
Simulation time 768935304 ps
CPU time 1.04 seconds
Started Jul 26 04:53:12 PM PDT 24
Finished Jul 26 04:53:13 PM PDT 24
Peak memory 208364 kb
Host smart-31b7a1d4-1786-4eb2-ae55-a201a5c42fad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563451886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.3563451886
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.2086689130
Short name T593
Test name
Test status
Simulation time 9286236983 ps
CPU time 15.45 seconds
Started Jul 26 04:53:19 PM PDT 24
Finished Jul 26 04:53:35 PM PDT 24
Peak memory 217128 kb
Host smart-7345b4d2-49f4-46ef-9691-0770d15df7f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086689130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.2086689130
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.1290361839
Short name T788
Test name
Test status
Simulation time 111598242 ps
CPU time 1.41 seconds
Started Jul 26 04:53:16 PM PDT 24
Finished Jul 26 04:53:18 PM PDT 24
Peak memory 208432 kb
Host smart-7d097bf4-82ff-4823-bd75-a8a9b75c9644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290361839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.1290361839
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.1595245674
Short name T967
Test name
Test status
Simulation time 68600064 ps
CPU time 1.73 seconds
Started Jul 26 04:53:16 PM PDT 24
Finished Jul 26 04:53:18 PM PDT 24
Peak memory 217036 kb
Host smart-ec46e384-785a-4695-bd57-ffae6c096784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595245674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.1595245674
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.2040232133
Short name T68
Test name
Test status
Simulation time 13009475 ps
CPU time 0.7 seconds
Started Jul 26 04:53:13 PM PDT 24
Finished Jul 26 04:53:14 PM PDT 24
Peak memory 206240 kb
Host smart-c510f75c-c93b-43b3-8303-51b917a71922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040232133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.2040232133
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.2293841324
Short name T459
Test name
Test status
Simulation time 94937238 ps
CPU time 2.15 seconds
Started Jul 26 04:53:19 PM PDT 24
Finished Jul 26 04:53:22 PM PDT 24
Peak memory 224400 kb
Host smart-5c831a82-e363-4186-8c52-01c3199d9b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293841324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.2293841324
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.1386204820
Short name T764
Test name
Test status
Simulation time 74687644 ps
CPU time 0.72 seconds
Started Jul 26 04:53:14 PM PDT 24
Finished Jul 26 04:53:15 PM PDT 24
Peak memory 206252 kb
Host smart-68268629-7e8c-435a-9879-55e0a0c97092
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386204820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
1386204820
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.1309861265
Short name T468
Test name
Test status
Simulation time 31661759 ps
CPU time 2.46 seconds
Started Jul 26 04:53:19 PM PDT 24
Finished Jul 26 04:53:22 PM PDT 24
Peak memory 233104 kb
Host smart-2cf53520-b17d-4269-88ba-8573f86d5e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309861265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.1309861265
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.462547591
Short name T761
Test name
Test status
Simulation time 74354591 ps
CPU time 0.8 seconds
Started Jul 26 04:53:17 PM PDT 24
Finished Jul 26 04:53:18 PM PDT 24
Peak memory 207060 kb
Host smart-a81f5c01-df47-4d73-b75e-dda9eeffdf4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462547591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.462547591
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.2740999332
Short name T221
Test name
Test status
Simulation time 6268360225 ps
CPU time 42.81 seconds
Started Jul 26 04:53:19 PM PDT 24
Finished Jul 26 04:54:02 PM PDT 24
Peak memory 235316 kb
Host smart-5a22e8ac-1b4a-414a-a08d-7aaae2037554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740999332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.2740999332
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.1008663192
Short name T1025
Test name
Test status
Simulation time 344841344073 ps
CPU time 661.07 seconds
Started Jul 26 04:53:19 PM PDT 24
Finished Jul 26 05:04:20 PM PDT 24
Peak memory 266744 kb
Host smart-4756a924-3c09-48a1-89c2-e70d0c222eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008663192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.1008663192
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.542826931
Short name T706
Test name
Test status
Simulation time 3096942895 ps
CPU time 6.87 seconds
Started Jul 26 04:53:19 PM PDT 24
Finished Jul 26 04:53:26 PM PDT 24
Peak memory 238908 kb
Host smart-2b85c31b-2b3b-4146-bc16-90d7a19106e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542826931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.542826931
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.2897707068
Short name T290
Test name
Test status
Simulation time 2710526188 ps
CPU time 58.08 seconds
Started Jul 26 04:53:17 PM PDT 24
Finished Jul 26 04:54:15 PM PDT 24
Peak memory 257848 kb
Host smart-0fdb2e77-5810-4692-8e50-45ce97dff740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897707068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmd
s.2897707068
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_intercept.2197859178
Short name T898
Test name
Test status
Simulation time 563166107 ps
CPU time 8.23 seconds
Started Jul 26 04:53:19 PM PDT 24
Finished Jul 26 04:53:28 PM PDT 24
Peak memory 225336 kb
Host smart-c4157855-0831-4efa-852d-e350a75b4f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197859178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.2197859178
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.431484154
Short name T642
Test name
Test status
Simulation time 30919487822 ps
CPU time 61.73 seconds
Started Jul 26 04:53:12 PM PDT 24
Finished Jul 26 04:54:14 PM PDT 24
Peak memory 252340 kb
Host smart-9243bfd7-371a-4366-ab70-28ebf8181237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431484154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.431484154
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.1505045770
Short name T1020
Test name
Test status
Simulation time 249163189 ps
CPU time 5.06 seconds
Started Jul 26 04:53:15 PM PDT 24
Finished Jul 26 04:53:20 PM PDT 24
Peak memory 233492 kb
Host smart-2a829cfc-7e51-4741-b7cc-046ec91cf470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505045770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.1505045770
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.1889877126
Short name T311
Test name
Test status
Simulation time 115850031 ps
CPU time 2.53 seconds
Started Jul 26 04:53:16 PM PDT 24
Finished Jul 26 04:53:18 PM PDT 24
Peak memory 233068 kb
Host smart-b7942738-c31a-493c-ab9e-ac55d3d8b6f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889877126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.1889877126
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.2191252554
Short name T767
Test name
Test status
Simulation time 316859021 ps
CPU time 3.73 seconds
Started Jul 26 04:53:21 PM PDT 24
Finished Jul 26 04:53:25 PM PDT 24
Peak memory 223712 kb
Host smart-635c9faf-c5de-4d80-9a4c-842c444ee9e2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2191252554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.2191252554
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.1458505881
Short name T398
Test name
Test status
Simulation time 201306087 ps
CPU time 0.99 seconds
Started Jul 26 04:53:15 PM PDT 24
Finished Jul 26 04:53:17 PM PDT 24
Peak memory 207512 kb
Host smart-b6419c33-610e-4906-89fc-b20bb29d3e5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458505881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.1458505881
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.4035896449
Short name T384
Test name
Test status
Simulation time 6889695663 ps
CPU time 7.59 seconds
Started Jul 26 04:53:16 PM PDT 24
Finished Jul 26 04:53:24 PM PDT 24
Peak memory 217156 kb
Host smart-25bc37f8-62ee-4c51-83e3-ddf3d9ede9df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035896449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.4035896449
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.516778765
Short name T867
Test name
Test status
Simulation time 876771362 ps
CPU time 4.08 seconds
Started Jul 26 04:53:11 PM PDT 24
Finished Jul 26 04:53:16 PM PDT 24
Peak memory 216964 kb
Host smart-393fd34c-2951-4aa8-87fb-662af59cf706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516778765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.516778765
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.1779071633
Short name T313
Test name
Test status
Simulation time 121268476 ps
CPU time 2.31 seconds
Started Jul 26 04:53:15 PM PDT 24
Finished Jul 26 04:53:18 PM PDT 24
Peak memory 217072 kb
Host smart-9112898a-6049-493d-a4f5-53180b01249f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779071633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.1779071633
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.2916682758
Short name T719
Test name
Test status
Simulation time 22500896 ps
CPU time 0.78 seconds
Started Jul 26 04:53:16 PM PDT 24
Finished Jul 26 04:53:17 PM PDT 24
Peak memory 206688 kb
Host smart-c4a6ccb3-ef02-4be5-9fe3-65d13f709b14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916682758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.2916682758
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.3977401829
Short name T982
Test name
Test status
Simulation time 1906067808 ps
CPU time 9.5 seconds
Started Jul 26 04:53:19 PM PDT 24
Finished Jul 26 04:53:29 PM PDT 24
Peak memory 241556 kb
Host smart-c05495ff-ad4a-4fa4-b794-34435fcb070f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977401829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.3977401829
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.2703476221
Short name T981
Test name
Test status
Simulation time 14304919 ps
CPU time 0.71 seconds
Started Jul 26 04:53:23 PM PDT 24
Finished Jul 26 04:53:24 PM PDT 24
Peak memory 205928 kb
Host smart-6785b84a-5abc-4087-8f14-bac8f84ba665
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703476221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
2703476221
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.99250403
Short name T236
Test name
Test status
Simulation time 3186206004 ps
CPU time 13.33 seconds
Started Jul 26 04:53:18 PM PDT 24
Finished Jul 26 04:53:31 PM PDT 24
Peak memory 233536 kb
Host smart-eba4bc66-e90c-4197-b6de-524d9e597e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99250403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.99250403
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.3814544657
Short name T1014
Test name
Test status
Simulation time 43895930 ps
CPU time 0.79 seconds
Started Jul 26 04:53:13 PM PDT 24
Finished Jul 26 04:53:14 PM PDT 24
Peak memory 207096 kb
Host smart-71bd653f-9461-47ef-93a5-e8833d134534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814544657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.3814544657
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.3338717706
Short name T915
Test name
Test status
Simulation time 12936866934 ps
CPU time 60.16 seconds
Started Jul 26 04:53:23 PM PDT 24
Finished Jul 26 04:54:23 PM PDT 24
Peak memory 252060 kb
Host smart-d3051aa6-2e28-4e16-a72e-0c6041b9edde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338717706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.3338717706
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.73099765
Short name T48
Test name
Test status
Simulation time 38144021963 ps
CPU time 327.48 seconds
Started Jul 26 04:53:26 PM PDT 24
Finished Jul 26 04:58:54 PM PDT 24
Peak memory 250192 kb
Host smart-afe724de-1654-48bd-a3de-ed1d2eb8a9e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73099765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.73099765
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.1307142019
Short name T451
Test name
Test status
Simulation time 15719765912 ps
CPU time 64.13 seconds
Started Jul 26 04:53:23 PM PDT 24
Finished Jul 26 04:54:27 PM PDT 24
Peak memory 250096 kb
Host smart-0bd98f1a-6a26-46d6-bcaa-e664295cd1fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307142019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.1307142019
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.3942682652
Short name T270
Test name
Test status
Simulation time 17674944196 ps
CPU time 122.46 seconds
Started Jul 26 04:53:23 PM PDT 24
Finished Jul 26 04:55:26 PM PDT 24
Peak memory 255352 kb
Host smart-fdf91b54-8b9a-49fa-9dce-4036dc9178d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942682652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmd
s.3942682652
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_intercept.391605517
Short name T214
Test name
Test status
Simulation time 2076418787 ps
CPU time 7 seconds
Started Jul 26 04:53:14 PM PDT 24
Finished Jul 26 04:53:21 PM PDT 24
Peak memory 233508 kb
Host smart-5b2b4e71-5cc5-488c-8665-05f2b837d6df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391605517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.391605517
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.231975652
Short name T1006
Test name
Test status
Simulation time 31245338562 ps
CPU time 110 seconds
Started Jul 26 04:53:18 PM PDT 24
Finished Jul 26 04:55:08 PM PDT 24
Peak memory 241216 kb
Host smart-fa93d6c5-f0b6-427c-90bb-0e2d3ab006aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231975652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.231975652
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.3110131424
Short name T444
Test name
Test status
Simulation time 277686987 ps
CPU time 3.32 seconds
Started Jul 26 04:53:15 PM PDT 24
Finished Jul 26 04:53:19 PM PDT 24
Peak memory 225272 kb
Host smart-36596cf1-b2c4-490a-ab7b-619914e7ed2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110131424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.3110131424
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.103203024
Short name T208
Test name
Test status
Simulation time 302539233 ps
CPU time 3.32 seconds
Started Jul 26 04:53:17 PM PDT 24
Finished Jul 26 04:53:20 PM PDT 24
Peak memory 225336 kb
Host smart-5bf13b73-c0c8-4974-8e8d-5f88aaa6adb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103203024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.103203024
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.817134014
Short name T850
Test name
Test status
Simulation time 148195590 ps
CPU time 3.5 seconds
Started Jul 26 04:53:24 PM PDT 24
Finished Jul 26 04:53:28 PM PDT 24
Peak memory 223600 kb
Host smart-37bbb3fd-dc5f-4b7c-9a09-b7d32907b1df
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=817134014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dire
ct.817134014
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.1779990594
Short name T1005
Test name
Test status
Simulation time 275991257732 ps
CPU time 640.87 seconds
Started Jul 26 04:53:26 PM PDT 24
Finished Jul 26 05:04:07 PM PDT 24
Peak memory 287236 kb
Host smart-2a4fa5ef-c085-4f15-949f-75505141ed1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779990594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.1779990594
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.2875846351
Short name T701
Test name
Test status
Simulation time 9358248483 ps
CPU time 24.23 seconds
Started Jul 26 04:53:16 PM PDT 24
Finished Jul 26 04:53:40 PM PDT 24
Peak memory 221300 kb
Host smart-1170983a-debc-40d9-a460-d28e024931b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875846351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.2875846351
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.1686760825
Short name T882
Test name
Test status
Simulation time 740729495 ps
CPU time 6.25 seconds
Started Jul 26 04:53:16 PM PDT 24
Finished Jul 26 04:53:23 PM PDT 24
Peak memory 217096 kb
Host smart-749b7324-0498-4c3a-817d-adcf93c964c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686760825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.1686760825
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.2232564852
Short name T515
Test name
Test status
Simulation time 31410108 ps
CPU time 1.11 seconds
Started Jul 26 04:53:16 PM PDT 24
Finished Jul 26 04:53:17 PM PDT 24
Peak memory 208196 kb
Host smart-5b52ad61-3765-4d30-86f7-19d68cd7805f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232564852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.2232564852
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.3266429975
Short name T343
Test name
Test status
Simulation time 21175889 ps
CPU time 0.75 seconds
Started Jul 26 04:53:18 PM PDT 24
Finished Jul 26 04:53:19 PM PDT 24
Peak memory 206700 kb
Host smart-df7dd810-98d6-4335-b0ab-02d34c75787e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266429975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.3266429975
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.553591678
Short name T921
Test name
Test status
Simulation time 344823607 ps
CPU time 4.57 seconds
Started Jul 26 04:53:20 PM PDT 24
Finished Jul 26 04:53:25 PM PDT 24
Peak memory 233552 kb
Host smart-cf876ec8-6666-4a24-b9d8-b6121df40597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553591678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.553591678
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.2054993704
Short name T973
Test name
Test status
Simulation time 37232449 ps
CPU time 0.69 seconds
Started Jul 26 04:53:24 PM PDT 24
Finished Jul 26 04:53:25 PM PDT 24
Peak memory 205996 kb
Host smart-7d55fbcc-b49c-42a5-b325-5726b2319f8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054993704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
2054993704
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.2472066024
Short name T527
Test name
Test status
Simulation time 166466620 ps
CPU time 3.65 seconds
Started Jul 26 04:53:24 PM PDT 24
Finished Jul 26 04:53:27 PM PDT 24
Peak memory 233496 kb
Host smart-069625c6-1476-4fe4-b049-18bdcf9c7d43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472066024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.2472066024
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.925867677
Short name T947
Test name
Test status
Simulation time 67342512 ps
CPU time 0.77 seconds
Started Jul 26 04:53:29 PM PDT 24
Finished Jul 26 04:53:30 PM PDT 24
Peak memory 207484 kb
Host smart-e20e07f7-3483-4fe3-bcff-e2a9919f9bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925867677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.925867677
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.918352515
Short name T251
Test name
Test status
Simulation time 25227781404 ps
CPU time 42.11 seconds
Started Jul 26 04:53:20 PM PDT 24
Finished Jul 26 04:54:02 PM PDT 24
Peak memory 234948 kb
Host smart-5cd8c13d-33cb-475b-9cf0-c10df8968514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918352515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.918352515
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.1737891027
Short name T802
Test name
Test status
Simulation time 1679523919 ps
CPU time 19.16 seconds
Started Jul 26 04:53:24 PM PDT 24
Finished Jul 26 04:53:43 PM PDT 24
Peak memory 241752 kb
Host smart-26209eb5-8ca9-4ae2-9afb-ab293058db3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737891027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.1737891027
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.2878056811
Short name T421
Test name
Test status
Simulation time 110522227287 ps
CPU time 152.43 seconds
Started Jul 26 04:53:27 PM PDT 24
Finished Jul 26 04:56:00 PM PDT 24
Peak memory 240928 kb
Host smart-e180088b-af32-4f83-bbfc-b5d40ef5a422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878056811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.2878056811
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.4015668373
Short name T316
Test name
Test status
Simulation time 35157755864 ps
CPU time 62.55 seconds
Started Jul 26 04:53:22 PM PDT 24
Finished Jul 26 04:54:25 PM PDT 24
Peak memory 249984 kb
Host smart-2a4d363e-b9f3-42e9-8810-a34a7e9d9e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015668373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.4015668373
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.2315948189
Short name T702
Test name
Test status
Simulation time 1191530481 ps
CPU time 6.77 seconds
Started Jul 26 04:53:26 PM PDT 24
Finished Jul 26 04:53:32 PM PDT 24
Peak memory 225252 kb
Host smart-3cb413e4-2cc0-4acd-8ffe-81fb4263c8e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315948189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmd
s.2315948189
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/23.spi_device_intercept.2309859296
Short name T240
Test name
Test status
Simulation time 458984987 ps
CPU time 4.94 seconds
Started Jul 26 04:53:24 PM PDT 24
Finished Jul 26 04:53:29 PM PDT 24
Peak memory 233480 kb
Host smart-0083bd78-ec51-4f96-9afb-4a5797be78ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309859296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.2309859296
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.3533804143
Short name T859
Test name
Test status
Simulation time 8392071946 ps
CPU time 20.56 seconds
Started Jul 26 04:53:26 PM PDT 24
Finished Jul 26 04:53:47 PM PDT 24
Peak memory 241788 kb
Host smart-7e67d184-4baf-4476-a839-2d6a26b6348c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533804143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.3533804143
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.2637652198
Short name T416
Test name
Test status
Simulation time 17224492503 ps
CPU time 14.98 seconds
Started Jul 26 04:53:23 PM PDT 24
Finished Jul 26 04:53:38 PM PDT 24
Peak memory 233500 kb
Host smart-0773ad2f-2e61-4215-a701-40a93155e955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637652198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.2637652198
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.2178407070
Short name T413
Test name
Test status
Simulation time 1868228277 ps
CPU time 8.83 seconds
Started Jul 26 04:53:24 PM PDT 24
Finished Jul 26 04:53:33 PM PDT 24
Peak memory 233448 kb
Host smart-96b7abac-761a-4163-8792-9f4b29242a7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178407070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.2178407070
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.35824803
Short name T966
Test name
Test status
Simulation time 122360347 ps
CPU time 4.05 seconds
Started Jul 26 04:53:23 PM PDT 24
Finished Jul 26 04:53:28 PM PDT 24
Peak memory 223620 kb
Host smart-59b60cae-9d62-47e1-bf74-110cd84bdbc5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=35824803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_direc
t.35824803
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.1201099700
Short name T777
Test name
Test status
Simulation time 1201102264 ps
CPU time 15.69 seconds
Started Jul 26 04:53:26 PM PDT 24
Finished Jul 26 04:53:42 PM PDT 24
Peak memory 217064 kb
Host smart-e8fc0895-621a-4e1d-b97b-a1a6b146056c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201099700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.1201099700
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.1662725070
Short name T760
Test name
Test status
Simulation time 11230234 ps
CPU time 0.73 seconds
Started Jul 26 04:53:21 PM PDT 24
Finished Jul 26 04:53:22 PM PDT 24
Peak memory 206584 kb
Host smart-8356eb01-066f-4be8-9ff7-5012ebb7e136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662725070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.1662725070
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.365996439
Short name T575
Test name
Test status
Simulation time 35425234 ps
CPU time 0.85 seconds
Started Jul 26 04:53:25 PM PDT 24
Finished Jul 26 04:53:26 PM PDT 24
Peak memory 206628 kb
Host smart-5b2b4dc2-14c8-4774-b5ab-9a494bb62783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365996439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.365996439
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.2468051846
Short name T537
Test name
Test status
Simulation time 135270438 ps
CPU time 0.76 seconds
Started Jul 26 04:53:21 PM PDT 24
Finished Jul 26 04:53:22 PM PDT 24
Peak memory 206624 kb
Host smart-6a94b4d5-8ac1-4538-a226-5e128eed118d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468051846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.2468051846
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.2343009028
Short name T408
Test name
Test status
Simulation time 678700190 ps
CPU time 11.67 seconds
Started Jul 26 04:53:22 PM PDT 24
Finished Jul 26 04:53:34 PM PDT 24
Peak memory 240380 kb
Host smart-3c57c0da-d731-4029-bf12-c817cf39ee36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343009028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.2343009028
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.745826810
Short name T649
Test name
Test status
Simulation time 13975741 ps
CPU time 0.75 seconds
Started Jul 26 04:53:26 PM PDT 24
Finished Jul 26 04:53:27 PM PDT 24
Peak memory 205972 kb
Host smart-4be678e5-db00-4b55-8274-5a113306d14c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745826810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.745826810
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.620906381
Short name T676
Test name
Test status
Simulation time 238992127 ps
CPU time 2.39 seconds
Started Jul 26 04:53:23 PM PDT 24
Finished Jul 26 04:53:26 PM PDT 24
Peak memory 233612 kb
Host smart-8576add6-43e6-41e6-9c5a-ee664970d5dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620906381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.620906381
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.1035694715
Short name T708
Test name
Test status
Simulation time 31881683 ps
CPU time 0.78 seconds
Started Jul 26 04:53:28 PM PDT 24
Finished Jul 26 04:53:29 PM PDT 24
Peak memory 207212 kb
Host smart-c48933b3-31d0-4915-a477-589b23300c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035694715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.1035694715
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.2006354376
Short name T457
Test name
Test status
Simulation time 1588417828 ps
CPU time 20.34 seconds
Started Jul 26 04:53:28 PM PDT 24
Finished Jul 26 04:53:49 PM PDT 24
Peak memory 236652 kb
Host smart-82187249-5d1b-49e6-a152-2c132fd58bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006354376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.2006354376
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.2628192063
Short name T573
Test name
Test status
Simulation time 23342216603 ps
CPU time 95 seconds
Started Jul 26 04:53:25 PM PDT 24
Finished Jul 26 04:55:00 PM PDT 24
Peak memory 249924 kb
Host smart-4b47671e-b760-42dd-8835-c7a282feffbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628192063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.2628192063
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.2965814366
Short name T1009
Test name
Test status
Simulation time 4159047916 ps
CPU time 16.67 seconds
Started Jul 26 04:53:23 PM PDT 24
Finished Jul 26 04:53:40 PM PDT 24
Peak memory 225400 kb
Host smart-00d25e99-4bc5-4ddc-a565-989f617b53fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965814366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.2965814366
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_intercept.1214034160
Short name T523
Test name
Test status
Simulation time 921923839 ps
CPU time 6.36 seconds
Started Jul 26 04:53:26 PM PDT 24
Finished Jul 26 04:53:32 PM PDT 24
Peak memory 225220 kb
Host smart-e9adc09c-b22c-4e99-b3dd-b3b116aaa5aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214034160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.1214034160
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.423183196
Short name T517
Test name
Test status
Simulation time 902353689 ps
CPU time 16.92 seconds
Started Jul 26 04:53:22 PM PDT 24
Finished Jul 26 04:53:39 PM PDT 24
Peak memory 241684 kb
Host smart-827906ef-7259-453a-9608-50aad5b35a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423183196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.423183196
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.2947076593
Short name T666
Test name
Test status
Simulation time 3190985933 ps
CPU time 10.69 seconds
Started Jul 26 04:53:27 PM PDT 24
Finished Jul 26 04:53:38 PM PDT 24
Peak memory 233568 kb
Host smart-a4bbb55d-52ea-4f5d-b63b-fee6e0c6c994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947076593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.2947076593
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.4033449801
Short name T342
Test name
Test status
Simulation time 305980253 ps
CPU time 2.53 seconds
Started Jul 26 04:53:22 PM PDT 24
Finished Jul 26 04:53:25 PM PDT 24
Peak memory 233476 kb
Host smart-ef7de41f-bbf7-4a63-937a-ab0ac713e09c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033449801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.4033449801
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.3732607587
Short name T493
Test name
Test status
Simulation time 1834115121 ps
CPU time 6.84 seconds
Started Jul 26 04:53:26 PM PDT 24
Finished Jul 26 04:53:33 PM PDT 24
Peak memory 220040 kb
Host smart-eff52140-dd8b-4419-bcb8-f183c2b4f6e8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3732607587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.3732607587
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.2968511578
Short name T287
Test name
Test status
Simulation time 5565354527 ps
CPU time 129.2 seconds
Started Jul 26 04:53:26 PM PDT 24
Finished Jul 26 04:55:35 PM PDT 24
Peak memory 273688 kb
Host smart-97db0d9b-619b-4c95-ba02-ca6adc19a859
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968511578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.2968511578
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.2151061367
Short name T746
Test name
Test status
Simulation time 5227344100 ps
CPU time 10.72 seconds
Started Jul 26 04:53:26 PM PDT 24
Finished Jul 26 04:53:37 PM PDT 24
Peak memory 220448 kb
Host smart-d6bf0960-0894-4cea-9523-9c21215fb1e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151061367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.2151061367
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.2997325975
Short name T79
Test name
Test status
Simulation time 1148161804 ps
CPU time 3.09 seconds
Started Jul 26 04:53:23 PM PDT 24
Finished Jul 26 04:53:27 PM PDT 24
Peak memory 216972 kb
Host smart-81532d75-0f70-4c0b-91da-2a62430ec68d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997325975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.2997325975
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.1176167002
Short name T561
Test name
Test status
Simulation time 11238570 ps
CPU time 0.71 seconds
Started Jul 26 04:53:22 PM PDT 24
Finished Jul 26 04:53:23 PM PDT 24
Peak memory 206148 kb
Host smart-5ab7fab0-8db3-4550-8851-6beb097e502a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176167002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.1176167002
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.2392529334
Short name T721
Test name
Test status
Simulation time 19694833 ps
CPU time 0.77 seconds
Started Jul 26 04:53:26 PM PDT 24
Finished Jul 26 04:53:27 PM PDT 24
Peak memory 206544 kb
Host smart-3d6bd967-7ac5-442d-bbea-e3f115345290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392529334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.2392529334
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.3962353529
Short name T464
Test name
Test status
Simulation time 4384174690 ps
CPU time 11.38 seconds
Started Jul 26 04:53:25 PM PDT 24
Finished Jul 26 04:53:36 PM PDT 24
Peak memory 225492 kb
Host smart-7bebb54c-d11a-4702-8d61-74b7c1c04068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962353529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.3962353529
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.1088451999
Short name T498
Test name
Test status
Simulation time 61508148 ps
CPU time 0.77 seconds
Started Jul 26 04:53:25 PM PDT 24
Finished Jul 26 04:53:26 PM PDT 24
Peak memory 206292 kb
Host smart-8b051b3c-4cb1-4118-b463-250bcd32b70a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088451999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
1088451999
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.502622062
Short name T175
Test name
Test status
Simulation time 37570756 ps
CPU time 2.41 seconds
Started Jul 26 04:53:21 PM PDT 24
Finished Jul 26 04:53:23 PM PDT 24
Peak memory 233500 kb
Host smart-74c75985-7e79-4934-a8ef-484f2daf1514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502622062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.502622062
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.1211267532
Short name T668
Test name
Test status
Simulation time 58051998 ps
CPU time 0.83 seconds
Started Jul 26 04:53:25 PM PDT 24
Finished Jul 26 04:53:26 PM PDT 24
Peak memory 207480 kb
Host smart-6d0d0f61-298a-4b55-ab8c-456cb1a554c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211267532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.1211267532
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.1920554807
Short name T506
Test name
Test status
Simulation time 20407166403 ps
CPU time 134.62 seconds
Started Jul 26 04:53:27 PM PDT 24
Finished Jul 26 04:55:42 PM PDT 24
Peak memory 250088 kb
Host smart-f456ae08-46e9-4ea9-baa2-1ac2e2e8abb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920554807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.1920554807
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.1886871613
Short name T254
Test name
Test status
Simulation time 66079246376 ps
CPU time 198.05 seconds
Started Jul 26 04:53:26 PM PDT 24
Finished Jul 26 04:56:44 PM PDT 24
Peak memory 254884 kb
Host smart-f99ce792-d662-4f5c-bb5e-fc46b8e81cde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886871613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.1886871613
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.1628753681
Short name T549
Test name
Test status
Simulation time 3412173385 ps
CPU time 14.55 seconds
Started Jul 26 04:53:26 PM PDT 24
Finished Jul 26 04:53:41 PM PDT 24
Peak memory 233600 kb
Host smart-17d24e8f-0119-448b-a966-cbf5c657f33e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628753681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.1628753681
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.1461564975
Short name T158
Test name
Test status
Simulation time 84507937228 ps
CPU time 96.13 seconds
Started Jul 26 04:53:27 PM PDT 24
Finished Jul 26 04:55:04 PM PDT 24
Peak memory 255132 kb
Host smart-5307ee5c-88a1-4163-a529-d276e2025319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461564975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmd
s.1461564975
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_intercept.3249986729
Short name T799
Test name
Test status
Simulation time 716670325 ps
CPU time 2.98 seconds
Started Jul 26 04:53:24 PM PDT 24
Finished Jul 26 04:53:27 PM PDT 24
Peak memory 225252 kb
Host smart-2fafef7d-6dd0-4ae0-8487-332791946a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249986729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.3249986729
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.2607856728
Short name T443
Test name
Test status
Simulation time 8134308844 ps
CPU time 66.74 seconds
Started Jul 26 04:53:27 PM PDT 24
Finished Jul 26 04:54:34 PM PDT 24
Peak memory 241388 kb
Host smart-a9e778aa-e220-4e64-9850-74e701610c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607856728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.2607856728
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.1312564559
Short name T597
Test name
Test status
Simulation time 4480444798 ps
CPU time 14.41 seconds
Started Jul 26 04:53:27 PM PDT 24
Finished Jul 26 04:53:42 PM PDT 24
Peak memory 219788 kb
Host smart-148d6f16-8316-45d6-9f70-7ddf7dccf850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312564559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.1312564559
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.369589403
Short name T990
Test name
Test status
Simulation time 3979512254 ps
CPU time 9.66 seconds
Started Jul 26 04:53:27 PM PDT 24
Finished Jul 26 04:53:37 PM PDT 24
Peak memory 250224 kb
Host smart-768c8f8a-0ffb-4759-ac42-f121d97111d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369589403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.369589403
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.221869576
Short name T12
Test name
Test status
Simulation time 3694738008 ps
CPU time 6.61 seconds
Started Jul 26 04:53:27 PM PDT 24
Finished Jul 26 04:53:34 PM PDT 24
Peak memory 222856 kb
Host smart-d1078d7c-7a72-49cf-8203-5498e87d9adb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=221869576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dire
ct.221869576
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.2961287075
Short name T503
Test name
Test status
Simulation time 40102503 ps
CPU time 0.94 seconds
Started Jul 26 04:53:23 PM PDT 24
Finished Jul 26 04:53:24 PM PDT 24
Peak memory 206472 kb
Host smart-cf0c1f0c-3cfb-49ce-a204-9a7a80e70f2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961287075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.2961287075
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.527996567
Short name T381
Test name
Test status
Simulation time 8356084245 ps
CPU time 11.57 seconds
Started Jul 26 04:53:23 PM PDT 24
Finished Jul 26 04:53:34 PM PDT 24
Peak memory 217040 kb
Host smart-8d5661f6-4360-45f9-b269-bef1cb7b727e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527996567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.527996567
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.3622572343
Short name T905
Test name
Test status
Simulation time 5624614914 ps
CPU time 13.73 seconds
Started Jul 26 04:53:28 PM PDT 24
Finished Jul 26 04:53:42 PM PDT 24
Peak memory 217140 kb
Host smart-2885538e-2a78-46df-8460-35323276b92a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622572343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.3622572343
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.3240157701
Short name T518
Test name
Test status
Simulation time 462828530 ps
CPU time 4.14 seconds
Started Jul 26 04:53:24 PM PDT 24
Finished Jul 26 04:53:29 PM PDT 24
Peak memory 217100 kb
Host smart-e891a7df-e542-42ed-b9aa-2b0abc37868e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240157701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.3240157701
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.2320418245
Short name T816
Test name
Test status
Simulation time 358248779 ps
CPU time 0.99 seconds
Started Jul 26 04:53:25 PM PDT 24
Finished Jul 26 04:53:26 PM PDT 24
Peak memory 206876 kb
Host smart-1c18dcfb-2210-4809-a89d-429362243ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320418245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.2320418245
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.3637836856
Short name T347
Test name
Test status
Simulation time 6784515572 ps
CPU time 14.04 seconds
Started Jul 26 04:53:23 PM PDT 24
Finished Jul 26 04:53:37 PM PDT 24
Peak memory 240800 kb
Host smart-b534c240-9693-44dc-988d-9252e945eaf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637836856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.3637836856
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.4122933447
Short name T930
Test name
Test status
Simulation time 15992590 ps
CPU time 0.81 seconds
Started Jul 26 04:53:40 PM PDT 24
Finished Jul 26 04:53:41 PM PDT 24
Peak memory 206272 kb
Host smart-93ef0870-5f10-4101-bc49-d48d7f0af90d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122933447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
4122933447
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.847423773
Short name T713
Test name
Test status
Simulation time 34380249 ps
CPU time 1.91 seconds
Started Jul 26 04:53:37 PM PDT 24
Finished Jul 26 04:53:39 PM PDT 24
Peak memory 225232 kb
Host smart-ed69a239-9463-4402-a6e8-e705838298e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847423773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.847423773
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.598461052
Short name T428
Test name
Test status
Simulation time 80833310 ps
CPU time 0.75 seconds
Started Jul 26 04:53:26 PM PDT 24
Finished Jul 26 04:53:27 PM PDT 24
Peak memory 207140 kb
Host smart-475e6995-e6e5-4d5a-8001-2e12e5beba7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598461052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.598461052
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.2986686340
Short name T616
Test name
Test status
Simulation time 104297270114 ps
CPU time 265.6 seconds
Started Jul 26 04:53:33 PM PDT 24
Finished Jul 26 04:57:59 PM PDT 24
Peak memory 256420 kb
Host smart-45e4e472-87d1-4839-8ccb-87782d6d94aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986686340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.2986686340
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.4008082757
Short name T822
Test name
Test status
Simulation time 27198827614 ps
CPU time 246.79 seconds
Started Jul 26 04:53:39 PM PDT 24
Finished Jul 26 04:57:46 PM PDT 24
Peak memory 266852 kb
Host smart-9a72a00a-a0bf-4d61-b7aa-cf7f51bfe023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008082757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.4008082757
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.3493265745
Short name T26
Test name
Test status
Simulation time 8680325279 ps
CPU time 75.76 seconds
Started Jul 26 04:53:36 PM PDT 24
Finished Jul 26 04:54:52 PM PDT 24
Peak memory 241772 kb
Host smart-1b23415d-22d0-4a51-b6c7-d74d37774d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493265745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.3493265745
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.1064808206
Short name T1022
Test name
Test status
Simulation time 232889984 ps
CPU time 7.07 seconds
Started Jul 26 04:53:36 PM PDT 24
Finished Jul 26 04:53:44 PM PDT 24
Peak memory 233500 kb
Host smart-c4c4af40-6767-4524-9905-15203362fcc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064808206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.1064808206
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.3885250620
Short name T594
Test name
Test status
Simulation time 30621647253 ps
CPU time 209.35 seconds
Started Jul 26 04:53:33 PM PDT 24
Finished Jul 26 04:57:03 PM PDT 24
Peak memory 256684 kb
Host smart-2db389f9-ba71-4340-a69d-7095f4758abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885250620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmd
s.3885250620
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_intercept.1566554408
Short name T379
Test name
Test status
Simulation time 213103440 ps
CPU time 3.79 seconds
Started Jul 26 04:53:35 PM PDT 24
Finished Jul 26 04:53:39 PM PDT 24
Peak memory 225400 kb
Host smart-6cb87fad-1101-44c2-b49c-77d96d7d879c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566554408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.1566554408
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.3507970705
Short name T673
Test name
Test status
Simulation time 2791821007 ps
CPU time 32.3 seconds
Started Jul 26 04:53:35 PM PDT 24
Finished Jul 26 04:54:07 PM PDT 24
Peak memory 225360 kb
Host smart-4ade4f97-7995-4bc6-8457-1a4cd0c49e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507970705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.3507970705
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.868803151
Short name T657
Test name
Test status
Simulation time 3647610853 ps
CPU time 8.77 seconds
Started Jul 26 04:53:37 PM PDT 24
Finished Jul 26 04:53:46 PM PDT 24
Peak memory 233556 kb
Host smart-05c8e170-dd75-427e-a203-2d57bc53af0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868803151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swap
.868803151
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.213978216
Short name T581
Test name
Test status
Simulation time 1409926905 ps
CPU time 7.24 seconds
Started Jul 26 04:53:38 PM PDT 24
Finished Jul 26 04:53:45 PM PDT 24
Peak memory 241316 kb
Host smart-3300decb-d504-4073-aaa0-344fc2b37e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213978216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.213978216
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.493598811
Short name T473
Test name
Test status
Simulation time 3069491717 ps
CPU time 8.8 seconds
Started Jul 26 04:53:33 PM PDT 24
Finished Jul 26 04:53:42 PM PDT 24
Peak memory 220656 kb
Host smart-db517ccc-7ad9-4ada-bb32-f30b0532caa7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=493598811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dire
ct.493598811
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.2512223790
Short name T16
Test name
Test status
Simulation time 6915136446 ps
CPU time 42.99 seconds
Started Jul 26 04:53:35 PM PDT 24
Finished Jul 26 04:54:18 PM PDT 24
Peak memory 241796 kb
Host smart-be6d85e7-724a-4248-a6c2-fee93a62bdf4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512223790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.2512223790
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.2323032583
Short name T817
Test name
Test status
Simulation time 3341108917 ps
CPU time 9.13 seconds
Started Jul 26 04:53:24 PM PDT 24
Finished Jul 26 04:53:34 PM PDT 24
Peak memory 220184 kb
Host smart-459fa659-c2c7-462b-86b7-52061e75e7eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323032583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.2323032583
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.1132733483
Short name T925
Test name
Test status
Simulation time 697247912 ps
CPU time 1.23 seconds
Started Jul 26 04:53:25 PM PDT 24
Finished Jul 26 04:53:27 PM PDT 24
Peak memory 208576 kb
Host smart-d99b8dd6-19e9-4636-b128-4dcdb5e3a50b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132733483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.1132733483
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.502277606
Short name T785
Test name
Test status
Simulation time 29092589 ps
CPU time 1.21 seconds
Started Jul 26 04:53:34 PM PDT 24
Finished Jul 26 04:53:36 PM PDT 24
Peak memory 216864 kb
Host smart-c6697252-53d5-4568-9aab-6fb5ded601b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502277606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.502277606
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.4187546014
Short name T69
Test name
Test status
Simulation time 31891843 ps
CPU time 0.65 seconds
Started Jul 26 04:53:35 PM PDT 24
Finished Jul 26 04:53:36 PM PDT 24
Peak memory 206212 kb
Host smart-b3149754-9f88-463c-b66a-258fb6720967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187546014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.4187546014
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.2335421490
Short name T888
Test name
Test status
Simulation time 264707962 ps
CPU time 2.69 seconds
Started Jul 26 04:53:36 PM PDT 24
Finished Jul 26 04:53:39 PM PDT 24
Peak memory 233136 kb
Host smart-fcfd3c01-c7ad-452c-9971-6acc945a94ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335421490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.2335421490
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.3258072986
Short name T418
Test name
Test status
Simulation time 14521877 ps
CPU time 0.74 seconds
Started Jul 26 04:53:40 PM PDT 24
Finished Jul 26 04:53:41 PM PDT 24
Peak memory 205320 kb
Host smart-4e2313ab-c2d1-4a16-b202-379cd523aae2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258072986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
3258072986
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.3475410977
Short name T502
Test name
Test status
Simulation time 160680867 ps
CPU time 2.51 seconds
Started Jul 26 04:53:35 PM PDT 24
Finished Jul 26 04:53:38 PM PDT 24
Peak memory 224884 kb
Host smart-38081323-362b-4e68-8b60-ebfc09daf7eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475410977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.3475410977
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.524418591
Short name T363
Test name
Test status
Simulation time 65683491 ps
CPU time 0.81 seconds
Started Jul 26 04:53:34 PM PDT 24
Finished Jul 26 04:53:35 PM PDT 24
Peak memory 207208 kb
Host smart-22aedfdb-8003-4722-a076-154577f46b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524418591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.524418591
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.3888085848
Short name T193
Test name
Test status
Simulation time 103571891529 ps
CPU time 239.04 seconds
Started Jul 26 04:53:35 PM PDT 24
Finished Jul 26 04:57:35 PM PDT 24
Peak memory 269740 kb
Host smart-b95ae414-ad40-4a13-8e71-c2a20907a7d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888085848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.3888085848
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.810007319
Short name T609
Test name
Test status
Simulation time 11964540660 ps
CPU time 55.22 seconds
Started Jul 26 04:53:40 PM PDT 24
Finished Jul 26 04:54:35 PM PDT 24
Peak memory 249948 kb
Host smart-39f19bc6-c660-4523-be7e-aef62971d169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810007319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idle
.810007319
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.3778748095
Short name T1031
Test name
Test status
Simulation time 924227170 ps
CPU time 8.04 seconds
Started Jul 26 04:53:39 PM PDT 24
Finished Jul 26 04:53:47 PM PDT 24
Peak memory 250056 kb
Host smart-42488370-5a7b-49cf-ad29-41c7ee883888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778748095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.3778748095
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.595693475
Short name T172
Test name
Test status
Simulation time 16428759379 ps
CPU time 108.67 seconds
Started Jul 26 04:53:37 PM PDT 24
Finished Jul 26 04:55:26 PM PDT 24
Peak memory 250996 kb
Host smart-24030139-bb36-4557-8794-8a739b8571f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595693475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmds
.595693475
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_intercept.1174739799
Short name T787
Test name
Test status
Simulation time 77323116 ps
CPU time 3.27 seconds
Started Jul 26 04:53:40 PM PDT 24
Finished Jul 26 04:53:44 PM PDT 24
Peak memory 225220 kb
Host smart-6d4305a5-53f8-4236-a155-dc7009163fce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174739799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.1174739799
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.2839449992
Short name T823
Test name
Test status
Simulation time 3346117370 ps
CPU time 22.41 seconds
Started Jul 26 04:53:37 PM PDT 24
Finished Jul 26 04:54:00 PM PDT 24
Peak memory 249716 kb
Host smart-7f6af40b-2eb2-4016-9473-ea945fefa32a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839449992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.2839449992
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.2712900969
Short name T979
Test name
Test status
Simulation time 2785232894 ps
CPU time 4.84 seconds
Started Jul 26 04:53:36 PM PDT 24
Finished Jul 26 04:53:41 PM PDT 24
Peak memory 225324 kb
Host smart-d1cb2789-6eb6-4910-ac48-fb846187f695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712900969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.2712900969
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.1191070803
Short name T223
Test name
Test status
Simulation time 1521456229 ps
CPU time 6.7 seconds
Started Jul 26 04:53:39 PM PDT 24
Finished Jul 26 04:53:46 PM PDT 24
Peak memory 225320 kb
Host smart-eee15919-df0c-4545-88d2-d584fca9b9aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191070803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.1191070803
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.3274316746
Short name T634
Test name
Test status
Simulation time 66579069 ps
CPU time 3.28 seconds
Started Jul 26 04:53:37 PM PDT 24
Finished Jul 26 04:53:41 PM PDT 24
Peak memory 220640 kb
Host smart-0ae7a4da-6428-4359-9280-5d65e5be5e57
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3274316746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.3274316746
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.1085808193
Short name T354
Test name
Test status
Simulation time 19814890305 ps
CPU time 23.76 seconds
Started Jul 26 04:53:37 PM PDT 24
Finished Jul 26 04:54:01 PM PDT 24
Peak memory 217132 kb
Host smart-4252cc4a-69b4-40b5-9528-3070986a01ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085808193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.1085808193
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.4083022800
Short name T584
Test name
Test status
Simulation time 12712724 ps
CPU time 0.77 seconds
Started Jul 26 04:53:37 PM PDT 24
Finished Jul 26 04:53:37 PM PDT 24
Peak memory 206308 kb
Host smart-a4de6c3d-d330-4e1d-80cb-fdc91c8d6592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083022800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.4083022800
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.2436477858
Short name T710
Test name
Test status
Simulation time 89409414 ps
CPU time 0.98 seconds
Started Jul 26 04:53:41 PM PDT 24
Finished Jul 26 04:53:42 PM PDT 24
Peak memory 207732 kb
Host smart-dcb57026-6bc1-4f34-8eae-1533cb3fe5c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436477858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.2436477858
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.3301126476
Short name T1030
Test name
Test status
Simulation time 277443295 ps
CPU time 0.82 seconds
Started Jul 26 04:53:34 PM PDT 24
Finished Jul 26 04:53:35 PM PDT 24
Peak memory 206556 kb
Host smart-102f2a89-d4dc-4115-98d3-03601e13c4cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301126476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.3301126476
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.2527711466
Short name T110
Test name
Test status
Simulation time 23857866829 ps
CPU time 18.36 seconds
Started Jul 26 04:53:40 PM PDT 24
Finished Jul 26 04:53:59 PM PDT 24
Peak memory 225268 kb
Host smart-1ee402a9-ab4d-4082-bbfe-8b4172f05fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527711466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.2527711466
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.1140078691
Short name T974
Test name
Test status
Simulation time 44695196 ps
CPU time 0.77 seconds
Started Jul 26 04:53:36 PM PDT 24
Finished Jul 26 04:53:37 PM PDT 24
Peak memory 206252 kb
Host smart-8b1a94f8-4091-49df-8f38-187c31352d5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140078691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
1140078691
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.3144339599
Short name T83
Test name
Test status
Simulation time 2068313438 ps
CPU time 14.08 seconds
Started Jul 26 04:53:37 PM PDT 24
Finished Jul 26 04:53:51 PM PDT 24
Peak memory 225336 kb
Host smart-88df72db-00d1-48b7-9de2-55b519631bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144339599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.3144339599
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.2401755958
Short name T489
Test name
Test status
Simulation time 38817676 ps
CPU time 0.74 seconds
Started Jul 26 04:53:40 PM PDT 24
Finished Jul 26 04:53:40 PM PDT 24
Peak memory 205964 kb
Host smart-a235f394-bcd9-4a23-9aae-9e037a0b1148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401755958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.2401755958
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.4240669437
Short name T177
Test name
Test status
Simulation time 339173080585 ps
CPU time 344.21 seconds
Started Jul 26 04:53:35 PM PDT 24
Finished Jul 26 04:59:20 PM PDT 24
Peak memory 252396 kb
Host smart-41edabf1-d652-4dc2-bbb4-0fe67707e3c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240669437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.4240669437
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.3023208229
Short name T279
Test name
Test status
Simulation time 93153976182 ps
CPU time 218.82 seconds
Started Jul 26 04:53:36 PM PDT 24
Finished Jul 26 04:57:15 PM PDT 24
Peak memory 258164 kb
Host smart-cf5dfeac-133c-48ce-8925-4e383e2f0854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023208229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.3023208229
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.1176801077
Short name T295
Test name
Test status
Simulation time 111052438 ps
CPU time 5.62 seconds
Started Jul 26 04:53:40 PM PDT 24
Finished Jul 26 04:53:45 PM PDT 24
Peak memory 234188 kb
Host smart-bcec621a-604c-4004-8512-c15426c89243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176801077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.1176801077
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.1927315680
Short name T179
Test name
Test status
Simulation time 165021681752 ps
CPU time 103.1 seconds
Started Jul 26 04:53:38 PM PDT 24
Finished Jul 26 04:55:21 PM PDT 24
Peak memory 254484 kb
Host smart-9a297035-2727-4d0f-8c03-85f388b3a6c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927315680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmd
s.1927315680
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_intercept.444258919
Short name T89
Test name
Test status
Simulation time 320429496 ps
CPU time 6.29 seconds
Started Jul 26 04:53:41 PM PDT 24
Finished Jul 26 04:53:47 PM PDT 24
Peak memory 225308 kb
Host smart-9d66cee9-9c9e-473d-ae4c-baa20bd9f7c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444258919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.444258919
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.1997241206
Short name T54
Test name
Test status
Simulation time 4761178570 ps
CPU time 29.41 seconds
Started Jul 26 04:53:41 PM PDT 24
Finished Jul 26 04:54:11 PM PDT 24
Peak memory 251868 kb
Host smart-359cc1b7-862b-433c-86eb-5b448e2d5fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997241206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.1997241206
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.117461607
Short name T198
Test name
Test status
Simulation time 282562058 ps
CPU time 6.24 seconds
Started Jul 26 04:53:37 PM PDT 24
Finished Jul 26 04:53:43 PM PDT 24
Peak memory 241448 kb
Host smart-51754a38-dac8-4d31-8505-66405dce6923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117461607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swap
.117461607
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.4072909341
Short name T586
Test name
Test status
Simulation time 2105146334 ps
CPU time 6.24 seconds
Started Jul 26 04:53:37 PM PDT 24
Finished Jul 26 04:53:43 PM PDT 24
Peak memory 233508 kb
Host smart-e2238b46-7472-4179-9d5d-374eb2a7a466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072909341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.4072909341
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.69083197
Short name T845
Test name
Test status
Simulation time 167029447 ps
CPU time 4 seconds
Started Jul 26 04:53:41 PM PDT 24
Finished Jul 26 04:53:45 PM PDT 24
Peak memory 220748 kb
Host smart-ef66641d-2713-4dd8-b06c-196634b7ee40
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=69083197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_direc
t.69083197
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.3569540272
Short name T956
Test name
Test status
Simulation time 3849200131 ps
CPU time 102.11 seconds
Started Jul 26 04:53:36 PM PDT 24
Finished Jul 26 04:55:18 PM PDT 24
Peak memory 257812 kb
Host smart-238213ad-bd55-4c82-baf4-24fd9a5f7aeb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569540272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.3569540272
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.2176494554
Short name T738
Test name
Test status
Simulation time 5790984187 ps
CPU time 16.25 seconds
Started Jul 26 04:53:40 PM PDT 24
Finished Jul 26 04:53:56 PM PDT 24
Peak memory 220968 kb
Host smart-9a83faca-1f96-4216-bb26-452b514df39a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176494554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.2176494554
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.592416339
Short name T768
Test name
Test status
Simulation time 2389140420 ps
CPU time 2.73 seconds
Started Jul 26 04:53:40 PM PDT 24
Finished Jul 26 04:53:43 PM PDT 24
Peak memory 217076 kb
Host smart-a1fb2c9f-8919-44b4-aa40-f6bf7df5b4ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592416339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.592416339
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.3400937333
Short name T433
Test name
Test status
Simulation time 572074981 ps
CPU time 1.41 seconds
Started Jul 26 04:53:40 PM PDT 24
Finished Jul 26 04:53:42 PM PDT 24
Peak memory 217104 kb
Host smart-2f0c804d-ca55-448c-accc-3eb23960a8a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400937333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.3400937333
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.1331533878
Short name T926
Test name
Test status
Simulation time 245846849 ps
CPU time 0.73 seconds
Started Jul 26 04:53:40 PM PDT 24
Finished Jul 26 04:53:41 PM PDT 24
Peak memory 206684 kb
Host smart-4f52f320-4675-4c3a-b4ea-26fefb9c99ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331533878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.1331533878
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.2981135868
Short name T242
Test name
Test status
Simulation time 1666656259 ps
CPU time 6.1 seconds
Started Jul 26 04:53:42 PM PDT 24
Finished Jul 26 04:53:48 PM PDT 24
Peak memory 234532 kb
Host smart-21b6301e-cbc7-4a80-a1dd-b6c8bc7241e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981135868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.2981135868
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.436814591
Short name T543
Test name
Test status
Simulation time 38299077 ps
CPU time 0.78 seconds
Started Jul 26 04:53:46 PM PDT 24
Finished Jul 26 04:53:47 PM PDT 24
Peak memory 205308 kb
Host smart-beb65b26-8563-4d0a-9ac2-2df21991e562
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436814591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.436814591
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.3431937048
Short name T628
Test name
Test status
Simulation time 492926583 ps
CPU time 3.04 seconds
Started Jul 26 04:53:42 PM PDT 24
Finished Jul 26 04:53:46 PM PDT 24
Peak memory 225204 kb
Host smart-3af802bd-4d99-430d-ad2d-11eb00358270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431937048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.3431937048
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.3029333340
Short name T547
Test name
Test status
Simulation time 35712036 ps
CPU time 0.79 seconds
Started Jul 26 04:53:33 PM PDT 24
Finished Jul 26 04:53:34 PM PDT 24
Peak memory 207504 kb
Host smart-3c4743d3-da2d-413a-a213-350df8c2839e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029333340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.3029333340
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.1407608827
Short name T455
Test name
Test status
Simulation time 504513121 ps
CPU time 7.05 seconds
Started Jul 26 04:53:44 PM PDT 24
Finished Jul 26 04:53:51 PM PDT 24
Peak memory 237588 kb
Host smart-d0845693-a21c-4784-bfe5-4d64e35f29dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407608827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.1407608827
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.3144973934
Short name T284
Test name
Test status
Simulation time 7980356566 ps
CPU time 63.88 seconds
Started Jul 26 04:53:41 PM PDT 24
Finished Jul 26 04:54:45 PM PDT 24
Peak memory 234592 kb
Host smart-e54e1f3a-38b4-4b5b-b013-b5d75d11066e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144973934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.3144973934
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.1574128653
Short name T289
Test name
Test status
Simulation time 151503908547 ps
CPU time 311.57 seconds
Started Jul 26 04:53:46 PM PDT 24
Finished Jul 26 04:58:58 PM PDT 24
Peak memory 258004 kb
Host smart-79f66a4d-cff8-40c5-ab02-4e759770cfbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574128653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.1574128653
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.2325610680
Short name T658
Test name
Test status
Simulation time 54157462 ps
CPU time 2.73 seconds
Started Jul 26 04:53:44 PM PDT 24
Finished Jul 26 04:53:46 PM PDT 24
Peak memory 225228 kb
Host smart-5002fea1-d6f0-4b7f-9847-c9ce8bb873d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325610680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.2325610680
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.344886524
Short name T358
Test name
Test status
Simulation time 59451275670 ps
CPU time 63.51 seconds
Started Jul 26 04:53:43 PM PDT 24
Finished Jul 26 04:54:47 PM PDT 24
Peak memory 241820 kb
Host smart-09cdcae8-77cf-4897-9a62-51b43d31404b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344886524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmds
.344886524
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_intercept.2537893169
Short name T908
Test name
Test status
Simulation time 225098698 ps
CPU time 3.07 seconds
Started Jul 26 04:53:35 PM PDT 24
Finished Jul 26 04:53:38 PM PDT 24
Peak memory 233456 kb
Host smart-48119a0d-1342-452d-9a62-28891edc35b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537893169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.2537893169
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.379414170
Short name T314
Test name
Test status
Simulation time 2814583188 ps
CPU time 28.33 seconds
Started Jul 26 04:53:42 PM PDT 24
Finished Jul 26 04:54:10 PM PDT 24
Peak memory 250024 kb
Host smart-c1435fb4-de2c-447b-ae14-c1da9b34b027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379414170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.379414170
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.3806402861
Short name T564
Test name
Test status
Simulation time 418732371 ps
CPU time 2.28 seconds
Started Jul 26 04:53:38 PM PDT 24
Finished Jul 26 04:53:40 PM PDT 24
Peak memory 225176 kb
Host smart-0dfc4ce8-7b06-426c-a32c-352cc27b9ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806402861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.3806402861
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.2081883771
Short name T511
Test name
Test status
Simulation time 849650389 ps
CPU time 5.18 seconds
Started Jul 26 04:53:36 PM PDT 24
Finished Jul 26 04:53:41 PM PDT 24
Peak memory 225296 kb
Host smart-cd7490b2-172c-4c12-9f15-792f90fb3d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081883771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.2081883771
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.202644048
Short name T923
Test name
Test status
Simulation time 1980012348 ps
CPU time 5.44 seconds
Started Jul 26 04:53:46 PM PDT 24
Finished Jul 26 04:53:52 PM PDT 24
Peak memory 220672 kb
Host smart-ea417c26-8c73-4ab9-ae3b-25e5c0cc43c9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=202644048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dire
ct.202644048
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.2192216199
Short name T6
Test name
Test status
Simulation time 6216558856 ps
CPU time 32.89 seconds
Started Jul 26 04:53:45 PM PDT 24
Finished Jul 26 04:54:18 PM PDT 24
Peak memory 249948 kb
Host smart-4359ce30-8b80-4b48-a2cb-fba6deba1b34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192216199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.2192216199
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.3383531513
Short name T688
Test name
Test status
Simulation time 53119301 ps
CPU time 0.74 seconds
Started Jul 26 04:53:37 PM PDT 24
Finished Jul 26 04:53:38 PM PDT 24
Peak memory 206304 kb
Host smart-e5ef66f9-e83b-45bb-b82a-69c4018986bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383531513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.3383531513
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.4140634216
Short name T794
Test name
Test status
Simulation time 18954553333 ps
CPU time 12.52 seconds
Started Jul 26 04:53:32 PM PDT 24
Finished Jul 26 04:53:45 PM PDT 24
Peak memory 217168 kb
Host smart-22ab3e84-7ac9-4781-8773-19feaacd91c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140634216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.4140634216
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.2994607201
Short name T546
Test name
Test status
Simulation time 124767736 ps
CPU time 1.75 seconds
Started Jul 26 04:53:34 PM PDT 24
Finished Jul 26 04:53:36 PM PDT 24
Peak memory 217060 kb
Host smart-bfc0cc62-cda3-438c-8c68-e334aadcf54f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994607201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.2994607201
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.3472110564
Short name T812
Test name
Test status
Simulation time 42284357 ps
CPU time 0.72 seconds
Started Jul 26 04:53:35 PM PDT 24
Finished Jul 26 04:53:35 PM PDT 24
Peak memory 206632 kb
Host smart-6b8ebc20-894e-4112-8084-fa577ab218e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472110564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.3472110564
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.1341258991
Short name T447
Test name
Test status
Simulation time 17295315621 ps
CPU time 11.47 seconds
Started Jul 26 04:53:44 PM PDT 24
Finished Jul 26 04:53:56 PM PDT 24
Peak memory 240908 kb
Host smart-f77a30ee-078a-4b01-9551-e0c3a3bc6a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341258991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.1341258991
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.3894278295
Short name T890
Test name
Test status
Simulation time 14626152 ps
CPU time 0.72 seconds
Started Jul 26 04:52:18 PM PDT 24
Finished Jul 26 04:52:19 PM PDT 24
Peak memory 205256 kb
Host smart-39aa16ac-bd9f-462d-9a08-810a428fb2c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894278295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.3
894278295
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.3838414395
Short name T887
Test name
Test status
Simulation time 161947172 ps
CPU time 2.95 seconds
Started Jul 26 04:52:15 PM PDT 24
Finished Jul 26 04:52:18 PM PDT 24
Peak memory 225304 kb
Host smart-38a7362d-433d-4622-937f-1771d3e093c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838414395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.3838414395
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.3620095621
Short name T540
Test name
Test status
Simulation time 21995066 ps
CPU time 0.83 seconds
Started Jul 26 04:52:08 PM PDT 24
Finished Jul 26 04:52:09 PM PDT 24
Peak memory 207164 kb
Host smart-d7ded2a6-c343-4ae8-9339-02630b640c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620095621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.3620095621
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.2956943833
Short name T401
Test name
Test status
Simulation time 4026507010 ps
CPU time 15.01 seconds
Started Jul 26 04:52:15 PM PDT 24
Finished Jul 26 04:52:31 PM PDT 24
Peak memory 241836 kb
Host smart-8692ac55-228e-4b4a-aa04-588c38c5912c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956943833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.2956943833
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.977773357
Short name T835
Test name
Test status
Simulation time 5714989516 ps
CPU time 55.36 seconds
Started Jul 26 04:52:13 PM PDT 24
Finished Jul 26 04:53:08 PM PDT 24
Peak memory 251728 kb
Host smart-24017cf3-b009-4e1a-b84f-4faba51f0a6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977773357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.977773357
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.2209554758
Short name T203
Test name
Test status
Simulation time 9640588169 ps
CPU time 48.14 seconds
Started Jul 26 04:52:23 PM PDT 24
Finished Jul 26 04:53:12 PM PDT 24
Peak memory 265312 kb
Host smart-f8f34142-9ff3-4a3a-9938-5d43da51e33a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209554758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.2209554758
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.3398121352
Short name T803
Test name
Test status
Simulation time 274497159 ps
CPU time 3.17 seconds
Started Jul 26 04:52:16 PM PDT 24
Finished Jul 26 04:52:19 PM PDT 24
Peak memory 233512 kb
Host smart-1285ee38-3f7e-4a26-94fa-6a1d2a8acd39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398121352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.3398121352
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.1586553892
Short name T829
Test name
Test status
Simulation time 34303021005 ps
CPU time 117.53 seconds
Started Jul 26 04:52:14 PM PDT 24
Finished Jul 26 04:54:12 PM PDT 24
Peak memory 250496 kb
Host smart-b3b8752d-a548-4cc8-b93a-1b09518c914a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586553892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds
.1586553892
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_intercept.3791516744
Short name T225
Test name
Test status
Simulation time 477527477 ps
CPU time 5.1 seconds
Started Jul 26 04:52:14 PM PDT 24
Finished Jul 26 04:52:19 PM PDT 24
Peak memory 225396 kb
Host smart-799845b2-6bb0-452b-bbcf-efdd2eed3305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791516744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.3791516744
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.3104426817
Short name T530
Test name
Test status
Simulation time 9421660865 ps
CPU time 23.69 seconds
Started Jul 26 04:52:12 PM PDT 24
Finished Jul 26 04:52:35 PM PDT 24
Peak memory 233560 kb
Host smart-cc8c2901-4f84-4933-a6b9-3e49c2a55486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104426817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.3104426817
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.2008813423
Short name T916
Test name
Test status
Simulation time 28748346 ps
CPU time 1.02 seconds
Started Jul 26 04:52:05 PM PDT 24
Finished Jul 26 04:52:06 PM PDT 24
Peak memory 217284 kb
Host smart-77a25cd0-72d2-4a70-ba4b-c017d2a49d5f
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008813423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.spi_device_mem_parity.2008813423
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.2516762979
Short name T795
Test name
Test status
Simulation time 4447033513 ps
CPU time 15.5 seconds
Started Jul 26 04:52:15 PM PDT 24
Finished Jul 26 04:52:31 PM PDT 24
Peak memory 233556 kb
Host smart-76a728aa-80de-40c5-8b4d-a9f11149e75d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516762979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.2516762979
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.3163185182
Short name T727
Test name
Test status
Simulation time 64667944 ps
CPU time 2.35 seconds
Started Jul 26 04:52:07 PM PDT 24
Finished Jul 26 04:52:10 PM PDT 24
Peak memory 225268 kb
Host smart-9dbd8fd1-dfba-4f17-a3dc-a26ea4590d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163185182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.3163185182
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.2761767040
Short name T55
Test name
Test status
Simulation time 488011327 ps
CPU time 5.72 seconds
Started Jul 26 04:53:57 PM PDT 24
Finished Jul 26 04:54:03 PM PDT 24
Peak memory 223240 kb
Host smart-55c9c2aa-77f6-4b6b-a805-3005d77d7805
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2761767040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.2761767040
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.315973146
Short name T60
Test name
Test status
Simulation time 243232342 ps
CPU time 1.06 seconds
Started Jul 26 04:52:13 PM PDT 24
Finished Jul 26 04:52:14 PM PDT 24
Peak memory 235720 kb
Host smart-63c9e03d-2de2-443e-8dd2-c00e541341d5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315973146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.315973146
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.2154039850
Short name T589
Test name
Test status
Simulation time 213040629 ps
CPU time 1.1 seconds
Started Jul 26 04:53:56 PM PDT 24
Finished Jul 26 04:53:57 PM PDT 24
Peak memory 207628 kb
Host smart-3bd2c123-c8a5-4992-8ad2-3b3017aac00b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154039850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.2154039850
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.1205884925
Short name T304
Test name
Test status
Simulation time 11761644805 ps
CPU time 33.16 seconds
Started Jul 26 04:52:05 PM PDT 24
Finished Jul 26 04:52:38 PM PDT 24
Peak memory 217152 kb
Host smart-01535856-49e1-4154-966e-fa9e8e078c3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205884925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.1205884925
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.3010559767
Short name T737
Test name
Test status
Simulation time 9055239197 ps
CPU time 23.04 seconds
Started Jul 26 04:52:16 PM PDT 24
Finished Jul 26 04:52:39 PM PDT 24
Peak memory 217120 kb
Host smart-ef99cf8a-708b-48bd-97c3-eb9d50e0e9ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010559767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.3010559767
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.3010387008
Short name T695
Test name
Test status
Simulation time 65710118 ps
CPU time 0.92 seconds
Started Jul 26 04:52:06 PM PDT 24
Finished Jul 26 04:52:07 PM PDT 24
Peak memory 207644 kb
Host smart-a13ed103-9f0b-484e-99c2-bd2c6b2725cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010387008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.3010387008
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.1310147391
Short name T446
Test name
Test status
Simulation time 30705860 ps
CPU time 0.71 seconds
Started Jul 26 04:52:16 PM PDT 24
Finished Jul 26 04:52:17 PM PDT 24
Peak memory 206600 kb
Host smart-fa98dcd0-ae4e-4dc7-b075-d790fc2e97ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310147391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.1310147391
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.784664162
Short name T684
Test name
Test status
Simulation time 1792437223 ps
CPU time 3.68 seconds
Started Jul 26 04:52:14 PM PDT 24
Finished Jul 26 04:52:18 PM PDT 24
Peak memory 233492 kb
Host smart-caeb965c-8d53-46d7-873a-754953e82b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784664162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.784664162
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.1350393143
Short name T505
Test name
Test status
Simulation time 49191894 ps
CPU time 0.69 seconds
Started Jul 26 05:30:36 PM PDT 24
Finished Jul 26 05:30:37 PM PDT 24
Peak memory 206112 kb
Host smart-4566fcc0-a499-4c1b-b8c7-46bd3e360af9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350393143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
1350393143
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.1797360166
Short name T964
Test name
Test status
Simulation time 758942345 ps
CPU time 4.83 seconds
Started Jul 26 05:04:23 PM PDT 24
Finished Jul 26 05:04:28 PM PDT 24
Peak memory 233584 kb
Host smart-f324db8b-b593-4fc1-97ac-2a291633f5bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797360166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.1797360166
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.3905005361
Short name T324
Test name
Test status
Simulation time 46207991 ps
CPU time 0.78 seconds
Started Jul 26 04:53:46 PM PDT 24
Finished Jul 26 04:53:47 PM PDT 24
Peak memory 207492 kb
Host smart-034d8b84-35b6-4d81-83eb-f37ff287fa6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905005361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.3905005361
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.1601875679
Short name T1008
Test name
Test status
Simulation time 90878480912 ps
CPU time 84.91 seconds
Started Jul 26 05:41:08 PM PDT 24
Finished Jul 26 05:42:33 PM PDT 24
Peak memory 250072 kb
Host smart-88ca810a-a6b9-4ccc-bacf-b5f0de6b1ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601875679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.1601875679
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.754631619
Short name T797
Test name
Test status
Simulation time 4204312105 ps
CPU time 17.21 seconds
Started Jul 26 05:06:59 PM PDT 24
Finished Jul 26 05:07:16 PM PDT 24
Peak memory 239456 kb
Host smart-12785586-12ac-4183-82fd-6ecd1ccce7e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754631619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.754631619
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.814980242
Short name T578
Test name
Test status
Simulation time 30789810451 ps
CPU time 82.86 seconds
Started Jul 26 04:56:57 PM PDT 24
Finished Jul 26 04:58:21 PM PDT 24
Peak memory 236844 kb
Host smart-96c7f1be-d849-4f8d-86b7-0f9b55460f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814980242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idle
.814980242
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.1687537528
Short name T222
Test name
Test status
Simulation time 7844581383 ps
CPU time 32.07 seconds
Started Jul 26 05:28:43 PM PDT 24
Finished Jul 26 05:29:15 PM PDT 24
Peak memory 225428 kb
Host smart-0614f25c-9089-4395-bb25-29324acb2fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687537528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.1687537528
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.3583510116
Short name T577
Test name
Test status
Simulation time 5710225150 ps
CPU time 35.54 seconds
Started Jul 26 04:53:46 PM PDT 24
Finished Jul 26 04:54:22 PM PDT 24
Peak memory 235896 kb
Host smart-a00bb0b7-b6b9-4b5c-b2d5-255f1cdebb5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583510116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmd
s.3583510116
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/30.spi_device_intercept.920391145
Short name T640
Test name
Test status
Simulation time 9675979061 ps
CPU time 39.41 seconds
Started Jul 26 04:53:48 PM PDT 24
Finished Jul 26 04:54:28 PM PDT 24
Peak memory 225372 kb
Host smart-76e79aea-c4f8-4b98-9e26-1c01c2b31b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920391145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.920391145
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.2786223139
Short name T837
Test name
Test status
Simulation time 701128631 ps
CPU time 2.41 seconds
Started Jul 26 05:17:20 PM PDT 24
Finished Jul 26 05:17:23 PM PDT 24
Peak memory 225368 kb
Host smart-c3604a1a-72d0-47da-81a2-938aa114af7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786223139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.2786223139
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.2910088122
Short name T261
Test name
Test status
Simulation time 9672248181 ps
CPU time 30.25 seconds
Started Jul 26 04:53:48 PM PDT 24
Finished Jul 26 04:54:18 PM PDT 24
Peak memory 225324 kb
Host smart-ae191d9d-decb-45ed-90c7-ae5f6009dcf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910088122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.2910088122
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.4192105106
Short name T538
Test name
Test status
Simulation time 472014586 ps
CPU time 3.59 seconds
Started Jul 26 05:30:42 PM PDT 24
Finished Jul 26 05:30:46 PM PDT 24
Peak memory 225380 kb
Host smart-d710deab-82b6-43f9-88ef-56b5cf5a6416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192105106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.4192105106
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.2590927122
Short name T932
Test name
Test status
Simulation time 1021571672 ps
CPU time 7.13 seconds
Started Jul 26 04:56:22 PM PDT 24
Finished Jul 26 04:56:29 PM PDT 24
Peak memory 220012 kb
Host smart-8ecd3592-44ea-4da6-ba43-e18cf51388ad
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2590927122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.2590927122
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.1590974806
Short name T827
Test name
Test status
Simulation time 18294318203 ps
CPU time 81.97 seconds
Started Jul 26 05:36:41 PM PDT 24
Finished Jul 26 05:38:03 PM PDT 24
Peak memory 257860 kb
Host smart-cec083b8-5d8a-449e-b57a-4f1ea96e455c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590974806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.1590974806
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.3392728758
Short name T742
Test name
Test status
Simulation time 21309134999 ps
CPU time 48.14 seconds
Started Jul 26 04:53:46 PM PDT 24
Finished Jul 26 04:54:35 PM PDT 24
Peak memory 217196 kb
Host smart-af469ba5-c381-48d4-8086-69d899b26377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392728758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.3392728758
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.993613805
Short name T402
Test name
Test status
Simulation time 556336823 ps
CPU time 4.43 seconds
Started Jul 26 04:53:46 PM PDT 24
Finished Jul 26 04:53:51 PM PDT 24
Peak memory 217048 kb
Host smart-d001730a-a582-4d6d-9c9b-60ab5fb6bc32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993613805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.993613805
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.2622309458
Short name T534
Test name
Test status
Simulation time 97721320 ps
CPU time 1.43 seconds
Started Jul 26 04:53:43 PM PDT 24
Finished Jul 26 04:53:45 PM PDT 24
Peak memory 208900 kb
Host smart-0a7dc41c-56e9-405e-b749-0896c3451496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622309458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.2622309458
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.903179891
Short name T876
Test name
Test status
Simulation time 165764350 ps
CPU time 0.82 seconds
Started Jul 26 04:53:44 PM PDT 24
Finished Jul 26 04:53:45 PM PDT 24
Peak memory 206540 kb
Host smart-6e4798b1-5908-4871-bcaf-59a32f274f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903179891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.903179891
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.1376135142
Short name T230
Test name
Test status
Simulation time 265535309 ps
CPU time 2.37 seconds
Started Jul 26 05:14:30 PM PDT 24
Finished Jul 26 05:14:33 PM PDT 24
Peak memory 225364 kb
Host smart-7f0ff260-1d9c-490d-9d67-b4184fb9811f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376135142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.1376135142
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.1855829089
Short name T555
Test name
Test status
Simulation time 30851370 ps
CPU time 0.69 seconds
Started Jul 26 04:53:46 PM PDT 24
Finished Jul 26 04:53:47 PM PDT 24
Peak memory 205960 kb
Host smart-c528772f-8bbc-4289-b059-813025c76704
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855829089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
1855829089
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.1329171363
Short name T975
Test name
Test status
Simulation time 413523518 ps
CPU time 2.55 seconds
Started Jul 26 04:53:47 PM PDT 24
Finished Jul 26 04:53:50 PM PDT 24
Peak memory 225352 kb
Host smart-839633a6-2e7e-4bc4-b055-d956295c1976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329171363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.1329171363
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.2713234661
Short name T10
Test name
Test status
Simulation time 19271173 ps
CPU time 0.84 seconds
Started Jul 26 05:09:03 PM PDT 24
Finished Jul 26 05:09:04 PM PDT 24
Peak memory 207292 kb
Host smart-5a654d45-3d82-4239-950c-bb202a72c862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713234661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.2713234661
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.2393042979
Short name T992
Test name
Test status
Simulation time 12993401444 ps
CPU time 162.51 seconds
Started Jul 26 04:53:49 PM PDT 24
Finished Jul 26 04:56:31 PM PDT 24
Peak memory 257692 kb
Host smart-d9bf9c1e-7393-46ba-b65b-6798115fe4f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393042979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.2393042979
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.2803864288
Short name T745
Test name
Test status
Simulation time 81501529350 ps
CPU time 202.84 seconds
Started Jul 26 04:53:48 PM PDT 24
Finished Jul 26 04:57:11 PM PDT 24
Peak memory 250044 kb
Host smart-dfef05bd-92e2-4a41-b9fa-5619038c9356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803864288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.2803864288
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.2787738757
Short name T917
Test name
Test status
Simulation time 4494063444 ps
CPU time 68.68 seconds
Started Jul 26 04:53:47 PM PDT 24
Finished Jul 26 04:54:56 PM PDT 24
Peak memory 225312 kb
Host smart-9a7fd6f4-60f1-4f7c-b2aa-a0f642cc11e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787738757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.2787738757
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.3122382559
Short name T215
Test name
Test status
Simulation time 6724390882 ps
CPU time 50.41 seconds
Started Jul 26 04:53:44 PM PDT 24
Finished Jul 26 04:54:35 PM PDT 24
Peak memory 238816 kb
Host smart-eb96913c-f33c-4fc7-9875-649a89043824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122382559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmd
s.3122382559
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/31.spi_device_intercept.2643335515
Short name T217
Test name
Test status
Simulation time 338681326 ps
CPU time 5.38 seconds
Started Jul 26 04:53:45 PM PDT 24
Finished Jul 26 04:53:50 PM PDT 24
Peak memory 233556 kb
Host smart-849c4684-f18a-401d-b2cc-4a1d7127b66f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643335515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.2643335515
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.3338405603
Short name T259
Test name
Test status
Simulation time 1666160910 ps
CPU time 27.04 seconds
Started Jul 26 04:53:47 PM PDT 24
Finished Jul 26 04:54:14 PM PDT 24
Peak memory 233476 kb
Host smart-10f63383-22a0-43c1-b402-7b6a60c1f312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338405603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.3338405603
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.4203741573
Short name T808
Test name
Test status
Simulation time 681796801 ps
CPU time 6.01 seconds
Started Jul 26 04:53:46 PM PDT 24
Finished Jul 26 04:53:52 PM PDT 24
Peak memory 225316 kb
Host smart-68e78e79-ce4f-4237-8a95-673af00dab1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203741573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.4203741573
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.1408977043
Short name T995
Test name
Test status
Simulation time 137664264 ps
CPU time 2.6 seconds
Started Jul 26 04:53:43 PM PDT 24
Finished Jul 26 04:53:45 PM PDT 24
Peak memory 233140 kb
Host smart-5b18a5d8-9814-48f5-8edb-57c8cc357224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408977043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.1408977043
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.3287316254
Short name T144
Test name
Test status
Simulation time 556189316 ps
CPU time 8.16 seconds
Started Jul 26 04:53:45 PM PDT 24
Finished Jul 26 04:53:53 PM PDT 24
Peak memory 222956 kb
Host smart-59f977e7-742a-4bc2-9154-753f462afb5b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3287316254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.3287316254
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.3334911003
Short name T300
Test name
Test status
Simulation time 1972749938 ps
CPU time 19.18 seconds
Started Jul 26 05:21:15 PM PDT 24
Finished Jul 26 05:21:34 PM PDT 24
Peak memory 217136 kb
Host smart-2c55e1fc-690a-43fb-b83d-91f5f2e4f834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334911003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.3334911003
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.3675924579
Short name T846
Test name
Test status
Simulation time 9075447635 ps
CPU time 24.23 seconds
Started Jul 26 05:01:42 PM PDT 24
Finished Jul 26 05:02:06 PM PDT 24
Peak memory 217152 kb
Host smart-7e1c3b03-cd6d-4bc8-96eb-894308a8293f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675924579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.3675924579
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.1241498615
Short name T977
Test name
Test status
Simulation time 86252080 ps
CPU time 1.3 seconds
Started Jul 26 05:11:48 PM PDT 24
Finished Jul 26 05:11:49 PM PDT 24
Peak memory 217132 kb
Host smart-176f3d76-7905-4078-9855-d401ef99eda1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241498615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.1241498615
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.3757370175
Short name T927
Test name
Test status
Simulation time 76452680 ps
CPU time 0.78 seconds
Started Jul 26 04:53:48 PM PDT 24
Finished Jul 26 04:53:49 PM PDT 24
Peak memory 206628 kb
Host smart-9491c74e-df50-490d-8f4c-cf7b8230907e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757370175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.3757370175
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.2532666554
Short name T924
Test name
Test status
Simulation time 17385858870 ps
CPU time 11.71 seconds
Started Jul 26 04:53:47 PM PDT 24
Finished Jul 26 04:53:59 PM PDT 24
Peak memory 225340 kb
Host smart-556d7ef1-9c37-49b0-971f-27148e3f7c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532666554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.2532666554
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.3229226783
Short name T528
Test name
Test status
Simulation time 13538579 ps
CPU time 0.71 seconds
Started Jul 26 04:53:44 PM PDT 24
Finished Jul 26 04:53:45 PM PDT 24
Peak memory 206228 kb
Host smart-8091fd47-6b73-4d02-bc8c-c737e6dfb465
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229226783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
3229226783
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.3823045100
Short name T237
Test name
Test status
Simulation time 261117934 ps
CPU time 3.29 seconds
Started Jul 26 04:54:06 PM PDT 24
Finished Jul 26 04:54:10 PM PDT 24
Peak memory 233544 kb
Host smart-e1d035ea-f6ae-4e22-87b7-6955cf70dda5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823045100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.3823045100
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.840086651
Short name T367
Test name
Test status
Simulation time 50495956 ps
CPU time 0.8 seconds
Started Jul 26 04:53:49 PM PDT 24
Finished Jul 26 04:53:50 PM PDT 24
Peak memory 207020 kb
Host smart-b003e903-e756-4744-a840-b3a10dd92bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840086651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.840086651
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.2957347364
Short name T159
Test name
Test status
Simulation time 5245220054 ps
CPU time 37.5 seconds
Started Jul 26 04:53:52 PM PDT 24
Finished Jul 26 04:54:29 PM PDT 24
Peak memory 225356 kb
Host smart-433b3d2f-494f-43e0-b350-42acbff1f09a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957347364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.2957347364
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.1383378168
Short name T361
Test name
Test status
Simulation time 7441562450 ps
CPU time 26.8 seconds
Started Jul 26 04:53:49 PM PDT 24
Finished Jul 26 04:54:16 PM PDT 24
Peak memory 233580 kb
Host smart-19ab9427-352e-4fd5-a09a-3ba96d60c1b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383378168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.1383378168
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.2778276529
Short name T286
Test name
Test status
Simulation time 3918162544 ps
CPU time 37.35 seconds
Started Jul 26 04:53:47 PM PDT 24
Finished Jul 26 04:54:24 PM PDT 24
Peak memory 249932 kb
Host smart-3e2ea87b-84d7-4b36-b190-e4130582eb4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778276529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmd
s.2778276529
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_intercept.634761345
Short name T535
Test name
Test status
Simulation time 557214942 ps
CPU time 3.57 seconds
Started Jul 26 04:53:50 PM PDT 24
Finished Jul 26 04:53:54 PM PDT 24
Peak memory 219696 kb
Host smart-f72965cc-f428-4301-a32b-dc4a4dbf54df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634761345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.634761345
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.2874045909
Short name T811
Test name
Test status
Simulation time 1458232693 ps
CPU time 7.89 seconds
Started Jul 26 04:53:51 PM PDT 24
Finished Jul 26 04:53:59 PM PDT 24
Peak memory 233448 kb
Host smart-26fa261f-79fd-4ca4-8d08-f261366daa80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874045909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.2874045909
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.2890730176
Short name T257
Test name
Test status
Simulation time 2044626225 ps
CPU time 4.52 seconds
Started Jul 26 04:53:50 PM PDT 24
Finished Jul 26 04:53:55 PM PDT 24
Peak memory 225216 kb
Host smart-50da1b27-ea80-41b0-831e-c952a2226a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890730176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.2890730176
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.88551351
Short name T722
Test name
Test status
Simulation time 689261112 ps
CPU time 4.69 seconds
Started Jul 26 04:53:45 PM PDT 24
Finished Jul 26 04:53:50 PM PDT 24
Peak memory 233496 kb
Host smart-1ca8dfba-7bb8-4e08-b640-fd8c5a050c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88551351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.88551351
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.3446460222
Short name T142
Test name
Test status
Simulation time 740726097 ps
CPU time 5.15 seconds
Started Jul 26 04:53:47 PM PDT 24
Finished Jul 26 04:53:52 PM PDT 24
Peak memory 221460 kb
Host smart-bf42cea9-5aea-414c-a358-ac56767887a2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3446460222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.3446460222
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.1888017816
Short name T301
Test name
Test status
Simulation time 7336619704 ps
CPU time 12.72 seconds
Started Jul 26 04:53:45 PM PDT 24
Finished Jul 26 04:53:58 PM PDT 24
Peak memory 217160 kb
Host smart-8e414723-6a42-46b1-bfb7-9323cae807fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888017816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.1888017816
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.504570992
Short name T994
Test name
Test status
Simulation time 5569469075 ps
CPU time 4.98 seconds
Started Jul 26 04:53:44 PM PDT 24
Finished Jul 26 04:53:49 PM PDT 24
Peak memory 217000 kb
Host smart-73e36623-0126-451c-8547-b6e026bf7c3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504570992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.504570992
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.3064214690
Short name T369
Test name
Test status
Simulation time 32619487 ps
CPU time 0.89 seconds
Started Jul 26 04:53:54 PM PDT 24
Finished Jul 26 04:53:55 PM PDT 24
Peak memory 207564 kb
Host smart-ae7a0519-52cd-4a14-af93-c3a3a383169f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064214690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.3064214690
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.2920580766
Short name T749
Test name
Test status
Simulation time 16403737 ps
CPU time 0.72 seconds
Started Jul 26 04:53:49 PM PDT 24
Finished Jul 26 04:53:50 PM PDT 24
Peak memory 206640 kb
Host smart-d4eaedf9-9b40-48df-89b0-ebfbc1b4a835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920580766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.2920580766
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.968430376
Short name T585
Test name
Test status
Simulation time 960360731 ps
CPU time 4.78 seconds
Started Jul 26 04:53:46 PM PDT 24
Finished Jul 26 04:53:51 PM PDT 24
Peak memory 233540 kb
Host smart-357b92a6-646f-441b-98b4-e714234e6591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968430376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.968430376
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.783451735
Short name T815
Test name
Test status
Simulation time 26897297 ps
CPU time 0.71 seconds
Started Jul 26 04:53:58 PM PDT 24
Finished Jul 26 04:53:59 PM PDT 24
Peak memory 205932 kb
Host smart-e90ac0be-a093-4b6a-af70-2cd5c8f2cd70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783451735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.783451735
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.589016293
Short name T243
Test name
Test status
Simulation time 1061936639 ps
CPU time 5.86 seconds
Started Jul 26 04:53:55 PM PDT 24
Finished Jul 26 04:54:01 PM PDT 24
Peak memory 233380 kb
Host smart-dd3bff0e-6282-471a-9f5f-d010f9bad30b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589016293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.589016293
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.1035847730
Short name T776
Test name
Test status
Simulation time 25820410 ps
CPU time 0.78 seconds
Started Jul 26 04:53:46 PM PDT 24
Finished Jul 26 04:53:47 PM PDT 24
Peak memory 207056 kb
Host smart-57ff2e1a-8215-4334-9db0-1a5a5ca679c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035847730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.1035847730
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.3160791592
Short name T754
Test name
Test status
Simulation time 52168927502 ps
CPU time 101.94 seconds
Started Jul 26 04:53:53 PM PDT 24
Finished Jul 26 04:55:35 PM PDT 24
Peak memory 250440 kb
Host smart-77b1a51e-9a09-43e8-ae72-70e6e067c355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160791592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.3160791592
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.2304510229
Short name T32
Test name
Test status
Simulation time 171312478918 ps
CPU time 350.39 seconds
Started Jul 26 04:53:51 PM PDT 24
Finished Jul 26 04:59:42 PM PDT 24
Peak memory 271720 kb
Host smart-ef6d0a31-479c-4a71-8394-63a5d5e78c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304510229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.2304510229
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.1797740050
Short name T751
Test name
Test status
Simulation time 50739153576 ps
CPU time 49.35 seconds
Started Jul 26 04:54:06 PM PDT 24
Finished Jul 26 04:54:55 PM PDT 24
Peak memory 250068 kb
Host smart-a0097933-8e37-4460-b028-ad586637eea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797740050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.1797740050
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.1489079864
Short name T310
Test name
Test status
Simulation time 1596609401 ps
CPU time 5.42 seconds
Started Jul 26 04:54:01 PM PDT 24
Finished Jul 26 04:54:07 PM PDT 24
Peak memory 225336 kb
Host smart-ae652fd1-9acf-4f13-a153-55d68d0a3c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489079864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.1489079864
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.4034383325
Short name T278
Test name
Test status
Simulation time 5459392222 ps
CPU time 108.22 seconds
Started Jul 26 04:53:52 PM PDT 24
Finished Jul 26 04:55:40 PM PDT 24
Peak memory 267092 kb
Host smart-885bc948-6b65-46e9-a1cd-9e005c6d1278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034383325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmd
s.4034383325
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_intercept.2668651458
Short name T210
Test name
Test status
Simulation time 1220093545 ps
CPU time 3.93 seconds
Started Jul 26 04:53:44 PM PDT 24
Finished Jul 26 04:53:48 PM PDT 24
Peak memory 225204 kb
Host smart-c2311234-3f6f-4089-8759-2ffac645339d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668651458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.2668651458
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.707766276
Short name T229
Test name
Test status
Simulation time 9313727904 ps
CPU time 11.08 seconds
Started Jul 26 04:53:55 PM PDT 24
Finished Jul 26 04:54:06 PM PDT 24
Peak memory 241280 kb
Host smart-74af4bb9-f85f-4c0c-b1c7-477aa2497bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707766276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.707766276
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.657087530
Short name T857
Test name
Test status
Simulation time 104027795 ps
CPU time 2.17 seconds
Started Jul 26 04:53:42 PM PDT 24
Finished Jul 26 04:53:45 PM PDT 24
Peak memory 224564 kb
Host smart-9b1b1569-bf3e-45e6-b8db-569e1f5f54a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657087530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swap
.657087530
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.4195479962
Short name T456
Test name
Test status
Simulation time 2606839781 ps
CPU time 4.82 seconds
Started Jul 26 04:53:45 PM PDT 24
Finished Jul 26 04:53:50 PM PDT 24
Peak memory 225248 kb
Host smart-a7240222-b39b-4980-a819-2b9202912ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195479962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.4195479962
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.1076682991
Short name T320
Test name
Test status
Simulation time 720289814 ps
CPU time 8.57 seconds
Started Jul 26 04:54:08 PM PDT 24
Finished Jul 26 04:54:17 PM PDT 24
Peak memory 222696 kb
Host smart-6a81644b-1e9d-4844-ac2b-4c5a8ee87d89
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1076682991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.1076682991
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.1873513736
Short name T539
Test name
Test status
Simulation time 625680835 ps
CPU time 3.66 seconds
Started Jul 26 04:53:48 PM PDT 24
Finished Jul 26 04:53:52 PM PDT 24
Peak memory 216996 kb
Host smart-c26fb79f-1191-430b-9790-47b14104e7e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873513736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.1873513736
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.799188634
Short name T960
Test name
Test status
Simulation time 45779031 ps
CPU time 0.7 seconds
Started Jul 26 04:53:42 PM PDT 24
Finished Jul 26 04:53:43 PM PDT 24
Peak memory 206300 kb
Host smart-3ee6bd41-a247-4733-a503-9f9ecdf467a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799188634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.799188634
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.4287435534
Short name T853
Test name
Test status
Simulation time 68069793 ps
CPU time 1.09 seconds
Started Jul 26 04:53:46 PM PDT 24
Finished Jul 26 04:53:47 PM PDT 24
Peak memory 208624 kb
Host smart-cc89a904-e4b7-40d2-a232-59f661f53b26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287435534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.4287435534
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.3637774208
Short name T958
Test name
Test status
Simulation time 10043694 ps
CPU time 0.72 seconds
Started Jul 26 04:53:44 PM PDT 24
Finished Jul 26 04:53:45 PM PDT 24
Peak memory 206260 kb
Host smart-09ac0546-6bb1-41dc-9eff-cf19a048852b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637774208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.3637774208
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.2534390829
Short name T655
Test name
Test status
Simulation time 155740694 ps
CPU time 2.4 seconds
Started Jul 26 04:53:52 PM PDT 24
Finished Jul 26 04:53:54 PM PDT 24
Peak memory 233560 kb
Host smart-ae458139-b6b4-407d-8fc3-59303d147687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534390829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.2534390829
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.863631128
Short name T480
Test name
Test status
Simulation time 15355702 ps
CPU time 0.72 seconds
Started Jul 26 04:53:58 PM PDT 24
Finished Jul 26 04:53:59 PM PDT 24
Peak memory 205312 kb
Host smart-b71aeb95-183a-4b4a-8d98-02f53e81fb34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863631128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.863631128
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.1303790745
Short name T494
Test name
Test status
Simulation time 793056362 ps
CPU time 4.27 seconds
Started Jul 26 04:54:04 PM PDT 24
Finished Jul 26 04:54:09 PM PDT 24
Peak memory 225344 kb
Host smart-7f296561-a174-4056-9ef0-2bac1e3cc008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303790745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.1303790745
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.3004832675
Short name T896
Test name
Test status
Simulation time 26078660 ps
CPU time 0.73 seconds
Started Jul 26 04:53:55 PM PDT 24
Finished Jul 26 04:53:56 PM PDT 24
Peak memory 206152 kb
Host smart-c6cb8fcb-85bb-44fc-bebe-f13f8ae7bc99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004832675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.3004832675
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.1137713080
Short name T192
Test name
Test status
Simulation time 11463897502 ps
CPU time 102.44 seconds
Started Jul 26 04:53:50 PM PDT 24
Finished Jul 26 04:55:33 PM PDT 24
Peak memory 255516 kb
Host smart-40e38e0a-b27a-4064-a41f-49d762be0ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137713080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.1137713080
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.1302576098
Short name T25
Test name
Test status
Simulation time 31114885174 ps
CPU time 15.83 seconds
Started Jul 26 04:54:04 PM PDT 24
Finished Jul 26 04:54:20 PM PDT 24
Peak memory 218344 kb
Host smart-984b9ea7-d013-4ed8-aae5-9e790b4cb2a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302576098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.1302576098
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.34006855
Short name T303
Test name
Test status
Simulation time 94127428550 ps
CPU time 238.82 seconds
Started Jul 26 04:53:53 PM PDT 24
Finished Jul 26 04:57:52 PM PDT 24
Peak memory 250976 kb
Host smart-3b334d22-f931-47b6-9238-615b68175565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34006855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idle.34006855
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.1793066593
Short name T218
Test name
Test status
Simulation time 1398873351 ps
CPU time 20.11 seconds
Started Jul 26 04:53:52 PM PDT 24
Finished Jul 26 04:54:12 PM PDT 24
Peak memory 241968 kb
Host smart-cab07f6f-e2e2-4147-9507-9d6acd5b6582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793066593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.1793066593
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.2824537384
Short name T509
Test name
Test status
Simulation time 42538753660 ps
CPU time 81.72 seconds
Started Jul 26 04:53:56 PM PDT 24
Finished Jul 26 04:55:18 PM PDT 24
Peak memory 251332 kb
Host smart-b1fc9ea2-1100-42c8-9cc7-8585f9d1a0bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824537384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmd
s.2824537384
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/34.spi_device_intercept.2073500162
Short name T24
Test name
Test status
Simulation time 2592926183 ps
CPU time 10.16 seconds
Started Jul 26 04:53:58 PM PDT 24
Finished Jul 26 04:54:08 PM PDT 24
Peak memory 225300 kb
Host smart-87549c48-cf14-402c-8761-b0a075890f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073500162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.2073500162
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.2698310286
Short name T793
Test name
Test status
Simulation time 6359882118 ps
CPU time 42.33 seconds
Started Jul 26 04:54:05 PM PDT 24
Finished Jul 26 04:54:47 PM PDT 24
Peak memory 233524 kb
Host smart-8808c5c2-ed24-4aae-821e-1bde228d6198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698310286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.2698310286
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.700917734
Short name T893
Test name
Test status
Simulation time 3822955380 ps
CPU time 11.65 seconds
Started Jul 26 04:53:53 PM PDT 24
Finished Jul 26 04:54:05 PM PDT 24
Peak memory 233480 kb
Host smart-f4f537c0-1b34-4e21-ba72-e10aa003f0a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700917734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swap
.700917734
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.1646850269
Short name T779
Test name
Test status
Simulation time 4081542659 ps
CPU time 2.6 seconds
Started Jul 26 04:53:55 PM PDT 24
Finished Jul 26 04:53:58 PM PDT 24
Peak memory 225380 kb
Host smart-11fd3660-383c-47b4-bc89-120f511216bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646850269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.1646850269
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.1905121576
Short name T556
Test name
Test status
Simulation time 669580620 ps
CPU time 3.31 seconds
Started Jul 26 04:54:01 PM PDT 24
Finished Jul 26 04:54:05 PM PDT 24
Peak memory 220104 kb
Host smart-c3e0e41e-04ff-432b-8bc9-f5042cf2b1f4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1905121576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.1905121576
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.2872799961
Short name T152
Test name
Test status
Simulation time 54121168 ps
CPU time 1.04 seconds
Started Jul 26 04:53:59 PM PDT 24
Finished Jul 26 04:54:00 PM PDT 24
Peak memory 207444 kb
Host smart-2cc5b778-5bf1-4f31-b4bf-3a7f7a4a30ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872799961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.2872799961
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.419045549
Short name T127
Test name
Test status
Simulation time 332086766 ps
CPU time 3.69 seconds
Started Jul 26 04:54:01 PM PDT 24
Finished Jul 26 04:54:05 PM PDT 24
Peak memory 217084 kb
Host smart-52bd14b0-f0e2-4f50-99fb-783c9ee91c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419045549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.419045549
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.3109877592
Short name T615
Test name
Test status
Simulation time 27976414519 ps
CPU time 16.68 seconds
Started Jul 26 04:53:52 PM PDT 24
Finished Jul 26 04:54:09 PM PDT 24
Peak memory 217408 kb
Host smart-2fc76fda-2d59-4255-99e0-56c89b1a554d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109877592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.3109877592
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.4150066440
Short name T400
Test name
Test status
Simulation time 141743606 ps
CPU time 1.49 seconds
Started Jul 26 04:53:56 PM PDT 24
Finished Jul 26 04:53:58 PM PDT 24
Peak memory 208852 kb
Host smart-3c8fd25a-5254-44e2-8e51-d82c66928ef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150066440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.4150066440
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.3951632747
Short name T339
Test name
Test status
Simulation time 27498555 ps
CPU time 0.75 seconds
Started Jul 26 04:53:52 PM PDT 24
Finished Jul 26 04:53:53 PM PDT 24
Peak memory 206624 kb
Host smart-f362e6ee-1688-4b24-88bd-0c09633d739b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951632747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.3951632747
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.4098639830
Short name T512
Test name
Test status
Simulation time 9645416061 ps
CPU time 15.32 seconds
Started Jul 26 04:53:59 PM PDT 24
Finished Jul 26 04:54:15 PM PDT 24
Peak memory 225280 kb
Host smart-843515d7-1bcb-4f82-95cc-1bba0dfcf60f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098639830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.4098639830
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.1300267382
Short name T941
Test name
Test status
Simulation time 21286513 ps
CPU time 0.7 seconds
Started Jul 26 04:53:58 PM PDT 24
Finished Jul 26 04:53:59 PM PDT 24
Peak memory 205900 kb
Host smart-d5bbed67-ba49-42b7-b36d-326dd3d375d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300267382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
1300267382
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.1585960395
Short name T717
Test name
Test status
Simulation time 802275015 ps
CPU time 10.09 seconds
Started Jul 26 04:53:59 PM PDT 24
Finished Jul 26 04:54:09 PM PDT 24
Peak memory 233416 kb
Host smart-983a425c-e6f8-457f-ba7e-d27de2ef6059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585960395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.1585960395
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.3630279683
Short name T385
Test name
Test status
Simulation time 52849156 ps
CPU time 0.77 seconds
Started Jul 26 04:53:51 PM PDT 24
Finished Jul 26 04:53:52 PM PDT 24
Peak memory 207448 kb
Host smart-d4f017d1-8200-4924-98d6-5902605e962f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630279683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.3630279683
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.220021924
Short name T572
Test name
Test status
Simulation time 11129560131 ps
CPU time 79.03 seconds
Started Jul 26 04:53:59 PM PDT 24
Finished Jul 26 04:55:18 PM PDT 24
Peak memory 249936 kb
Host smart-cebd7e31-a038-4779-8643-cac8acacbe88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220021924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.220021924
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.3120386485
Short name T911
Test name
Test status
Simulation time 32130898394 ps
CPU time 235.63 seconds
Started Jul 26 04:54:01 PM PDT 24
Finished Jul 26 04:57:57 PM PDT 24
Peak memory 252292 kb
Host smart-84ad8eac-f22e-48b4-84ef-48edbcbbe455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120386485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.3120386485
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.820394984
Short name T219
Test name
Test status
Simulation time 34297291329 ps
CPU time 255.31 seconds
Started Jul 26 04:53:58 PM PDT 24
Finished Jul 26 04:58:14 PM PDT 24
Peak memory 257716 kb
Host smart-f688cd8f-83b0-4aac-bcc8-6625b282c5ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820394984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idle
.820394984
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.2266554211
Short name T365
Test name
Test status
Simulation time 133926128 ps
CPU time 3.44 seconds
Started Jul 26 04:53:55 PM PDT 24
Finished Jul 26 04:53:58 PM PDT 24
Peak memory 233696 kb
Host smart-199dbb14-f954-4045-992f-fb243e96a56a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266554211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.2266554211
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.1427176171
Short name T508
Test name
Test status
Simulation time 29448009753 ps
CPU time 75.25 seconds
Started Jul 26 04:53:57 PM PDT 24
Finished Jul 26 04:55:13 PM PDT 24
Peak memory 254280 kb
Host smart-ca2b0c45-51dd-4455-9650-65114de62218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427176171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmd
s.1427176171
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/35.spi_device_intercept.2419594504
Short name T748
Test name
Test status
Simulation time 163769016 ps
CPU time 3.48 seconds
Started Jul 26 04:53:57 PM PDT 24
Finished Jul 26 04:54:01 PM PDT 24
Peak memory 233480 kb
Host smart-e828b2b7-c56d-4d6d-85a5-1e5e2140f060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419594504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.2419594504
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.2231248556
Short name T769
Test name
Test status
Simulation time 31840122553 ps
CPU time 65.66 seconds
Started Jul 26 04:53:59 PM PDT 24
Finished Jul 26 04:55:05 PM PDT 24
Peak memory 249920 kb
Host smart-f2a232d4-bb40-4892-a90d-6cf064176c8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231248556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.2231248556
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.1505114948
Short name T249
Test name
Test status
Simulation time 2978302700 ps
CPU time 9.2 seconds
Started Jul 26 04:54:03 PM PDT 24
Finished Jul 26 04:54:12 PM PDT 24
Peak memory 233580 kb
Host smart-94d3e0cc-d977-4e0c-94ec-894e1fe2c8b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505114948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.1505114948
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.2635571563
Short name T891
Test name
Test status
Simulation time 87244283876 ps
CPU time 19.03 seconds
Started Jul 26 04:54:03 PM PDT 24
Finished Jul 26 04:54:23 PM PDT 24
Peak memory 233560 kb
Host smart-353d8754-a946-40fc-b36c-9ba73b94afe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635571563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.2635571563
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.3424502098
Short name T436
Test name
Test status
Simulation time 8387318990 ps
CPU time 8.61 seconds
Started Jul 26 04:53:57 PM PDT 24
Finished Jul 26 04:54:06 PM PDT 24
Peak memory 223712 kb
Host smart-d0306083-1841-428d-a340-bfb6f9f2f492
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3424502098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.3424502098
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.378008040
Short name T491
Test name
Test status
Simulation time 3325037521 ps
CPU time 33.07 seconds
Started Jul 26 04:53:51 PM PDT 24
Finished Jul 26 04:54:24 PM PDT 24
Peak memory 255016 kb
Host smart-24f0bebc-103e-4d87-8eb6-7e836226bf3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378008040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stres
s_all.378008040
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.1828246406
Short name T427
Test name
Test status
Simulation time 43193673 ps
CPU time 0.75 seconds
Started Jul 26 04:53:53 PM PDT 24
Finished Jul 26 04:53:54 PM PDT 24
Peak memory 206276 kb
Host smart-ef84d7db-d207-4f31-b2e6-6920354807ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828246406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.1828246406
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.1281575271
Short name T596
Test name
Test status
Simulation time 1761002851 ps
CPU time 4.85 seconds
Started Jul 26 04:53:53 PM PDT 24
Finished Jul 26 04:53:58 PM PDT 24
Peak memory 216984 kb
Host smart-f6dbc2fb-1c50-4124-8996-64831d537b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281575271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.1281575271
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.519653839
Short name T871
Test name
Test status
Simulation time 580100559 ps
CPU time 4.69 seconds
Started Jul 26 04:53:54 PM PDT 24
Finished Jul 26 04:53:59 PM PDT 24
Peak memory 217016 kb
Host smart-542d44b6-d815-4a9a-88ec-f99abe992ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519653839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.519653839
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.2914630236
Short name T396
Test name
Test status
Simulation time 427829313 ps
CPU time 0.91 seconds
Started Jul 26 04:53:55 PM PDT 24
Finished Jul 26 04:53:56 PM PDT 24
Peak memory 207636 kb
Host smart-116b932f-9691-4cf2-a6fb-138d3fbff8e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914630236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.2914630236
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.450526469
Short name T156
Test name
Test status
Simulation time 686013936 ps
CPU time 6.89 seconds
Started Jul 26 04:54:01 PM PDT 24
Finished Jul 26 04:54:08 PM PDT 24
Peak memory 233528 kb
Host smart-5539fca0-9272-417a-a96d-30ad50bb9e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450526469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.450526469
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.168172096
Short name T913
Test name
Test status
Simulation time 59819564 ps
CPU time 0.78 seconds
Started Jul 26 04:54:03 PM PDT 24
Finished Jul 26 04:54:04 PM PDT 24
Peak memory 205992 kb
Host smart-5e650fde-9597-4204-b0e1-f2fd340a71c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168172096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.168172096
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.1264932298
Short name T778
Test name
Test status
Simulation time 1197287438 ps
CPU time 9.11 seconds
Started Jul 26 04:54:01 PM PDT 24
Finished Jul 26 04:54:10 PM PDT 24
Peak memory 233608 kb
Host smart-e33de57f-2668-4adc-8492-f471c7144771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264932298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.1264932298
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.2245156260
Short name T394
Test name
Test status
Simulation time 21270257 ps
CPU time 0.76 seconds
Started Jul 26 04:53:54 PM PDT 24
Finished Jul 26 04:53:55 PM PDT 24
Peak memory 206036 kb
Host smart-640e247e-2080-4fcc-9111-5893a06504f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245156260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.2245156260
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.1652115852
Short name T667
Test name
Test status
Simulation time 5208507089 ps
CPU time 12.09 seconds
Started Jul 26 04:54:00 PM PDT 24
Finished Jul 26 04:54:12 PM PDT 24
Peak memory 241708 kb
Host smart-8436118f-bf51-4ab8-bf92-7e430b1c2de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652115852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.1652115852
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.1225673245
Short name T679
Test name
Test status
Simulation time 49047589929 ps
CPU time 128.44 seconds
Started Jul 26 04:53:59 PM PDT 24
Finished Jul 26 04:56:07 PM PDT 24
Peak memory 250332 kb
Host smart-8cc240e8-8d6b-4349-9fe5-1572e0a5da54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225673245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.1225673245
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.1925550698
Short name T969
Test name
Test status
Simulation time 4399737798 ps
CPU time 93.68 seconds
Started Jul 26 04:54:00 PM PDT 24
Finished Jul 26 04:55:34 PM PDT 24
Peak memory 257652 kb
Host smart-6c6331a3-aaed-479d-ac49-51e45a7cd6a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925550698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.1925550698
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.3977040295
Short name T672
Test name
Test status
Simulation time 6387782035 ps
CPU time 11.76 seconds
Started Jul 26 04:54:09 PM PDT 24
Finished Jul 26 04:54:22 PM PDT 24
Peak memory 233576 kb
Host smart-8077cbb4-5449-45b1-9fd2-4ccf399cfe51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977040295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.3977040295
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.1438424030
Short name T950
Test name
Test status
Simulation time 21845614 ps
CPU time 0.73 seconds
Started Jul 26 04:53:59 PM PDT 24
Finished Jul 26 04:54:00 PM PDT 24
Peak memory 216580 kb
Host smart-0e8d2504-3f91-4bcc-a88b-b481d7738bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438424030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmd
s.1438424030
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_intercept.2450788137
Short name T1
Test name
Test status
Simulation time 875734058 ps
CPU time 3.11 seconds
Started Jul 26 04:53:58 PM PDT 24
Finished Jul 26 04:54:01 PM PDT 24
Peak memory 233576 kb
Host smart-ce969c17-94be-46ca-89eb-cd9fa12cdf65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450788137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.2450788137
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.3096937684
Short name T406
Test name
Test status
Simulation time 6169404564 ps
CPU time 63.45 seconds
Started Jul 26 04:53:59 PM PDT 24
Finished Jul 26 04:55:02 PM PDT 24
Peak memory 233528 kb
Host smart-4a142f54-da62-4ef1-b717-46c0c2e18304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096937684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.3096937684
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.4190495604
Short name T993
Test name
Test status
Simulation time 37846559491 ps
CPU time 27 seconds
Started Jul 26 04:54:05 PM PDT 24
Finished Jul 26 04:54:32 PM PDT 24
Peak memory 241788 kb
Host smart-de7451e6-cba6-45b0-bd73-dcba0f52057c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190495604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.4190495604
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.3434616013
Short name T902
Test name
Test status
Simulation time 2039188415 ps
CPU time 2.25 seconds
Started Jul 26 04:54:11 PM PDT 24
Finished Jul 26 04:54:13 PM PDT 24
Peak memory 224864 kb
Host smart-865147a5-1c28-48bb-bd1d-3b2ed7278c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434616013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.3434616013
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.2780137968
Short name T325
Test name
Test status
Simulation time 14281397953 ps
CPU time 17.02 seconds
Started Jul 26 04:54:02 PM PDT 24
Finished Jul 26 04:54:19 PM PDT 24
Peak memory 223776 kb
Host smart-55aac565-d78c-4521-b852-9497123f2ef3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2780137968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.2780137968
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.2718689932
Short name T607
Test name
Test status
Simulation time 12988100250 ps
CPU time 130.86 seconds
Started Jul 26 04:54:03 PM PDT 24
Finished Jul 26 04:56:14 PM PDT 24
Peak memory 257944 kb
Host smart-d3bc48f7-ca1c-4b95-8b94-cff2e50cceca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718689932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.2718689932
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.1740339241
Short name T550
Test name
Test status
Simulation time 4636505130 ps
CPU time 22.05 seconds
Started Jul 26 04:54:01 PM PDT 24
Finished Jul 26 04:54:24 PM PDT 24
Peak memory 217152 kb
Host smart-90315342-1d30-4ba0-be69-c58a78862cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740339241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.1740339241
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.3128640518
Short name T474
Test name
Test status
Simulation time 1704482963 ps
CPU time 5.89 seconds
Started Jul 26 04:53:55 PM PDT 24
Finished Jul 26 04:54:01 PM PDT 24
Peak memory 216984 kb
Host smart-58820fa2-4ae0-4968-af33-449d6b7dc345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128640518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.3128640518
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.3519643401
Short name T841
Test name
Test status
Simulation time 325348871 ps
CPU time 1.62 seconds
Started Jul 26 04:54:05 PM PDT 24
Finished Jul 26 04:54:07 PM PDT 24
Peak memory 217100 kb
Host smart-52462af0-6dc5-4fcd-9a36-d02e1e0ce968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519643401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.3519643401
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.4091630042
Short name T906
Test name
Test status
Simulation time 12416109 ps
CPU time 0.67 seconds
Started Jul 26 04:53:52 PM PDT 24
Finished Jul 26 04:53:53 PM PDT 24
Peak memory 206416 kb
Host smart-62898bd4-2278-4f49-b9f6-1e7bb3292e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091630042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.4091630042
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.1253326048
Short name T955
Test name
Test status
Simulation time 1218621552 ps
CPU time 7.49 seconds
Started Jul 26 04:54:10 PM PDT 24
Finished Jul 26 04:54:18 PM PDT 24
Peak memory 249800 kb
Host smart-d8abc635-ba96-48b9-9ada-55885b3c011c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253326048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.1253326048
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.2650532150
Short name T758
Test name
Test status
Simulation time 12657999 ps
CPU time 0.71 seconds
Started Jul 26 04:53:58 PM PDT 24
Finished Jul 26 04:53:59 PM PDT 24
Peak memory 205348 kb
Host smart-10a0aa14-f0fe-43b6-b0ed-d448258ec818
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650532150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
2650532150
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.3883922359
Short name T483
Test name
Test status
Simulation time 94308396 ps
CPU time 3.38 seconds
Started Jul 26 04:54:10 PM PDT 24
Finished Jul 26 04:54:13 PM PDT 24
Peak memory 225252 kb
Host smart-c94c5c14-45d9-4e99-92a2-6db7b86aa5ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883922359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.3883922359
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.2887108991
Short name T948
Test name
Test status
Simulation time 29868139 ps
CPU time 0.78 seconds
Started Jul 26 04:54:01 PM PDT 24
Finished Jul 26 04:54:02 PM PDT 24
Peak memory 207556 kb
Host smart-b52e508a-d5fb-4fbe-a8c9-90ccdeb8aebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887108991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.2887108991
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.276777230
Short name T544
Test name
Test status
Simulation time 13617759 ps
CPU time 0.73 seconds
Started Jul 26 04:54:06 PM PDT 24
Finished Jul 26 04:54:07 PM PDT 24
Peak memory 216464 kb
Host smart-1259b24b-84a8-4c91-8f01-7434369c9349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276777230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.276777230
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.720474063
Short name T180
Test name
Test status
Simulation time 118970274093 ps
CPU time 437.41 seconds
Started Jul 26 04:54:07 PM PDT 24
Finished Jul 26 05:01:24 PM PDT 24
Peak memory 266056 kb
Host smart-9f5b1651-a21d-41be-850c-c497b45e2e20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720474063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.720474063
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.3216141331
Short name T133
Test name
Test status
Simulation time 28897909172 ps
CPU time 114.78 seconds
Started Jul 26 04:53:59 PM PDT 24
Finished Jul 26 04:55:54 PM PDT 24
Peak memory 258116 kb
Host smart-a4959532-e821-4804-9e21-f87e507dd8f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216141331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.3216141331
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.3784842414
Short name T472
Test name
Test status
Simulation time 234247295 ps
CPU time 5.62 seconds
Started Jul 26 04:54:06 PM PDT 24
Finished Jul 26 04:54:12 PM PDT 24
Peak memory 234664 kb
Host smart-ad3c6c5d-f594-4a36-a89b-b6d0ae509ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784842414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.3784842414
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.1153397259
Short name T186
Test name
Test status
Simulation time 36300090501 ps
CPU time 64.75 seconds
Started Jul 26 04:53:59 PM PDT 24
Finished Jul 26 04:55:04 PM PDT 24
Peak memory 251176 kb
Host smart-8661b879-c76a-433e-a7f8-9695b6748046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153397259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmd
s.1153397259
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/37.spi_device_intercept.4194681508
Short name T643
Test name
Test status
Simulation time 402458041 ps
CPU time 3.73 seconds
Started Jul 26 04:54:03 PM PDT 24
Finished Jul 26 04:54:07 PM PDT 24
Peak memory 225292 kb
Host smart-d9edf077-dd8f-4a42-a74b-eb0805cbf79c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194681508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.4194681508
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.3244184423
Short name T877
Test name
Test status
Simulation time 362043671 ps
CPU time 2.74 seconds
Started Jul 26 04:54:07 PM PDT 24
Finished Jul 26 04:54:10 PM PDT 24
Peak memory 233524 kb
Host smart-fec6c368-ca16-4c57-b93a-1dae9b21871d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244184423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.3244184423
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.830337255
Short name T255
Test name
Test status
Simulation time 3478989705 ps
CPU time 11.08 seconds
Started Jul 26 04:54:06 PM PDT 24
Finished Jul 26 04:54:17 PM PDT 24
Peak memory 233472 kb
Host smart-aaa1ed60-99ea-4aed-be7d-a092b04f63f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830337255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swap
.830337255
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.1302807025
Short name T389
Test name
Test status
Simulation time 2278182742 ps
CPU time 5.25 seconds
Started Jul 26 04:54:10 PM PDT 24
Finished Jul 26 04:54:16 PM PDT 24
Peak memory 233568 kb
Host smart-89840a7a-5100-4521-a714-8d38f3ccbf7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302807025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.1302807025
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.4198600970
Short name T836
Test name
Test status
Simulation time 529914528 ps
CPU time 7.2 seconds
Started Jul 26 04:54:04 PM PDT 24
Finished Jul 26 04:54:12 PM PDT 24
Peak memory 222572 kb
Host smart-9472784c-e5bd-4d3d-862f-70c38a5b86ce
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4198600970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.4198600970
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.1609587945
Short name T280
Test name
Test status
Simulation time 43805714735 ps
CPU time 450.49 seconds
Started Jul 26 04:54:00 PM PDT 24
Finished Jul 26 05:01:31 PM PDT 24
Peak memory 271736 kb
Host smart-499a2760-acb7-4269-a38d-413e40b992c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609587945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.1609587945
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.2030584389
Short name T500
Test name
Test status
Simulation time 1429075579 ps
CPU time 12.08 seconds
Started Jul 26 04:54:03 PM PDT 24
Finished Jul 26 04:54:15 PM PDT 24
Peak memory 217100 kb
Host smart-14aa5290-c83a-41a2-bd7f-c97f2c63d7ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030584389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.2030584389
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.1328379269
Short name T388
Test name
Test status
Simulation time 9862242976 ps
CPU time 12.4 seconds
Started Jul 26 04:54:02 PM PDT 24
Finished Jul 26 04:54:14 PM PDT 24
Peak memory 217196 kb
Host smart-20a1a67c-114e-4c54-a5f1-cb198dc0b6be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328379269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.1328379269
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.3876253122
Short name T884
Test name
Test status
Simulation time 231017667 ps
CPU time 3.01 seconds
Started Jul 26 04:54:05 PM PDT 24
Finished Jul 26 04:54:08 PM PDT 24
Peak memory 217048 kb
Host smart-2d7dd2fe-a526-4041-9c86-dc2803690388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876253122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.3876253122
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.1444547714
Short name T82
Test name
Test status
Simulation time 408333565 ps
CPU time 0.85 seconds
Started Jul 26 04:54:11 PM PDT 24
Finished Jul 26 04:54:11 PM PDT 24
Peak memory 206512 kb
Host smart-13d25cb0-d437-4db8-ab51-49e85f1fe2cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444547714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.1444547714
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.330747844
Short name T235
Test name
Test status
Simulation time 27434875813 ps
CPU time 33.18 seconds
Started Jul 26 04:54:00 PM PDT 24
Finished Jul 26 04:54:33 PM PDT 24
Peak memory 241812 kb
Host smart-cad8dd92-b231-43a2-abf6-46995e1de1ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330747844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.330747844
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.783982907
Short name T638
Test name
Test status
Simulation time 68094709 ps
CPU time 0.74 seconds
Started Jul 26 04:54:00 PM PDT 24
Finished Jul 26 04:54:00 PM PDT 24
Peak memory 205980 kb
Host smart-42c34b3b-0849-4360-ae7a-19f007f5d399
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783982907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.783982907
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.4208718687
Short name T226
Test name
Test status
Simulation time 1787086062 ps
CPU time 17.23 seconds
Started Jul 26 04:54:05 PM PDT 24
Finished Jul 26 04:54:22 PM PDT 24
Peak memory 233384 kb
Host smart-7802b22e-d676-4c29-b1d8-8caedab12137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208718687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.4208718687
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.2226070192
Short name T610
Test name
Test status
Simulation time 22754917 ps
CPU time 0.83 seconds
Started Jul 26 04:54:02 PM PDT 24
Finished Jul 26 04:54:03 PM PDT 24
Peak memory 207104 kb
Host smart-23c13585-3a54-4fd7-833b-b9083c369c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226070192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.2226070192
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.1730582804
Short name T801
Test name
Test status
Simulation time 18206875330 ps
CPU time 26.07 seconds
Started Jul 26 04:53:59 PM PDT 24
Finished Jul 26 04:54:25 PM PDT 24
Peak memory 225384 kb
Host smart-315acc85-3be9-48fe-a454-15008d77059f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730582804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.1730582804
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.2127096791
Short name T38
Test name
Test status
Simulation time 5656626558 ps
CPU time 75.92 seconds
Started Jul 26 04:54:03 PM PDT 24
Finished Jul 26 04:55:20 PM PDT 24
Peak memory 256092 kb
Host smart-243f7675-ac97-4f39-a2ac-a7b98144408e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127096791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.2127096791
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.2444851434
Short name T484
Test name
Test status
Simulation time 18951096484 ps
CPU time 95.68 seconds
Started Jul 26 04:54:07 PM PDT 24
Finished Jul 26 04:55:43 PM PDT 24
Peak memory 249960 kb
Host smart-ae1f6e1a-1c85-4cdd-a439-f7ce0527503c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444851434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.2444851434
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.2548046759
Short name T920
Test name
Test status
Simulation time 1792735726 ps
CPU time 29.54 seconds
Started Jul 26 04:54:01 PM PDT 24
Finished Jul 26 04:54:30 PM PDT 24
Peak memory 235740 kb
Host smart-68823e7f-a895-49f8-a0a7-1b64b83aeaaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548046759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.2548046759
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.2890624851
Short name T851
Test name
Test status
Simulation time 30049468716 ps
CPU time 104.28 seconds
Started Jul 26 04:54:00 PM PDT 24
Finished Jul 26 04:55:44 PM PDT 24
Peak memory 250052 kb
Host smart-673bf2e6-75b4-4377-a183-02d4408b6a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890624851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmd
s.2890624851
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/38.spi_device_intercept.1130842671
Short name T726
Test name
Test status
Simulation time 405904865 ps
CPU time 4.24 seconds
Started Jul 26 04:53:59 PM PDT 24
Finished Jul 26 04:54:03 PM PDT 24
Peak memory 225360 kb
Host smart-4f54318c-7304-4506-8435-c23b360fcfb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130842671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.1130842671
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.3455567372
Short name T674
Test name
Test status
Simulation time 19042505333 ps
CPU time 38.11 seconds
Started Jul 26 04:54:01 PM PDT 24
Finished Jul 26 04:54:40 PM PDT 24
Peak memory 241780 kb
Host smart-69208dfa-203d-4b5d-8535-77b0be5c48b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455567372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.3455567372
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.3262504652
Short name T42
Test name
Test status
Simulation time 605156527 ps
CPU time 4.14 seconds
Started Jul 26 04:54:02 PM PDT 24
Finished Jul 26 04:54:07 PM PDT 24
Peak memory 225208 kb
Host smart-b843f360-2223-474c-b7d2-dc5a5eaba097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262504652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.3262504652
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.2376040511
Short name T711
Test name
Test status
Simulation time 4232954291 ps
CPU time 6.37 seconds
Started Jul 26 04:54:09 PM PDT 24
Finished Jul 26 04:54:15 PM PDT 24
Peak memory 241776 kb
Host smart-37abef3f-9075-41ce-8d26-9096c3fa0ba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376040511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.2376040511
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.1720606461
Short name T699
Test name
Test status
Simulation time 504595173 ps
CPU time 5.33 seconds
Started Jul 26 04:54:02 PM PDT 24
Finished Jul 26 04:54:08 PM PDT 24
Peak memory 223804 kb
Host smart-f3afd2e2-b606-443b-a491-dbca3229d456
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1720606461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.1720606461
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.2743383881
Short name T277
Test name
Test status
Simulation time 71242570691 ps
CPU time 642.57 seconds
Started Jul 26 04:54:04 PM PDT 24
Finished Jul 26 05:04:46 PM PDT 24
Peak memory 257268 kb
Host smart-9e878563-0d6e-4142-8c00-af7ac4c3c3b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743383881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.2743383881
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.1766204819
Short name T386
Test name
Test status
Simulation time 15998788799 ps
CPU time 30.04 seconds
Started Jul 26 04:53:59 PM PDT 24
Finished Jul 26 04:54:29 PM PDT 24
Peak memory 221776 kb
Host smart-588ad902-251b-48a5-8766-8d254e22b705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766204819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.1766204819
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.3752205136
Short name T879
Test name
Test status
Simulation time 15530548 ps
CPU time 0.74 seconds
Started Jul 26 04:54:00 PM PDT 24
Finished Jul 26 04:54:01 PM PDT 24
Peak memory 206264 kb
Host smart-6f2c7b2a-4e9c-402c-a8ab-dbbe853e3e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752205136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.3752205136
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.1982292216
Short name T685
Test name
Test status
Simulation time 15449329 ps
CPU time 0.71 seconds
Started Jul 26 04:54:01 PM PDT 24
Finished Jul 26 04:54:02 PM PDT 24
Peak memory 206176 kb
Host smart-9d54decb-bfee-477b-ba36-d70b0ace5df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982292216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.1982292216
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.954077760
Short name T353
Test name
Test status
Simulation time 123583163 ps
CPU time 0.98 seconds
Started Jul 26 04:53:59 PM PDT 24
Finished Jul 26 04:54:00 PM PDT 24
Peak memory 207628 kb
Host smart-b5a73d0d-1603-45d3-a22e-41839772d855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954077760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.954077760
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.822219059
Short name T264
Test name
Test status
Simulation time 8311020068 ps
CPU time 14.11 seconds
Started Jul 26 04:54:01 PM PDT 24
Finished Jul 26 04:54:15 PM PDT 24
Peak memory 233472 kb
Host smart-a3355df0-4b9b-4359-8c7a-ec4082d1624f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822219059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.822219059
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.461049833
Short name T477
Test name
Test status
Simulation time 232905660 ps
CPU time 0.71 seconds
Started Jul 26 04:54:09 PM PDT 24
Finished Jul 26 04:54:10 PM PDT 24
Peak memory 205948 kb
Host smart-f4f0349f-4d7d-4209-bb00-69bc7bc8a1b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461049833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.461049833
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.3191361133
Short name T881
Test name
Test status
Simulation time 1424576161 ps
CPU time 3.43 seconds
Started Jul 26 04:54:13 PM PDT 24
Finished Jul 26 04:54:17 PM PDT 24
Peak memory 225264 kb
Host smart-a74f7e54-90e4-4f9c-b0b1-0928e8fc19fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191361133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.3191361133
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.1464315672
Short name T953
Test name
Test status
Simulation time 16447578 ps
CPU time 0.77 seconds
Started Jul 26 04:54:02 PM PDT 24
Finished Jul 26 04:54:03 PM PDT 24
Peak memory 206128 kb
Host smart-4c69187d-3470-4893-840d-57857e2dc60c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464315672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.1464315672
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.2698279346
Short name T907
Test name
Test status
Simulation time 114833981786 ps
CPU time 210.25 seconds
Started Jul 26 04:54:14 PM PDT 24
Finished Jul 26 04:57:44 PM PDT 24
Peak memory 254856 kb
Host smart-33a90e5e-4841-4637-bb6c-03cfd20684e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698279346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.2698279346
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.3503409394
Short name T126
Test name
Test status
Simulation time 7299165444 ps
CPU time 46.12 seconds
Started Jul 26 04:54:15 PM PDT 24
Finished Jul 26 04:55:01 PM PDT 24
Peak memory 225364 kb
Host smart-7267c749-c3f6-4de7-80c5-dc76afa86dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503409394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.3503409394
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.97668388
Short name T181
Test name
Test status
Simulation time 32345266614 ps
CPU time 88.82 seconds
Started Jul 26 04:54:09 PM PDT 24
Finished Jul 26 04:55:39 PM PDT 24
Peak memory 249940 kb
Host smart-7c1e16bc-0b19-4ab8-a570-6fef5cf34ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97668388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idle.97668388
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.3733698540
Short name T399
Test name
Test status
Simulation time 434856578 ps
CPU time 3.26 seconds
Started Jul 26 04:54:09 PM PDT 24
Finished Jul 26 04:54:13 PM PDT 24
Peak memory 237748 kb
Host smart-98ad1960-c8a1-43c3-af98-e1d26c5a8876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733698540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.3733698540
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.3903786984
Short name T441
Test name
Test status
Simulation time 3408221384 ps
CPU time 42.12 seconds
Started Jul 26 04:54:10 PM PDT 24
Finished Jul 26 04:54:52 PM PDT 24
Peak memory 253068 kb
Host smart-bba0f121-f3a3-4589-b576-6b2f947d2dad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903786984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmd
s.3903786984
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/39.spi_device_intercept.4244949775
Short name T485
Test name
Test status
Simulation time 31062227 ps
CPU time 2.33 seconds
Started Jul 26 04:54:10 PM PDT 24
Finished Jul 26 04:54:13 PM PDT 24
Peak memory 233164 kb
Host smart-22409968-140c-4321-943a-d657a426ee89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244949775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.4244949775
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.823430891
Short name T3
Test name
Test status
Simulation time 38234333693 ps
CPU time 49.65 seconds
Started Jul 26 04:54:06 PM PDT 24
Finished Jul 26 04:54:56 PM PDT 24
Peak memory 225352 kb
Host smart-ea7bb556-42a0-4c66-a983-3740df922510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823430891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.823430891
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.1050334515
Short name T588
Test name
Test status
Simulation time 33723780578 ps
CPU time 11.18 seconds
Started Jul 26 04:54:14 PM PDT 24
Finished Jul 26 04:54:26 PM PDT 24
Peak memory 233560 kb
Host smart-0991a210-cb43-4615-818d-38025c88853a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050334515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.1050334515
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.1130483319
Short name T743
Test name
Test status
Simulation time 1619540335 ps
CPU time 4.18 seconds
Started Jul 26 04:54:08 PM PDT 24
Finished Jul 26 04:54:13 PM PDT 24
Peak memory 225292 kb
Host smart-158aed82-07de-4ac1-a151-756051d2ca7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130483319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.1130483319
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.1558872869
Short name T563
Test name
Test status
Simulation time 361640433 ps
CPU time 5.76 seconds
Started Jul 26 04:54:14 PM PDT 24
Finished Jul 26 04:54:20 PM PDT 24
Peak memory 222620 kb
Host smart-cebc0e02-023b-4044-860e-6ef88a0b42a5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1558872869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.1558872869
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.3871820392
Short name T533
Test name
Test status
Simulation time 64839229 ps
CPU time 0.9 seconds
Started Jul 26 04:54:07 PM PDT 24
Finished Jul 26 04:54:08 PM PDT 24
Peak memory 208016 kb
Host smart-2841bacb-b1bc-499d-8b72-1d7a4dd57b06
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871820392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.3871820392
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.2914566697
Short name T963
Test name
Test status
Simulation time 49877597029 ps
CPU time 44.83 seconds
Started Jul 26 04:54:15 PM PDT 24
Finished Jul 26 04:55:00 PM PDT 24
Peak memory 217080 kb
Host smart-9d217075-2ed2-4e68-83d6-9c6b0240be48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914566697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.2914566697
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.2092321872
Short name T302
Test name
Test status
Simulation time 3443254072 ps
CPU time 14.27 seconds
Started Jul 26 04:54:11 PM PDT 24
Finished Jul 26 04:54:26 PM PDT 24
Peak memory 217244 kb
Host smart-2b141910-8fc4-4607-9a04-792598f7385c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092321872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.2092321872
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.2975980077
Short name T641
Test name
Test status
Simulation time 51141079 ps
CPU time 1.23 seconds
Started Jul 26 04:54:15 PM PDT 24
Finished Jul 26 04:54:16 PM PDT 24
Peak memory 217028 kb
Host smart-23979a8d-c0e9-426f-afae-a72e8234b918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975980077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.2975980077
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.3902588260
Short name T639
Test name
Test status
Simulation time 79380189 ps
CPU time 0.77 seconds
Started Jul 26 04:54:09 PM PDT 24
Finished Jul 26 04:54:11 PM PDT 24
Peak memory 206636 kb
Host smart-3afce588-3666-4373-bb01-2f03df21ca23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902588260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.3902588260
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.3729834095
Short name T682
Test name
Test status
Simulation time 4141604011 ps
CPU time 7.76 seconds
Started Jul 26 04:54:11 PM PDT 24
Finished Jul 26 04:54:19 PM PDT 24
Peak memory 249416 kb
Host smart-b9daff96-b5a9-40df-b0ae-bc1e35dbd8ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729834095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.3729834095
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.981938226
Short name T57
Test name
Test status
Simulation time 71354647 ps
CPU time 0.69 seconds
Started Jul 26 04:53:55 PM PDT 24
Finished Jul 26 04:53:56 PM PDT 24
Peak memory 206288 kb
Host smart-871f478b-e604-4490-bb7a-a95d858fc825
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981938226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.981938226
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.1903111198
Short name T909
Test name
Test status
Simulation time 90272696 ps
CPU time 2.24 seconds
Started Jul 26 04:52:11 PM PDT 24
Finished Jul 26 04:52:14 PM PDT 24
Peak memory 224792 kb
Host smart-dfad9222-b7cc-4035-a44f-85fe46b17267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903111198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.1903111198
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.814704105
Short name T497
Test name
Test status
Simulation time 61822280 ps
CPU time 0.83 seconds
Started Jul 26 04:52:15 PM PDT 24
Finished Jul 26 04:52:16 PM PDT 24
Peak memory 207068 kb
Host smart-ba8ec0f0-1414-491c-a321-1096d8221a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814704105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.814704105
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.272606645
Short name T874
Test name
Test status
Simulation time 763651572 ps
CPU time 9.8 seconds
Started Jul 26 04:52:16 PM PDT 24
Finished Jul 26 04:52:26 PM PDT 24
Peak memory 249968 kb
Host smart-b4b783b8-892d-470c-bea2-e12909453d26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272606645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.272606645
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.1418768411
Short name T292
Test name
Test status
Simulation time 93256547984 ps
CPU time 237.85 seconds
Started Jul 26 04:52:14 PM PDT 24
Finished Jul 26 04:56:12 PM PDT 24
Peak memory 250068 kb
Host smart-879ffe90-4578-4f8f-ae12-baa19ff51be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418768411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.1418768411
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.4036739682
Short name T880
Test name
Test status
Simulation time 176829889769 ps
CPU time 439.77 seconds
Started Jul 26 04:52:16 PM PDT 24
Finished Jul 26 04:59:36 PM PDT 24
Peak memory 258180 kb
Host smart-01c25aee-bcf3-4196-b520-5960e555d157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036739682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.4036739682
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.3912631937
Short name T335
Test name
Test status
Simulation time 1386036634 ps
CPU time 9.21 seconds
Started Jul 26 04:52:14 PM PDT 24
Finished Jul 26 04:52:23 PM PDT 24
Peak memory 225380 kb
Host smart-f87d10ce-f6f5-4d68-a08a-c17934ad1206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912631937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.3912631937
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_intercept.2450719872
Short name T486
Test name
Test status
Simulation time 528505523 ps
CPU time 5.03 seconds
Started Jul 26 04:52:14 PM PDT 24
Finished Jul 26 04:52:20 PM PDT 24
Peak memory 220556 kb
Host smart-4aee6556-f767-477c-ad4c-9b22669ea2de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450719872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.2450719872
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.600017741
Short name T532
Test name
Test status
Simulation time 474446840 ps
CPU time 7.23 seconds
Started Jul 26 04:52:15 PM PDT 24
Finished Jul 26 04:52:23 PM PDT 24
Peak memory 237940 kb
Host smart-1b3a0b64-8cf8-45d9-94ad-22179e6b8eef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600017741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.600017741
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.4088810622
Short name T336
Test name
Test status
Simulation time 118141642 ps
CPU time 1.08 seconds
Started Jul 26 04:52:14 PM PDT 24
Finished Jul 26 04:52:16 PM PDT 24
Peak memory 217304 kb
Host smart-a9517278-d524-447a-909c-0c7d4159fdcd
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088810622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.spi_device_mem_parity.4088810622
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.2083500067
Short name T847
Test name
Test status
Simulation time 487067191 ps
CPU time 4.45 seconds
Started Jul 26 04:52:15 PM PDT 24
Finished Jul 26 04:52:20 PM PDT 24
Peak memory 225308 kb
Host smart-e6f98fa1-8ec9-4538-940b-fcabfcea70b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083500067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.2083500067
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.1000673841
Short name T414
Test name
Test status
Simulation time 99079699 ps
CPU time 2.14 seconds
Started Jul 26 04:52:15 PM PDT 24
Finished Jul 26 04:52:17 PM PDT 24
Peak memory 224624 kb
Host smart-5a337bcb-14a1-4627-b4bb-499c32b0c3d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000673841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.1000673841
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.3380394492
Short name T675
Test name
Test status
Simulation time 648662385 ps
CPU time 8.79 seconds
Started Jul 26 04:52:14 PM PDT 24
Finished Jul 26 04:52:23 PM PDT 24
Peak memory 220620 kb
Host smart-42b33c1d-32a3-4882-9509-fb74edf33c4d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3380394492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.3380394492
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.1044761875
Short name T64
Test name
Test status
Simulation time 59250394 ps
CPU time 1.12 seconds
Started Jul 26 04:52:15 PM PDT 24
Finished Jul 26 04:52:16 PM PDT 24
Peak memory 236176 kb
Host smart-a7917251-9127-443d-b1aa-61f73bfa47b0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044761875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.1044761875
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.3847378796
Short name T19
Test name
Test status
Simulation time 129027422 ps
CPU time 0.9 seconds
Started Jul 26 04:52:15 PM PDT 24
Finished Jul 26 04:52:16 PM PDT 24
Peak memory 206172 kb
Host smart-88f16d84-fc63-4d41-805a-6dab675d3ec5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847378796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.3847378796
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.3186488547
Short name T465
Test name
Test status
Simulation time 2254686261 ps
CPU time 15.67 seconds
Started Jul 26 04:52:15 PM PDT 24
Finished Jul 26 04:52:31 PM PDT 24
Peak memory 220648 kb
Host smart-3ce29a6a-0934-4e39-97e2-d1f58fe99119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186488547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.3186488547
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.793282744
Short name T838
Test name
Test status
Simulation time 2237094803 ps
CPU time 4.87 seconds
Started Jul 26 04:52:15 PM PDT 24
Finished Jul 26 04:52:20 PM PDT 24
Peak memory 216972 kb
Host smart-0061e864-0c1c-4aa5-83bf-789455c47a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793282744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.793282744
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.4233443317
Short name T50
Test name
Test status
Simulation time 800005258 ps
CPU time 2.96 seconds
Started Jul 26 04:52:11 PM PDT 24
Finished Jul 26 04:52:14 PM PDT 24
Peak memory 217088 kb
Host smart-4d2e2a2a-cf4f-4795-be9c-55af708584d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233443317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.4233443317
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.56831447
Short name T919
Test name
Test status
Simulation time 80178753 ps
CPU time 0.76 seconds
Started Jul 26 04:52:13 PM PDT 24
Finished Jul 26 04:52:14 PM PDT 24
Peak memory 206692 kb
Host smart-5bb8528a-37e2-46a5-b54f-896901f5a3cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56831447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.56831447
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.23919570
Short name T373
Test name
Test status
Simulation time 506546726 ps
CPU time 2.2 seconds
Started Jul 26 04:52:13 PM PDT 24
Finished Jul 26 04:52:15 PM PDT 24
Peak memory 224144 kb
Host smart-3261df32-a783-441f-8797-f476221bdec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23919570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.23919570
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.4012000315
Short name T897
Test name
Test status
Simulation time 130754614 ps
CPU time 0.71 seconds
Started Jul 26 04:54:09 PM PDT 24
Finished Jul 26 04:54:10 PM PDT 24
Peak memory 205288 kb
Host smart-c8c6f495-4bce-459f-b3c1-abdced252edb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012000315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
4012000315
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.1813247224
Short name T1013
Test name
Test status
Simulation time 61080360 ps
CPU time 2.07 seconds
Started Jul 26 04:54:20 PM PDT 24
Finished Jul 26 04:54:22 PM PDT 24
Peak memory 225256 kb
Host smart-adf8d1c0-db99-43c1-aa0a-8bad2daf693d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813247224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.1813247224
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.3322965750
Short name T392
Test name
Test status
Simulation time 39297131 ps
CPU time 0.76 seconds
Started Jul 26 04:54:11 PM PDT 24
Finished Jul 26 04:54:12 PM PDT 24
Peak memory 207204 kb
Host smart-1ae0532b-bff0-424c-be49-d6a937a9e49b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322965750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.3322965750
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.398026967
Short name T1007
Test name
Test status
Simulation time 5131465730 ps
CPU time 29.01 seconds
Started Jul 26 04:54:12 PM PDT 24
Finished Jul 26 04:54:42 PM PDT 24
Peak memory 250992 kb
Host smart-598e04ba-46b5-4bfa-ac75-d3254307e65b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398026967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.398026967
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.2208824891
Short name T132
Test name
Test status
Simulation time 4441002328 ps
CPU time 96.48 seconds
Started Jul 26 04:54:15 PM PDT 24
Finished Jul 26 04:55:52 PM PDT 24
Peak memory 258004 kb
Host smart-f48d79a3-2d9e-4ca0-ae1f-b5a508e230c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208824891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.2208824891
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.4074488793
Short name T271
Test name
Test status
Simulation time 99108393976 ps
CPU time 226.67 seconds
Started Jul 26 04:54:11 PM PDT 24
Finished Jul 26 04:57:58 PM PDT 24
Peak memory 268340 kb
Host smart-6d1ce861-6c18-44df-9832-be296bc3d001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074488793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.4074488793
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.1183031636
Short name T552
Test name
Test status
Simulation time 994010498 ps
CPU time 6.71 seconds
Started Jul 26 04:54:09 PM PDT 24
Finished Jul 26 04:54:16 PM PDT 24
Peak memory 234568 kb
Host smart-76f9509a-8645-4a4c-b3d9-97f2b59fc1a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183031636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.1183031636
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.3545424548
Short name T946
Test name
Test status
Simulation time 61301272882 ps
CPU time 137.38 seconds
Started Jul 26 04:54:09 PM PDT 24
Finished Jul 26 04:56:27 PM PDT 24
Peak memory 254008 kb
Host smart-e173ef64-dc20-4679-bcad-e709ff16bf9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545424548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmd
s.3545424548
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/40.spi_device_intercept.306011238
Short name T224
Test name
Test status
Simulation time 45689236 ps
CPU time 2.58 seconds
Started Jul 26 04:54:09 PM PDT 24
Finished Jul 26 04:54:12 PM PDT 24
Peak memory 233516 kb
Host smart-e0ff0056-9229-4ac2-b1f6-84eb05686325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306011238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.306011238
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.122955476
Short name T752
Test name
Test status
Simulation time 1757428067 ps
CPU time 25.27 seconds
Started Jul 26 04:54:15 PM PDT 24
Finished Jul 26 04:54:41 PM PDT 24
Peak memory 249928 kb
Host smart-e4641bbf-75ff-47ea-868b-baf92df49f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122955476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.122955476
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.1197349835
Short name T256
Test name
Test status
Simulation time 38222873106 ps
CPU time 35.61 seconds
Started Jul 26 04:54:14 PM PDT 24
Finished Jul 26 04:54:50 PM PDT 24
Peak memory 233556 kb
Host smart-1a88c604-4d96-4129-b82f-cd08a5c74051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197349835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.1197349835
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.3664814844
Short name T558
Test name
Test status
Simulation time 2916804276 ps
CPU time 9.82 seconds
Started Jul 26 04:54:07 PM PDT 24
Finished Jul 26 04:54:17 PM PDT 24
Peak memory 225404 kb
Host smart-4213cd00-4402-4dae-a9a5-ba11d22070e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664814844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.3664814844
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.3852888873
Short name T698
Test name
Test status
Simulation time 1673630145 ps
CPU time 5.19 seconds
Started Jul 26 04:54:15 PM PDT 24
Finished Jul 26 04:54:20 PM PDT 24
Peak memory 223616 kb
Host smart-2cf7d39d-dda5-4471-ab8f-52ce2c696875
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3852888873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.3852888873
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.2274651695
Short name T809
Test name
Test status
Simulation time 49919417379 ps
CPU time 65.41 seconds
Started Jul 26 04:54:10 PM PDT 24
Finished Jul 26 04:55:16 PM PDT 24
Peak memory 252084 kb
Host smart-e6e507e1-37e0-4416-92e2-1ad325c836ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274651695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.2274651695
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.1093861451
Short name T419
Test name
Test status
Simulation time 13332011086 ps
CPU time 7.96 seconds
Started Jul 26 04:54:17 PM PDT 24
Finished Jul 26 04:54:25 PM PDT 24
Peak memory 217064 kb
Host smart-6b0422a7-a9d4-4f46-b8b1-f36a12fd7e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093861451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.1093861451
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.1052402301
Short name T364
Test name
Test status
Simulation time 510536535 ps
CPU time 2.85 seconds
Started Jul 26 04:54:09 PM PDT 24
Finished Jul 26 04:54:13 PM PDT 24
Peak memory 217056 kb
Host smart-f14bda95-d86d-4e37-827c-777e821d33f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052402301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.1052402301
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.1082916108
Short name T458
Test name
Test status
Simulation time 189563651 ps
CPU time 1.14 seconds
Started Jul 26 04:54:09 PM PDT 24
Finished Jul 26 04:54:10 PM PDT 24
Peak memory 216788 kb
Host smart-b06b9f41-288e-4c0b-a31d-c965e64184ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082916108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.1082916108
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.2981162165
Short name T496
Test name
Test status
Simulation time 133819197 ps
CPU time 0.86 seconds
Started Jul 26 04:54:16 PM PDT 24
Finished Jul 26 04:54:17 PM PDT 24
Peak memory 206692 kb
Host smart-4513ffa3-12da-4c14-92b2-7146a8c7c5e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981162165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.2981162165
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.3451317245
Short name T681
Test name
Test status
Simulation time 1747368082 ps
CPU time 5.51 seconds
Started Jul 26 04:54:15 PM PDT 24
Finished Jul 26 04:54:21 PM PDT 24
Peak memory 233420 kb
Host smart-87e132db-7452-40e8-886d-e3bc06c00744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451317245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.3451317245
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.51373604
Short name T600
Test name
Test status
Simulation time 13774515 ps
CPU time 0.71 seconds
Started Jul 26 04:54:14 PM PDT 24
Finished Jul 26 04:54:15 PM PDT 24
Peak memory 205364 kb
Host smart-ebb13c92-bbf3-451f-bf15-112cffb20e08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51373604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.51373604
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.448621805
Short name T131
Test name
Test status
Simulation time 1681873966 ps
CPU time 9.65 seconds
Started Jul 26 04:54:20 PM PDT 24
Finished Jul 26 04:54:30 PM PDT 24
Peak memory 225360 kb
Host smart-b616ca75-cfef-49f0-a315-0fa07d11bc82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448621805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.448621805
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.3326428962
Short name T322
Test name
Test status
Simulation time 19332348 ps
CPU time 0.75 seconds
Started Jul 26 04:54:12 PM PDT 24
Finished Jul 26 04:54:13 PM PDT 24
Peak memory 207108 kb
Host smart-634defb4-efd0-456b-b3b7-94903ce7945b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326428962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.3326428962
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.3709306888
Short name T798
Test name
Test status
Simulation time 5423596979 ps
CPU time 68.11 seconds
Started Jul 26 04:54:16 PM PDT 24
Finished Jul 26 04:55:24 PM PDT 24
Peak memory 257144 kb
Host smart-08f11c41-8472-42d0-87b6-5e1874a85117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709306888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.3709306888
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.3011058363
Short name T720
Test name
Test status
Simulation time 18607089874 ps
CPU time 167.55 seconds
Started Jul 26 04:54:08 PM PDT 24
Finished Jul 26 04:56:56 PM PDT 24
Peak memory 258188 kb
Host smart-df7ffacb-3fff-41be-af56-6da6945b804b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011058363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.3011058363
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.3686103896
Short name T182
Test name
Test status
Simulation time 2180769933 ps
CPU time 22.87 seconds
Started Jul 26 04:54:20 PM PDT 24
Finished Jul 26 04:54:44 PM PDT 24
Peak memory 241676 kb
Host smart-35baf104-f144-47cc-b5a7-dbf8a4e03a41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686103896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.3686103896
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.987988801
Short name T70
Test name
Test status
Simulation time 186162912 ps
CPU time 4.27 seconds
Started Jul 26 04:54:14 PM PDT 24
Finished Jul 26 04:54:18 PM PDT 24
Peak memory 233524 kb
Host smart-355aadd9-1f85-4f9b-ae87-ad93789a9fcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987988801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.987988801
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.649950642
Short name T4
Test name
Test status
Simulation time 1053598088 ps
CPU time 20.6 seconds
Started Jul 26 04:54:13 PM PDT 24
Finished Jul 26 04:54:34 PM PDT 24
Peak memory 255248 kb
Host smart-9e223bed-9ce8-4672-abd1-6cd20aa4aea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649950642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmds
.649950642
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_intercept.3556771167
Short name T983
Test name
Test status
Simulation time 34640924 ps
CPU time 2.45 seconds
Started Jul 26 04:54:19 PM PDT 24
Finished Jul 26 04:54:22 PM PDT 24
Peak memory 233084 kb
Host smart-66b1a766-f98b-45cf-8d00-f8fa55326479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556771167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.3556771167
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.948040181
Short name T553
Test name
Test status
Simulation time 3090263763 ps
CPU time 17.08 seconds
Started Jul 26 04:54:16 PM PDT 24
Finished Jul 26 04:54:33 PM PDT 24
Peak memory 225368 kb
Host smart-994ebd3d-e2a1-4810-9172-9dd5ce46276d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948040181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.948040181
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.1070515049
Short name T653
Test name
Test status
Simulation time 10058395151 ps
CPU time 10.39 seconds
Started Jul 26 04:54:15 PM PDT 24
Finished Jul 26 04:54:26 PM PDT 24
Peak memory 225336 kb
Host smart-fea2a496-7ded-4f7d-83dc-f45796c5ee5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070515049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.1070515049
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.4050200610
Short name T429
Test name
Test status
Simulation time 9690051299 ps
CPU time 9.02 seconds
Started Jul 26 04:54:19 PM PDT 24
Finished Jul 26 04:54:28 PM PDT 24
Peak memory 233508 kb
Host smart-df32f9d1-9a15-4a3d-ada2-8218d6dfb539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050200610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.4050200610
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.1609764922
Short name T407
Test name
Test status
Simulation time 1769735740 ps
CPU time 7.75 seconds
Started Jul 26 04:54:19 PM PDT 24
Finished Jul 26 04:54:27 PM PDT 24
Peak memory 223176 kb
Host smart-7f623836-f4fd-44f2-93ee-a1b7d18bdfdd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1609764922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.1609764922
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.575183183
Short name T452
Test name
Test status
Simulation time 147685212 ps
CPU time 1.99 seconds
Started Jul 26 04:54:20 PM PDT 24
Finished Jul 26 04:54:23 PM PDT 24
Peak memory 217060 kb
Host smart-a1933693-48ab-43b6-9809-db670ba47727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575183183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.575183183
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.2811134889
Short name T331
Test name
Test status
Simulation time 12673038487 ps
CPU time 8.15 seconds
Started Jul 26 04:54:15 PM PDT 24
Finished Jul 26 04:54:24 PM PDT 24
Peak memory 219348 kb
Host smart-349c82e0-0da2-4835-81e0-aef32fc4ec1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811134889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.2811134889
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.69661868
Short name T382
Test name
Test status
Simulation time 85051040 ps
CPU time 1.27 seconds
Started Jul 26 04:54:20 PM PDT 24
Finished Jul 26 04:54:21 PM PDT 24
Peak memory 208748 kb
Host smart-d009270e-4eee-4cea-9b5d-84ac04a9e7f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69661868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.69661868
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.2444017864
Short name T377
Test name
Test status
Simulation time 58452553 ps
CPU time 0.88 seconds
Started Jul 26 04:54:10 PM PDT 24
Finished Jul 26 04:54:11 PM PDT 24
Peak memory 207712 kb
Host smart-97e869cf-bcf4-4cd3-8d9f-57aaf5214c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444017864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.2444017864
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.4054145498
Short name T422
Test name
Test status
Simulation time 189199092 ps
CPU time 3.35 seconds
Started Jul 26 04:54:09 PM PDT 24
Finished Jul 26 04:54:13 PM PDT 24
Peak memory 233564 kb
Host smart-311cf52f-7eea-415c-a7a3-fffae34dee02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054145498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.4054145498
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.4161684141
Short name T629
Test name
Test status
Simulation time 63345379 ps
CPU time 0.72 seconds
Started Jul 26 04:54:29 PM PDT 24
Finished Jul 26 04:54:30 PM PDT 24
Peak memory 206300 kb
Host smart-2c226bc1-a646-402f-b992-b1be1701f0c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161684141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
4161684141
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.1054120346
Short name T481
Test name
Test status
Simulation time 36924844 ps
CPU time 2.52 seconds
Started Jul 26 04:54:28 PM PDT 24
Finished Jul 26 04:54:31 PM PDT 24
Peak memory 233480 kb
Host smart-e5ac77a0-8830-4670-98c7-ee22f5bd7ebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054120346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.1054120346
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.703451716
Short name T957
Test name
Test status
Simulation time 119029322 ps
CPU time 0.78 seconds
Started Jul 26 04:54:11 PM PDT 24
Finished Jul 26 04:54:12 PM PDT 24
Peak memory 207428 kb
Host smart-d1abd634-74e9-4b8e-88ca-474fc31c4752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703451716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.703451716
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.840134514
Short name T780
Test name
Test status
Simulation time 19521438 ps
CPU time 0.77 seconds
Started Jul 26 04:54:23 PM PDT 24
Finished Jul 26 04:54:24 PM PDT 24
Peak memory 216584 kb
Host smart-9d6a6038-6239-4bfa-8332-cdd2cd433566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840134514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.840134514
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.3490291497
Short name T216
Test name
Test status
Simulation time 148829619377 ps
CPU time 213.6 seconds
Started Jul 26 04:54:17 PM PDT 24
Finished Jul 26 04:57:51 PM PDT 24
Peak memory 249964 kb
Host smart-14c9697d-578c-4d31-be2d-423b2deb3a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490291497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.3490291497
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.874073910
Short name T139
Test name
Test status
Simulation time 4297926208 ps
CPU time 19.53 seconds
Started Jul 26 04:54:18 PM PDT 24
Finished Jul 26 04:54:37 PM PDT 24
Peak memory 236724 kb
Host smart-a8ba91e1-e3d7-4dfa-b59f-e2f750ca6642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874073910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.874073910
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.1654752418
Short name T171
Test name
Test status
Simulation time 113173136190 ps
CPU time 199.29 seconds
Started Jul 26 04:54:28 PM PDT 24
Finished Jul 26 04:57:47 PM PDT 24
Peak memory 254476 kb
Host smart-313b10bb-79bf-4a80-8479-7f2baea6834a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654752418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmd
s.1654752418
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_intercept.2039814271
Short name T774
Test name
Test status
Simulation time 779419607 ps
CPU time 9.72 seconds
Started Jul 26 04:54:30 PM PDT 24
Finished Jul 26 04:54:40 PM PDT 24
Peak memory 219420 kb
Host smart-943411ce-ca1a-4da1-8048-b7c92d3aa08a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039814271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.2039814271
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.3897908768
Short name T391
Test name
Test status
Simulation time 117169259 ps
CPU time 2.38 seconds
Started Jul 26 04:54:31 PM PDT 24
Finished Jul 26 04:54:34 PM PDT 24
Peak memory 225296 kb
Host smart-4db275ee-0859-453f-88bb-643a6995855c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897908768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.3897908768
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.1608266856
Short name T213
Test name
Test status
Simulation time 12668781270 ps
CPU time 9.38 seconds
Started Jul 26 04:54:18 PM PDT 24
Finished Jul 26 04:54:27 PM PDT 24
Peak memory 225316 kb
Host smart-1c59d8be-dbb9-4bf7-bfac-ca933605066f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608266856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.1608266856
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.1749910020
Short name T432
Test name
Test status
Simulation time 3086983374 ps
CPU time 5.51 seconds
Started Jul 26 04:54:16 PM PDT 24
Finished Jul 26 04:54:22 PM PDT 24
Peak memory 225452 kb
Host smart-ef94e470-18a7-4ed1-b0d8-ea1c364b4748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749910020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.1749910020
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.984804160
Short name T1028
Test name
Test status
Simulation time 574230025 ps
CPU time 3.46 seconds
Started Jul 26 04:54:18 PM PDT 24
Finished Jul 26 04:54:22 PM PDT 24
Peak memory 219884 kb
Host smart-6a77c268-b7a1-4f52-b07c-46ec30cf3204
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=984804160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dire
ct.984804160
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.2115264464
Short name T568
Test name
Test status
Simulation time 1513146758 ps
CPU time 6 seconds
Started Jul 26 04:54:28 PM PDT 24
Finished Jul 26 04:54:34 PM PDT 24
Peak memory 225252 kb
Host smart-3e419c7a-4992-4a3c-9012-8c62d735446a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115264464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.2115264464
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.1098811319
Short name T961
Test name
Test status
Simulation time 1056064979 ps
CPU time 16.52 seconds
Started Jul 26 04:54:12 PM PDT 24
Finished Jul 26 04:54:29 PM PDT 24
Peak memory 217064 kb
Host smart-ebca6c7f-fab6-43d1-960a-5672ef2c2f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098811319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.1098811319
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.3460611846
Short name T1021
Test name
Test status
Simulation time 13307808 ps
CPU time 0.7 seconds
Started Jul 26 04:54:16 PM PDT 24
Finished Jul 26 04:54:17 PM PDT 24
Peak memory 206304 kb
Host smart-c67e3fa6-7e71-4582-a051-dda6c2e1bb91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460611846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.3460611846
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.2163791484
Short name T703
Test name
Test status
Simulation time 1489836796 ps
CPU time 1.18 seconds
Started Jul 26 04:54:20 PM PDT 24
Finished Jul 26 04:54:22 PM PDT 24
Peak memory 208520 kb
Host smart-ed41ca79-9725-4593-8bee-95f7459f2b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163791484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.2163791484
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.2563840037
Short name T80
Test name
Test status
Simulation time 52999541 ps
CPU time 0.86 seconds
Started Jul 26 04:54:20 PM PDT 24
Finished Jul 26 04:54:21 PM PDT 24
Peak memory 206568 kb
Host smart-6299765c-50d3-4485-a455-4617394f75cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563840037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.2563840037
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.651809260
Short name T989
Test name
Test status
Simulation time 7190954883 ps
CPU time 16.54 seconds
Started Jul 26 04:54:28 PM PDT 24
Finished Jul 26 04:54:45 PM PDT 24
Peak memory 241860 kb
Host smart-5d52b805-99c2-4ec6-b5d7-8e484fb2e94b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651809260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.651809260
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.2052751191
Short name T542
Test name
Test status
Simulation time 14158116 ps
CPU time 0.71 seconds
Started Jul 26 04:54:31 PM PDT 24
Finished Jul 26 04:54:32 PM PDT 24
Peak memory 205240 kb
Host smart-e81f3637-ee0d-4f99-9dc2-1367fd233077
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052751191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
2052751191
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.967896505
Short name T438
Test name
Test status
Simulation time 1283157205 ps
CPU time 14.97 seconds
Started Jul 26 04:54:29 PM PDT 24
Finished Jul 26 04:54:44 PM PDT 24
Peak memory 233468 kb
Host smart-a0a9d10d-4c2f-427f-97ed-8f2c579e701d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967896505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.967896505
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.3489438595
Short name T482
Test name
Test status
Simulation time 42837303 ps
CPU time 0.81 seconds
Started Jul 26 04:54:20 PM PDT 24
Finished Jul 26 04:54:21 PM PDT 24
Peak memory 207144 kb
Host smart-c7d13c06-f5fb-48f9-a98a-633cc577ca52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489438595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.3489438595
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.3901727102
Short name T652
Test name
Test status
Simulation time 5570615903 ps
CPU time 27.37 seconds
Started Jul 26 04:54:27 PM PDT 24
Finished Jul 26 04:54:55 PM PDT 24
Peak memory 250028 kb
Host smart-58943bcd-18c3-456f-a79c-f6f99bb139a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901727102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.3901727102
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.118713960
Short name T31
Test name
Test status
Simulation time 127397599198 ps
CPU time 131.62 seconds
Started Jul 26 04:54:17 PM PDT 24
Finished Jul 26 04:56:29 PM PDT 24
Peak memory 274592 kb
Host smart-a6523689-8639-46f6-9756-d8c4e2240410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118713960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.118713960
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.4274011275
Short name T247
Test name
Test status
Simulation time 16998032554 ps
CPU time 63.48 seconds
Started Jul 26 04:54:20 PM PDT 24
Finished Jul 26 04:55:23 PM PDT 24
Peak memory 225360 kb
Host smart-72de8d80-6fd2-4e29-b82e-bd06b20cea04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274011275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.4274011275
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.1031862101
Short name T298
Test name
Test status
Simulation time 5730275775 ps
CPU time 16.46 seconds
Started Jul 26 04:54:31 PM PDT 24
Finished Jul 26 04:54:47 PM PDT 24
Peak memory 233576 kb
Host smart-0b75468d-dc3b-47a4-a8e4-2553f34b0d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031862101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.1031862101
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_intercept.2455043219
Short name T519
Test name
Test status
Simulation time 752986997 ps
CPU time 4.55 seconds
Started Jul 26 04:54:31 PM PDT 24
Finished Jul 26 04:54:35 PM PDT 24
Peak memory 225308 kb
Host smart-fd37c3f5-9123-4ff7-abc0-0c899917c889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455043219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.2455043219
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.3358877256
Short name T707
Test name
Test status
Simulation time 2450559851 ps
CPU time 6.17 seconds
Started Jul 26 04:54:16 PM PDT 24
Finished Jul 26 04:54:23 PM PDT 24
Peak memory 225412 kb
Host smart-eff8f158-2911-4c36-a731-ea8bd985380a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358877256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.3358877256
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.1635063345
Short name T130
Test name
Test status
Simulation time 39568173890 ps
CPU time 27.61 seconds
Started Jul 26 04:54:20 PM PDT 24
Finished Jul 26 04:54:48 PM PDT 24
Peak memory 233644 kb
Host smart-46ca0e0c-e094-46f6-bf74-dfd8401971da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635063345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.1635063345
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.1754436843
Short name T807
Test name
Test status
Simulation time 29579409739 ps
CPU time 18.76 seconds
Started Jul 26 04:54:26 PM PDT 24
Finished Jul 26 04:54:45 PM PDT 24
Peak memory 225284 kb
Host smart-5c336edb-8a0b-444f-a968-f52c68479c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754436843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.1754436843
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.2380618582
Short name T592
Test name
Test status
Simulation time 17213362490 ps
CPU time 16.83 seconds
Started Jul 26 04:54:25 PM PDT 24
Finished Jul 26 04:54:42 PM PDT 24
Peak memory 220728 kb
Host smart-fe01bae2-17c5-4910-bf79-f1577a878b1f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2380618582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.2380618582
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.1840085712
Short name T204
Test name
Test status
Simulation time 37869030736 ps
CPU time 296.31 seconds
Started Jul 26 04:54:17 PM PDT 24
Finished Jul 26 04:59:14 PM PDT 24
Peak memory 258248 kb
Host smart-dd78ed68-1e6a-4362-89be-8e3c8eabd68d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840085712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.1840085712
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.2931828016
Short name T937
Test name
Test status
Simulation time 69009073 ps
CPU time 0.73 seconds
Started Jul 26 04:54:29 PM PDT 24
Finished Jul 26 04:54:29 PM PDT 24
Peak memory 206224 kb
Host smart-79411451-da38-4a9a-aca2-7938b31128f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931828016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.2931828016
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.1983755919
Short name T697
Test name
Test status
Simulation time 1023268403 ps
CPU time 6 seconds
Started Jul 26 04:54:31 PM PDT 24
Finished Jul 26 04:54:37 PM PDT 24
Peak memory 217008 kb
Host smart-42955b7f-f276-4b3e-9ea4-0a2659664c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983755919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.1983755919
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.103515237
Short name T306
Test name
Test status
Simulation time 95924930 ps
CPU time 1.63 seconds
Started Jul 26 04:54:18 PM PDT 24
Finished Jul 26 04:54:20 PM PDT 24
Peak memory 217016 kb
Host smart-4b620ede-65aa-40f2-8b0e-bd59f98631ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103515237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.103515237
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.1296998059
Short name T359
Test name
Test status
Simulation time 39332015 ps
CPU time 0.84 seconds
Started Jul 26 04:54:27 PM PDT 24
Finished Jul 26 04:54:28 PM PDT 24
Peak memory 206512 kb
Host smart-e84ee19c-0964-4458-aac0-4946440bfc17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296998059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.1296998059
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.2203709508
Short name T885
Test name
Test status
Simulation time 5690013277 ps
CPU time 13.62 seconds
Started Jul 26 04:54:26 PM PDT 24
Finished Jul 26 04:54:39 PM PDT 24
Peak memory 249988 kb
Host smart-49ff62fe-8c1c-44a1-8d58-fcbbf06cc70b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203709508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.2203709508
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.1595075916
Short name T971
Test name
Test status
Simulation time 29211764 ps
CPU time 0.72 seconds
Started Jul 26 04:54:26 PM PDT 24
Finished Jul 26 04:54:27 PM PDT 24
Peak memory 205864 kb
Host smart-c2cbe843-25d7-4569-aaf7-136c3fa077bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595075916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
1595075916
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.1531794493
Short name T238
Test name
Test status
Simulation time 3946898926 ps
CPU time 5.33 seconds
Started Jul 26 04:54:16 PM PDT 24
Finished Jul 26 04:54:22 PM PDT 24
Peak memory 233556 kb
Host smart-91aa5701-6306-4062-bbba-131d66094053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531794493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.1531794493
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.1869630516
Short name T647
Test name
Test status
Simulation time 24079051 ps
CPU time 0.75 seconds
Started Jul 26 04:54:16 PM PDT 24
Finished Jul 26 04:54:17 PM PDT 24
Peak memory 206144 kb
Host smart-08c851d6-74a2-44a2-bf5a-f22125a1642e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869630516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.1869630516
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.2325913914
Short name T744
Test name
Test status
Simulation time 4841505611 ps
CPU time 48.97 seconds
Started Jul 26 04:54:31 PM PDT 24
Finished Jul 26 04:55:20 PM PDT 24
Peak memory 253192 kb
Host smart-ee1604ad-2413-4593-8cb3-b22ac6ae2dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325913914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.2325913914
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.1902924478
Short name T466
Test name
Test status
Simulation time 3698876068 ps
CPU time 38.16 seconds
Started Jul 26 04:54:33 PM PDT 24
Finished Jul 26 04:55:12 PM PDT 24
Peak memory 240528 kb
Host smart-b698868a-e333-482e-9fd4-a59b4a5782f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902924478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.1902924478
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.1626970693
Short name T188
Test name
Test status
Simulation time 4804015987 ps
CPU time 34.09 seconds
Started Jul 26 04:54:28 PM PDT 24
Finished Jul 26 04:55:02 PM PDT 24
Peak memory 241448 kb
Host smart-862f29a0-9606-4a8b-856f-2c35f3734a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626970693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.1626970693
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.895655032
Short name T959
Test name
Test status
Simulation time 7061924183 ps
CPU time 49.1 seconds
Started Jul 26 04:54:30 PM PDT 24
Finished Jul 26 04:55:19 PM PDT 24
Peak memory 256232 kb
Host smart-4a9cd9a9-8f4e-4983-9613-a3e708539888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895655032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmds
.895655032
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/44.spi_device_intercept.779117961
Short name T608
Test name
Test status
Simulation time 2853711874 ps
CPU time 15.64 seconds
Started Jul 26 04:54:28 PM PDT 24
Finished Jul 26 04:54:44 PM PDT 24
Peak memory 225316 kb
Host smart-5627a4a0-2e36-477f-8192-4b26eb7481a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779117961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.779117961
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.1540387910
Short name T560
Test name
Test status
Simulation time 1635539255 ps
CPU time 9.07 seconds
Started Jul 26 04:54:13 PM PDT 24
Finished Jul 26 04:54:23 PM PDT 24
Peak memory 225280 kb
Host smart-4ca6d611-b059-419e-bc6c-eaf53e9d6eb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540387910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.1540387910
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.3434689496
Short name T632
Test name
Test status
Simulation time 115302183 ps
CPU time 2.38 seconds
Started Jul 26 04:54:19 PM PDT 24
Finished Jul 26 04:54:21 PM PDT 24
Peak memory 233508 kb
Host smart-9bffa00a-e3ba-4c49-864c-a8f1ae854a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434689496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.3434689496
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.682332863
Short name T602
Test name
Test status
Simulation time 14413528214 ps
CPU time 10.69 seconds
Started Jul 26 04:54:21 PM PDT 24
Finished Jul 26 04:54:32 PM PDT 24
Peak memory 225424 kb
Host smart-5caffe06-8529-4f3a-8847-7818e757e3c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682332863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.682332863
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.3903668089
Short name T323
Test name
Test status
Simulation time 860907303 ps
CPU time 11.01 seconds
Started Jul 26 04:54:33 PM PDT 24
Finished Jul 26 04:54:45 PM PDT 24
Peak memory 221412 kb
Host smart-5eef7ed0-ceab-45c9-9693-b328b9fc81e3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3903668089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.3903668089
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.3653998366
Short name T22
Test name
Test status
Simulation time 4170055850 ps
CPU time 77.3 seconds
Started Jul 26 04:54:36 PM PDT 24
Finished Jul 26 04:55:53 PM PDT 24
Peak memory 253040 kb
Host smart-1c2960bb-66f0-4af1-94b7-7c64ecee0404
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653998366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.3653998366
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.1964893645
Short name T844
Test name
Test status
Simulation time 36093859364 ps
CPU time 11.83 seconds
Started Jul 26 04:54:30 PM PDT 24
Finished Jul 26 04:54:42 PM PDT 24
Peak memory 217004 kb
Host smart-14d7d899-fbcd-403a-bbdc-a748e5234c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964893645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.1964893645
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.3583010368
Short name T723
Test name
Test status
Simulation time 1278187306 ps
CPU time 3.89 seconds
Started Jul 26 04:54:26 PM PDT 24
Finished Jul 26 04:54:30 PM PDT 24
Peak memory 217092 kb
Host smart-16182982-4626-4de7-99b6-8cc8de6cda82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583010368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.3583010368
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.2571505170
Short name T583
Test name
Test status
Simulation time 87118727 ps
CPU time 3.06 seconds
Started Jul 26 04:54:33 PM PDT 24
Finished Jul 26 04:54:36 PM PDT 24
Peak memory 217128 kb
Host smart-1481abad-630d-4be9-b151-6884d5162637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571505170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.2571505170
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.2788990538
Short name T378
Test name
Test status
Simulation time 187733751 ps
CPU time 0.85 seconds
Started Jul 26 04:54:22 PM PDT 24
Finished Jul 26 04:54:23 PM PDT 24
Peak memory 207696 kb
Host smart-fead08ac-977c-4842-a88f-0b47113f6234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788990538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.2788990538
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.3263508855
Short name T603
Test name
Test status
Simulation time 968716083 ps
CPU time 6.89 seconds
Started Jul 26 04:54:25 PM PDT 24
Finished Jul 26 04:54:32 PM PDT 24
Peak memory 233496 kb
Host smart-db94acbb-c17b-473a-a7b0-98e3e0d6044f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263508855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.3263508855
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.2060943337
Short name T520
Test name
Test status
Simulation time 30310529 ps
CPU time 0.71 seconds
Started Jul 26 04:54:30 PM PDT 24
Finished Jul 26 04:54:31 PM PDT 24
Peak memory 205976 kb
Host smart-92f8dc67-df90-4696-9d31-8c981a499ca8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060943337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
2060943337
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.370245
Short name T988
Test name
Test status
Simulation time 256588971 ps
CPU time 4.49 seconds
Started Jul 26 04:54:34 PM PDT 24
Finished Jul 26 04:54:39 PM PDT 24
Peak memory 225360 kb
Host smart-a44981fd-2119-44fc-8ca4-4897d1dec372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.370245
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.356470386
Short name T984
Test name
Test status
Simulation time 46043231 ps
CPU time 0.78 seconds
Started Jul 26 04:54:32 PM PDT 24
Finished Jul 26 04:54:33 PM PDT 24
Peak memory 207176 kb
Host smart-5ff8f43a-0469-4ec2-83d8-715a6a649bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356470386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.356470386
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.130848604
Short name T195
Test name
Test status
Simulation time 137054980952 ps
CPU time 286.12 seconds
Started Jul 26 04:54:27 PM PDT 24
Finished Jul 26 04:59:13 PM PDT 24
Peak memory 271664 kb
Host smart-0ebf659b-fc71-4f87-98b6-2eba7198d244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130848604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.130848604
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.2403197586
Short name T356
Test name
Test status
Simulation time 6632295476 ps
CPU time 121.35 seconds
Started Jul 26 04:54:34 PM PDT 24
Finished Jul 26 04:56:36 PM PDT 24
Peak memory 252080 kb
Host smart-996fbfa2-08f3-4145-a2f3-501fdc5f6190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403197586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.2403197586
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.3352124258
Short name T732
Test name
Test status
Simulation time 781569122 ps
CPU time 10.39 seconds
Started Jul 26 04:54:33 PM PDT 24
Finished Jul 26 04:54:44 PM PDT 24
Peak memory 233416 kb
Host smart-f5372554-f4c6-4cbe-b524-58622299e990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352124258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.3352124258
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.2777031648
Short name T176
Test name
Test status
Simulation time 19023081234 ps
CPU time 34.74 seconds
Started Jul 26 04:54:30 PM PDT 24
Finished Jul 26 04:55:05 PM PDT 24
Peak memory 241880 kb
Host smart-aeacb7c0-6ac7-42eb-b6ec-f235977cc12b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777031648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmd
s.2777031648
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_intercept.4195747958
Short name T784
Test name
Test status
Simulation time 1108716179 ps
CPU time 12.76 seconds
Started Jul 26 04:54:31 PM PDT 24
Finished Jul 26 04:54:44 PM PDT 24
Peak memory 225160 kb
Host smart-e3d7b5fe-b53d-4550-8e05-e7b61459412f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195747958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.4195747958
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.4263335983
Short name T644
Test name
Test status
Simulation time 480630912 ps
CPU time 3.69 seconds
Started Jul 26 04:54:32 PM PDT 24
Finished Jul 26 04:54:36 PM PDT 24
Peak memory 225348 kb
Host smart-7cf241b2-6371-4d63-91c8-87e827fcea26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263335983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.4263335983
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.1622278724
Short name T410
Test name
Test status
Simulation time 596530829 ps
CPU time 3.08 seconds
Started Jul 26 04:54:30 PM PDT 24
Finished Jul 26 04:54:33 PM PDT 24
Peak memory 233528 kb
Host smart-b02e7140-7c56-4341-b5c9-13e272a93659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622278724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.1622278724
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.3032307536
Short name T952
Test name
Test status
Simulation time 61400149477 ps
CPU time 14.25 seconds
Started Jul 26 04:54:42 PM PDT 24
Finished Jul 26 04:54:56 PM PDT 24
Peak memory 233576 kb
Host smart-49d9a26f-674f-475a-97f5-20550277f94b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032307536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.3032307536
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.1222399464
Short name T23
Test name
Test status
Simulation time 330658985 ps
CPU time 4.23 seconds
Started Jul 26 04:54:34 PM PDT 24
Finished Jul 26 04:54:38 PM PDT 24
Peak memory 223776 kb
Host smart-bb856458-e00b-4439-9ba0-2bc828034232
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1222399464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.1222399464
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.2082759906
Short name T870
Test name
Test status
Simulation time 28509658718 ps
CPU time 96.05 seconds
Started Jul 26 04:54:28 PM PDT 24
Finished Jul 26 04:56:04 PM PDT 24
Peak memory 251904 kb
Host smart-51521578-27a0-4eaa-8144-025dc4a6306c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082759906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.2082759906
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.519714622
Short name T627
Test name
Test status
Simulation time 48840392548 ps
CPU time 13.81 seconds
Started Jul 26 04:54:32 PM PDT 24
Finished Jul 26 04:54:45 PM PDT 24
Peak memory 217064 kb
Host smart-6e758e56-0de8-4998-b89e-3f5f9a583fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519714622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.519714622
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.3330357808
Short name T843
Test name
Test status
Simulation time 2429808274 ps
CPU time 4.4 seconds
Started Jul 26 04:54:27 PM PDT 24
Finished Jul 26 04:54:31 PM PDT 24
Peak memory 217108 kb
Host smart-e678dece-23d5-4c3f-ad77-ff38c0819bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330357808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.3330357808
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.2306329284
Short name T855
Test name
Test status
Simulation time 170079450 ps
CPU time 1.52 seconds
Started Jul 26 04:54:28 PM PDT 24
Finished Jul 26 04:54:30 PM PDT 24
Peak memory 217020 kb
Host smart-5e4f5b41-038e-48f2-b59e-77f07b155907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306329284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.2306329284
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.564054705
Short name T440
Test name
Test status
Simulation time 23583552 ps
CPU time 0.72 seconds
Started Jul 26 04:54:37 PM PDT 24
Finished Jul 26 04:54:38 PM PDT 24
Peak memory 206564 kb
Host smart-896976ac-3f1d-4c1c-a46d-7292564e500a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564054705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.564054705
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.3414455954
Short name T914
Test name
Test status
Simulation time 1757342028 ps
CPU time 7.74 seconds
Started Jul 26 04:54:30 PM PDT 24
Finished Jul 26 04:54:38 PM PDT 24
Peak memory 233496 kb
Host smart-4a8c570e-7b70-4649-90f8-be4a69d40744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414455954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.3414455954
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.941794631
Short name T129
Test name
Test status
Simulation time 31374556 ps
CPU time 0.7 seconds
Started Jul 26 04:54:36 PM PDT 24
Finished Jul 26 04:54:37 PM PDT 24
Peak memory 205928 kb
Host smart-af04e45a-2f90-4dd5-bb57-0cf11a91fd56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941794631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.941794631
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.3445631934
Short name T806
Test name
Test status
Simulation time 6224822175 ps
CPU time 19.91 seconds
Started Jul 26 04:54:30 PM PDT 24
Finished Jul 26 04:54:50 PM PDT 24
Peak memory 233668 kb
Host smart-ab7aba6f-8d9b-4af8-8bc4-9e9979bd7257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445631934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.3445631934
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.560931166
Short name T478
Test name
Test status
Simulation time 48632791 ps
CPU time 0.77 seconds
Started Jul 26 04:54:31 PM PDT 24
Finished Jul 26 04:54:32 PM PDT 24
Peak memory 207212 kb
Host smart-1ec94fa9-43cf-4942-8dcf-63ea997005d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560931166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.560931166
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.3759486168
Short name T267
Test name
Test status
Simulation time 213934126500 ps
CPU time 404.85 seconds
Started Jul 26 04:54:35 PM PDT 24
Finished Jul 26 05:01:20 PM PDT 24
Peak memory 282408 kb
Host smart-d69cae8a-e5fc-43c5-a975-33c4cb22d1a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759486168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.3759486168
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.3937566147
Short name T134
Test name
Test status
Simulation time 8579558822 ps
CPU time 82.24 seconds
Started Jul 26 04:54:29 PM PDT 24
Finished Jul 26 04:55:52 PM PDT 24
Peak memory 241156 kb
Host smart-c5c1ac47-a947-4344-a973-0774da415168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937566147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.3937566147
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.1772000256
Short name T962
Test name
Test status
Simulation time 29650181326 ps
CPU time 284.45 seconds
Started Jul 26 04:54:32 PM PDT 24
Finished Jul 26 04:59:16 PM PDT 24
Peak memory 258196 kb
Host smart-dc7ab9b1-e4dd-4302-8def-717a7a3f57fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772000256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.1772000256
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.923893367
Short name T296
Test name
Test status
Simulation time 334599782 ps
CPU time 7.81 seconds
Started Jul 26 04:54:29 PM PDT 24
Finished Jul 26 04:54:36 PM PDT 24
Peak memory 241688 kb
Host smart-064a77c6-e81d-44ae-96e7-349221671c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923893367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.923893367
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.589401191
Short name T716
Test name
Test status
Simulation time 2173247648 ps
CPU time 37.97 seconds
Started Jul 26 04:54:34 PM PDT 24
Finished Jul 26 04:55:12 PM PDT 24
Peak memory 249996 kb
Host smart-1ec91aeb-b4b3-42a6-a0a3-6800f4d46ee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589401191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmds
.589401191
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_intercept.1502763845
Short name T942
Test name
Test status
Simulation time 71922939 ps
CPU time 2.06 seconds
Started Jul 26 04:54:28 PM PDT 24
Finished Jul 26 04:54:30 PM PDT 24
Peak memory 224532 kb
Host smart-82a0d2d2-97a7-44ce-8a44-bac094ddf716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502763845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.1502763845
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.2113612526
Short name T1002
Test name
Test status
Simulation time 264670477 ps
CPU time 3.34 seconds
Started Jul 26 04:54:28 PM PDT 24
Finished Jul 26 04:54:32 PM PDT 24
Peak memory 225332 kb
Host smart-76e32ba0-4fd1-4fe3-8de2-10591cf94456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113612526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.2113612526
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.1429715242
Short name T650
Test name
Test status
Simulation time 1029285107 ps
CPU time 8.36 seconds
Started Jul 26 04:54:28 PM PDT 24
Finished Jul 26 04:54:37 PM PDT 24
Peak memory 241652 kb
Host smart-75e0dd5a-93c8-42f1-b0eb-928f32374b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429715242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.1429715242
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.1177633017
Short name T190
Test name
Test status
Simulation time 80990315019 ps
CPU time 19.51 seconds
Started Jul 26 04:54:29 PM PDT 24
Finished Jul 26 04:54:48 PM PDT 24
Peak memory 233548 kb
Host smart-4483bf3e-66cf-4bc0-a8d3-4ee52a784f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177633017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.1177633017
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.2773166812
Short name T818
Test name
Test status
Simulation time 1215158259 ps
CPU time 7.25 seconds
Started Jul 26 04:54:28 PM PDT 24
Finished Jul 26 04:54:36 PM PDT 24
Peak memory 219672 kb
Host smart-d2589c5c-f39e-4fb8-90f5-9876af4cd3de
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2773166812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.2773166812
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.1627452233
Short name T1017
Test name
Test status
Simulation time 37318869622 ps
CPU time 234.07 seconds
Started Jul 26 04:54:35 PM PDT 24
Finished Jul 26 04:58:29 PM PDT 24
Peak memory 264508 kb
Host smart-be3eef4e-97f3-47ce-97ea-ad2d0b8d4a5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627452233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.1627452233
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.932358353
Short name T29
Test name
Test status
Simulation time 32935670685 ps
CPU time 31.26 seconds
Started Jul 26 04:54:27 PM PDT 24
Finished Jul 26 04:54:59 PM PDT 24
Peak memory 217128 kb
Host smart-9b5d1598-4831-43b0-918b-0f05e266b9ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932358353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.932358353
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.789044764
Short name T863
Test name
Test status
Simulation time 17550813116 ps
CPU time 15.5 seconds
Started Jul 26 04:54:32 PM PDT 24
Finished Jul 26 04:54:48 PM PDT 24
Peak memory 217140 kb
Host smart-f3cc906d-3019-49c2-a3c9-3e524ae98256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789044764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.789044764
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.3838666759
Short name T912
Test name
Test status
Simulation time 304395901 ps
CPU time 5.54 seconds
Started Jul 26 04:54:28 PM PDT 24
Finished Jul 26 04:54:33 PM PDT 24
Peak memory 217024 kb
Host smart-7cf3d2c1-5abc-4abb-8eca-c5e3485daa98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838666759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.3838666759
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.1071452537
Short name T576
Test name
Test status
Simulation time 16519447 ps
CPU time 0.81 seconds
Started Jul 26 04:54:58 PM PDT 24
Finished Jul 26 04:54:59 PM PDT 24
Peak memory 206692 kb
Host smart-14ea5f73-9a55-4d1c-82dd-518fff05e8ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071452537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.1071452537
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.2135872658
Short name T854
Test name
Test status
Simulation time 33240822962 ps
CPU time 11.61 seconds
Started Jul 26 04:54:34 PM PDT 24
Finished Jul 26 04:54:46 PM PDT 24
Peak memory 225400 kb
Host smart-dd00347d-0cb7-4d99-87f9-8283090a4268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135872658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.2135872658
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.2288678832
Short name T450
Test name
Test status
Simulation time 61131348 ps
CPU time 0.75 seconds
Started Jul 26 04:54:34 PM PDT 24
Finished Jul 26 04:54:35 PM PDT 24
Peak memory 206288 kb
Host smart-ab4b0aa3-5784-469b-bed4-f22f8a37ebc6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288678832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
2288678832
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.4161643649
Short name T417
Test name
Test status
Simulation time 1124396693 ps
CPU time 4.65 seconds
Started Jul 26 04:54:36 PM PDT 24
Finished Jul 26 04:54:40 PM PDT 24
Peak memory 233536 kb
Host smart-0f8a6a79-a244-491b-be54-9f4b675f5ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161643649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.4161643649
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.2380894726
Short name T327
Test name
Test status
Simulation time 41943005 ps
CPU time 0.77 seconds
Started Jul 26 04:54:36 PM PDT 24
Finished Jul 26 04:54:37 PM PDT 24
Peak memory 207116 kb
Host smart-36bab07f-5aeb-439e-9a3c-8093a5fca20d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380894726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.2380894726
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.502969065
Short name T488
Test name
Test status
Simulation time 40749316 ps
CPU time 0.8 seconds
Started Jul 26 04:54:31 PM PDT 24
Finished Jul 26 04:54:32 PM PDT 24
Peak memory 216772 kb
Host smart-2441e226-bca5-461e-82e3-7787ce148343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502969065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.502969065
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.294969594
Short name T934
Test name
Test status
Simulation time 11976965398 ps
CPU time 187.43 seconds
Started Jul 26 04:54:30 PM PDT 24
Finished Jul 26 04:57:37 PM PDT 24
Peak memory 262812 kb
Host smart-2e955cc0-72a1-4f4e-a416-49235f8cfe1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294969594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.294969594
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.4145011724
Short name T662
Test name
Test status
Simulation time 6023375315 ps
CPU time 76.72 seconds
Started Jul 26 04:54:31 PM PDT 24
Finished Jul 26 04:55:48 PM PDT 24
Peak memory 257840 kb
Host smart-2ae1d304-47b8-4ee3-af6b-31a3e5a36d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145011724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.4145011724
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.916212863
Short name T691
Test name
Test status
Simulation time 6086104027 ps
CPU time 21.57 seconds
Started Jul 26 04:54:33 PM PDT 24
Finished Jul 26 04:54:54 PM PDT 24
Peak memory 233604 kb
Host smart-ba16baf6-3173-4bda-9506-b489668617e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916212863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.916212863
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.805468664
Short name T569
Test name
Test status
Simulation time 98730653113 ps
CPU time 191.41 seconds
Started Jul 26 04:54:31 PM PDT 24
Finished Jul 26 04:57:43 PM PDT 24
Peak memory 258032 kb
Host smart-03a319d3-3fcd-4da9-8eee-067310c99351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805468664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmds
.805468664
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_intercept.3533736951
Short name T686
Test name
Test status
Simulation time 48881721 ps
CPU time 2.58 seconds
Started Jul 26 04:54:34 PM PDT 24
Finished Jul 26 04:54:37 PM PDT 24
Peak memory 233532 kb
Host smart-3803949d-1ba4-496b-bae3-7517fc087074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533736951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.3533736951
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.1125385947
Short name T475
Test name
Test status
Simulation time 1041704840 ps
CPU time 14.13 seconds
Started Jul 26 04:54:33 PM PDT 24
Finished Jul 26 04:54:48 PM PDT 24
Peak memory 225200 kb
Host smart-b1a17350-1ea5-43af-8a40-8d056d29a318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125385947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.1125385947
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.1216449497
Short name T209
Test name
Test status
Simulation time 1203106384 ps
CPU time 10.25 seconds
Started Jul 26 04:54:27 PM PDT 24
Finished Jul 26 04:54:38 PM PDT 24
Peak memory 233492 kb
Host smart-05196463-34e8-4f10-9ff3-f985bcda2b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216449497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.1216449497
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.270658856
Short name T471
Test name
Test status
Simulation time 17631254798 ps
CPU time 13.92 seconds
Started Jul 26 04:54:29 PM PDT 24
Finished Jul 26 04:54:43 PM PDT 24
Peak memory 240812 kb
Host smart-85c3edb8-d2f0-4585-80f8-0c012d1a2f4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270658856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.270658856
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.746324303
Short name T617
Test name
Test status
Simulation time 677131039 ps
CPU time 3.14 seconds
Started Jul 26 04:54:35 PM PDT 24
Finished Jul 26 04:54:38 PM PDT 24
Peak memory 220768 kb
Host smart-29491b5d-85e8-4356-a4ad-ccb54c02c383
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=746324303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dire
ct.746324303
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.2924445024
Short name T821
Test name
Test status
Simulation time 34484662391 ps
CPU time 82.92 seconds
Started Jul 26 04:54:35 PM PDT 24
Finished Jul 26 04:55:58 PM PDT 24
Peak memory 256444 kb
Host smart-0615a847-77a7-4f3a-b52e-7da23daedf6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924445024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.2924445024
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.1414079071
Short name T765
Test name
Test status
Simulation time 1605806830 ps
CPU time 6.34 seconds
Started Jul 26 04:54:29 PM PDT 24
Finished Jul 26 04:54:35 PM PDT 24
Peak memory 216976 kb
Host smart-77fd88f6-85fc-4f37-bc37-c2a51f821e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414079071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.1414079071
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.2376789802
Short name T439
Test name
Test status
Simulation time 1609720537 ps
CPU time 3.71 seconds
Started Jul 26 04:54:31 PM PDT 24
Finished Jul 26 04:54:35 PM PDT 24
Peak memory 216988 kb
Host smart-d162de7c-9a6f-42f5-a0bd-c83153f7b4e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376789802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.2376789802
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.758850931
Short name T820
Test name
Test status
Simulation time 334020552 ps
CPU time 1.55 seconds
Started Jul 26 04:54:31 PM PDT 24
Finished Jul 26 04:54:33 PM PDT 24
Peak memory 217044 kb
Host smart-868d7947-3c58-4ed3-a35d-a842436ce80c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758850931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.758850931
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.4143686035
Short name T81
Test name
Test status
Simulation time 17472188 ps
CPU time 0.74 seconds
Started Jul 26 04:54:32 PM PDT 24
Finished Jul 26 04:54:32 PM PDT 24
Peak memory 206616 kb
Host smart-95a28868-bd6b-4e8c-affa-ad009b106869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143686035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.4143686035
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.2291894493
Short name T918
Test name
Test status
Simulation time 1050958598 ps
CPU time 4.46 seconds
Started Jul 26 04:54:35 PM PDT 24
Finished Jul 26 04:54:39 PM PDT 24
Peak memory 219836 kb
Host smart-0ab8517e-b063-4dea-a963-e80d09eb2ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291894493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.2291894493
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.1963982769
Short name T826
Test name
Test status
Simulation time 35148511 ps
CPU time 0.75 seconds
Started Jul 26 04:54:53 PM PDT 24
Finished Jul 26 04:54:54 PM PDT 24
Peak memory 205300 kb
Host smart-f45e02ce-3f37-417c-8b04-e6fbeb77f6a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963982769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
1963982769
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.763191830
Short name T883
Test name
Test status
Simulation time 1220710679 ps
CPU time 4.72 seconds
Started Jul 26 04:54:43 PM PDT 24
Finished Jul 26 04:54:48 PM PDT 24
Peak memory 233476 kb
Host smart-92053ed7-e7d3-4b06-af9b-d9378836c15f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763191830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.763191830
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.3382643297
Short name T315
Test name
Test status
Simulation time 45527010 ps
CPU time 0.74 seconds
Started Jul 26 04:54:34 PM PDT 24
Finished Jul 26 04:54:35 PM PDT 24
Peak memory 207028 kb
Host smart-0cab1fa1-1fda-4c00-a222-fbece7b3000a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382643297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.3382643297
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.1359083169
Short name T868
Test name
Test status
Simulation time 11143238572 ps
CPU time 46.82 seconds
Started Jul 26 04:54:41 PM PDT 24
Finished Jul 26 04:55:28 PM PDT 24
Peak memory 250016 kb
Host smart-6022414b-3c27-4245-8cc5-69d111b542bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359083169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.1359083169
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.444522677
Short name T873
Test name
Test status
Simulation time 38481210086 ps
CPU time 57.95 seconds
Started Jul 26 04:54:45 PM PDT 24
Finished Jul 26 04:55:43 PM PDT 24
Peak memory 250004 kb
Host smart-609577fc-95ad-4525-ab7f-ada375920d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444522677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.444522677
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.2474011663
Short name T938
Test name
Test status
Simulation time 23778838592 ps
CPU time 91.7 seconds
Started Jul 26 04:54:39 PM PDT 24
Finished Jul 26 04:56:11 PM PDT 24
Peak memory 250704 kb
Host smart-42c0372f-a5eb-4dff-a688-156a482c2d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474011663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.2474011663
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.3431130085
Short name T796
Test name
Test status
Simulation time 4420823847 ps
CPU time 20.36 seconds
Started Jul 26 04:54:42 PM PDT 24
Finished Jul 26 04:55:02 PM PDT 24
Peak memory 241772 kb
Host smart-9e9ce5e5-3ce2-498f-86ae-d2e7441141a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431130085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.3431130085
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.1740275379
Short name T85
Test name
Test status
Simulation time 4826045219 ps
CPU time 55.97 seconds
Started Jul 26 04:54:41 PM PDT 24
Finished Jul 26 04:55:37 PM PDT 24
Peak memory 250044 kb
Host smart-b7db0ecc-06c2-446b-9559-81b510424099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740275379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmd
s.1740275379
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/48.spi_device_intercept.1710972374
Short name T88
Test name
Test status
Simulation time 302079670 ps
CPU time 4.39 seconds
Started Jul 26 04:54:43 PM PDT 24
Finished Jul 26 04:54:47 PM PDT 24
Peak memory 225380 kb
Host smart-bcc6e153-6075-45b4-ab51-2d63c2d4b3b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710972374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.1710972374
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.1503449303
Short name T360
Test name
Test status
Simulation time 169682420 ps
CPU time 2.14 seconds
Started Jul 26 04:54:46 PM PDT 24
Finished Jul 26 04:54:48 PM PDT 24
Peak memory 224956 kb
Host smart-c881cd5c-8f74-48c1-8c87-a9df0aa3575a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503449303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.1503449303
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.3360253788
Short name T757
Test name
Test status
Simulation time 2164946203 ps
CPU time 7.33 seconds
Started Jul 26 04:54:43 PM PDT 24
Finished Jul 26 04:54:50 PM PDT 24
Peak memory 233636 kb
Host smart-ee712131-120d-4383-be90-81958e3dcbdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360253788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.3360253788
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.3010204473
Short name T431
Test name
Test status
Simulation time 806710026 ps
CPU time 3.84 seconds
Started Jul 26 04:54:41 PM PDT 24
Finished Jul 26 04:54:45 PM PDT 24
Peak memory 233408 kb
Host smart-33ddb55a-dfb4-4f1a-9997-2aae0b71c8ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010204473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.3010204473
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.2594036608
Short name T1004
Test name
Test status
Simulation time 114416312 ps
CPU time 4.25 seconds
Started Jul 26 04:54:42 PM PDT 24
Finished Jul 26 04:54:46 PM PDT 24
Peak memory 223868 kb
Host smart-e619a7ed-7a87-4d06-a01a-810557052cbf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2594036608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.2594036608
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.519345700
Short name T281
Test name
Test status
Simulation time 10962493011 ps
CPU time 92.52 seconds
Started Jul 26 04:54:40 PM PDT 24
Finished Jul 26 04:56:13 PM PDT 24
Peak memory 233584 kb
Host smart-07da4d0b-8bf8-4e68-b4ad-1f29f17919e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519345700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stres
s_all.519345700
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.155943981
Short name T27
Test name
Test status
Simulation time 7239972715 ps
CPU time 28.98 seconds
Started Jul 26 04:54:36 PM PDT 24
Finished Jul 26 04:55:05 PM PDT 24
Peak memory 217084 kb
Host smart-3290651e-4df6-4038-a8ae-556154e954aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155943981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.155943981
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.2540832780
Short name T348
Test name
Test status
Simulation time 558949918 ps
CPU time 4.53 seconds
Started Jul 26 04:54:35 PM PDT 24
Finished Jul 26 04:54:39 PM PDT 24
Peak memory 217076 kb
Host smart-9f0d0ae5-4c41-4482-9554-fc22f2c8db15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540832780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.2540832780
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.1138761768
Short name T949
Test name
Test status
Simulation time 166146962 ps
CPU time 6.39 seconds
Started Jul 26 04:54:41 PM PDT 24
Finished Jul 26 04:54:47 PM PDT 24
Peak memory 217072 kb
Host smart-77895723-c223-4fca-84c6-64e982757b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138761768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.1138761768
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.1486233940
Short name T1024
Test name
Test status
Simulation time 34444272 ps
CPU time 0.77 seconds
Started Jul 26 04:54:40 PM PDT 24
Finished Jul 26 04:54:41 PM PDT 24
Peak memory 206608 kb
Host smart-a400d6b7-a76f-4346-a136-739f7c97c1ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486233940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.1486233940
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.3801876066
Short name T341
Test name
Test status
Simulation time 723129889 ps
CPU time 3.5 seconds
Started Jul 26 04:54:41 PM PDT 24
Finished Jul 26 04:54:45 PM PDT 24
Peak memory 233500 kb
Host smart-a6db30c4-cc87-4d98-b4c0-8e3bd534356b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801876066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.3801876066
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.3183218551
Short name T2
Test name
Test status
Simulation time 14295321 ps
CPU time 0.71 seconds
Started Jul 26 04:54:43 PM PDT 24
Finished Jul 26 04:54:44 PM PDT 24
Peak memory 205352 kb
Host smart-5b6da623-db28-42a2-a3ba-95729541c825
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183218551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
3183218551
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.2439513483
Short name T462
Test name
Test status
Simulation time 79208852 ps
CPU time 2.3 seconds
Started Jul 26 04:54:41 PM PDT 24
Finished Jul 26 04:54:44 PM PDT 24
Peak memory 224776 kb
Host smart-74734054-ea96-4d11-8582-db27d6b7644c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439513483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.2439513483
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.684870405
Short name T328
Test name
Test status
Simulation time 40410099 ps
CPU time 0.76 seconds
Started Jul 26 04:54:45 PM PDT 24
Finished Jul 26 04:54:46 PM PDT 24
Peak memory 207508 kb
Host smart-32bfb202-894f-4bec-a8df-849bc690d738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684870405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.684870405
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.2272809818
Short name T349
Test name
Test status
Simulation time 12704459 ps
CPU time 0.74 seconds
Started Jul 26 04:54:36 PM PDT 24
Finished Jul 26 04:54:37 PM PDT 24
Peak memory 216520 kb
Host smart-3b2fbaf9-daad-473e-86b6-906204e5539f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272809818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.2272809818
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.1355993777
Short name T499
Test name
Test status
Simulation time 7589719076 ps
CPU time 96.98 seconds
Started Jul 26 04:54:40 PM PDT 24
Finished Jul 26 04:56:17 PM PDT 24
Peak memory 268868 kb
Host smart-b39bfa9e-b660-4a64-bc6f-701a63b30d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355993777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.1355993777
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.3497288340
Short name T842
Test name
Test status
Simulation time 5676241421 ps
CPU time 40.81 seconds
Started Jul 26 04:54:41 PM PDT 24
Finished Jul 26 04:55:22 PM PDT 24
Peak memory 241756 kb
Host smart-209d038b-360b-45a9-9843-da1b617c2fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497288340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.3497288340
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.4085684887
Short name T524
Test name
Test status
Simulation time 5367055533 ps
CPU time 25.68 seconds
Started Jul 26 04:54:43 PM PDT 24
Finished Jul 26 04:55:08 PM PDT 24
Peak memory 225416 kb
Host smart-a1195fec-306c-423c-aa4c-10a8dd96664f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085684887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmd
s.4085684887
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/49.spi_device_intercept.3338907226
Short name T626
Test name
Test status
Simulation time 554410816 ps
CPU time 5.03 seconds
Started Jul 26 04:54:41 PM PDT 24
Finished Jul 26 04:54:47 PM PDT 24
Peak memory 225276 kb
Host smart-8195ac81-4371-4692-979c-566aab2c34bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338907226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.3338907226
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.3788528275
Short name T813
Test name
Test status
Simulation time 1593050757 ps
CPU time 11.2 seconds
Started Jul 26 04:54:46 PM PDT 24
Finished Jul 26 04:54:58 PM PDT 24
Peak memory 238412 kb
Host smart-465cc88e-226d-44b5-a63a-fd2fd8c4969d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788528275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.3788528275
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.1639850910
Short name T665
Test name
Test status
Simulation time 5840140557 ps
CPU time 18.84 seconds
Started Jul 26 04:54:40 PM PDT 24
Finished Jul 26 04:54:59 PM PDT 24
Peak memory 233588 kb
Host smart-100e7b9f-7e84-42fe-b8e9-ab34060bba1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639850910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.1639850910
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.3996659174
Short name T824
Test name
Test status
Simulation time 177361545 ps
CPU time 2.03 seconds
Started Jul 26 04:54:43 PM PDT 24
Finished Jul 26 04:54:45 PM PDT 24
Peak memory 225004 kb
Host smart-314919b5-9543-4c1a-882a-d2f168c7b424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996659174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.3996659174
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.3166525322
Short name T141
Test name
Test status
Simulation time 5030430878 ps
CPU time 8.11 seconds
Started Jul 26 04:54:48 PM PDT 24
Finished Jul 26 04:54:56 PM PDT 24
Peak memory 223284 kb
Host smart-b358a279-e04b-4b0b-90df-b9a3b947d947
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3166525322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.3166525322
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.2090637259
Short name T862
Test name
Test status
Simulation time 58248160 ps
CPU time 1.05 seconds
Started Jul 26 04:54:51 PM PDT 24
Finished Jul 26 04:54:53 PM PDT 24
Peak memory 208020 kb
Host smart-218a2ea5-acb2-4678-a641-7c816f5cb529
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090637259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.2090637259
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.1944247609
Short name T308
Test name
Test status
Simulation time 20099433079 ps
CPU time 50.53 seconds
Started Jul 26 04:54:41 PM PDT 24
Finished Jul 26 04:55:31 PM PDT 24
Peak memory 217160 kb
Host smart-74924b07-59db-48b9-b54a-c08ba8f59e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944247609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.1944247609
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.2098648543
Short name T425
Test name
Test status
Simulation time 982386682 ps
CPU time 1.23 seconds
Started Jul 26 04:54:42 PM PDT 24
Finished Jul 26 04:54:44 PM PDT 24
Peak memory 208692 kb
Host smart-4f00d993-faba-44b5-ab0a-e330cdc166a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098648543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.2098648543
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.1839532181
Short name T326
Test name
Test status
Simulation time 168904316 ps
CPU time 1.1 seconds
Started Jul 26 04:54:43 PM PDT 24
Finished Jul 26 04:54:44 PM PDT 24
Peak memory 208720 kb
Host smart-c335defd-fb9f-4289-ae29-300a444fd1be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839532181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.1839532181
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.102593481
Short name T810
Test name
Test status
Simulation time 116626035 ps
CPU time 0.79 seconds
Started Jul 26 04:54:41 PM PDT 24
Finished Jul 26 04:54:42 PM PDT 24
Peak memory 206672 kb
Host smart-1d20baf8-08d7-4f0b-9dd3-52a005c46ee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102593481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.102593481
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.174340179
Short name T605
Test name
Test status
Simulation time 6172242955 ps
CPU time 17.19 seconds
Started Jul 26 04:54:45 PM PDT 24
Finished Jul 26 04:55:02 PM PDT 24
Peak memory 233588 kb
Host smart-61ab93d8-8ebe-463d-adc4-2259de4f77b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174340179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.174340179
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.1763784733
Short name T510
Test name
Test status
Simulation time 15223870 ps
CPU time 0.72 seconds
Started Jul 26 04:52:21 PM PDT 24
Finished Jul 26 04:52:22 PM PDT 24
Peak memory 205880 kb
Host smart-c41daba9-d67f-46ae-bd0b-7350171a236b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763784733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.1
763784733
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.1388002448
Short name T848
Test name
Test status
Simulation time 101948149 ps
CPU time 2.32 seconds
Started Jul 26 04:52:24 PM PDT 24
Finished Jul 26 04:52:27 PM PDT 24
Peak memory 225288 kb
Host smart-45895ab6-e63a-4776-8b91-72d1425c7483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388002448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.1388002448
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.786381065
Short name T936
Test name
Test status
Simulation time 26579590 ps
CPU time 0.74 seconds
Started Jul 26 04:52:24 PM PDT 24
Finished Jul 26 04:52:25 PM PDT 24
Peak memory 207176 kb
Host smart-e8ba60f1-8a12-4d15-a3ec-f7a6e9d79433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786381065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.786381065
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.1511713498
Short name T212
Test name
Test status
Simulation time 48852082560 ps
CPU time 337.59 seconds
Started Jul 26 04:52:22 PM PDT 24
Finished Jul 26 04:57:59 PM PDT 24
Peak memory 251860 kb
Host smart-702d8496-e0be-486d-86b0-2f56fc1121ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511713498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.1511713498
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.3756910245
Short name T220
Test name
Test status
Simulation time 10980451217 ps
CPU time 161.48 seconds
Started Jul 26 04:52:22 PM PDT 24
Finished Jul 26 04:55:03 PM PDT 24
Peak memory 265180 kb
Host smart-9971cd4e-5a94-48e2-a685-388bfa454431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756910245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.3756910245
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.2156773760
Short name T734
Test name
Test status
Simulation time 1414897844 ps
CPU time 23.9 seconds
Started Jul 26 04:52:24 PM PDT 24
Finished Jul 26 04:52:48 PM PDT 24
Peak memory 225424 kb
Host smart-f5a55059-17a4-49f0-8e28-487b626c9f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156773760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.2156773760
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.4049044246
Short name T423
Test name
Test status
Simulation time 479222846 ps
CPU time 13.35 seconds
Started Jul 26 04:52:24 PM PDT 24
Finished Jul 26 04:52:37 PM PDT 24
Peak memory 249836 kb
Host smart-a06f89ce-1399-4cd3-be9e-8d9017fd5c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049044246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.4049044246
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.2478011097
Short name T800
Test name
Test status
Simulation time 2696351805 ps
CPU time 25.08 seconds
Started Jul 26 04:52:28 PM PDT 24
Finished Jul 26 04:52:53 PM PDT 24
Peak memory 237924 kb
Host smart-b0c31aeb-8587-4214-bb2b-4d6bef3937e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478011097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds
.2478011097
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/5.spi_device_intercept.868200062
Short name T889
Test name
Test status
Simulation time 760851124 ps
CPU time 7.98 seconds
Started Jul 26 04:52:22 PM PDT 24
Finished Jul 26 04:52:30 PM PDT 24
Peak memory 233616 kb
Host smart-08529582-6a88-4bee-a896-58b1a7a3115d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868200062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.868200062
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.3418420803
Short name T45
Test name
Test status
Simulation time 3770006808 ps
CPU time 20.42 seconds
Started Jul 26 04:52:21 PM PDT 24
Finished Jul 26 04:52:41 PM PDT 24
Peak memory 239280 kb
Host smart-14886d20-d926-4e27-9680-f7febf774510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418420803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.3418420803
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.3713850983
Short name T346
Test name
Test status
Simulation time 27546253 ps
CPU time 1.03 seconds
Started Jul 26 04:52:15 PM PDT 24
Finished Jul 26 04:52:16 PM PDT 24
Peak memory 218712 kb
Host smart-09ebeb27-b7b3-43e8-8a92-fefeb4da079a
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713850983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.spi_device_mem_parity.3713850983
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.3516094778
Short name T258
Test name
Test status
Simulation time 100690862 ps
CPU time 2.32 seconds
Started Jul 26 04:52:16 PM PDT 24
Finished Jul 26 04:52:18 PM PDT 24
Peak memory 225392 kb
Host smart-3de95cc4-3c9d-4ebe-8d70-152d134984c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516094778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.3516094778
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.4044029360
Short name T207
Test name
Test status
Simulation time 1119131623 ps
CPU time 6.91 seconds
Started Jul 26 04:52:15 PM PDT 24
Finished Jul 26 04:52:22 PM PDT 24
Peak memory 233440 kb
Host smart-28470e7d-a35c-4e84-adbf-4eb34d1493dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044029360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.4044029360
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.4135737065
Short name T86
Test name
Test status
Simulation time 559019681 ps
CPU time 5.85 seconds
Started Jul 26 04:52:23 PM PDT 24
Finished Jul 26 04:52:29 PM PDT 24
Peak memory 219644 kb
Host smart-96b811cf-613c-4531-9570-aaff0d0c54f0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4135737065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.4135737065
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.2232133851
Short name T154
Test name
Test status
Simulation time 177039848 ps
CPU time 1 seconds
Started Jul 26 04:52:27 PM PDT 24
Finished Jul 26 04:52:28 PM PDT 24
Peak memory 207384 kb
Host smart-62fd9174-b050-442f-ab66-68e3a8bdbaa0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232133851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.2232133851
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.4248909492
Short name T305
Test name
Test status
Simulation time 1633814889 ps
CPU time 5.16 seconds
Started Jul 26 04:52:17 PM PDT 24
Finished Jul 26 04:52:22 PM PDT 24
Peak memory 217024 kb
Host smart-41e9cd44-0398-4578-b276-4b0ba29191ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248909492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.4248909492
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.1190600588
Short name T669
Test name
Test status
Simulation time 54475738225 ps
CPU time 17.63 seconds
Started Jul 26 04:52:11 PM PDT 24
Finished Jul 26 04:52:29 PM PDT 24
Peak memory 218192 kb
Host smart-e91ae96f-9c78-4172-aa2b-bfdaa8be296f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190600588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.1190600588
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.3603295773
Short name T852
Test name
Test status
Simulation time 14271515 ps
CPU time 0.69 seconds
Started Jul 26 04:52:14 PM PDT 24
Finished Jul 26 04:52:15 PM PDT 24
Peak memory 206148 kb
Host smart-f0a4a8bd-0a2e-4cb4-85a2-dc4cabf79d9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603295773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.3603295773
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.189067908
Short name T445
Test name
Test status
Simulation time 511678372 ps
CPU time 0.77 seconds
Started Jul 26 04:52:23 PM PDT 24
Finished Jul 26 04:52:24 PM PDT 24
Peak memory 206616 kb
Host smart-3566ab2d-a7fd-445d-86e1-2ce932339579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189067908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.189067908
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.3738632574
Short name T536
Test name
Test status
Simulation time 984882890 ps
CPU time 5.05 seconds
Started Jul 26 04:52:24 PM PDT 24
Finished Jul 26 04:52:29 PM PDT 24
Peak memory 233532 kb
Host smart-b35ca1f0-6262-4cf8-9044-1d6ffc637830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738632574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.3738632574
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.593594736
Short name T904
Test name
Test status
Simulation time 46708294 ps
CPU time 0.77 seconds
Started Jul 26 04:52:26 PM PDT 24
Finished Jul 26 04:52:27 PM PDT 24
Peak memory 205380 kb
Host smart-68393c38-314f-4e7a-a422-b61b8c901ea2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593594736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.593594736
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.3782223069
Short name T858
Test name
Test status
Simulation time 305172969 ps
CPU time 3.23 seconds
Started Jul 26 04:52:24 PM PDT 24
Finished Jul 26 04:52:27 PM PDT 24
Peak memory 233468 kb
Host smart-a0ecc465-4403-407a-961d-9bdca460937b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782223069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.3782223069
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.1698087123
Short name T338
Test name
Test status
Simulation time 23294191 ps
CPU time 0.79 seconds
Started Jul 26 04:52:24 PM PDT 24
Finished Jul 26 04:52:25 PM PDT 24
Peak memory 207100 kb
Host smart-ceb0a477-70c7-42a4-90b8-02dbab7c178d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698087123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.1698087123
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.1943229102
Short name T291
Test name
Test status
Simulation time 14732202352 ps
CPU time 119.39 seconds
Started Jul 26 04:52:24 PM PDT 24
Finished Jul 26 04:54:23 PM PDT 24
Peak memory 250068 kb
Host smart-a17e51bd-55a6-4bb7-8571-a232a20471fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943229102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.1943229102
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.1614118689
Short name T574
Test name
Test status
Simulation time 104042282254 ps
CPU time 259.3 seconds
Started Jul 26 04:52:22 PM PDT 24
Finished Jul 26 04:56:41 PM PDT 24
Peak memory 265752 kb
Host smart-4e0082b8-e4a7-4a84-bf8f-b6e6b8efd713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614118689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.1614118689
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.4041473851
Short name T299
Test name
Test status
Simulation time 1152132450 ps
CPU time 23.24 seconds
Started Jul 26 04:52:22 PM PDT 24
Finished Jul 26 04:52:45 PM PDT 24
Peak memory 240528 kb
Host smart-974aeb5b-8cd8-4b4c-aeb9-654ad5dc43a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041473851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.4041473851
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.1527667728
Short name T733
Test name
Test status
Simulation time 2509878735 ps
CPU time 27.79 seconds
Started Jul 26 04:52:23 PM PDT 24
Finished Jul 26 04:52:51 PM PDT 24
Peak memory 251064 kb
Host smart-960a4ef8-f973-4bca-8a0a-a3743ff27c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527667728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds
.1527667728
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/6.spi_device_intercept.1990329440
Short name T1015
Test name
Test status
Simulation time 276781101 ps
CPU time 3.73 seconds
Started Jul 26 04:52:21 PM PDT 24
Finished Jul 26 04:52:24 PM PDT 24
Peak memory 233532 kb
Host smart-d39ce8a5-7dbd-459f-a8b4-d122bb1ecce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990329440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.1990329440
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.3122775905
Short name T954
Test name
Test status
Simulation time 254440516 ps
CPU time 3.01 seconds
Started Jul 26 04:52:23 PM PDT 24
Finished Jul 26 04:52:26 PM PDT 24
Peak memory 225352 kb
Host smart-29d147d6-1636-4aff-8fd5-4636f844b620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122775905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.3122775905
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.651293372
Short name T630
Test name
Test status
Simulation time 32049237 ps
CPU time 1.05 seconds
Started Jul 26 04:52:21 PM PDT 24
Finished Jul 26 04:52:22 PM PDT 24
Peak memory 217252 kb
Host smart-1eaab3ba-3a6b-4dbd-a44b-dbf6e27b5ae8
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651293372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.spi_device_mem_parity.651293372
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.1973896163
Short name T840
Test name
Test status
Simulation time 5426089097 ps
CPU time 14.28 seconds
Started Jul 26 04:52:26 PM PDT 24
Finished Jul 26 04:52:40 PM PDT 24
Peak memory 225452 kb
Host smart-c489f0c2-3d78-43fc-962b-9349c19e0ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973896163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.1973896163
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.124503510
Short name T329
Test name
Test status
Simulation time 9723060955 ps
CPU time 15.77 seconds
Started Jul 26 04:52:22 PM PDT 24
Finished Jul 26 04:52:38 PM PDT 24
Peak memory 225352 kb
Host smart-e6e8fb7a-8f1c-43d9-b3f2-9648ea8f2ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124503510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.124503510
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.3623705449
Short name T344
Test name
Test status
Simulation time 4677423304 ps
CPU time 6.64 seconds
Started Jul 26 04:52:25 PM PDT 24
Finished Jul 26 04:52:32 PM PDT 24
Peak memory 220176 kb
Host smart-866fd074-bc52-49d3-8196-512209fb3938
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3623705449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.3623705449
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.1517081952
Short name T197
Test name
Test status
Simulation time 21373730590 ps
CPU time 212.14 seconds
Started Jul 26 04:52:22 PM PDT 24
Finished Jul 26 04:55:54 PM PDT 24
Peak memory 256776 kb
Host smart-3b89e3e5-aef8-4bdf-b8a3-e9903c159dd9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517081952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.1517081952
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.3633352807
Short name T13
Test name
Test status
Simulation time 1121600472 ps
CPU time 2.47 seconds
Started Jul 26 04:52:22 PM PDT 24
Finished Jul 26 04:52:25 PM PDT 24
Peak memory 216928 kb
Host smart-bed9fe22-c530-46ea-b67d-eea2eaef51d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633352807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.3633352807
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.1945620586
Short name T337
Test name
Test status
Simulation time 3144125628 ps
CPU time 7.89 seconds
Started Jul 26 04:52:24 PM PDT 24
Finished Jul 26 04:52:32 PM PDT 24
Peak memory 217128 kb
Host smart-f65c9f4a-77f0-4f79-bc14-a15327969275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945620586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.1945620586
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.2923745591
Short name T595
Test name
Test status
Simulation time 12359118 ps
CPU time 0.68 seconds
Started Jul 26 04:52:24 PM PDT 24
Finished Jul 26 04:52:25 PM PDT 24
Peak memory 206120 kb
Host smart-5ab8c335-7a79-4cfe-82aa-582a3d12dd4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923745591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.2923745591
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.2838221943
Short name T448
Test name
Test status
Simulation time 175503283 ps
CPU time 0.91 seconds
Started Jul 26 04:52:24 PM PDT 24
Finished Jul 26 04:52:25 PM PDT 24
Peak memory 207660 kb
Host smart-9216b5c0-ca2b-4d0f-80c7-eb99ee9d8280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838221943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.2838221943
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.1343031520
Short name T241
Test name
Test status
Simulation time 8705383771 ps
CPU time 17.78 seconds
Started Jul 26 04:52:23 PM PDT 24
Finished Jul 26 04:52:41 PM PDT 24
Peak memory 237172 kb
Host smart-9399004f-35d1-45b9-8aab-3e614633931f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343031520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.1343031520
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.1672658265
Short name T618
Test name
Test status
Simulation time 36877276 ps
CPU time 0.7 seconds
Started Jul 26 04:52:33 PM PDT 24
Finished Jul 26 04:52:34 PM PDT 24
Peak memory 205872 kb
Host smart-5fb4ea62-ad5b-4a39-985c-2e74b2fd1410
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672658265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.1
672658265
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.2234279834
Short name T878
Test name
Test status
Simulation time 34971658 ps
CPU time 2.13 seconds
Started Jul 26 04:52:23 PM PDT 24
Finished Jul 26 04:52:26 PM PDT 24
Peak memory 233464 kb
Host smart-f6d5c332-af69-426a-ad03-80395208612a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234279834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.2234279834
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.1846739046
Short name T782
Test name
Test status
Simulation time 18877348 ps
CPU time 0.84 seconds
Started Jul 26 04:52:23 PM PDT 24
Finished Jul 26 04:52:24 PM PDT 24
Peak memory 207156 kb
Host smart-878ecd6c-a6bb-4d5e-b16d-1d6dfd8ee5e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846739046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.1846739046
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.2075975094
Short name T677
Test name
Test status
Simulation time 203293339 ps
CPU time 0.85 seconds
Started Jul 26 04:52:32 PM PDT 24
Finished Jul 26 04:52:34 PM PDT 24
Peak memory 216736 kb
Host smart-32ae30ce-4309-479f-ac1b-83845e2c0f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075975094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.2075975094
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.3601026938
Short name T189
Test name
Test status
Simulation time 11550189780 ps
CPU time 146.32 seconds
Started Jul 26 04:52:34 PM PDT 24
Finished Jul 26 04:55:00 PM PDT 24
Peak memory 258184 kb
Host smart-637e0fd3-8a82-4d9f-b11d-2f61dd250663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601026938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.3601026938
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.1166492471
Short name T670
Test name
Test status
Simulation time 13437781105 ps
CPU time 39.3 seconds
Started Jul 26 04:52:34 PM PDT 24
Finished Jul 26 04:53:14 PM PDT 24
Peak memory 225484 kb
Host smart-909db1a6-d878-4a9f-8d4c-f36434b710b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166492471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.1166492471
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.3966073269
Short name T740
Test name
Test status
Simulation time 376323040 ps
CPU time 9.14 seconds
Started Jul 26 04:52:22 PM PDT 24
Finished Jul 26 04:52:31 PM PDT 24
Peak memory 233736 kb
Host smart-3affa0a8-96ee-4f51-abe3-03d0ad80ce2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966073269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.3966073269
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.4018061090
Short name T252
Test name
Test status
Simulation time 8026195469 ps
CPU time 35.82 seconds
Started Jul 26 04:52:32 PM PDT 24
Finished Jul 26 04:53:08 PM PDT 24
Peak memory 249944 kb
Host smart-2163a0b8-4edd-4310-9833-8c1285017acd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018061090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds
.4018061090
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_intercept.2501401521
Short name T501
Test name
Test status
Simulation time 1148758056 ps
CPU time 13.99 seconds
Started Jul 26 04:52:25 PM PDT 24
Finished Jul 26 04:52:40 PM PDT 24
Peak memory 233520 kb
Host smart-37b0ec37-eeca-49f6-81c7-278cb8c093c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501401521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.2501401521
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.1155388211
Short name T395
Test name
Test status
Simulation time 424413965 ps
CPU time 2.7 seconds
Started Jul 26 04:52:24 PM PDT 24
Finished Jul 26 04:52:27 PM PDT 24
Peak memory 225392 kb
Host smart-ab8dbea4-6bdf-4330-b5bc-8902f4a5785a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155388211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.1155388211
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.227295864
Short name T729
Test name
Test status
Simulation time 91853947 ps
CPU time 1.09 seconds
Started Jul 26 04:52:23 PM PDT 24
Finished Jul 26 04:52:24 PM PDT 24
Peak memory 217292 kb
Host smart-bf156123-59b8-4a44-ba05-895bab55bf1c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227295864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.spi_device_mem_parity.227295864
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.3834432818
Short name T671
Test name
Test status
Simulation time 22159716259 ps
CPU time 15.49 seconds
Started Jul 26 04:52:24 PM PDT 24
Finished Jul 26 04:52:40 PM PDT 24
Peak memory 241256 kb
Host smart-f53552ff-3b79-4469-a3ed-4a6d467113bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834432818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.3834432818
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.3528295791
Short name T239
Test name
Test status
Simulation time 58896286444 ps
CPU time 10.62 seconds
Started Jul 26 04:52:25 PM PDT 24
Finished Jul 26 04:52:35 PM PDT 24
Peak memory 225412 kb
Host smart-66036400-fec3-4b71-88b4-e97edcfa3e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528295791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.3528295791
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.1937143673
Short name T39
Test name
Test status
Simulation time 4123154283 ps
CPU time 9.12 seconds
Started Jul 26 04:52:32 PM PDT 24
Finished Jul 26 04:52:42 PM PDT 24
Peak memory 222316 kb
Host smart-18d8a50d-f2a4-46df-8dd1-ff0d64c106d9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1937143673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.1937143673
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.3567103682
Short name T557
Test name
Test status
Simulation time 84969746 ps
CPU time 1 seconds
Started Jul 26 04:52:36 PM PDT 24
Finished Jul 26 04:52:37 PM PDT 24
Peak memory 207664 kb
Host smart-9233337a-a3b8-4750-a141-f135fe9b99dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567103682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.3567103682
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.270897771
Short name T375
Test name
Test status
Simulation time 36947890138 ps
CPU time 16.31 seconds
Started Jul 26 04:52:22 PM PDT 24
Finished Jul 26 04:52:38 PM PDT 24
Peak memory 221452 kb
Host smart-db74b093-a5f4-4d99-8283-3c2961b5e263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270897771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.270897771
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.1514263930
Short name T78
Test name
Test status
Simulation time 7887142184 ps
CPU time 11.15 seconds
Started Jul 26 04:52:20 PM PDT 24
Finished Jul 26 04:52:32 PM PDT 24
Peak memory 217060 kb
Host smart-be6830c9-c317-4cb8-affa-bb5f0fd1c289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514263930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.1514263930
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.372967614
Short name T694
Test name
Test status
Simulation time 586492106 ps
CPU time 2.8 seconds
Started Jul 26 04:52:26 PM PDT 24
Finished Jul 26 04:52:29 PM PDT 24
Peak memory 217044 kb
Host smart-90e8515b-1ef1-40d1-81e7-3dcd1de8ce76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372967614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.372967614
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.3939897632
Short name T350
Test name
Test status
Simulation time 54807699 ps
CPU time 0.83 seconds
Started Jul 26 04:52:26 PM PDT 24
Finished Jul 26 04:52:27 PM PDT 24
Peak memory 206692 kb
Host smart-39bec40a-e727-4a58-b8d8-2f5262a6ce13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939897632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.3939897632
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.58338609
Short name T244
Test name
Test status
Simulation time 2067748515 ps
CPU time 9.24 seconds
Started Jul 26 04:52:23 PM PDT 24
Finished Jul 26 04:52:32 PM PDT 24
Peak memory 233508 kb
Host smart-4c0e0575-f72f-4605-b657-3618fb8daf65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58338609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.58338609
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.4037674473
Short name T453
Test name
Test status
Simulation time 28596329 ps
CPU time 0.67 seconds
Started Jul 26 04:52:32 PM PDT 24
Finished Jul 26 04:52:33 PM PDT 24
Peak memory 206288 kb
Host smart-1b967310-fdd0-4ed2-8614-0b2354eb879f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037674473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.4
037674473
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.2978107439
Short name T551
Test name
Test status
Simulation time 430650687 ps
CPU time 5.85 seconds
Started Jul 26 04:52:34 PM PDT 24
Finished Jul 26 04:52:40 PM PDT 24
Peak memory 225260 kb
Host smart-884e2f04-6896-4e28-8d77-4466a5b70e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978107439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.2978107439
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.1831926435
Short name T1016
Test name
Test status
Simulation time 16584938 ps
CPU time 0.8 seconds
Started Jul 26 04:52:31 PM PDT 24
Finished Jul 26 04:52:32 PM PDT 24
Peak memory 207084 kb
Host smart-51754c26-d014-4263-835e-8f6f9a46e441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831926435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.1831926435
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.1870531642
Short name T36
Test name
Test status
Simulation time 42458249876 ps
CPU time 46.61 seconds
Started Jul 26 04:52:34 PM PDT 24
Finished Jul 26 04:53:21 PM PDT 24
Peak memory 252264 kb
Host smart-d876f035-6281-41ea-bde0-bf81d78be2c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870531642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.1870531642
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.2042928343
Short name T74
Test name
Test status
Simulation time 5179846971 ps
CPU time 106.05 seconds
Started Jul 26 04:52:32 PM PDT 24
Finished Jul 26 04:54:18 PM PDT 24
Peak memory 260052 kb
Host smart-9e34d92b-3913-4512-9f05-ff55064666c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042928343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.2042928343
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.3862073186
Short name T830
Test name
Test status
Simulation time 4409930361 ps
CPU time 58.23 seconds
Started Jul 26 04:52:33 PM PDT 24
Finished Jul 26 04:53:31 PM PDT 24
Peak memory 251864 kb
Host smart-da38cc8b-e0bd-4bd8-a6b0-3fa4aa775f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862073186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.3862073186
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.1807916344
Short name T1011
Test name
Test status
Simulation time 538903987 ps
CPU time 10.4 seconds
Started Jul 26 04:52:36 PM PDT 24
Finished Jul 26 04:52:47 PM PDT 24
Peak memory 233516 kb
Host smart-d245d77b-2878-4dc5-839d-c24f390bf0a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807916344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.1807916344
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.1898012588
Short name T731
Test name
Test status
Simulation time 1326127774 ps
CPU time 6.81 seconds
Started Jul 26 04:52:31 PM PDT 24
Finished Jul 26 04:52:38 PM PDT 24
Peak memory 235700 kb
Host smart-36ed2b79-56f9-478b-8639-039b6fb682e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898012588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds
.1898012588
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/8.spi_device_intercept.1659059667
Short name T321
Test name
Test status
Simulation time 486788801 ps
CPU time 6.61 seconds
Started Jul 26 04:52:31 PM PDT 24
Finished Jul 26 04:52:38 PM PDT 24
Peak memory 225268 kb
Host smart-b0e93338-e2b1-4f5c-8340-4d16b8e546d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659059667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.1659059667
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.3481181486
Short name T637
Test name
Test status
Simulation time 8494000043 ps
CPU time 34.11 seconds
Started Jul 26 04:52:33 PM PDT 24
Finished Jul 26 04:53:07 PM PDT 24
Peak memory 241488 kb
Host smart-89deab98-68dc-4de6-ae15-e49b9f418f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481181486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.3481181486
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.42559659
Short name T33
Test name
Test status
Simulation time 15318519 ps
CPU time 1.04 seconds
Started Jul 26 04:52:33 PM PDT 24
Finished Jul 26 04:52:35 PM PDT 24
Peak memory 217272 kb
Host smart-13b4875c-6398-45af-b746-596b3d95c4dc
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42559659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TES
T_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.spi_device_mem_parity.42559659
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.1856658878
Short name T516
Test name
Test status
Simulation time 322405382 ps
CPU time 2.61 seconds
Started Jul 26 04:52:33 PM PDT 24
Finished Jul 26 04:52:36 PM PDT 24
Peak memory 233424 kb
Host smart-202aea03-a04f-4a22-98e5-d2c6a483f2bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856658878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.1856658878
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.1330209549
Short name T762
Test name
Test status
Simulation time 303838099 ps
CPU time 3.89 seconds
Started Jul 26 04:52:32 PM PDT 24
Finished Jul 26 04:52:36 PM PDT 24
Peak memory 225192 kb
Host smart-9e108375-0cc4-4393-9c05-9e6fc2db47cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330209549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.1330209549
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.2861885720
Short name T849
Test name
Test status
Simulation time 223941857 ps
CPU time 4.26 seconds
Started Jul 26 04:52:34 PM PDT 24
Finished Jul 26 04:52:38 PM PDT 24
Peak memory 224084 kb
Host smart-0dc32a34-3e58-469a-845b-9b745baeecd0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2861885720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.2861885720
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.3480503463
Short name T390
Test name
Test status
Simulation time 196754017 ps
CPU time 1.13 seconds
Started Jul 26 04:53:40 PM PDT 24
Finished Jul 26 04:53:42 PM PDT 24
Peak memory 205388 kb
Host smart-54229a03-da71-4ce3-9799-1ccf22fbb924
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480503463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.3480503463
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.559732811
Short name T562
Test name
Test status
Simulation time 7361083805 ps
CPU time 38.95 seconds
Started Jul 26 04:52:32 PM PDT 24
Finished Jul 26 04:53:11 PM PDT 24
Peak memory 217436 kb
Host smart-db829b77-954f-4124-8b78-400837e9495e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559732811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.559732811
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.3272739142
Short name T437
Test name
Test status
Simulation time 11567415468 ps
CPU time 15.15 seconds
Started Jul 26 04:52:33 PM PDT 24
Finished Jul 26 04:52:48 PM PDT 24
Peak memory 217092 kb
Host smart-ad2f26e5-1eb9-45c1-a150-505388c85233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272739142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.3272739142
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.53324640
Short name T725
Test name
Test status
Simulation time 263341281 ps
CPU time 3.32 seconds
Started Jul 26 04:52:33 PM PDT 24
Finished Jul 26 04:52:37 PM PDT 24
Peak memory 217012 kb
Host smart-e8960d39-ab8e-4db0-bdd9-111770f18f57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53324640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.53324640
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.3320899656
Short name T886
Test name
Test status
Simulation time 79856135 ps
CPU time 0.87 seconds
Started Jul 26 04:52:32 PM PDT 24
Finished Jul 26 04:52:33 PM PDT 24
Peak memory 207720 kb
Host smart-604d82c8-5bc9-401b-9a1b-ea2aa34b2217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320899656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.3320899656
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.610873467
Short name T624
Test name
Test status
Simulation time 72893675259 ps
CPU time 29.38 seconds
Started Jul 26 04:52:32 PM PDT 24
Finished Jul 26 04:53:02 PM PDT 24
Peak memory 233532 kb
Host smart-5e4c9452-babe-4bf3-b734-94df256ed711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610873467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.610873467
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.3449332388
Short name T1027
Test name
Test status
Simulation time 48398653 ps
CPU time 0.69 seconds
Started Jul 26 04:52:31 PM PDT 24
Finished Jul 26 04:52:32 PM PDT 24
Peak memory 205296 kb
Host smart-4fed8fea-7084-4c3d-b9ea-9fa217487855
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449332388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.3
449332388
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.1787500652
Short name T345
Test name
Test status
Simulation time 32018854 ps
CPU time 2.2 seconds
Started Jul 26 04:53:40 PM PDT 24
Finished Jul 26 04:53:43 PM PDT 24
Peak memory 231104 kb
Host smart-087cf4ae-d7c2-4cea-b2d8-1f226e69d793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787500652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.1787500652
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.2537455061
Short name T939
Test name
Test status
Simulation time 19033011 ps
CPU time 0.78 seconds
Started Jul 26 04:52:32 PM PDT 24
Finished Jul 26 04:52:33 PM PDT 24
Peak memory 207436 kb
Host smart-4d7fa00c-9937-423c-9eb6-880cd2e8a423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537455061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.2537455061
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.1045708118
Short name T9
Test name
Test status
Simulation time 4386087061 ps
CPU time 24.96 seconds
Started Jul 26 04:52:35 PM PDT 24
Finished Jul 26 04:53:00 PM PDT 24
Peak memory 249980 kb
Host smart-9fbda2b8-1060-4e33-b7be-4d94973472b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045708118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.1045708118
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.1627920773
Short name T951
Test name
Test status
Simulation time 2115131253 ps
CPU time 20.95 seconds
Started Jul 26 04:53:40 PM PDT 24
Finished Jul 26 04:54:02 PM PDT 24
Peak memory 236648 kb
Host smart-dede044f-ed12-42b5-839f-a72a9cec1eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627920773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.1627920773
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.3282536901
Short name T435
Test name
Test status
Simulation time 1094734212 ps
CPU time 7.33 seconds
Started Jul 26 04:52:33 PM PDT 24
Finished Jul 26 04:52:41 PM PDT 24
Peak memory 233468 kb
Host smart-71aeb0a3-d822-4ff1-9c09-bc8f0d50dbde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282536901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.3282536901
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.337980228
Short name T747
Test name
Test status
Simulation time 620965711 ps
CPU time 7.09 seconds
Started Jul 26 04:52:33 PM PDT 24
Finished Jul 26 04:52:40 PM PDT 24
Peak memory 249920 kb
Host smart-eb619399-d5bd-4a9f-97ff-cabe5c9493af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337980228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds.
337980228
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_intercept.1946622433
Short name T234
Test name
Test status
Simulation time 651592154 ps
CPU time 9.24 seconds
Started Jul 26 04:53:41 PM PDT 24
Finished Jul 26 04:53:50 PM PDT 24
Peak memory 224692 kb
Host smart-dab3035c-55db-4eb2-aff0-48cf75239e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946622433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.1946622433
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.1903309021
Short name T772
Test name
Test status
Simulation time 24806193729 ps
CPU time 42.28 seconds
Started Jul 26 04:53:40 PM PDT 24
Finished Jul 26 04:54:23 PM PDT 24
Peak memory 237944 kb
Host smart-023135d7-d1de-4bba-94bb-ac19ac2075e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903309021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.1903309021
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.235960170
Short name T371
Test name
Test status
Simulation time 119824612 ps
CPU time 1.02 seconds
Started Jul 26 04:53:40 PM PDT 24
Finished Jul 26 04:53:42 PM PDT 24
Peak memory 215224 kb
Host smart-e1d1abdb-f848-4ac3-8f89-5a7529c12637
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235960170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.spi_device_mem_parity.235960170
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.2280653926
Short name T1001
Test name
Test status
Simulation time 23939581563 ps
CPU time 10.46 seconds
Started Jul 26 04:52:34 PM PDT 24
Finished Jul 26 04:52:45 PM PDT 24
Peak memory 225320 kb
Host smart-39eed538-4c21-44e3-a903-5864b94ba848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280653926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.2280653926
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.1292271309
Short name T865
Test name
Test status
Simulation time 687352157 ps
CPU time 4.13 seconds
Started Jul 26 04:52:32 PM PDT 24
Finished Jul 26 04:52:37 PM PDT 24
Peak memory 225300 kb
Host smart-154c5af4-4194-443a-afcd-15a38efaff96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292271309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.1292271309
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.4131924731
Short name T678
Test name
Test status
Simulation time 572637448 ps
CPU time 4.49 seconds
Started Jul 26 04:52:32 PM PDT 24
Finished Jul 26 04:52:37 PM PDT 24
Peak memory 223664 kb
Host smart-42d8e500-d323-4c26-8386-2c4b95fd52aa
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4131924731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.4131924731
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.887896406
Short name T47
Test name
Test status
Simulation time 9599215039 ps
CPU time 84.43 seconds
Started Jul 26 04:52:33 PM PDT 24
Finished Jul 26 04:53:58 PM PDT 24
Peak memory 257048 kb
Host smart-0183fce9-18a9-4fe4-8148-823db505fdd1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887896406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stress
_all.887896406
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.3764778660
Short name T1012
Test name
Test status
Simulation time 9894381732 ps
CPU time 30.28 seconds
Started Jul 26 04:52:34 PM PDT 24
Finished Jul 26 04:53:04 PM PDT 24
Peak memory 220988 kb
Host smart-98b8de8c-b287-4105-98de-5413f652f63c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764778660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.3764778660
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.1652736704
Short name T986
Test name
Test status
Simulation time 2764986252 ps
CPU time 3.38 seconds
Started Jul 26 04:52:33 PM PDT 24
Finished Jul 26 04:52:37 PM PDT 24
Peak memory 217140 kb
Host smart-a900caa3-c513-4418-bc2a-1b34a3d7eebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652736704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.1652736704
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.3775628078
Short name T571
Test name
Test status
Simulation time 16930063 ps
CPU time 0.77 seconds
Started Jul 26 04:52:32 PM PDT 24
Finished Jul 26 04:52:33 PM PDT 24
Peak memory 206604 kb
Host smart-6c14cbda-4625-4c2b-ac49-32a8e265da53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775628078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.3775628078
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.4005792007
Short name T690
Test name
Test status
Simulation time 105196747 ps
CPU time 0.73 seconds
Started Jul 26 04:52:33 PM PDT 24
Finished Jul 26 04:52:34 PM PDT 24
Peak memory 206600 kb
Host smart-89e34027-fd70-492a-82fd-3c8bf944318d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005792007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.4005792007
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.302029610
Short name T741
Test name
Test status
Simulation time 726982044 ps
CPU time 2.5 seconds
Started Jul 26 04:52:33 PM PDT 24
Finished Jul 26 04:52:35 PM PDT 24
Peak memory 233448 kb
Host smart-d3127f6b-401b-4df8-96d4-2637181e2055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302029610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.302029610
Directory /workspace/9.spi_device_upload/latest
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