Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2402820	1			T1	18371		T2	23		T3	1
all_values[1]	2402820	1			T1	18371		T2	23		T3	1
all_values[2]	2402820	1			T1	18371		T2	23		T3	1
all_values[3]	2402820	1			T1	18371		T2	23		T3	1
all_values[4]	2402820	1			T1	18371		T2	23		T3	1
all_values[5]	2402820	1			T1	18371		T2	23		T3	1
all_values[6]	2402820	1			T1	18371		T2	23		T3	1
all_values[7]	2402820	1			T1	18371		T2	23		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18900208

1

T1

146968

T2

184

T3

8

auto[1]

322352

1

T17

32

T18

33

T19

60

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19196812

1

T1

146916

T2

184

T3

8

auto[1]

25748

1

T1

52

T13

39

T32

18

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2388368	1			T1	18339		T2	23		T3	1
all_values[0]	auto[0]	auto[1]	12324	1			T1	32		T13	25		T32	6
all_values[0]	auto[1]	auto[0]	1911	1			T17	5		T18	1		T19	2
all_values[0]	auto[1]	auto[1]	217	1			T17	2		T18	1		T19	6
all_values[1]	auto[0]	auto[0]	2327800	1			T1	18359		T2	23		T3	1
all_values[1]	auto[0]	auto[1]	7691	1			T1	12		T13	11		T32	6
all_values[1]	auto[1]	auto[0]	66650	1			T18	2		T19	5		T20	7
all_values[1]	auto[1]	auto[1]	679	1			T18	3		T19	4		T20	9
all_values[2]	auto[0]	auto[0]	2396202	1			T1	18363		T2	23		T3	1
all_values[2]	auto[0]	auto[1]	2887	1			T1	8		T13	3		T32	6
all_values[2]	auto[1]	auto[0]	3525	1			T17	3		T19	4		T20	10
all_values[2]	auto[1]	auto[1]	206	1			T17	3		T18	2		T19	2
all_values[3]	auto[0]	auto[0]	2398128	1			T1	18371		T2	23		T3	1
all_values[3]	auto[0]	auto[1]	180	1			T18	2		T19	5		T20	5
all_values[3]	auto[1]	auto[0]	4356	1			T17	6		T18	2		T19	3
all_values[3]	auto[1]	auto[1]	156	1			T18	2		T19	4		T20	7
all_values[4]	auto[0]	auto[0]	2337087	1			T1	18371		T2	23		T3	1
all_values[4]	auto[0]	auto[1]	166	1			T17	3		T18	2		T19	9
all_values[4]	auto[1]	auto[0]	65380	1			T18	3		T19	1		T20	347
all_values[4]	auto[1]	auto[1]	187	1			T18	3		T19	2		T20	5
all_values[5]	auto[0]	auto[0]	2333977	1			T1	18371		T2	23		T3	1
all_values[5]	auto[0]	auto[1]	154	1			T18	2		T20	5		T21	3
all_values[5]	auto[1]	auto[0]	68536	1			T17	5		T18	4		T19	8
all_values[5]	auto[1]	auto[1]	153	1			T17	2		T18	2		T19	6
all_values[6]	auto[0]	auto[0]	2361551	1			T1	18371		T2	23		T3	1
all_values[6]	auto[0]	auto[1]	187	1			T18	1		T19	5		T20	6
all_values[6]	auto[1]	auto[0]	40872	1			T17	5		T18	5		T19	2
all_values[6]	auto[1]	auto[1]	210	1			T18	2		T19	4		T20	6
all_values[7]	auto[0]	auto[0]	2333351	1			T1	18371		T2	23		T3	1
all_values[7]	auto[0]	auto[1]	155	1			T17	3		T18	2		T19	2
all_values[7]	auto[1]	auto[0]	69118	1			T18	1		T19	6		T20	347
all_values[7]	auto[1]	auto[1]	196	1			T17	1		T19	1		T20	7