Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	34701	1			T1	44		T2	4		T4	595
auto[SpiFlashAddrCfg]	7550	1			T1	11		T2	2		T4	48
auto[SpiFlashAddr3b]	9114	1			T1	19		T4	54		T7	90
auto[SpiFlashAddr4b]	7649	1			T1	14		T4	51		T7	40

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33249

1

T1

54

T2

6

T4

162

auto[1]

25765

1

T1

34

T4

586

T7

162

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31312

1

T1

53

T2

2

T4

229

auto[1]

27702

1

T1

35

T2

4

T4

519

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	39198	1			T1	53		T2	4		T4	606
values[1]	1128	1			T1	3		T4	1		T7	4
values[2]	1466	1			T1	1		T4	4		T7	11
values[3]	1430	1			T1	4		T4	13		T7	9
values[4]	1431	1			T1	2		T4	17		T7	20
values[5]	1516	1			T1	2		T4	6		T7	23
values[6]	1423	1			T1	2		T4	7		T7	12
values[7]	1473	1			T1	5		T4	20		T7	10
values[8]	9949	1			T1	16		T2	2		T4	74

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31001

1

T2

6

T4

748

T7

368

auto[1]

28013

1

T1

88

T11

1

T37

161

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

55739

1

T1

77

T2

6

T4

730

write

3275

1

T1

11

T4

18

T7

13

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

19100

1

T1

34

T4

125

T7

140

valids[0x1]

39914

1

T1

54

T2

6

T4

623

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1593	1			T1	2		T2	2		T4	6
internal_process_ops[0x5a]	1613	1			T1	6		T4	11		T7	12
internal_process_ops[0x05]	20818	1			T1	9		T4	506		T7	104
internal_process_ops[0x35]	1584	1			T1	2		T4	9		T7	8
internal_process_ops[0x15]	1610	1			T1	4		T2	2		T4	7
internal_process_ops[0x03]	1015	1			T1	1		T4	16		T7	4
internal_process_ops[0x0b]	1108	1			T4	9		T7	15		T12	4
internal_process_ops[0x3b]	1041	1			T4	10		T7	13		T13	12
internal_process_ops[0x6b]	1024	1			T4	3		T7	13		T12	2
internal_process_ops[0xbb]	982	1			T1	2		T4	6		T7	13
internal_process_ops[0xeb]	987	1			T1	1		T4	15		T7	14

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

57399

1

T1

81

T2

6

T4

737

auto[1]

1615

1

T1

7

T4

11

T7

6

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

56729

1

T1

83

T2

6

T4

734

auto[1]

2285

1

T1

5

T4

14

T7

8

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10315

1

T2

4

T4

84

T7

120

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7359

1

T4

503

T7

63

T13

114

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2003

1

T2

2

T4

18

T7

25

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1664

1

T4

30

T7

23

T13

18

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2402

1

T4

20

T7

42

T12

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2055

1

T4

30

T7

44

T13

27

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2013

1

T4

31

T7

14

T12

6

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1656

1

T4

14

T7

24

T13

28

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

136

1

T4

1

T7

1

T13

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

90

1

T13

4

T32

1

T48

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

91

1

T4

5

T7

1

T13

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

89

1

T4

2

T13

1

T26

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

108

1

T7

2

T32

3

T48

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

73

1

T13

1

T32

1

T49

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

77

1

T7

1

T32

2

T48

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

107

1

T7

2

T13

2

T32

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

110

1

T13

1

T32

2

T48

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

67

1

T4

4

T7

1

T32

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

91

1

T7

1

T13

1

T49

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

97

1

T7

2

T13

1

T15

6

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

94

1

T7

1

T32

3

T179

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

125

1

T4

4

T13

1

T32

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

88

1

T4

1

T13

4

T32

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

91

1

T4

1

T7

1

T32

1

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9752

1

T1

26

T37

67

T38

156

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6418

1

T1

11

T37

13

T38

37

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1598

1

T1

7

T37

13

T38

19

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1502

1

T1

2

T37

10

T38

21

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1961

1

T1

13

T37

7

T38

22

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1894

1

T1

5

T37

13

T38

17

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1536

1

T1

6

T11

1

T37

12

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1611

1

T1

7

T37

9

T38

29

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

109

1

T68

4

T96

1

T180

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

125

1

T1

1

T37

7

T68

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

102

1

T1

2

T96

2

T181

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

115

1

T1

4

T68

1

T96

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

107

1

T37

3

T96

1

T180

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

116

1

T37

1

T38

3

T96

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

108

1

T68

1

T96

1

T111

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

87

1

T1

2

T37

2

T38

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

106

1

T1

1

T55

1

T96

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

101

1

T96

1

T181

4

T182

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

127

1

T37

2

T38

1

T96

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

103

1

T37

1

T68

4

T97

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

114

1

T38

1

T96

1

T97

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

88

1

T38

2

T96

3

T97

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

92

1

T1

1

T68

1

T96

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

141

1

T37

1

T38

4

T68

1

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3522	1			T4	48		T7	40		T8	12
auto[0]	values[0]	valids[0x1]	16849	1			T2	4		T4	558		T7	163
auto[0]	values[1]	valids[0x1]	539	1			T4	1		T7	4		T12	2
auto[0]	values[2]	valids[0x0]	522	1			T4	1		T7	4		T12	2
auto[0]	values[2]	valids[0x1]	295	1			T4	3		T7	7		T32	4
auto[0]	values[3]	valids[0x0]	492	1			T4	6		T7	3		T13	8
auto[0]	values[3]	valids[0x1]	284	1			T4	7		T7	6		T12	4
auto[0]	values[4]	valids[0x0]	484	1			T4	9		T7	13		T13	5
auto[0]	values[4]	valids[0x1]	282	1			T4	8		T7	7		T13	6
auto[0]	values[5]	valids[0x0]	535	1			T4	3		T7	15		T13	10
auto[0]	values[5]	valids[0x1]	293	1			T4	3		T7	8		T13	1
auto[0]	values[6]	valids[0x0]	507	1			T4	7		T7	11		T13	3
auto[0]	values[6]	valids[0x1]	270	1			T7	1		T13	5		T32	2
auto[0]	values[7]	valids[0x0]	531	1			T4	10		T7	7		T13	2
auto[0]	values[7]	valids[0x1]	268	1			T4	10		T7	3		T13	1
auto[0]	values[8]	valids[0x0]	3294	1			T4	41		T7	47		T13	43
auto[0]	values[8]	valids[0x1]	2034	1			T2	2		T4	33		T7	29
auto[1]	values[0]	valids[0x0]	4071	1			T1	16		T37	39		T38	49
auto[1]	values[0]	valids[0x1]	14756	1			T1	37		T37	63		T38	170
auto[1]	values[1]	valids[0x1]	589	1			T1	3		T38	13		T68	2
auto[1]	values[2]	valids[0x0]	386	1			T1	1		T37	5		T38	7
auto[1]	values[2]	valids[0x1]	263	1			T37	1		T38	4		T68	1
auto[1]	values[3]	valids[0x0]	370	1			T1	1		T37	2		T38	4
auto[1]	values[3]	valids[0x1]	284	1			T1	3		T37	5		T38	2
auto[1]	values[4]	valids[0x0]	397	1			T37	4		T38	6		T68	2
auto[1]	values[4]	valids[0x1]	268	1			T1	2		T38	3		T68	2
auto[1]	values[5]	valids[0x0]	439	1			T1	2		T37	2		T38	9
auto[1]	values[5]	valids[0x1]	249	1			T37	3		T38	4		T68	2
auto[1]	values[6]	valids[0x0]	421	1			T37	3		T38	5		T68	3
auto[1]	values[6]	valids[0x1]	225	1			T1	2		T37	2		T38	1
auto[1]	values[7]	valids[0x0]	420	1			T1	3		T11	1		T37	2
auto[1]	values[7]	valids[0x1]	254	1			T1	2		T38	1		T68	2
auto[1]	values[8]	valids[0x0]	2709	1			T1	11		T37	18		T38	36
auto[1]	values[8]	valids[0x1]	1912	1			T1	5		T37	12		T38	20