Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3128415

1

T1

3595

T2

11

T3

1

auto[1]

30002

1

T1

8

T4

488

T7

88

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

862719

1

T1

29

T2

1

T3

1

auto[1]

2295698

1

T1

3574

T2

10

T4

26480

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	561609	1			T1	261		T2	11		T3	1
auto[524288:1048575]	382597	1			T1	2803		T4	2695		T7	2972
auto[1048576:1572863]	328596	1			T1	6		T7	7836		T8	37
auto[1572864:2097151]	378815	1			T1	6		T4	5181		T7	138
auto[2097152:2621439]	337724	1			T1	515		T4	167		T7	37
auto[2621440:3145727]	391930	1			T1	1		T4	615		T7	29
auto[3145728:3670015]	391685	1			T1	7		T4	7090		T7	2483
auto[3670016:4194303]	385461	1			T1	4		T4	10272		T7	4540

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2326268

1

T1

3602

T2

11

T3

1

auto[1]

832149

1

T1

1

T4

10

T7

10

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2742545

1

T1

806

T2

11

T3

1

auto[1]

415872

1

T1

2797

T4

8744

T7

5237

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	173804	1			T1	10		T2	1		T3	1
auto[0]	auto[0]	auto[0:524287]	auto[1]	319744	1			T1	248		T2	10		T4	259
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	111338	1			T1	3		T4	3		T7	10
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	197133	1			T1	1		T4	2586		T7	395
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	89410	1			T1	4		T7	10		T8	2
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	191315	1			T1	1		T7	7812		T12	258
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	89773	1			T1	1		T4	16		T7	2
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	235364	1			T1	5		T4	5009		T7	5
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	74422	1			T1	3		T4	6		T7	4
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	216472	1			T1	512		T4	3		T7	2
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	129539	1			T1	1		T7	5		T12	1411
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	216422	1			T4	5		T7	2		T13	1364
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	105211	1			T4	4		T7	4		T12	6
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	226758	1			T1	7		T4	773		T7	2223
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	76703	1			T1	1		T4	10		T7	4
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	264818	1			T1	1		T4	8663		T7	2240
auto[0]	auto[1]	auto[0:524287]	auto[0]	1393	1			T8	57		T13	5		T32	4
auto[0]	auto[1]	auto[0:524287]	auto[1]	61099	1			T4	256		T13	1		T32	1024
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	1220	1			T1	1		T4	5		T7	3
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	70264	1			T1	2796		T4	1		T7	2553
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	677	1			T8	35		T32	3		T37	6
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	43981	1			T32	764		T37	1		T48	512
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	516	1			T7	3		T55	1		T96	2
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	48896	1			T7	128		T29	5		T15	4785
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	2370	1			T4	3		T38	3		T68	1
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	40929	1			T38	1280		T68	1		T96	803
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	1390	1			T13	2		T37	3		T38	2
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	40461	1			T4	610		T13	5		T37	896
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	571	1			T4	4		T37	3		T38	2
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	55710	1			T4	6305		T7	256		T37	3
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	510	1			T4	3		T7	1		T13	2
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	40202	1			T4	1536		T7	2293		T13	256
auto[1]	auto[0]	auto[0:524287]	auto[0]	510	1			T1	2		T4	1		T7	1
auto[1]	auto[0]	auto[0:524287]	auto[1]	3650	1			T1	1		T4	12		T7	7
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	360	1			T1	1		T4	1		T7	1
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	1601	1			T1	1		T4	78		T7	10
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	447	1			T1	1		T7	1		T32	2
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2282	1			T7	13		T32	1		T37	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	416	1			T4	4		T13	3		T37	2
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	3162	1			T4	152		T13	5		T37	2
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	379	1			T4	3		T7	2		T13	2
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2535	1			T4	152		T7	29		T13	8
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	392	1			T7	2		T32	2		T37	2
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	2594	1			T7	20		T32	10		T68	12
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	336	1			T4	1		T13	2		T32	3
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	2724	1			T4	3		T13	9		T32	41
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	405	1			T1	1		T4	3		T7	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	2526	1			T1	1		T4	57		T7	1
auto[1]	auto[1]	auto[0:524287]	auto[0]	70	1			T13	1		T111	1		T16	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	1339	1			T111	1		T212	10		T80	1
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	80	1			T4	1		T37	1		T15	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	601	1			T4	20		T37	2		T15	6
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	70	1			T32	1		T37	1		T181	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	414	1			T32	1		T37	1		T181	15
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	73	1			T29	7		T51	1		T179	3
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	615	1			T51	3		T79	14		T80	17
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	93	1			T68	1		T96	16		T81	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	524	1			T68	4		T96	256		T83	6
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	80	1			T96	2		T111	2		T82	3
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	1052	1			T111	2		T16	1		T20	6
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	81	1			T37	3		T68	1		T15	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	294	1			T37	1		T68	3		T15	44
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	80	1			T26	17		T97	7		T82	6
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	217	1			T195	12		T22	1		T39	3

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1890720	1			T1	798		T2	11		T3	1
auto[0]	auto[0]	auto[1]	827506	1			T4	6		T7	3		T8	78
auto[0]	auto[1]	auto[0]	406170	1			T1	2797		T4	8723		T7	5237
auto[0]	auto[1]	auto[1]	4019	1			T8	84		T181	2		T195	1
auto[1]	auto[0]	auto[0]	23799	1			T1	7		T4	464		T7	81
auto[1]	auto[0]	auto[1]	520	1			T1	1		T4	3		T7	7
auto[1]	auto[1]	auto[0]	5579	1			T4	20		T13	1		T32	2
auto[1]	auto[1]	auto[1]	104	1			T4	1		T68	2		T29	1