Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2402820	1			T1	18371		T2	23		T3	1
all_pins[1]	2402820	1			T1	18371		T2	23		T3	1
all_pins[2]	2402820	1			T1	18371		T2	23		T3	1
all_pins[3]	2402820	1			T1	18371		T2	23		T3	1
all_pins[4]	2402820	1			T1	18371		T2	23		T3	1
all_pins[5]	2402820	1			T1	18371		T2	23		T3	1
all_pins[6]	2402820	1			T1	18371		T2	23		T3	1
all_pins[7]	2402820	1			T1	18371		T2	23		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	19178977	1			T1	146968		T2	184		T3	8
values[0x1]	43583	1			T17	8		T18	15		T19	29
transitions[0x0=>0x1]	42284	1			T17	7		T18	11		T19	21
transitions[0x1=>0x0]	42295	1			T17	7		T18	11		T19	21

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2402589	1			T1	18371		T2	23		T3	1
all_pins[0]	values[0x1]	231	1			T17	2		T18	1		T19	6
all_pins[0]	transitions[0x0=>0x1]	184	1			T17	2		T19	5		T20	3
all_pins[0]	transitions[0x1=>0x0]	664	1			T18	2		T19	3		T20	6
all_pins[1]	values[0x0]	2402109	1			T1	18371		T2	23		T3	1
all_pins[1]	values[0x1]	711	1			T18	3		T19	4		T20	9
all_pins[1]	transitions[0x0=>0x1]	657	1			T18	3		T19	3		T20	5
all_pins[1]	transitions[0x1=>0x0]	155	1			T17	3		T18	2		T19	1
all_pins[2]	values[0x0]	2402611	1			T1	18371		T2	23		T3	1
all_pins[2]	values[0x1]	209	1			T17	3		T18	2		T19	2
all_pins[2]	transitions[0x0=>0x1]	162	1			T17	3		T18	2		T20	7
all_pins[2]	transitions[0x1=>0x0]	109	1			T18	2		T19	2		T20	6
all_pins[3]	values[0x0]	2402664	1			T1	18371		T2	23		T3	1
all_pins[3]	values[0x1]	156	1			T18	2		T19	4		T20	7
all_pins[3]	transitions[0x0=>0x1]	114	1			T19	3		T20	6		T21	1
all_pins[3]	transitions[0x1=>0x0]	145	1			T18	1		T19	1		T20	4
all_pins[4]	values[0x0]	2402633	1			T1	18371		T2	23		T3	1
all_pins[4]	values[0x1]	187	1			T18	3		T19	2		T20	5
all_pins[4]	transitions[0x0=>0x1]	149	1			T18	2		T19	2		T20	4
all_pins[4]	transitions[0x1=>0x0]	1426	1			T17	2		T18	1		T19	6
all_pins[5]	values[0x0]	2401356	1			T1	18371		T2	23		T3	1
all_pins[5]	values[0x1]	1464	1			T17	2		T18	2		T19	6
all_pins[5]	transitions[0x0=>0x1]	503	1			T17	2		T18	2		T19	4
all_pins[5]	transitions[0x1=>0x0]	39468	1			T18	2		T19	2		T20	6
all_pins[6]	values[0x0]	2362391	1			T1	18371		T2	23		T3	1
all_pins[6]	values[0x1]	40429	1			T18	2		T19	4		T20	6
all_pins[6]	transitions[0x0=>0x1]	40372	1			T18	2		T19	3		T20	6
all_pins[6]	transitions[0x1=>0x0]	139	1			T17	1		T20	7		T21	1
all_pins[7]	values[0x0]	2402624	1			T1	18371		T2	23		T3	1
all_pins[7]	values[0x1]	196	1			T17	1		T19	1		T20	7
all_pins[7]	transitions[0x0=>0x1]	143	1			T19	1		T20	6		T21	1
all_pins[7]	transitions[0x1=>0x0]	189	1			T17	1		T18	1		T19	6