Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17536

1

T2

6

T4

162

T7

206

auto[1]

13465

1

T4

586

T7

162

T13

198

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4266	1			T4	38		T7	89		T32	44
values[1]	4322	1			T4	20		T7	82		T13	71
values[2]	3993	1			T4	106		T8	12		T32	20
values[3]	3995	1			T2	6		T4	121		T7	57
values[4]	3489	1			T4	20		T7	92		T32	107
values[5]	3786	1			T4	298		T7	28		T13	23
values[6]	3700	1			T7	20		T13	164		T32	32
values[7]	3450	1			T4	145		T12	12		T13	76

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3339	1			T7	109		T13	75		T32	20
values[1]	3447	1			T13	94		T131	6		T48	65
values[2]	4089	1			T4	51		T7	42		T32	48
values[3]	5394	1			T4	194		T7	104		T13	51
values[4]	3887	1			T4	218		T7	40		T13	51
values[5]	3954	1			T2	6		T4	226		T13	43
values[6]	3301	1			T4	59		T7	73		T12	12
values[7]	3590	1			T8	12		T48	58		T49	20

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	328	1			T7	61		T53	7		T239	12
auto[0]	values[0]	values[1]	297	1			T240	4		T61	14		T170	12
auto[0]	values[0]	values[2]	455	1			T53	12		T51	54		T52	14
auto[0]	values[0]	values[3]	414	1			T49	22		T98	20		T15	23
auto[0]	values[0]	values[4]	444	1			T4	13		T15	33		T195	13
auto[0]	values[0]	values[5]	315	1			T32	21		T53	20		T52	12
auto[0]	values[0]	values[6]	222	1			T32	14		T51	26		T190	15
auto[0]	values[0]	values[7]	218	1			T241	13		T242	17		T243	13
auto[0]	values[1]	values[0]	144	1			T195	10		T212	15		T197	16
auto[0]	values[1]	values[1]	320	1			T13	24		T244	16		T194	12
auto[0]	values[1]	values[2]	265	1			T7	21		T15	10		T195	60
auto[0]	values[1]	values[3]	471	1			T7	16		T32	13		T49	11
auto[0]	values[1]	values[4]	221	1			T7	6		T28	4		T59	12
auto[0]	values[1]	values[5]	170	1			T4	13		T13	12		T29	14
auto[0]	values[1]	values[6]	220	1			T21	12		T93	14		T245	9
auto[0]	values[1]	values[7]	388	1			T29	14		T190	60		T204	11
auto[0]	values[2]	values[0]	172	1			T195	28		T21	13		T194	12
auto[0]	values[2]	values[1]	267	1			T51	11		T61	15		T219	11
auto[0]	values[2]	values[2]	280	1			T4	13		T194	27		T177	6
auto[0]	values[2]	values[3]	474	1			T53	12		T195	10		T212	15
auto[0]	values[2]	values[4]	406	1			T4	8		T32	11		T26	23
auto[0]	values[2]	values[5]	333	1			T246	19		T227	10		T247	8
auto[0]	values[2]	values[6]	280	1			T4	22		T48	19		T51	9
auto[0]	values[2]	values[7]	150	1			T8	12		T26	12		T53	15
auto[0]	values[3]	values[0]	231	1			T7	13		T32	8		T29	11
auto[0]	values[3]	values[1]	275	1			T190	17		T225	62		T204	25
auto[0]	values[3]	values[2]	335	1			T32	26		T48	15		T26	12
auto[0]	values[3]	values[3]	388	1			T4	14		T7	25		T53	12
auto[0]	values[3]	values[4]	194	1			T4	9		T187	15		T61	11
auto[0]	values[3]	values[5]	276	1			T2	6		T4	14		T59	13
auto[0]	values[3]	values[6]	236	1			T248	10		T51	16		T52	12
auto[0]	values[3]	values[7]	280	1			T26	11		T15	15		T20	15
auto[0]	values[4]	values[0]	309	1			T48	12		T229	28		T249	16
auto[0]	values[4]	values[1]	167	1			T48	52		T232	2		T219	7
auto[0]	values[4]	values[2]	376	1			T52	9		T190	13		T194	15
auto[0]	values[4]	values[3]	293	1			T7	33		T250	4		T217	14
auto[0]	values[4]	values[4]	220	1			T32	13		T15	7		T53	7
auto[0]	values[4]	values[5]	382	1			T4	11		T24	12		T251	18
auto[0]	values[4]	values[6]	232	1			T7	12		T32	11		T48	71
auto[0]	values[4]	values[7]	46	1			T48	7		T252	2		T253	29
auto[0]	values[5]	values[0]	57	1			T237	20		T215	9		T254	17
auto[0]	values[5]	values[1]	165	1			T51	11		T179	12		T212	13
auto[0]	values[5]	values[2]	121	1			T32	12		T51	9		T61	9
auto[0]	values[5]	values[3]	299	1			T4	13		T48	11		T15	12
auto[0]	values[5]	values[4]	366	1			T4	9		T13	12		T48	10
auto[0]	values[5]	values[5]	380	1			T51	26		T179	11		T194	10
auto[0]	values[5]	values[6]	144	1			T4	13		T7	12		T15	19
auto[0]	values[5]	values[7]	416	1			T15	10		T215	20		T94	11
auto[0]	values[6]	values[0]	244	1			T13	8		T26	16		T190	12
auto[0]	values[6]	values[1]	210	1			T13	27		T131	6		T53	21
auto[0]	values[6]	values[2]	219	1			T23	10		T51	12		T255	14
auto[0]	values[6]	values[3]	393	1			T13	7		T32	22		T256	4
auto[0]	values[6]	values[4]	270	1			T7	7		T257	6		T194	72
auto[0]	values[6]	values[5]	345	1			T225	63		T222	14		T94	26
auto[0]	values[6]	values[6]	310	1			T13	13		T92	10		T29	15
auto[0]	values[6]	values[7]	237	1			T49	7		T191	16		T20	12
auto[0]	values[7]	values[0]	366	1			T53	14		T51	36		T258	105
auto[0]	values[7]	values[1]	228	1			T259	6		T195	23		T20	11
auto[0]	values[7]	values[2]	187	1			T62	10		T194	58		T200	12
auto[0]	values[7]	values[3]	320	1			T13	12		T225	22		T177	17
auto[0]	values[7]	values[4]	170	1			T13	5		T221	18		T61	9
auto[0]	values[7]	values[5]	183	1			T4	10		T13	16		T260	4
auto[0]	values[7]	values[6]	171	1			T12	12		T32	11		T48	9
auto[0]	values[7]	values[7]	241	1			T190	25		T59	39		T21	20
auto[1]	values[0]	values[0]	228	1			T7	28		T53	13		T194	25
auto[1]	values[0]	values[1]	163	1			T61	8		T170	8		T261	18
auto[1]	values[0]	values[2]	239	1			T53	8		T51	4		T52	6
auto[1]	values[0]	values[3]	245	1			T49	12		T15	17		T212	8
auto[1]	values[0]	values[4]	240	1			T4	25		T15	16		T195	15
auto[1]	values[0]	values[5]	246	1			T32	3		T53	20		T52	9
auto[1]	values[0]	values[6]	91	1			T32	6		T51	19		T190	28
auto[1]	values[0]	values[7]	121	1			T241	7		T242	23		T243	7
auto[1]	values[1]	values[0]	196	1			T195	10		T212	5		T197	4
auto[1]	values[1]	values[1]	192	1			T13	27		T194	8		T197	11
auto[1]	values[1]	values[2]	315	1			T7	21		T15	15		T195	9
auto[1]	values[1]	values[3]	247	1			T7	4		T32	51		T49	9
auto[1]	values[1]	values[4]	221	1			T7	14		T59	8		T170	9
auto[1]	values[1]	values[5]	155	1			T4	7		T13	8		T29	6
auto[1]	values[1]	values[6]	249	1			T21	18		T245	11		T242	3
auto[1]	values[1]	values[7]	548	1			T29	6		T190	8		T204	9
auto[1]	values[2]	values[0]	153	1			T195	8		T64	26		T21	8
auto[1]	values[2]	values[1]	249	1			T51	9		T192	20		T61	5
auto[1]	values[2]	values[2]	241	1			T4	38		T194	5		T177	14
auto[1]	values[2]	values[3]	369	1			T53	8		T195	23		T212	5
auto[1]	values[2]	values[4]	218	1			T4	12		T32	9		T26	17
auto[1]	values[2]	values[5]	167	1			T227	10		T262	8		T236	24
auto[1]	values[2]	values[6]	137	1			T4	13		T48	4		T51	11
auto[1]	values[2]	values[7]	97	1			T26	8		T53	5		T188	12
auto[1]	values[3]	values[0]	303	1			T7	7		T32	12		T29	9
auto[1]	values[3]	values[1]	99	1			T190	15		T225	8		T204	15
auto[1]	values[3]	values[2]	289	1			T32	2		T48	5		T26	8
auto[1]	values[3]	values[3]	331	1			T4	6		T7	12		T53	8
auto[1]	values[3]	values[4]	220	1			T4	51		T187	5		T61	9
auto[1]	values[3]	values[5]	185	1			T4	27		T59	36		T194	6
auto[1]	values[3]	values[6]	201	1			T51	4		T52	10		T61	10
auto[1]	values[3]	values[7]	152	1			T26	9		T15	5		T20	5
auto[1]	values[4]	values[0]	147	1			T48	8		T188	9		T245	4
auto[1]	values[4]	values[1]	278	1			T48	13		T219	18		T263	4
auto[1]	values[4]	values[2]	136	1			T52	11		T190	7		T194	5
auto[1]	values[4]	values[3]	218	1			T7	14		T110	4		T21	21
auto[1]	values[4]	values[4]	216	1			T32	8		T15	66		T53	13
auto[1]	values[4]	values[5]	193	1			T4	9		T195	76		T190	12
auto[1]	values[4]	values[6]	192	1			T7	33		T32	75		T48	3
auto[1]	values[4]	values[7]	84	1			T48	51		T264	14		T253	7
auto[1]	values[5]	values[0]	25	1			T215	11		T254	5		T265	9
auto[1]	values[5]	values[1]	204	1			T51	10		T179	8		T212	84
auto[1]	values[5]	values[2]	264	1			T32	8		T51	24		T61	52
auto[1]	values[5]	values[3]	516	1			T4	161		T48	9		T15	8
auto[1]	values[5]	values[4]	229	1			T4	91		T13	11		T48	10
auto[1]	values[5]	values[5]	211	1			T51	21		T179	9		T194	18
auto[1]	values[5]	values[6]	154	1			T4	11		T7	16		T15	21
auto[1]	values[5]	values[7]	235	1			T15	10		T228	20		T215	4
auto[1]	values[6]	values[0]	274	1			T13	67		T26	4		T190	20
auto[1]	values[6]	values[1]	124	1			T13	16		T53	19		T197	10
auto[1]	values[6]	values[2]	113	1			T51	8		T195	8		T179	12
auto[1]	values[6]	values[3]	265	1			T13	19		T32	10		T266	11
auto[1]	values[6]	values[4]	119	1			T7	13		T194	8		T43	8
auto[1]	values[6]	values[5]	219	1			T225	11		T222	6		T94	14
auto[1]	values[6]	values[6]	94	1			T13	7		T29	5		T179	5
auto[1]	values[6]	values[7]	264	1			T49	13		T20	8		T21	5
auto[1]	values[7]	values[0]	162	1			T53	6		T51	19		T179	13
auto[1]	values[7]	values[1]	209	1			T195	5		T20	9		T267	6
auto[1]	values[7]	values[2]	254	1			T268	4		T194	6		T200	8
auto[1]	values[7]	values[3]	151	1			T13	13		T225	9		T177	3
auto[1]	values[7]	values[4]	133	1			T13	23		T61	11		T216	6
auto[1]	values[7]	values[5]	194	1			T4	135		T13	7		T170	8
auto[1]	values[7]	values[6]	368	1			T32	9		T48	11		T195	11
auto[1]	values[7]	values[7]	113	1			T190	8		T59	8		T21	5