Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	350	1			T4	7		T7	6		T12	6
auto[ReadAddrCrossIntoMailbox]	250	1			T4	6		T7	2		T32	2
auto[ReadAddrCrossOutOfMailbox]	271	1			T4	7		T7	9		T13	2
auto[ReadAddrCrossAllMailbox]	188	1			T4	3		T7	1		T13	2
auto[ReadAddrOutsideMailbox]	3441	1			T4	36		T7	54		T13	46

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2184

1

T4

31

T7

37

T12

3

auto[1]

2316

1

T4

28

T7

35

T12

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	742	1			T4	16		T7	4		T13	10
read_ops[0x0b]	791	1			T4	9		T7	15		T12	4
read_ops[0x3b]	755	1			T4	10		T7	13		T13	12
read_ops[0x6b]	761	1			T4	3		T7	13		T12	2
read_ops[0xbb]	740	1			T4	6		T7	13		T13	8
read_ops[0xeb]	711	1			T4	15		T7	14		T13	10

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	34	1			T131	1		T26	1		T195	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	25	1			T4	2		T131	1		T52	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	27	1			T53	1		T222	1		T197	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	21	1			T4	1		T15	1		T241	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T4	1		T131	1		T15	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	19	1			T4	1		T7	1		T131	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	20	1			T4	1		T32	1		T51	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	8	1			T221	1		T269	2		T270	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	273	1			T4	6		T7	1		T13	7
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	292	1			T4	4		T7	2		T13	3
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	38	1			T4	1		T12	2		T53	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	33	1			T7	2		T12	2		T26	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	20	1			T4	1		T15	1		T179	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	17	1			T53	1		T61	1		T225	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	19	1			T4	1		T190	1		T188	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	31	1			T4	1		T7	1		T29	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T51	1		T230	1		T271	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	24	1			T29	1		T241	1		T230	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	280	1			T4	3		T7	7		T13	3
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	311	1			T4	2		T7	5		T13	2
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	25	1			T32	1		T26	1		T53	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	31	1			T13	2		T29	1		T53	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	14	1			T4	1		T26	1		T190	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	12	1			T4	2		T48	1		T20	2
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	25	1			T4	1		T15	1		T195	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	21	1			T13	1		T48	1		T15	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T32	1		T53	1		T194	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	9	1			T53	1		T21	1		T94	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	314	1			T4	3		T7	9		T13	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	289	1			T4	3		T7	4		T13	8
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	30	1			T7	2		T12	1		T13	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	29	1			T12	1		T15	1		T53	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	21	1			T221	2		T20	2		T215	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	29	1			T221	2		T179	2		T21	2
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	19	1			T7	2		T13	1		T51	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	20	1			T29	1		T15	1		T53	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	20	1			T7	1		T13	1		T221	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	13	1			T32	1		T53	1		T221	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	271	1			T4	1		T7	6		T32	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	309	1			T4	2		T7	2		T13	5
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	19	1			T4	1		T26	1		T232	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	36	1			T4	1		T7	1		T232	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	16	1			T7	1		T32	1		T29	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	30	1			T4	1		T26	1		T53	2
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	18	1			T7	1		T29	1		T190	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	23	1			T7	2		T15	2		T51	2
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T4	1		T179	1		T212	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	15	1			T53	2		T51	1		T194	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	284	1			T4	1		T7	4		T13	3
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	284	1			T4	1		T7	4		T13	5
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	26	1			T4	1		T48	1		T59	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	24	1			T4	1		T7	1		T241	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	19	1			T59	1		T272	1		T215	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	24	1			T7	1		T32	1		T53	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	26	1			T4	1		T7	1		T29	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	27	1			T4	1		T7	1		T48	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T13	1		T195	1		T194	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	14	1			T4	1		T61	1		T212	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	238	1			T4	6		T7	2		T13	4
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	296	1			T4	4		T7	8		T13	5