Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4207	1			T4	120		T7	22		T12	12
values[1]	4222	1			T4	35		T7	113		T13	120
values[2]	3104	1			T2	6		T13	73		T32	21
values[3]	3595	1			T4	41		T7	27		T32	20
values[4]	3417	1			T4	185		T7	40		T13	20
values[5]	4278	1			T4	258		T7	101		T8	12
values[6]	4235	1			T4	58		T7	20		T13	23
values[7]	3943	1			T4	51		T7	45		T13	21

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3977	1			T4	80		T7	45		T32	20
values[1]	3554	1			T4	73		T13	126		T32	138
values[2]	3931	1			T4	44		T7	65		T12	12
values[3]	3361	1			T4	61		T7	40		T13	53
values[4]	4155	1			T4	225		T7	49		T13	43
values[5]	4291	1			T2	6		T4	165		T7	84
values[6]	3948	1			T4	100		T7	25		T32	21
values[7]	3784	1			T7	60		T13	25		T32	20

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30262

1

T2

6

T4

737

T7

362

auto[1]

739

1

T4

11

T7

6

T13

10

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	564	1			T4	20		T273	6		T249	16
auto[0]	values[0]	values[1]	569	1			T188	20		T197	70		T177	20
auto[0]	values[0]	values[2]	577	1			T12	12		T26	18		T15	20
auto[0]	values[0]	values[3]	629	1			T51	20		T194	217		T267	22
auto[0]	values[0]	values[4]	479	1			T7	21		T258	105		T194	32
auto[0]	values[0]	values[5]	439	1			T255	14		T274	4		T21	20
auto[0]	values[0]	values[6]	491	1			T4	100		T240	4		T204	19
auto[0]	values[0]	values[7]	335	1			T48	19		T15	23		T53	20
auto[0]	values[1]	values[0]	308	1			T131	6		T201	20		T145	23
auto[0]	values[1]	values[1]	385	1			T4	33		T13	73		T32	20
auto[0]	values[1]	values[2]	643	1			T7	26		T13	20		T53	20
auto[0]	values[1]	values[3]	420	1			T7	20		T32	23		T51	58
auto[0]	values[1]	values[4]	751	1			T26	20		T29	20		T51	19
auto[0]	values[1]	values[5]	483	1			T7	20		T195	18		T65	4
auto[0]	values[1]	values[6]	571	1			T7	24		T51	27		T197	20
auto[0]	values[1]	values[7]	549	1			T7	20		T13	25		T194	20
auto[0]	values[2]	values[0]	510	1			T53	18		T190	49		T194	18
auto[0]	values[2]	values[1]	142	1			T15	19		T179	20		T212	20
auto[0]	values[2]	values[2]	200	1			T26	20		T61	20		T225	20
auto[0]	values[2]	values[3]	496	1			T13	29		T230	8		T204	20
auto[0]	values[2]	values[4]	485	1			T13	43		T29	19		T53	20
auto[0]	values[2]	values[5]	566	1			T2	6		T92	10		T48	64
auto[0]	values[2]	values[6]	300	1			T32	20		T275	2		T210	18
auto[0]	values[2]	values[7]	327	1			T20	18		T245	20		T276	8
auto[0]	values[3]	values[0]	340	1			T48	58		T15	22		T53	19
auto[0]	values[3]	values[1]	470	1			T48	20		T277	2		T21	21
auto[0]	values[3]	values[2]	551	1			T32	17		T15	179		T53	20
auto[0]	values[3]	values[3]	260	1			T4	41		T239	12		T268	2
auto[0]	values[3]	values[4]	339	1			T7	26		T52	22		T278	10
auto[0]	values[3]	values[5]	540	1			T260	4		T15	20		T279	20
auto[0]	values[3]	values[6]	493	1			T48	19		T179	20		T190	29
auto[0]	values[3]	values[7]	501	1			T24	12		T53	20		T280	4
auto[0]	values[4]	values[0]	494	1			T28	4		T15	20		T51	19
auto[0]	values[4]	values[1]	357	1			T21	25		T212	32		T225	30
auto[0]	values[4]	values[2]	339	1			T4	20		T187	20		T179	19
auto[0]	values[4]	values[3]	233	1			T7	20		T281	8		T267	20
auto[0]	values[4]	values[4]	272	1			T53	20		T282	19		T283	6
auto[0]	values[4]	values[5]	596	1			T4	163		T7	20		T13	20
auto[0]	values[4]	values[6]	336	1			T94	20		T200	19		T207	30
auto[0]	values[4]	values[7]	716	1			T53	18		T59	49		T194	100
auto[0]	values[5]	values[0]	636	1			T4	59		T217	14		T256	4
auto[0]	values[5]	values[1]	292	1			T13	26		T195	66		T61	20
auto[0]	values[5]	values[2]	710	1			T4	24		T7	36		T13	26
auto[0]	values[5]	values[3]	353	1			T13	18		T32	28		T15	26
auto[0]	values[5]	values[4]	571	1			T4	171		T23	10		T53	20
auto[0]	values[5]	values[5]	552	1			T7	44		T8	12		T53	20
auto[0]	values[5]	values[6]	819	1			T49	20		T110	4		T187	20
auto[0]	values[5]	values[7]	249	1			T7	20		T15	20		T284	6
auto[0]	values[6]	values[0]	499	1			T15	18		T228	20		T194	28
auto[0]	values[6]	values[1]	634	1			T4	37		T13	23		T15	20
auto[0]	values[6]	values[2]	368	1			T48	73		T52	20		T194	20
auto[0]	values[6]	values[3]	644	1			T4	20		T232	2		T179	19
auto[0]	values[6]	values[4]	550	1			T51	58		T241	20		T257	6
auto[0]	values[6]	values[5]	437	1			T29	40		T285	14		T286	67
auto[0]	values[6]	values[6]	465	1			T49	19		T26	20		T218	24
auto[0]	values[6]	values[7]	570	1			T7	20		T32	19		T52	19
auto[0]	values[7]	values[0]	532	1			T7	45		T32	20		T229	28
auto[0]	values[7]	values[1]	616	1			T32	117		T49	34		T187	71
auto[0]	values[7]	values[2]	451	1			T248	10		T51	20		T17	20
auto[0]	values[7]	values[3]	238	1			T221	18		T204	36		T263	41
auto[0]	values[7]	values[4]	624	1			T4	49		T26	20		T241	20
auto[0]	values[7]	values[5]	594	1			T13	21		T48	20		T259	6
auto[0]	values[7]	values[6]	354	1			T48	18		T191	16		T51	24
auto[0]	values[7]	values[7]	448	1			T250	4		T244	16		T195	20
auto[1]	values[0]	values[0]	18	1			T177	3		T94	2		T219	2
auto[1]	values[0]	values[1]	23	1			T197	2		T287	6		T201	2
auto[1]	values[0]	values[2]	16	1			T26	2		T225	2		T204	2
auto[1]	values[0]	values[3]	23	1			T194	3		T267	1		T177	2
auto[1]	values[0]	values[4]	10	1			T7	1		T210	2		T236	1
auto[1]	values[0]	values[5]	7	1			T225	1		T242	1		T254	1
auto[1]	values[0]	values[6]	16	1			T204	1		T288	1		T289	2
auto[1]	values[0]	values[7]	11	1			T48	1		T15	2		T21	2
auto[1]	values[1]	values[0]	3	1			T145	1		T164	1		T254	1
auto[1]	values[1]	values[1]	11	1			T4	2		T13	2		T195	2
auto[1]	values[1]	values[2]	17	1			T7	2		T261	4		T286	1
auto[1]	values[1]	values[3]	5	1			T32	1		T170	1		T242	1
auto[1]	values[1]	values[4]	16	1			T51	2		T197	3		T220	1
auto[1]	values[1]	values[5]	19	1			T195	2		T194	1		T213	1
auto[1]	values[1]	values[6]	28	1			T7	1		T170	7		T245	1
auto[1]	values[1]	values[7]	13	1			T215	2		T220	3		T290	1
auto[1]	values[2]	values[0]	13	1			T53	2		T190	1		T194	2
auto[1]	values[2]	values[1]	4	1			T15	1		T245	3		-	-
auto[1]	values[2]	values[2]	6	1			T188	2		T291	2		T292	2
auto[1]	values[2]	values[3]	9	1			T13	1		T219	1		T145	1
auto[1]	values[2]	values[4]	17	1			T29	1		T194	1		T242	2
auto[1]	values[2]	values[5]	12	1			T48	1		T26	1		T21	4
auto[1]	values[2]	values[6]	9	1			T32	1		T210	2		T293	4
auto[1]	values[2]	values[7]	8	1			T20	2		T58	1		T254	1
auto[1]	values[3]	values[0]	6	1			T53	1		T59	1		T84	1
auto[1]	values[3]	values[1]	9	1			T263	1		T282	1		T294	1
auto[1]	values[3]	values[2]	23	1			T32	3		T15	4		T52	2
auto[1]	values[3]	values[3]	14	1			T268	2		T245	4		T295	1
auto[1]	values[3]	values[4]	7	1			T7	1		T263	1		T290	2
auto[1]	values[3]	values[5]	10	1			T286	2		T242	1		T207	1
auto[1]	values[3]	values[6]	15	1			T48	1		T190	3		T219	4
auto[1]	values[3]	values[7]	17	1			T201	1		T236	2		T296	2
auto[1]	values[4]	values[0]	12	1			T51	1		T195	1		T220	1
auto[1]	values[4]	values[1]	6	1			T225	1		T216	2		T231	1
auto[1]	values[4]	values[2]	7	1			T179	1		T262	1		T292	1
auto[1]	values[4]	values[3]	5	1			T267	1		T270	1		T292	1
auto[1]	values[4]	values[4]	7	1			T282	1		T231	1		T293	1
auto[1]	values[4]	values[5]	12	1			T4	2		T53	2		T297	2
auto[1]	values[4]	values[6]	10	1			T200	1		T298	2		T299	4
auto[1]	values[4]	values[7]	15	1			T53	2		T225	3		T270	2
auto[1]	values[5]	values[0]	14	1			T4	1		T197	3		T94	2
auto[1]	values[5]	values[1]	8	1			T13	2		T195	3		T263	1
auto[1]	values[5]	values[2]	14	1			T7	1		T32	1		T195	2
auto[1]	values[5]	values[3]	10	1			T13	5		T15	1		T51	1
auto[1]	values[5]	values[4]	14	1			T4	3		T215	1		T163	3
auto[1]	values[5]	values[5]	8	1			T51	1		T179	2		T190	1
auto[1]	values[5]	values[6]	21	1			T195	2		T190	1		T212	3
auto[1]	values[5]	values[7]	7	1			T286	3		T219	1		T43	3
auto[1]	values[6]	values[0]	12	1			T15	2		T227	2		T145	5
auto[1]	values[6]	values[1]	11	1			T4	1		T222	1		T245	1
auto[1]	values[6]	values[2]	4	1			T48	1		T292	1		T203	1
auto[1]	values[6]	values[3]	15	1			T179	1		T177	2		T216	3
auto[1]	values[6]	values[4]	5	1			T59	2		T84	1		T300	2
auto[1]	values[6]	values[5]	3	1			T201	2		T301	1		-	-
auto[1]	values[6]	values[6]	10	1			T49	1		T21	2		T163	2
auto[1]	values[6]	values[7]	8	1			T32	1		T52	1		T170	1
auto[1]	values[7]	values[0]	16	1			T204	2		T288	2		T282	5
auto[1]	values[7]	values[1]	17	1			T32	1		T187	3		T212	1
auto[1]	values[7]	values[2]	5	1			T212	1		T302	4		-	-
auto[1]	values[7]	values[3]	7	1			T204	4		T236	1		T270	1
auto[1]	values[7]	values[4]	8	1			T4	2		T212	1		T215	1
auto[1]	values[7]	values[5]	13	1			T170	1		T94	2		T262	4
auto[1]	values[7]	values[6]	10	1			T48	2		T51	2		T179	2
auto[1]	values[7]	values[7]	10	1			T207	1		T303	3		T304	3