Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	740	1			T17	4		T18	7		T19	14
all_values[1]	740	1			T17	4		T18	7		T19	14
all_values[2]	740	1			T17	4		T18	7		T19	14
all_values[3]	740	1			T17	4		T18	7		T19	14
all_values[4]	740	1			T17	4		T18	7		T19	14
all_values[5]	740	1			T17	4		T18	7		T19	14
all_values[6]	740	1			T17	4		T18	7		T19	14
all_values[7]	740	1			T17	4		T18	7		T19	14

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3182

1

T17

17

T18

34

T19

68

auto[1]

2738

1

T17

15

T18

22

T19

44

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2330

1

T17

14

T18

16

T19

39

auto[1]

3590

1

T17

18

T18

40

T19

73

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3346

1

T17

19

T18

31

T19

51

auto[1]

2574

1

T17

13

T18

25

T19

61

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	137	1			T18	1		T19	2		T20	5
all_values[0]	auto[0]	auto[0]	auto[1]	75	1			T18	1		T21	1		T57	1
all_values[0]	auto[0]	auto[1]	auto[0]	120	1			T17	2		T18	1		T20	5
all_values[0]	auto[0]	auto[1]	auto[1]	76	1			T19	1		T20	1		T21	1
all_values[0]	auto[1]	auto[0]	auto[1]	194	1			T17	1		T18	3		T19	6
all_values[0]	auto[1]	auto[1]	auto[1]	138	1			T17	1		T18	1		T19	5
all_values[1]	auto[0]	auto[0]	auto[0]	165	1			T17	2		T19	4		T20	2
all_values[1]	auto[0]	auto[0]	auto[1]	64	1			T17	1		T20	3		T22	1
all_values[1]	auto[0]	auto[1]	auto[0]	114	1			T19	3		T20	3		T21	4
all_values[1]	auto[0]	auto[1]	auto[1]	78	1			T18	2		T19	1		T20	3
all_values[1]	auto[1]	auto[0]	auto[1]	169	1			T17	1		T18	5		T19	3
all_values[1]	auto[1]	auto[1]	auto[1]	150	1			T19	3		T20	6		T21	1
all_values[2]	auto[0]	auto[0]	auto[0]	148	1			T18	2		T19	4		T20	4
all_values[2]	auto[0]	auto[0]	auto[1]	77	1			T18	2		T19	1		T20	1
all_values[2]	auto[0]	auto[1]	auto[0]	110	1			T19	1		T20	6		T21	4
all_values[2]	auto[0]	auto[1]	auto[1]	75	1			T17	1		T18	1		T19	1
all_values[2]	auto[1]	auto[0]	auto[1]	167	1			T17	1		T18	2		T19	5
all_values[2]	auto[1]	auto[1]	auto[1]	163	1			T17	2		T19	2		T20	9
all_values[3]	auto[0]	auto[0]	auto[0]	169	1			T18	2		T19	2		T20	8
all_values[3]	auto[0]	auto[0]	auto[1]	84	1			T18	2		T19	3		T20	2
all_values[3]	auto[0]	auto[1]	auto[0]	127	1			T17	3		T19	1		T20	3
all_values[3]	auto[0]	auto[1]	auto[1]	62	1			T18	1		T20	6		T22	2
all_values[3]	auto[1]	auto[0]	auto[1]	181	1			T17	1		T18	2		T19	2
all_values[3]	auto[1]	auto[1]	auto[1]	117	1			T19	6		T21	1		T22	1
all_values[4]	auto[0]	auto[0]	auto[0]	157	1			T17	1		T18	1		T19	1
all_values[4]	auto[0]	auto[0]	auto[1]	65	1			T17	1		T18	1		T19	2
all_values[4]	auto[0]	auto[1]	auto[0]	121	1			T19	1		T20	9		T21	2
all_values[4]	auto[0]	auto[1]	auto[1]	73	1			T18	1		T20	2		T57	1
all_values[4]	auto[1]	auto[0]	auto[1]	181	1			T17	2		T18	1		T19	9
all_values[4]	auto[1]	auto[1]	auto[1]	143	1			T18	3		T19	1		T20	4
all_values[5]	auto[0]	auto[0]	auto[0]	235	1			T17	1		T19	3		T20	13
all_values[5]	auto[0]	auto[1]	auto[0]	198	1			T17	1		T18	3		T19	5
all_values[5]	auto[1]	auto[0]	auto[1]	165	1			T18	1		T19	1		T20	6
all_values[5]	auto[1]	auto[1]	auto[1]	142	1			T17	2		T18	3		T19	5
all_values[6]	auto[0]	auto[0]	auto[0]	144	1			T17	3		T19	3		T20	6
all_values[6]	auto[0]	auto[0]	auto[1]	67	1			T18	1		T19	1		T20	3
all_values[6]	auto[0]	auto[1]	auto[0]	101	1			T17	1		T18	2		T20	5
all_values[6]	auto[0]	auto[1]	auto[1]	78	1			T18	1		T20	1		T21	1
all_values[6]	auto[1]	auto[0]	auto[1]	189	1			T18	1		T19	6		T20	3
all_values[6]	auto[1]	auto[1]	auto[1]	161	1			T18	2		T19	4		T20	6
all_values[7]	auto[0]	auto[0]	auto[0]	137	1			T18	3		T19	7		T20	4
all_values[7]	auto[0]	auto[0]	auto[1]	62	1			T17	1		T18	2		T19	2
all_values[7]	auto[0]	auto[1]	auto[0]	147	1			T18	1		T19	2		T20	4
all_values[7]	auto[0]	auto[1]	auto[1]	80	1			T17	1		T20	1		T57	2
all_values[7]	auto[1]	auto[0]	auto[1]	150	1			T17	1		T18	1		T19	1
all_values[7]	auto[1]	auto[1]	auto[1]	164	1			T17	1		T19	2		T20	7

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal