Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1894

1

T1

5

T6

2

T13

9

auto[1]

1875

1

T1

7

T6

2

T13

4

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1930

1

T1

9

T13

13

T32

4

auto[1]

1839

1

T1

3

T6

4

T31

10

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3057

1

T1

8

T6

4

T13

9

auto[1]

712

1

T1

4

T13

4

T32

1

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	777	1			T1	3		T6	1		T13	2
valid[1]	752	1			T1	3		T6	1		T13	5
valid[2]	757	1			T1	1		T13	1		T31	1
valid[3]	747	1			T1	2		T6	2		T13	2
valid[4]	736	1			T1	3		T13	3		T31	2

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	123	1			T1	1		T13	1		T55	1
auto[0]	auto[0]	valid[0]	auto[1]	184	1			T31	2		T34	2		T55	1
auto[0]	auto[0]	valid[1]	auto[0]	117	1			T1	2		T13	4		T15	1
auto[0]	auto[0]	valid[1]	auto[1]	175	1			T1	1		T6	1		T33	1
auto[0]	auto[0]	valid[2]	auto[0]	133	1			T37	3		T54	3		T55	2
auto[0]	auto[0]	valid[2]	auto[1]	174	1			T31	1		T33	1		T34	3
auto[0]	auto[0]	valid[3]	auto[0]	114	1			T13	2		T37	1		T111	1
auto[0]	auto[0]	valid[3]	auto[1]	193	1			T6	1		T31	1		T33	3
auto[0]	auto[0]	valid[4]	auto[0]	123	1			T37	1		T38	1		T55	1
auto[0]	auto[0]	valid[4]	auto[1]	180	1			T31	1		T90	1		T327	2
auto[0]	auto[1]	valid[0]	auto[0]	139	1			T1	1		T32	1		T37	1
auto[0]	auto[1]	valid[0]	auto[1]	198	1			T6	1		T31	1		T34	3
auto[0]	auto[1]	valid[1]	auto[0]	116	1			T32	2		T54	2		T55	2
auto[0]	auto[1]	valid[1]	auto[1]	198	1			T33	1		T34	2		T91	1
auto[0]	auto[1]	valid[2]	auto[0]	125	1			T1	1		T37	1		T38	1
auto[0]	auto[1]	valid[2]	auto[1]	184	1			T34	4		T91	3		T15	1
auto[0]	auto[1]	valid[3]	auto[0]	107	1			T37	2		T38	1		T316	1
auto[0]	auto[1]	valid[3]	auto[1]	184	1			T1	2		T6	1		T31	3
auto[0]	auto[1]	valid[4]	auto[0]	121	1			T13	2		T316	2		T111	1
auto[0]	auto[1]	valid[4]	auto[1]	169	1			T31	1		T33	1		T34	6
auto[1]	auto[0]	valid[0]	auto[0]	76	1			T1	1		T13	1		T32	1
auto[1]	auto[0]	valid[1]	auto[0]	73	1			T13	1		T15	1		T81	1
auto[1]	auto[0]	valid[2]	auto[0]	81	1			T37	2		T55	1		T182	1
auto[1]	auto[0]	valid[3]	auto[0]	80	1			T38	1		T15	1		T111	1
auto[1]	auto[0]	valid[4]	auto[0]	68	1			T37	1		T38	1		T30	1
auto[1]	auto[1]	valid[0]	auto[0]	57	1			T30	1		T83	1		T16	1
auto[1]	auto[1]	valid[1]	auto[0]	73	1			T37	1		T55	1		T111	1
auto[1]	auto[1]	valid[2]	auto[0]	60	1			T13	1		T37	3		T38	1
auto[1]	auto[1]	valid[3]	auto[0]	69	1			T37	2		T15	1		T52	1
auto[1]	auto[1]	valid[4]	auto[0]	75	1			T1	3		T13	1		T15	2

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal