Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

47984

1

T1

310

T13

388

T32

137

auto[1]

19059

1

T1

72

T6

4

T31

10

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

49675

1

T1

259

T6

4

T13

260

auto[1]

17368

1

T1

123

T13

128

T32

48

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	34780	1			T1	191		T6	4		T13	207
others[1]	5593	1			T1	30		T13	29		T32	8
others[2]	5521	1			T1	29		T13	32		T32	12
others[3]	6500	1			T1	41		T13	38		T32	14
interest[1]	3687	1			T1	18		T13	24		T32	11
interest[4]	22699	1			T1	127		T6	4		T13	148
interest[64]	10962	1			T1	73		T13	58		T32	28

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	15817	1			T1	92		T13	138		T32	44
auto[0]	auto[0]	others[1]	2604	1			T1	15		T13	20		T32	7
auto[0]	auto[0]	others[2]	2555	1			T1	15		T13	20		T32	7
auto[0]	auto[0]	others[3]	2993	1			T1	17		T13	29		T32	11
auto[0]	auto[0]	interest[1]	1717	1			T1	10		T13	17		T32	8
auto[0]	auto[0]	interest[4]	10290	1			T1	69		T13	97		T32	28
auto[0]	auto[0]	interest[64]	4930	1			T1	38		T13	36		T32	12
auto[0]	auto[1]	others[0]	9908	1			T1	38		T6	4		T31	10
auto[0]	auto[1]	others[1]	1573	1			T1	4		T34	23		T37	8
auto[0]	auto[1]	others[2]	1567	1			T1	4		T34	37		T37	9
auto[0]	auto[1]	others[3]	1842	1			T1	10		T34	39		T37	4
auto[0]	auto[1]	interest[1]	1024	1			T1	3		T34	22		T37	7
auto[0]	auto[1]	interest[4]	6527	1			T1	18		T6	4		T31	10
auto[0]	auto[1]	interest[64]	3145	1			T1	13		T34	79		T37	14
auto[1]	auto[0]	others[0]	9055	1			T1	61		T13	69		T32	20
auto[1]	auto[0]	others[1]	1416	1			T1	11		T13	9		T32	1
auto[1]	auto[0]	others[2]	1399	1			T1	10		T13	12		T32	5
auto[1]	auto[0]	others[3]	1665	1			T1	14		T13	9		T32	3
auto[1]	auto[0]	interest[1]	946	1			T1	5		T13	7		T32	3
auto[1]	auto[0]	interest[4]	5882	1			T1	40		T13	51		T32	14
auto[1]	auto[0]	interest[64]	2887	1			T1	22		T13	22		T32	16

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal