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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.06 98.44 94.10 98.62 89.36 97.28 95.43 99.21


Total test records in report: 1149
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T1040 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.4210778045 Jul 27 04:51:06 PM PDT 24 Jul 27 04:51:07 PM PDT 24 129051294 ps
T127 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1141869028 Jul 27 04:50:03 PM PDT 24 Jul 27 04:50:07 PM PDT 24 100566054 ps
T130 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3724282337 Jul 27 04:50:23 PM PDT 24 Jul 27 04:50:25 PM PDT 24 67683320 ps
T1041 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2183443276 Jul 27 04:50:27 PM PDT 24 Jul 27 04:50:28 PM PDT 24 35801271 ps
T156 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.3966150749 Jul 27 04:50:29 PM PDT 24 Jul 27 04:50:31 PM PDT 24 158166184 ps
T129 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.173246128 Jul 27 04:50:25 PM PDT 24 Jul 27 04:50:44 PM PDT 24 308873395 ps
T1042 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.2282306444 Jul 27 04:50:04 PM PDT 24 Jul 27 04:50:05 PM PDT 24 11368156 ps
T135 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.320720224 Jul 27 04:50:16 PM PDT 24 Jul 27 04:50:18 PM PDT 24 83094198 ps
T1043 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2682111491 Jul 27 04:50:13 PM PDT 24 Jul 27 04:50:14 PM PDT 24 64813687 ps
T1044 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.132854712 Jul 27 04:50:22 PM PDT 24 Jul 27 04:50:23 PM PDT 24 14347343 ps
T1045 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.1045573657 Jul 27 04:50:14 PM PDT 24 Jul 27 04:50:15 PM PDT 24 22681768 ps
T157 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3361360636 Jul 27 04:50:08 PM PDT 24 Jul 27 04:50:11 PM PDT 24 144268766 ps
T1046 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.1238386455 Jul 27 04:50:16 PM PDT 24 Jul 27 04:50:17 PM PDT 24 14569343 ps
T1047 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.4206245152 Jul 27 04:50:14 PM PDT 24 Jul 27 04:50:18 PM PDT 24 64024695 ps
T185 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.2492647043 Jul 27 04:50:12 PM PDT 24 Jul 27 04:50:25 PM PDT 24 978618421 ps
T136 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.1340312197 Jul 27 04:50:41 PM PDT 24 Jul 27 04:50:43 PM PDT 24 30095181 ps
T121 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.3860990599 Jul 27 04:50:27 PM PDT 24 Jul 27 04:50:29 PM PDT 24 65262196 ps
T1048 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.453769560 Jul 27 04:50:34 PM PDT 24 Jul 27 04:50:35 PM PDT 24 43313844 ps
T1049 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3061362112 Jul 27 04:50:03 PM PDT 24 Jul 27 04:50:07 PM PDT 24 44542872 ps
T158 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2764913471 Jul 27 04:50:21 PM PDT 24 Jul 27 04:50:23 PM PDT 24 75779642 ps
T1050 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3341495984 Jul 27 04:50:04 PM PDT 24 Jul 27 04:50:07 PM PDT 24 176285558 ps
T183 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.367412878 Jul 27 04:50:10 PM PDT 24 Jul 27 04:50:27 PM PDT 24 1201007735 ps
T112 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3004364549 Jul 27 04:49:54 PM PDT 24 Jul 27 04:49:57 PM PDT 24 307610206 ps
T1051 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.2651846476 Jul 27 04:50:16 PM PDT 24 Jul 27 04:50:42 PM PDT 24 3094403743 ps
T1052 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.3700952809 Jul 27 04:50:16 PM PDT 24 Jul 27 04:50:17 PM PDT 24 32734360 ps
T1053 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.78605609 Jul 27 04:50:42 PM PDT 24 Jul 27 04:50:42 PM PDT 24 65176078 ps
T159 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.1994459583 Jul 27 04:50:35 PM PDT 24 Jul 27 04:50:36 PM PDT 24 46328107 ps
T160 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.472726848 Jul 27 04:50:23 PM PDT 24 Jul 27 04:50:26 PM PDT 24 141153052 ps
T1054 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.3588459670 Jul 27 04:50:17 PM PDT 24 Jul 27 04:50:17 PM PDT 24 13736843 ps
T1055 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.2962273577 Jul 27 04:50:20 PM PDT 24 Jul 27 04:50:21 PM PDT 24 25860096 ps
T1056 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.3586220417 Jul 27 04:50:06 PM PDT 24 Jul 27 04:50:07 PM PDT 24 12633308 ps
T1057 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.4146447606 Jul 27 04:50:34 PM PDT 24 Jul 27 04:50:35 PM PDT 24 22967312 ps
T1058 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.3568369763 Jul 27 04:50:25 PM PDT 24 Jul 27 04:50:26 PM PDT 24 14188998 ps
T1059 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.480668673 Jul 27 04:50:28 PM PDT 24 Jul 27 04:50:29 PM PDT 24 12664556 ps
T1060 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2788022540 Jul 27 04:50:19 PM PDT 24 Jul 27 04:50:21 PM PDT 24 149810700 ps
T137 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.401794006 Jul 27 04:49:56 PM PDT 24 Jul 27 04:50:19 PM PDT 24 4350337249 ps
T1061 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.4154549499 Jul 27 04:50:11 PM PDT 24 Jul 27 04:50:12 PM PDT 24 32368474 ps
T1062 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.4060117733 Jul 27 04:50:18 PM PDT 24 Jul 27 04:50:19 PM PDT 24 12682473 ps
T1063 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.4143587027 Jul 27 04:50:31 PM PDT 24 Jul 27 04:50:32 PM PDT 24 11956686 ps
T1064 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.3168711047 Jul 27 04:50:17 PM PDT 24 Jul 27 04:50:33 PM PDT 24 1441198017 ps
T1065 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.3449716691 Jul 27 04:50:30 PM PDT 24 Jul 27 04:50:39 PM PDT 24 1671559651 ps
T1066 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.1915613092 Jul 27 04:50:27 PM PDT 24 Jul 27 04:50:34 PM PDT 24 434380422 ps
T138 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1036882348 Jul 27 04:50:16 PM PDT 24 Jul 27 04:50:18 PM PDT 24 200805196 ps
T1067 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.1663751253 Jul 27 04:49:52 PM PDT 24 Jul 27 04:49:53 PM PDT 24 15120228 ps
T114 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.1452399911 Jul 27 04:50:17 PM PDT 24 Jul 27 04:50:22 PM PDT 24 110993582 ps
T1068 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.3618634313 Jul 27 04:50:38 PM PDT 24 Jul 27 04:50:40 PM PDT 24 78796831 ps
T113 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2551066623 Jul 27 04:50:20 PM PDT 24 Jul 27 04:50:24 PM PDT 24 139809196 ps
T1069 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.246720530 Jul 27 04:50:11 PM PDT 24 Jul 27 04:50:14 PM PDT 24 132364598 ps
T1070 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.4071391852 Jul 27 04:50:28 PM PDT 24 Jul 27 04:50:29 PM PDT 24 60965706 ps
T126 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.1621987531 Jul 27 04:50:12 PM PDT 24 Jul 27 04:50:16 PM PDT 24 122729881 ps
T1071 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3843279915 Jul 27 04:50:30 PM PDT 24 Jul 27 04:50:31 PM PDT 24 150054564 ps
T115 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.2057913408 Jul 27 04:50:17 PM PDT 24 Jul 27 04:50:19 PM PDT 24 143497063 ps
T124 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.2249357987 Jul 27 04:50:20 PM PDT 24 Jul 27 04:50:23 PM PDT 24 276180370 ps
T119 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.1360863136 Jul 27 04:50:26 PM PDT 24 Jul 27 04:50:27 PM PDT 24 319601274 ps
T1072 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.4153413276 Jul 27 04:50:43 PM PDT 24 Jul 27 04:50:44 PM PDT 24 16302961 ps
T1073 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1493063581 Jul 27 04:50:02 PM PDT 24 Jul 27 04:50:14 PM PDT 24 204647196 ps
T120 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.3878085688 Jul 27 04:50:17 PM PDT 24 Jul 27 04:50:21 PM PDT 24 270207838 ps
T1074 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.818153572 Jul 27 04:50:28 PM PDT 24 Jul 27 04:50:32 PM PDT 24 156397233 ps
T139 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.3580700130 Jul 27 04:50:05 PM PDT 24 Jul 27 04:50:06 PM PDT 24 151817059 ps
T1075 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.982868987 Jul 27 04:50:17 PM PDT 24 Jul 27 04:50:20 PM PDT 24 264092763 ps
T88 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1520837506 Jul 27 04:50:01 PM PDT 24 Jul 27 04:50:03 PM PDT 24 44399651 ps
T125 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.79630929 Jul 27 04:50:13 PM PDT 24 Jul 27 04:50:17 PM PDT 24 101789523 ps
T184 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.3901660838 Jul 27 04:50:16 PM PDT 24 Jul 27 04:50:23 PM PDT 24 279718304 ps
T1076 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.153698498 Jul 27 04:50:16 PM PDT 24 Jul 27 04:50:17 PM PDT 24 15671047 ps
T1077 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.2329574904 Jul 27 04:50:32 PM PDT 24 Jul 27 04:50:45 PM PDT 24 419407415 ps
T1078 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.2872855611 Jul 27 04:50:27 PM PDT 24 Jul 27 04:50:28 PM PDT 24 14921299 ps
T186 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.4174206325 Jul 27 04:50:05 PM PDT 24 Jul 27 04:50:24 PM PDT 24 284400586 ps
T1079 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1010604796 Jul 27 04:50:17 PM PDT 24 Jul 27 04:50:18 PM PDT 24 42605622 ps
T122 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.1860554495 Jul 27 04:50:16 PM PDT 24 Jul 27 04:50:20 PM PDT 24 67715179 ps
T1080 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.587306345 Jul 27 04:50:18 PM PDT 24 Jul 27 04:50:19 PM PDT 24 11247330 ps
T1081 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.962037286 Jul 27 04:50:20 PM PDT 24 Jul 27 04:50:21 PM PDT 24 63719698 ps
T143 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2116975706 Jul 27 04:49:51 PM PDT 24 Jul 27 04:49:53 PM PDT 24 53852545 ps
T1082 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.2764049103 Jul 27 04:50:11 PM PDT 24 Jul 27 04:50:13 PM PDT 24 91838194 ps
T1083 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.1155999915 Jul 27 04:50:12 PM PDT 24 Jul 27 04:50:13 PM PDT 24 31422422 ps
T1084 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.3437792818 Jul 27 04:50:20 PM PDT 24 Jul 27 04:50:21 PM PDT 24 16038900 ps
T1085 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.4217770033 Jul 27 04:50:17 PM PDT 24 Jul 27 04:50:19 PM PDT 24 200689740 ps
T1086 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.2288941000 Jul 27 04:50:16 PM PDT 24 Jul 27 04:50:17 PM PDT 24 12930437 ps
T116 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3232276775 Jul 27 04:50:24 PM PDT 24 Jul 27 04:50:28 PM PDT 24 258143150 ps
T1087 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.2298969477 Jul 27 04:50:18 PM PDT 24 Jul 27 04:50:20 PM PDT 24 56617583 ps
T1088 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.230477206 Jul 27 04:50:12 PM PDT 24 Jul 27 04:50:13 PM PDT 24 87798761 ps
T1089 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2795659116 Jul 27 04:50:12 PM PDT 24 Jul 27 04:50:14 PM PDT 24 272387975 ps
T1090 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.755746162 Jul 27 04:50:23 PM PDT 24 Jul 27 04:50:24 PM PDT 24 14900473 ps
T1091 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2537880230 Jul 27 04:50:41 PM PDT 24 Jul 27 04:50:42 PM PDT 24 22411520 ps
T1092 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.2109072354 Jul 27 04:49:50 PM PDT 24 Jul 27 04:49:51 PM PDT 24 26652737 ps
T1093 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.2521825001 Jul 27 04:50:17 PM PDT 24 Jul 27 04:50:17 PM PDT 24 49871091 ps
T117 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2650425199 Jul 27 04:50:17 PM PDT 24 Jul 27 04:50:21 PM PDT 24 53455584 ps
T140 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1378585920 Jul 27 04:50:10 PM PDT 24 Jul 27 04:50:33 PM PDT 24 735420025 ps
T118 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.1380240096 Jul 27 04:50:21 PM PDT 24 Jul 27 04:50:24 PM PDT 24 612143777 ps
T141 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.3691193411 Jul 27 04:50:29 PM PDT 24 Jul 27 04:50:31 PM PDT 24 37607436 ps
T1094 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.4118060220 Jul 27 04:50:17 PM PDT 24 Jul 27 04:50:39 PM PDT 24 6266153218 ps
T123 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.419139387 Jul 27 04:49:58 PM PDT 24 Jul 27 04:50:01 PM PDT 24 130374468 ps
T142 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1109719164 Jul 27 04:49:59 PM PDT 24 Jul 27 04:50:14 PM PDT 24 1754821402 ps
T1095 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.221063887 Jul 27 04:50:26 PM PDT 24 Jul 27 04:50:27 PM PDT 24 41746388 ps
T1096 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1147918635 Jul 27 04:50:13 PM PDT 24 Jul 27 04:50:15 PM PDT 24 106510534 ps
T1097 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3560166525 Jul 27 04:49:50 PM PDT 24 Jul 27 04:50:04 PM PDT 24 15037908077 ps
T1098 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.3003467293 Jul 27 04:50:16 PM PDT 24 Jul 27 04:50:19 PM PDT 24 177486540 ps
T1099 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.2763970776 Jul 27 04:49:52 PM PDT 24 Jul 27 04:49:53 PM PDT 24 45886202 ps
T144 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1051667174 Jul 27 04:50:15 PM PDT 24 Jul 27 04:50:17 PM PDT 24 146489236 ps
T1100 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1457955760 Jul 27 04:50:19 PM PDT 24 Jul 27 04:50:21 PM PDT 24 23021384 ps
T1101 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.3085668270 Jul 27 04:50:01 PM PDT 24 Jul 27 04:50:22 PM PDT 24 2551450175 ps
T1102 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1682151719 Jul 27 04:50:16 PM PDT 24 Jul 27 04:50:18 PM PDT 24 702509380 ps
T1103 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2220317760 Jul 27 04:50:03 PM PDT 24 Jul 27 04:50:21 PM PDT 24 581769983 ps
T1104 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.570659162 Jul 27 04:50:25 PM PDT 24 Jul 27 04:50:26 PM PDT 24 27457999 ps
T1105 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.464708617 Jul 27 04:50:25 PM PDT 24 Jul 27 04:50:35 PM PDT 24 878944554 ps
T1106 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.185503903 Jul 27 04:50:30 PM PDT 24 Jul 27 04:50:31 PM PDT 24 174081120 ps
T89 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.3679428798 Jul 27 04:50:16 PM PDT 24 Jul 27 04:50:18 PM PDT 24 127227082 ps
T1107 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.750920990 Jul 27 04:50:16 PM PDT 24 Jul 27 04:50:18 PM PDT 24 265284092 ps
T1108 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3562357618 Jul 27 04:50:32 PM PDT 24 Jul 27 04:50:33 PM PDT 24 22171305 ps
T1109 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.1263503457 Jul 27 04:50:25 PM PDT 24 Jul 27 04:50:27 PM PDT 24 73564807 ps
T1110 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.2796159102 Jul 27 04:49:58 PM PDT 24 Jul 27 04:50:19 PM PDT 24 304877856 ps
T1111 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.1165339454 Jul 27 04:50:12 PM PDT 24 Jul 27 04:50:15 PM PDT 24 543727140 ps
T1112 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.2449414438 Jul 27 04:49:51 PM PDT 24 Jul 27 04:49:56 PM PDT 24 751167166 ps
T1113 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.649795967 Jul 27 04:50:30 PM PDT 24 Jul 27 04:50:57 PM PDT 24 1881480442 ps
T1114 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3909055845 Jul 27 04:50:08 PM PDT 24 Jul 27 04:50:09 PM PDT 24 58312273 ps
T1115 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.1060494865 Jul 27 04:50:24 PM PDT 24 Jul 27 04:50:26 PM PDT 24 804816103 ps
T1116 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3090432295 Jul 27 04:50:32 PM PDT 24 Jul 27 04:50:35 PM PDT 24 222116348 ps
T1117 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.494949035 Jul 27 04:50:06 PM PDT 24 Jul 27 04:50:07 PM PDT 24 72148844 ps
T1118 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2848219580 Jul 27 04:49:59 PM PDT 24 Jul 27 04:50:21 PM PDT 24 1196878378 ps
T1119 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.2385707297 Jul 27 04:50:16 PM PDT 24 Jul 27 04:50:18 PM PDT 24 372757174 ps
T1120 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.110304496 Jul 27 04:50:42 PM PDT 24 Jul 27 04:50:45 PM PDT 24 97594746 ps
T1121 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1981322070 Jul 27 04:50:27 PM PDT 24 Jul 27 04:50:30 PM PDT 24 1929329271 ps
T1122 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.2392409327 Jul 27 04:50:20 PM PDT 24 Jul 27 04:50:22 PM PDT 24 371136694 ps
T1123 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.3158377771 Jul 27 04:50:01 PM PDT 24 Jul 27 04:50:01 PM PDT 24 58306811 ps
T1124 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.1317290011 Jul 27 04:50:16 PM PDT 24 Jul 27 04:50:18 PM PDT 24 182424297 ps
T1125 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.3103451698 Jul 27 04:50:56 PM PDT 24 Jul 27 04:50:57 PM PDT 24 29975418 ps
T1126 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3243572799 Jul 27 04:49:56 PM PDT 24 Jul 27 04:49:59 PM PDT 24 114711681 ps
T1127 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2673833414 Jul 27 04:49:50 PM PDT 24 Jul 27 04:49:51 PM PDT 24 90156557 ps
T1128 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.330849163 Jul 27 04:50:20 PM PDT 24 Jul 27 04:50:21 PM PDT 24 14925843 ps
T1129 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.2957412580 Jul 27 04:50:16 PM PDT 24 Jul 27 04:50:17 PM PDT 24 52507997 ps
T1130 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3672434910 Jul 27 04:50:13 PM PDT 24 Jul 27 04:50:34 PM PDT 24 302930491 ps
T1131 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.1604579880 Jul 27 04:50:18 PM PDT 24 Jul 27 04:50:19 PM PDT 24 45986654 ps
T1132 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1339806362 Jul 27 04:50:17 PM PDT 24 Jul 27 04:50:24 PM PDT 24 357127659 ps
T1133 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.1934956403 Jul 27 04:50:15 PM PDT 24 Jul 27 04:50:16 PM PDT 24 20624542 ps
T1134 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.112825302 Jul 27 04:50:14 PM PDT 24 Jul 27 04:50:16 PM PDT 24 59334561 ps
T1135 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.1401071106 Jul 27 04:50:14 PM PDT 24 Jul 27 04:50:27 PM PDT 24 515217039 ps
T1136 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.3250790291 Jul 27 04:50:19 PM PDT 24 Jul 27 04:50:23 PM PDT 24 279519718 ps
T1137 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.134627433 Jul 27 04:50:21 PM PDT 24 Jul 27 04:50:22 PM PDT 24 13074815 ps
T1138 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.382535509 Jul 27 04:50:24 PM PDT 24 Jul 27 04:50:24 PM PDT 24 22827074 ps
T1139 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2983122801 Jul 27 04:50:29 PM PDT 24 Jul 27 04:50:33 PM PDT 24 235213858 ps
T1140 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.102717187 Jul 27 04:49:52 PM PDT 24 Jul 27 04:49:52 PM PDT 24 16968309 ps
T1141 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.1229917800 Jul 27 04:50:12 PM PDT 24 Jul 27 04:50:13 PM PDT 24 11940390 ps
T1142 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.849052253 Jul 27 04:50:19 PM PDT 24 Jul 27 04:50:23 PM PDT 24 82378878 ps
T1143 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.835597426 Jul 27 04:49:51 PM PDT 24 Jul 27 04:49:53 PM PDT 24 63826879 ps
T1144 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2758341923 Jul 27 04:50:07 PM PDT 24 Jul 27 04:50:11 PM PDT 24 158053621 ps
T1145 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2697305630 Jul 27 04:50:11 PM PDT 24 Jul 27 04:50:14 PM PDT 24 177199151 ps
T1146 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.302556399 Jul 27 04:50:14 PM PDT 24 Jul 27 04:50:21 PM PDT 24 309885380 ps
T1147 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.563764736 Jul 27 04:50:08 PM PDT 24 Jul 27 04:50:11 PM PDT 24 154231733 ps
T1148 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1330633284 Jul 27 04:50:13 PM PDT 24 Jul 27 04:50:21 PM PDT 24 1310179219 ps
T1149 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.354255806 Jul 27 04:50:19 PM PDT 24 Jul 27 04:50:21 PM PDT 24 41077668 ps

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.2210112002
Short name T1
Test name
Test status
Simulation time 17535008377 ps
CPU time 142.18 seconds
Started Jul 27 04:53:26 PM PDT 24
Finished Jul 27 04:55:48 PM PDT 24
Peak memory 255944 kb
Host smart-5457ecc5-5608-465b-9cb5-692c4468f25a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210112002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.2210112002
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.2742558813
Short name T13
Test name
Test status
Simulation time 7891541118 ps
CPU time 115.57 seconds
Started Jul 27 04:54:26 PM PDT 24
Finished Jul 27 04:56:22 PM PDT 24
Peak memory 265884 kb
Host smart-4f502fd6-7deb-43f8-b8d8-060750818fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742558813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.2742558813
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.111876669
Short name T55
Test name
Test status
Simulation time 10074722638 ps
CPU time 37.99 seconds
Started Jul 27 04:53:53 PM PDT 24
Finished Jul 27 04:54:31 PM PDT 24
Peak memory 233716 kb
Host smart-a98bab7a-1a82-4245-924f-19649f58fde5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111876669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idle
.111876669
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.567458419
Short name T21
Test name
Test status
Simulation time 112809723522 ps
CPU time 237.56 seconds
Started Jul 27 04:53:49 PM PDT 24
Finished Jul 27 04:57:47 PM PDT 24
Peak memory 274636 kb
Host smart-cef9c3cb-9501-4ad3-8e2b-64bb3248648b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567458419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stres
s_all.567458419
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1205138440
Short name T108
Test name
Test status
Simulation time 193825640 ps
CPU time 3.89 seconds
Started Jul 27 04:49:56 PM PDT 24
Finished Jul 27 04:50:00 PM PDT 24
Peak memory 216952 kb
Host smart-1ab12d1b-97d0-40ff-a0f0-eadc29d497bf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205138440 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.1205138440
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.455135319
Short name T7
Test name
Test status
Simulation time 70313600293 ps
CPU time 485.6 seconds
Started Jul 27 04:53:51 PM PDT 24
Finished Jul 27 05:01:57 PM PDT 24
Peak memory 263072 kb
Host smart-8797b151-4d5c-466c-bb70-676a09481c8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455135319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.455135319
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.2880106074
Short name T74
Test name
Test status
Simulation time 28410095 ps
CPU time 0.71 seconds
Started Jul 27 04:51:53 PM PDT 24
Finished Jul 27 04:51:54 PM PDT 24
Peak memory 216788 kb
Host smart-d6b8b65e-d4c4-42b6-8ab3-57c81ebcfe2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880106074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.2880106074
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.1875973909
Short name T15
Test name
Test status
Simulation time 46586414395 ps
CPU time 167.75 seconds
Started Jul 27 04:52:32 PM PDT 24
Finished Jul 27 04:55:20 PM PDT 24
Peak memory 264956 kb
Host smart-64eb389d-4058-4f41-bc39-3ce3459c2bc3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875973909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.1875973909
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.2096960798
Short name T51
Test name
Test status
Simulation time 90427953722 ps
CPU time 412.51 seconds
Started Jul 27 04:52:40 PM PDT 24
Finished Jul 27 04:59:33 PM PDT 24
Peak memory 266076 kb
Host smart-b3d046e5-6d15-4a3b-8c9f-15413fa97b16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096960798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.2096960798
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.405043381
Short name T20
Test name
Test status
Simulation time 56374226069 ps
CPU time 178.49 seconds
Started Jul 27 04:52:04 PM PDT 24
Finished Jul 27 04:55:02 PM PDT 24
Peak memory 256352 kb
Host smart-8a3b6743-1f70-45b2-9fae-857d6df8ac6e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405043381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stress
_all.405043381
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.2605955459
Short name T14
Test name
Test status
Simulation time 194984856 ps
CPU time 1.14 seconds
Started Jul 27 04:52:10 PM PDT 24
Finished Jul 27 04:52:11 PM PDT 24
Peak memory 236940 kb
Host smart-0f41e4e3-7928-4448-ac27-5826b0c570ea
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605955459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.2605955459
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.789681390
Short name T53
Test name
Test status
Simulation time 63797608576 ps
CPU time 274.6 seconds
Started Jul 27 04:53:28 PM PDT 24
Finished Jul 27 04:58:02 PM PDT 24
Peak memory 269740 kb
Host smart-48b47213-0a77-43ea-899c-27804d22a9c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789681390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmds
.789681390
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.3958846171
Short name T197
Test name
Test status
Simulation time 12895456781 ps
CPU time 117.77 seconds
Started Jul 27 04:54:45 PM PDT 24
Finished Jul 27 04:56:43 PM PDT 24
Peak memory 268436 kb
Host smart-4e351e9a-d3b8-41a8-beb7-790f56bcd2e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958846171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.3958846171
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.807713170
Short name T154
Test name
Test status
Simulation time 1609142749 ps
CPU time 28.69 seconds
Started Jul 27 04:53:51 PM PDT 24
Finished Jul 27 04:54:20 PM PDT 24
Peak memory 241840 kb
Host smart-5e4b04b9-fab8-4cde-9be2-13d0af71876c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807713170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.807713170
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.922542248
Short name T163
Test name
Test status
Simulation time 4854264472 ps
CPU time 106.3 seconds
Started Jul 27 04:54:24 PM PDT 24
Finished Jul 27 04:56:10 PM PDT 24
Peak memory 267564 kb
Host smart-3a4106c3-8828-4571-975b-420bfc22e69b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922542248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stres
s_all.922542248
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.367412878
Short name T183
Test name
Test status
Simulation time 1201007735 ps
CPU time 16.5 seconds
Started Jul 27 04:50:10 PM PDT 24
Finished Jul 27 04:50:27 PM PDT 24
Peak memory 216136 kb
Host smart-ac46376b-f882-4fca-a65d-edfea259cdaa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367412878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_
tl_intg_err.367412878
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.369632711
Short name T39
Test name
Test status
Simulation time 31518917365 ps
CPU time 384.44 seconds
Started Jul 27 04:53:10 PM PDT 24
Finished Jul 27 04:59:34 PM PDT 24
Peak memory 274612 kb
Host smart-eabbc2cd-b2a9-4265-9f72-683cc133b8dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369632711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stres
s_all.369632711
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.4249619205
Short name T177
Test name
Test status
Simulation time 30175413155 ps
CPU time 315.46 seconds
Started Jul 27 04:53:23 PM PDT 24
Finished Jul 27 04:58:39 PM PDT 24
Peak memory 257052 kb
Host smart-f9ce9f82-e081-4b83-bbb7-eda2323c815f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249619205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.4249619205
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.401794006
Short name T137
Test name
Test status
Simulation time 4350337249 ps
CPU time 22.89 seconds
Started Jul 27 04:49:56 PM PDT 24
Finished Jul 27 04:50:19 PM PDT 24
Peak memory 207708 kb
Host smart-3845a1d2-71f8-4f9b-9dfb-587411231c73
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401794006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_bit_bash.401794006
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.1812753249
Short name T263
Test name
Test status
Simulation time 14767147276 ps
CPU time 92.26 seconds
Started Jul 27 04:53:28 PM PDT 24
Finished Jul 27 04:55:00 PM PDT 24
Peak memory 267340 kb
Host smart-07d27b15-7ccf-49cb-aa8f-14e6fc4eb418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812753249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.1812753249
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2650425199
Short name T117
Test name
Test status
Simulation time 53455584 ps
CPU time 3.25 seconds
Started Jul 27 04:50:17 PM PDT 24
Finished Jul 27 04:50:21 PM PDT 24
Peak memory 216068 kb
Host smart-366ec44c-f7b8-4d67-98fd-059b7142b27d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650425199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
2650425199
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.3998224056
Short name T486
Test name
Test status
Simulation time 34238075 ps
CPU time 1.07 seconds
Started Jul 27 04:52:37 PM PDT 24
Finished Jul 27 04:52:38 PM PDT 24
Peak memory 218528 kb
Host smart-ffc1537c-3233-4493-abbc-1687f9888841
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998224056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.spi_device_mem_parity.3998224056
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.4209641514
Short name T204
Test name
Test status
Simulation time 3631909175 ps
CPU time 76.08 seconds
Started Jul 27 04:54:14 PM PDT 24
Finished Jul 27 04:55:30 PM PDT 24
Peak memory 258072 kb
Host smart-4c358097-2860-4fc9-8a94-1df527e55a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209641514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmd
s.4209641514
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.3931395081
Short name T16
Test name
Test status
Simulation time 85652368427 ps
CPU time 328.04 seconds
Started Jul 27 04:53:05 PM PDT 24
Finished Jul 27 04:58:34 PM PDT 24
Peak memory 271204 kb
Host smart-a85ffefe-7f5e-4e73-9f36-064f0ad076a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931395081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.3931395081
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.1246839366
Short name T231
Test name
Test status
Simulation time 4528855289 ps
CPU time 62.39 seconds
Started Jul 27 04:53:07 PM PDT 24
Finished Jul 27 04:54:10 PM PDT 24
Peak memory 249976 kb
Host smart-8969f264-3f7c-4ead-b72f-8f9b6861510d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246839366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmd
s.1246839366
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.430290473
Short name T32
Test name
Test status
Simulation time 31115195270 ps
CPU time 302.11 seconds
Started Jul 27 04:54:12 PM PDT 24
Finished Jul 27 04:59:14 PM PDT 24
Peak memory 265400 kb
Host smart-29d752ca-48b2-4e1d-b3a2-e38b308e91f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430290473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.430290473
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.4263276121
Short name T708
Test name
Test status
Simulation time 1069798402581 ps
CPU time 384.51 seconds
Started Jul 27 04:53:50 PM PDT 24
Finished Jul 27 05:00:14 PM PDT 24
Peak memory 273048 kb
Host smart-e4c3dabe-a88f-4cf2-bc10-92ad02b4ea66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263276121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.4263276121
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.320490538
Short name T58
Test name
Test status
Simulation time 14988127442 ps
CPU time 147.34 seconds
Started Jul 27 04:52:33 PM PDT 24
Finished Jul 27 04:55:00 PM PDT 24
Peak memory 251056 kb
Host smart-c27acf21-cd62-452e-8a9b-a3defbea73a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320490538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idle
.320490538
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.2998409895
Short name T40
Test name
Test status
Simulation time 16305209 ps
CPU time 0.7 seconds
Started Jul 27 04:52:04 PM PDT 24
Finished Jul 27 04:52:05 PM PDT 24
Peak memory 205364 kb
Host smart-315b79be-5baa-4f18-835f-dc2a56314d90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998409895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.2
998409895
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.2390357652
Short name T997
Test name
Test status
Simulation time 94953606863 ps
CPU time 342.27 seconds
Started Jul 27 04:54:17 PM PDT 24
Finished Jul 27 04:59:59 PM PDT 24
Peak memory 267960 kb
Host smart-9b05aad1-182b-4356-8aa3-e94a51265a77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390357652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.2390357652
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.2492923023
Short name T294
Test name
Test status
Simulation time 104393026017 ps
CPU time 357.08 seconds
Started Jul 27 04:52:32 PM PDT 24
Finished Jul 27 04:58:29 PM PDT 24
Peak memory 273396 kb
Host smart-de32225a-2cc7-4c6c-8029-2f3862303677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492923023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.2492923023
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.677279514
Short name T201
Test name
Test status
Simulation time 225411323074 ps
CPU time 309.85 seconds
Started Jul 27 04:53:08 PM PDT 24
Finished Jul 27 04:58:18 PM PDT 24
Peak memory 256180 kb
Host smart-f3a0aeb9-70cd-4255-8d8d-a10bb01986c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677279514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmds
.677279514
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.1697822672
Short name T17
Test name
Test status
Simulation time 158249299625 ps
CPU time 133.48 seconds
Started Jul 27 04:52:07 PM PDT 24
Finished Jul 27 04:54:21 PM PDT 24
Peak memory 241928 kb
Host smart-6010e4d3-8fe2-4677-a75b-2a8cf80d49fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697822672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.1697822672
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2551066623
Short name T113
Test name
Test status
Simulation time 139809196 ps
CPU time 3.66 seconds
Started Jul 27 04:50:20 PM PDT 24
Finished Jul 27 04:50:24 PM PDT 24
Peak memory 216076 kb
Host smart-c356b7d5-671d-402d-930d-a356e0f7a3b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551066623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.2
551066623
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.1505062300
Short name T306
Test name
Test status
Simulation time 1283397933 ps
CPU time 11.59 seconds
Started Jul 27 04:52:41 PM PDT 24
Finished Jul 27 04:52:53 PM PDT 24
Peak memory 236288 kb
Host smart-bd15dece-7ba6-44a8-8ce0-b60b84562903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505062300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.1505062300
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.1815263545
Short name T81
Test name
Test status
Simulation time 203704521038 ps
CPU time 294.49 seconds
Started Jul 27 04:52:56 PM PDT 24
Finished Jul 27 04:57:51 PM PDT 24
Peak memory 252012 kb
Host smart-c7ea77e6-0765-42cc-b473-2d920255a2bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815263545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.1815263545
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.2393579580
Short name T254
Test name
Test status
Simulation time 6807214603 ps
CPU time 112.83 seconds
Started Jul 27 04:53:11 PM PDT 24
Finished Jul 27 04:55:04 PM PDT 24
Peak memory 252940 kb
Host smart-7fbaf4f0-8692-4b8d-ba30-894cbac316dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393579580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.2393579580
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.708159641
Short name T292
Test name
Test status
Simulation time 31287810193 ps
CPU time 307.54 seconds
Started Jul 27 04:52:58 PM PDT 24
Finished Jul 27 04:58:06 PM PDT 24
Peak memory 257564 kb
Host smart-218124d1-a3f9-4680-b51c-8ece876f9b05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708159641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.708159641
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.406027663
Short name T94
Test name
Test status
Simulation time 73084593713 ps
CPU time 518.54 seconds
Started Jul 27 04:53:31 PM PDT 24
Finished Jul 27 05:02:10 PM PDT 24
Peak memory 266524 kb
Host smart-40d9a966-0786-4d3e-8406-9511665d7d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406027663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmds
.406027663
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.3848783015
Short name T101
Test name
Test status
Simulation time 565895395 ps
CPU time 15.26 seconds
Started Jul 27 04:50:13 PM PDT 24
Finished Jul 27 04:50:29 PM PDT 24
Peak memory 215944 kb
Host smart-a5552c8a-0a4e-4938-90fc-a627eeb8b3e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848783015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.3848783015
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.1171790611
Short name T84
Test name
Test status
Simulation time 8899106481 ps
CPU time 87.24 seconds
Started Jul 27 04:52:57 PM PDT 24
Finished Jul 27 04:54:25 PM PDT 24
Peak memory 266444 kb
Host smart-8cbbcb74-5a2b-4871-9079-2d1e2350d927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171790611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmd
s.1171790611
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.1475099351
Short name T207
Test name
Test status
Simulation time 9655739405 ps
CPU time 110.5 seconds
Started Jul 27 04:53:35 PM PDT 24
Finished Jul 27 04:55:25 PM PDT 24
Peak memory 256724 kb
Host smart-883ad684-44e5-4f01-b919-bbc933a638cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475099351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.1475099351
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.355624356
Short name T212
Test name
Test status
Simulation time 5599673619 ps
CPU time 63.01 seconds
Started Jul 27 04:53:50 PM PDT 24
Finished Jul 27 04:54:53 PM PDT 24
Peak memory 255740 kb
Host smart-a207e855-fcee-4439-b727-72b52c594afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355624356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.355624356
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.759808681
Short name T238
Test name
Test status
Simulation time 26381775675 ps
CPU time 65.18 seconds
Started Jul 27 04:54:13 PM PDT 24
Finished Jul 27 04:55:19 PM PDT 24
Peak memory 251472 kb
Host smart-bef92f34-3d21-4f48-8cc5-b8561b0ed313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759808681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.759808681
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.419139387
Short name T123
Test name
Test status
Simulation time 130374468 ps
CPU time 2.2 seconds
Started Jul 27 04:49:58 PM PDT 24
Finished Jul 27 04:50:01 PM PDT 24
Peak memory 216100 kb
Host smart-368d7730-c28e-47de-87a0-9fce3006f3ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419139387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.419139387
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.183056302
Short name T105
Test name
Test status
Simulation time 802260741 ps
CPU time 21.99 seconds
Started Jul 27 04:49:52 PM PDT 24
Finished Jul 27 04:50:19 PM PDT 24
Peak memory 215880 kb
Host smart-ef2445d7-3df0-41bf-b729-543fef63f3e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183056302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_
tl_intg_err.183056302
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.3844418521
Short name T181
Test name
Test status
Simulation time 17629944009 ps
CPU time 76.95 seconds
Started Jul 27 04:51:59 PM PDT 24
Finished Jul 27 04:53:16 PM PDT 24
Peak memory 255732 kb
Host smart-aa6fb7f0-51da-46e2-a18d-fad399413313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844418521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.3844418521
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.1809979952
Short name T313
Test name
Test status
Simulation time 64131187 ps
CPU time 4.41 seconds
Started Jul 27 04:52:43 PM PDT 24
Finished Jul 27 04:52:47 PM PDT 24
Peak memory 233552 kb
Host smart-71ea722d-6c6c-4126-828a-65004e2bd880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809979952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.1809979952
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.1122342211
Short name T984
Test name
Test status
Simulation time 312834282 ps
CPU time 5.25 seconds
Started Jul 27 04:52:42 PM PDT 24
Finished Jul 27 04:52:47 PM PDT 24
Peak memory 233528 kb
Host smart-586b9f18-fbf7-46ce-9935-2384dc64ada2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122342211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.1122342211
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.2175955326
Short name T182
Test name
Test status
Simulation time 23828601078 ps
CPU time 211.38 seconds
Started Jul 27 04:52:57 PM PDT 24
Finished Jul 27 04:56:29 PM PDT 24
Peak memory 250032 kb
Host smart-078f5ab7-f8a5-489f-a420-01505fff8b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175955326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.2175955326
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.28589972
Short name T43
Test name
Test status
Simulation time 17165576083 ps
CPU time 78.98 seconds
Started Jul 27 04:53:49 PM PDT 24
Finished Jul 27 04:55:09 PM PDT 24
Peak memory 266540 kb
Host smart-46e2a937-2805-4c1c-b4c0-577656ac0909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28589972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idle.28589972
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_intercept.3976221420
Short name T23
Test name
Test status
Simulation time 452064886 ps
CPU time 3.62 seconds
Started Jul 27 04:53:25 PM PDT 24
Finished Jul 27 04:53:29 PM PDT 24
Peak memory 225372 kb
Host smart-bf31410d-da53-4bc4-bbac-001d9dbb0a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976221420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.3976221420
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2615891702
Short name T86
Test name
Test status
Simulation time 125401872 ps
CPU time 1.18 seconds
Started Jul 27 04:49:51 PM PDT 24
Finished Jul 27 04:49:52 PM PDT 24
Peak memory 207464 kb
Host smart-c2e3d251-6bda-44c9-bcd3-8b861473edce
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615891702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.2615891702
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.2449414438
Short name T1112
Test name
Test status
Simulation time 751167166 ps
CPU time 4.5 seconds
Started Jul 27 04:49:51 PM PDT 24
Finished Jul 27 04:49:56 PM PDT 24
Peak memory 215976 kb
Host smart-36be524a-065e-4ce8-ac5b-7d42ef79dc27
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449414438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.2
449414438
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.3168105109
Short name T106
Test name
Test status
Simulation time 857524052 ps
CPU time 23.5 seconds
Started Jul 27 04:50:15 PM PDT 24
Finished Jul 27 04:50:39 PM PDT 24
Peak memory 215904 kb
Host smart-dc7dbd49-15df-4990-8067-974b042f032c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168105109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.3168105109
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1109719164
Short name T142
Test name
Test status
Simulation time 1754821402 ps
CPU time 14.46 seconds
Started Jul 27 04:49:59 PM PDT 24
Finished Jul 27 04:50:14 PM PDT 24
Peak memory 207552 kb
Host smart-5d8ebfb9-3aa5-401b-adc4-b12eea943f4d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109719164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.1109719164
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.649795967
Short name T1113
Test name
Test status
Simulation time 1881480442 ps
CPU time 27.08 seconds
Started Jul 27 04:50:30 PM PDT 24
Finished Jul 27 04:50:57 PM PDT 24
Peak memory 207760 kb
Host smart-f131bc68-312e-4831-a9ac-843ef09a863c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649795967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_bit_bash.649795967
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2673833414
Short name T1127
Test name
Test status
Simulation time 90156557 ps
CPU time 0.96 seconds
Started Jul 27 04:49:50 PM PDT 24
Finished Jul 27 04:49:51 PM PDT 24
Peak memory 207344 kb
Host smart-7c3cbb7c-9443-48f6-ac36-e8bafef5a12e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673833414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.2673833414
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1141869028
Short name T127
Test name
Test status
Simulation time 100566054 ps
CPU time 3.02 seconds
Started Jul 27 04:50:03 PM PDT 24
Finished Jul 27 04:50:07 PM PDT 24
Peak memory 217236 kb
Host smart-0481c9b7-9d40-4bfb-9ace-d909351d7b16
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141869028 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.1141869028
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2236978692
Short name T132
Test name
Test status
Simulation time 113310622 ps
CPU time 1.33 seconds
Started Jul 27 04:49:53 PM PDT 24
Finished Jul 27 04:49:55 PM PDT 24
Peak memory 215740 kb
Host smart-add8451a-3fa6-45c3-8674-13eda103382d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236978692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.2
236978692
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.132854712
Short name T1044
Test name
Test status
Simulation time 14347343 ps
CPU time 0.75 seconds
Started Jul 27 04:50:22 PM PDT 24
Finished Jul 27 04:50:23 PM PDT 24
Peak memory 204300 kb
Host smart-3214f7bb-89d8-4ab3-bbdc-ee9a80895bb3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132854712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.132854712
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.2763970776
Short name T1099
Test name
Test status
Simulation time 45886202 ps
CPU time 1.61 seconds
Started Jul 27 04:49:52 PM PDT 24
Finished Jul 27 04:49:53 PM PDT 24
Peak memory 215876 kb
Host smart-6792896b-5536-42f5-836c-af6074205515
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763970776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.2763970776
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.2282306444
Short name T1042
Test name
Test status
Simulation time 11368156 ps
CPU time 0.7 seconds
Started Jul 27 04:50:04 PM PDT 24
Finished Jul 27 04:50:05 PM PDT 24
Peak memory 204200 kb
Host smart-b08e3219-1055-4193-9564-a360037a5e3b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282306444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.2282306444
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3155857023
Short name T1037
Test name
Test status
Simulation time 166266834 ps
CPU time 2.76 seconds
Started Jul 27 04:49:58 PM PDT 24
Finished Jul 27 04:50:00 PM PDT 24
Peak memory 215836 kb
Host smart-e44b8a64-9c7b-45ec-8e91-6f8413a00974
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155857023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.3155857023
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.987613926
Short name T102
Test name
Test status
Simulation time 1564553059 ps
CPU time 21.6 seconds
Started Jul 27 04:49:56 PM PDT 24
Finished Jul 27 04:50:18 PM PDT 24
Peak memory 215468 kb
Host smart-6bd5ac12-cfd9-4da6-aae2-329c7e31d388
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987613926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_
tl_intg_err.987613926
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.2796159102
Short name T1110
Test name
Test status
Simulation time 304877856 ps
CPU time 20.66 seconds
Started Jul 27 04:49:58 PM PDT 24
Finished Jul 27 04:50:19 PM PDT 24
Peak memory 215888 kb
Host smart-4de5966f-2666-4716-a170-9f3afe72a924
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796159102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.2796159102
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3061362112
Short name T1049
Test name
Test status
Simulation time 44542872 ps
CPU time 3.44 seconds
Started Jul 27 04:50:03 PM PDT 24
Finished Jul 27 04:50:07 PM PDT 24
Peak memory 217296 kb
Host smart-b5b6e300-de2f-4999-81af-ce0136c07af0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061362112 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.3061362112
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3243572799
Short name T1126
Test name
Test status
Simulation time 114711681 ps
CPU time 2.72 seconds
Started Jul 27 04:49:56 PM PDT 24
Finished Jul 27 04:49:59 PM PDT 24
Peak memory 215788 kb
Host smart-4345c0ea-2d9d-4279-a5e9-b89a7b253784
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243572799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.3
243572799
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.1663751253
Short name T1067
Test name
Test status
Simulation time 15120228 ps
CPU time 0.69 seconds
Started Jul 27 04:49:52 PM PDT 24
Finished Jul 27 04:49:53 PM PDT 24
Peak memory 204572 kb
Host smart-a608ebec-0587-4f3b-b326-f7b4d69a5feb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663751253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.1
663751253
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2116975706
Short name T143
Test name
Test status
Simulation time 53852545 ps
CPU time 1.72 seconds
Started Jul 27 04:49:51 PM PDT 24
Finished Jul 27 04:49:53 PM PDT 24
Peak memory 215872 kb
Host smart-a5472cfd-f1d6-4728-b3a7-6d1af0583a0c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116975706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.2116975706
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.2109072354
Short name T1092
Test name
Test status
Simulation time 26652737 ps
CPU time 0.65 seconds
Started Jul 27 04:49:50 PM PDT 24
Finished Jul 27 04:49:51 PM PDT 24
Peak memory 204180 kb
Host smart-39a92af4-6dc5-42b1-90d3-2e0e90d4c48f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109072354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.2109072354
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3341495984
Short name T1050
Test name
Test status
Simulation time 176285558 ps
CPU time 2.88 seconds
Started Jul 27 04:50:04 PM PDT 24
Finished Jul 27 04:50:07 PM PDT 24
Peak memory 215916 kb
Host smart-e7a60949-29b5-42ba-918c-2074b64abd6f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341495984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.3341495984
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3785667666
Short name T100
Test name
Test status
Simulation time 201510554 ps
CPU time 1.67 seconds
Started Jul 27 04:50:38 PM PDT 24
Finished Jul 27 04:50:40 PM PDT 24
Peak memory 215956 kb
Host smart-287595ba-f4d5-4eb5-9594-810a8e69b637
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785667666 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.3785667666
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3562357618
Short name T1108
Test name
Test status
Simulation time 22171305 ps
CPU time 1.34 seconds
Started Jul 27 04:50:32 PM PDT 24
Finished Jul 27 04:50:33 PM PDT 24
Peak memory 207616 kb
Host smart-16440e38-8a55-475c-aa9f-9c23d68af7a2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562357618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
3562357618
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.221063887
Short name T1095
Test name
Test status
Simulation time 41746388 ps
CPU time 0.72 seconds
Started Jul 27 04:50:26 PM PDT 24
Finished Jul 27 04:50:27 PM PDT 24
Peak memory 204320 kb
Host smart-39fd9349-7432-4f57-8db5-896069b8822f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221063887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.221063887
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1147918635
Short name T1096
Test name
Test status
Simulation time 106510534 ps
CPU time 1.84 seconds
Started Jul 27 04:50:13 PM PDT 24
Finished Jul 27 04:50:15 PM PDT 24
Peak memory 216220 kb
Host smart-11ea5ce9-1cbb-4292-9b21-972f4b34b947
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147918635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.1147918635
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.3472745512
Short name T103
Test name
Test status
Simulation time 33786143 ps
CPU time 1.87 seconds
Started Jul 27 04:50:12 PM PDT 24
Finished Jul 27 04:50:14 PM PDT 24
Peak memory 216080 kb
Host smart-a5632cf4-1ac2-4ba3-81de-f935a35ce36f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472745512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
3472745512
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.302556399
Short name T1146
Test name
Test status
Simulation time 309885380 ps
CPU time 7.04 seconds
Started Jul 27 04:50:14 PM PDT 24
Finished Jul 27 04:50:21 PM PDT 24
Peak memory 215932 kb
Host smart-cfdea515-c0d2-4082-9d06-e4e299e8f715
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302556399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device
_tl_intg_err.302556399
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.373941263
Short name T104
Test name
Test status
Simulation time 104266057 ps
CPU time 2.52 seconds
Started Jul 27 04:50:31 PM PDT 24
Finished Jul 27 04:50:34 PM PDT 24
Peak memory 216884 kb
Host smart-52f2ae79-e963-4441-a2af-f0df27efb4d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373941263 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.373941263
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.110304496
Short name T1120
Test name
Test status
Simulation time 97594746 ps
CPU time 1.96 seconds
Started Jul 27 04:50:42 PM PDT 24
Finished Jul 27 04:50:45 PM PDT 24
Peak memory 215820 kb
Host smart-d1e9a93b-90fa-4d0d-adea-c38c6fd53e58
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110304496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.110304496
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.494949035
Short name T1117
Test name
Test status
Simulation time 72148844 ps
CPU time 0.67 seconds
Started Jul 27 04:50:06 PM PDT 24
Finished Jul 27 04:50:07 PM PDT 24
Peak memory 204324 kb
Host smart-f7e2af58-fb13-4748-9f10-5b7424c2da42
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494949035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.494949035
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.563764736
Short name T1147
Test name
Test status
Simulation time 154231733 ps
CPU time 2.74 seconds
Started Jul 27 04:50:08 PM PDT 24
Finished Jul 27 04:50:11 PM PDT 24
Peak memory 215612 kb
Host smart-fb93d763-0a50-42cc-8be6-0da65763b2c8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563764736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.s
pi_device_same_csr_outstanding.563764736
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3232276775
Short name T116
Test name
Test status
Simulation time 258143150 ps
CPU time 4.2 seconds
Started Jul 27 04:50:24 PM PDT 24
Finished Jul 27 04:50:28 PM PDT 24
Peak memory 216016 kb
Host smart-fa25d94c-d6de-4895-adce-51998f5ce143
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232276775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
3232276775
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.4118060220
Short name T1094
Test name
Test status
Simulation time 6266153218 ps
CPU time 20.88 seconds
Started Jul 27 04:50:17 PM PDT 24
Finished Jul 27 04:50:39 PM PDT 24
Peak memory 217320 kb
Host smart-f6df1b27-a065-4353-8f6d-c3c8ae77435a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118060220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.4118060220
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.1452399911
Short name T114
Test name
Test status
Simulation time 110993582 ps
CPU time 3.67 seconds
Started Jul 27 04:50:17 PM PDT 24
Finished Jul 27 04:50:22 PM PDT 24
Peak memory 218568 kb
Host smart-3f45c14f-c40b-489f-b971-6f472a8a5ae2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452399911 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.1452399911
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.1263503457
Short name T1109
Test name
Test status
Simulation time 73564807 ps
CPU time 2.5 seconds
Started Jul 27 04:50:25 PM PDT 24
Finished Jul 27 04:50:27 PM PDT 24
Peak memory 215780 kb
Host smart-8f6d152f-26e8-4a3c-851f-48c31900eb7b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263503457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
1263503457
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.276442727
Short name T1032
Test name
Test status
Simulation time 17353767 ps
CPU time 0.8 seconds
Started Jul 27 04:50:14 PM PDT 24
Finished Jul 27 04:50:14 PM PDT 24
Peak memory 204308 kb
Host smart-55baf773-fef4-4685-ad21-5ea7020e18d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276442727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.276442727
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.4073318788
Short name T148
Test name
Test status
Simulation time 58891875 ps
CPU time 1.8 seconds
Started Jul 27 04:50:13 PM PDT 24
Finished Jul 27 04:50:15 PM PDT 24
Peak memory 215800 kb
Host smart-f72bfa11-6cac-4c83-90e3-7ae65f4a75f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073318788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.4073318788
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3090432295
Short name T1116
Test name
Test status
Simulation time 222116348 ps
CPU time 2.94 seconds
Started Jul 27 04:50:32 PM PDT 24
Finished Jul 27 04:50:35 PM PDT 24
Peak memory 216240 kb
Host smart-aafc701d-3356-439b-b7c5-50082ad54f9c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090432295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
3090432295
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.2329574904
Short name T1077
Test name
Test status
Simulation time 419407415 ps
CPU time 13.15 seconds
Started Jul 27 04:50:32 PM PDT 24
Finished Jul 27 04:50:45 PM PDT 24
Peak memory 215832 kb
Host smart-1291021b-1cf1-4362-81bf-5fd7c7ce44c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329574904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.2329574904
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2697305630
Short name T1145
Test name
Test status
Simulation time 177199151 ps
CPU time 1.71 seconds
Started Jul 27 04:50:11 PM PDT 24
Finished Jul 27 04:50:14 PM PDT 24
Peak memory 216184 kb
Host smart-4765c369-8839-4308-a5cc-1d496760e129
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697305630 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.2697305630
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.2392409327
Short name T1122
Test name
Test status
Simulation time 371136694 ps
CPU time 2.21 seconds
Started Jul 27 04:50:20 PM PDT 24
Finished Jul 27 04:50:22 PM PDT 24
Peak memory 207660 kb
Host smart-5d07cf6b-2cc8-401a-b7c0-6087e7e1fe82
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392409327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
2392409327
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3661755284
Short name T1039
Test name
Test status
Simulation time 53592066 ps
CPU time 0.72 seconds
Started Jul 27 04:50:42 PM PDT 24
Finished Jul 27 04:50:42 PM PDT 24
Peak memory 204672 kb
Host smart-ffad803f-8ea1-47fc-ae32-09b6f512cb1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661755284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
3661755284
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.4227989183
Short name T1038
Test name
Test status
Simulation time 62276474 ps
CPU time 1.92 seconds
Started Jul 27 04:50:23 PM PDT 24
Finished Jul 27 04:50:25 PM PDT 24
Peak memory 215788 kb
Host smart-431638ea-327b-471e-95b8-f0920514007d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227989183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.4227989183
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.4174206325
Short name T186
Test name
Test status
Simulation time 284400586 ps
CPU time 18.22 seconds
Started Jul 27 04:50:05 PM PDT 24
Finished Jul 27 04:50:24 PM PDT 24
Peak memory 215852 kb
Host smart-8fd5b389-5753-47d9-baca-97554de38f37
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174206325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.4174206325
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.79630929
Short name T125
Test name
Test status
Simulation time 101789523 ps
CPU time 3.85 seconds
Started Jul 27 04:50:13 PM PDT 24
Finished Jul 27 04:50:17 PM PDT 24
Peak memory 218060 kb
Host smart-dc863e91-ac99-464b-b80c-c3b67e359770
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79630929 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.79630929
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.3691193411
Short name T141
Test name
Test status
Simulation time 37607436 ps
CPU time 2.65 seconds
Started Jul 27 04:50:29 PM PDT 24
Finished Jul 27 04:50:31 PM PDT 24
Peak memory 215900 kb
Host smart-d46ac2be-b418-49f9-aaad-a2f9a44839e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691193411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
3691193411
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.1604579880
Short name T1131
Test name
Test status
Simulation time 45986654 ps
CPU time 0.68 seconds
Started Jul 27 04:50:18 PM PDT 24
Finished Jul 27 04:50:19 PM PDT 24
Peak memory 204716 kb
Host smart-76025ced-196f-4b83-8ac5-5e9d26be9410
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604579880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
1604579880
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.4206245152
Short name T1047
Test name
Test status
Simulation time 64024695 ps
CPU time 3.68 seconds
Started Jul 27 04:50:14 PM PDT 24
Finished Jul 27 04:50:18 PM PDT 24
Peak memory 215740 kb
Host smart-5ec06734-49f5-4103-945b-045a9d00551e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206245152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.4206245152
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.1360863136
Short name T119
Test name
Test status
Simulation time 319601274 ps
CPU time 1.8 seconds
Started Jul 27 04:50:26 PM PDT 24
Finished Jul 27 04:50:27 PM PDT 24
Peak memory 216120 kb
Host smart-7bd4903a-a492-4dd0-bd80-b86a9b3ba225
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360863136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
1360863136
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2788022540
Short name T1060
Test name
Test status
Simulation time 149810700 ps
CPU time 2.46 seconds
Started Jul 27 04:50:19 PM PDT 24
Finished Jul 27 04:50:21 PM PDT 24
Peak memory 217328 kb
Host smart-e16f2a42-6b93-4561-9904-be34acdd4e45
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788022540 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.2788022540
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.2877890589
Short name T133
Test name
Test status
Simulation time 339213257 ps
CPU time 2.06 seconds
Started Jul 27 04:50:29 PM PDT 24
Finished Jul 27 04:50:31 PM PDT 24
Peak memory 215924 kb
Host smart-489eee81-7be4-44ca-a147-434515f3793d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877890589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
2877890589
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.3588459670
Short name T1054
Test name
Test status
Simulation time 13736843 ps
CPU time 0.71 seconds
Started Jul 27 04:50:17 PM PDT 24
Finished Jul 27 04:50:17 PM PDT 24
Peak memory 204616 kb
Host smart-efbda959-e91e-4ee5-bfa2-dca2a069a3c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588459670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
3588459670
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.1344378605
Short name T149
Test name
Test status
Simulation time 80314545 ps
CPU time 2.58 seconds
Started Jul 27 04:50:11 PM PDT 24
Finished Jul 27 04:50:14 PM PDT 24
Peak memory 215752 kb
Host smart-6d4d3f75-a231-45b2-ba42-aec4ebeef7da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344378605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.1344378605
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.1557648603
Short name T107
Test name
Test status
Simulation time 636176373 ps
CPU time 4.54 seconds
Started Jul 27 04:50:20 PM PDT 24
Finished Jul 27 04:50:25 PM PDT 24
Peak memory 216048 kb
Host smart-9d10879d-f5f7-402f-bb32-9846e8670f73
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557648603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
1557648603
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1493063581
Short name T1073
Test name
Test status
Simulation time 204647196 ps
CPU time 12.39 seconds
Started Jul 27 04:50:02 PM PDT 24
Finished Jul 27 04:50:14 PM PDT 24
Peak memory 215868 kb
Host smart-5bbe1a27-650c-46d1-ba5a-f1b9e87c617e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493063581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.1493063581
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.2249357987
Short name T124
Test name
Test status
Simulation time 276180370 ps
CPU time 2.74 seconds
Started Jul 27 04:50:20 PM PDT 24
Finished Jul 27 04:50:23 PM PDT 24
Peak memory 217716 kb
Host smart-0a50fcff-7411-4e36-9847-c9a5695e738e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249357987 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.2249357987
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.1994459583
Short name T159
Test name
Test status
Simulation time 46328107 ps
CPU time 1.33 seconds
Started Jul 27 04:50:35 PM PDT 24
Finished Jul 27 04:50:36 PM PDT 24
Peak memory 207728 kb
Host smart-ca0dbbf8-42df-42da-b3e5-9a2e486c604c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994459583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
1994459583
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.4060117733
Short name T1062
Test name
Test status
Simulation time 12682473 ps
CPU time 0.74 seconds
Started Jul 27 04:50:18 PM PDT 24
Finished Jul 27 04:50:19 PM PDT 24
Peak memory 204316 kb
Host smart-8cd46dc7-4c0e-4273-8611-cce141d78ed1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060117733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
4060117733
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3361360636
Short name T157
Test name
Test status
Simulation time 144268766 ps
CPU time 3.1 seconds
Started Jul 27 04:50:08 PM PDT 24
Finished Jul 27 04:50:11 PM PDT 24
Peak memory 207520 kb
Host smart-e6d9b882-d7b7-41f7-88bc-b07a6966456f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361360636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.3361360636
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.1165339454
Short name T1111
Test name
Test status
Simulation time 543727140 ps
CPU time 2.67 seconds
Started Jul 27 04:50:12 PM PDT 24
Finished Jul 27 04:50:15 PM PDT 24
Peak memory 216068 kb
Host smart-45ed7b3d-8c90-498d-b27e-460aaa0c18ec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165339454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
1165339454
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1330633284
Short name T1148
Test name
Test status
Simulation time 1310179219 ps
CPU time 7.71 seconds
Started Jul 27 04:50:13 PM PDT 24
Finished Jul 27 04:50:21 PM PDT 24
Peak memory 216108 kb
Host smart-926c1daa-af92-441c-be5c-46637da8ab40
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330633284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.1330633284
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1457955760
Short name T1100
Test name
Test status
Simulation time 23021384 ps
CPU time 1.43 seconds
Started Jul 27 04:50:19 PM PDT 24
Finished Jul 27 04:50:21 PM PDT 24
Peak memory 215880 kb
Host smart-fd05045b-aeb8-4240-9633-be958ac41294
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457955760 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.1457955760
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.3003467293
Short name T1098
Test name
Test status
Simulation time 177486540 ps
CPU time 2.72 seconds
Started Jul 27 04:50:16 PM PDT 24
Finished Jul 27 04:50:19 PM PDT 24
Peak memory 207712 kb
Host smart-7ba2b969-8db5-437d-9d2f-8e98b4ac32c4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003467293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
3003467293
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.330849163
Short name T1128
Test name
Test status
Simulation time 14925843 ps
CPU time 0.69 seconds
Started Jul 27 04:50:20 PM PDT 24
Finished Jul 27 04:50:21 PM PDT 24
Peak memory 204324 kb
Host smart-4d62bf47-af26-46d1-99b8-839466b091a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330849163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.330849163
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2983122801
Short name T1139
Test name
Test status
Simulation time 235213858 ps
CPU time 3.85 seconds
Started Jul 27 04:50:29 PM PDT 24
Finished Jul 27 04:50:33 PM PDT 24
Peak memory 215868 kb
Host smart-5da30134-e680-48a0-b36f-2f49b3b03bde
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983122801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.2983122801
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.2057913408
Short name T115
Test name
Test status
Simulation time 143497063 ps
CPU time 2.12 seconds
Started Jul 27 04:50:17 PM PDT 24
Finished Jul 27 04:50:19 PM PDT 24
Peak memory 216040 kb
Host smart-b9c7d829-c43e-41a5-b36c-c86f0ec1727b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057913408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
2057913408
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1339806362
Short name T1132
Test name
Test status
Simulation time 357127659 ps
CPU time 6.64 seconds
Started Jul 27 04:50:17 PM PDT 24
Finished Jul 27 04:50:24 PM PDT 24
Peak memory 215836 kb
Host smart-419a4e08-63a4-40c3-97a5-d2669e9790e9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339806362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.1339806362
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.4217770033
Short name T1085
Test name
Test status
Simulation time 200689740 ps
CPU time 1.74 seconds
Started Jul 27 04:50:17 PM PDT 24
Finished Jul 27 04:50:19 PM PDT 24
Peak memory 215900 kb
Host smart-6dffdf2a-d76d-42f7-b3da-4c17adf9da74
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217770033 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.4217770033
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.2764049103
Short name T1082
Test name
Test status
Simulation time 91838194 ps
CPU time 2.4 seconds
Started Jul 27 04:50:11 PM PDT 24
Finished Jul 27 04:50:13 PM PDT 24
Peak memory 207636 kb
Host smart-af4862f1-6104-4bf1-80d1-3af80435797a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764049103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
2764049103
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.134627433
Short name T1137
Test name
Test status
Simulation time 13074815 ps
CPU time 0.71 seconds
Started Jul 27 04:50:21 PM PDT 24
Finished Jul 27 04:50:22 PM PDT 24
Peak memory 204364 kb
Host smart-5184396e-07f8-40e2-9296-2c8f435396bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134627433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.134627433
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1981322070
Short name T1121
Test name
Test status
Simulation time 1929329271 ps
CPU time 2.98 seconds
Started Jul 27 04:50:27 PM PDT 24
Finished Jul 27 04:50:30 PM PDT 24
Peak memory 215904 kb
Host smart-5cd14fbc-f988-433a-b835-75469578cc17
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981322070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.1981322070
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.464708617
Short name T1105
Test name
Test status
Simulation time 878944554 ps
CPU time 4.9 seconds
Started Jul 27 04:50:25 PM PDT 24
Finished Jul 27 04:50:35 PM PDT 24
Peak memory 217108 kb
Host smart-3897f015-a5bc-490e-afa8-2cce3af52c18
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464708617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.464708617
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.2492647043
Short name T185
Test name
Test status
Simulation time 978618421 ps
CPU time 12.5 seconds
Started Jul 27 04:50:12 PM PDT 24
Finished Jul 27 04:50:25 PM PDT 24
Peak memory 217648 kb
Host smart-d1e82c2d-df62-426b-9965-d46ea364d7ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492647043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.2492647043
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2795659116
Short name T1089
Test name
Test status
Simulation time 272387975 ps
CPU time 1.67 seconds
Started Jul 27 04:50:12 PM PDT 24
Finished Jul 27 04:50:14 PM PDT 24
Peak memory 216080 kb
Host smart-5f2e2dc1-bdb2-48f0-836d-46aa063aecbe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795659116 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.2795659116
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1051667174
Short name T144
Test name
Test status
Simulation time 146489236 ps
CPU time 1.4 seconds
Started Jul 27 04:50:15 PM PDT 24
Finished Jul 27 04:50:17 PM PDT 24
Peak memory 207576 kb
Host smart-2636ccc7-1e69-4c7a-8c51-1478af7108ab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051667174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
1051667174
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2682111491
Short name T1043
Test name
Test status
Simulation time 64813687 ps
CPU time 0.78 seconds
Started Jul 27 04:50:13 PM PDT 24
Finished Jul 27 04:50:14 PM PDT 24
Peak memory 204340 kb
Host smart-10cbf968-3b62-40cd-8d40-0a02391a000a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682111491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
2682111491
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.246720530
Short name T1069
Test name
Test status
Simulation time 132364598 ps
CPU time 2.9 seconds
Started Jul 27 04:50:11 PM PDT 24
Finished Jul 27 04:50:14 PM PDT 24
Peak memory 215824 kb
Host smart-d4f46742-e4f0-4257-8029-3cf235896b2f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246720530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.s
pi_device_same_csr_outstanding.246720530
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.3878085688
Short name T120
Test name
Test status
Simulation time 270207838 ps
CPU time 3.68 seconds
Started Jul 27 04:50:17 PM PDT 24
Finished Jul 27 04:50:21 PM PDT 24
Peak memory 216144 kb
Host smart-12403eb5-b8da-448a-9aaf-07cf1ba20e9c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878085688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
3878085688
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2848219580
Short name T1118
Test name
Test status
Simulation time 1196878378 ps
CPU time 21.32 seconds
Started Jul 27 04:49:59 PM PDT 24
Finished Jul 27 04:50:21 PM PDT 24
Peak memory 215872 kb
Host smart-ed94512a-1cb6-435b-af9e-3c0c408ebf7e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848219580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.2848219580
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3560166525
Short name T1097
Test name
Test status
Simulation time 15037908077 ps
CPU time 13.93 seconds
Started Jul 27 04:49:50 PM PDT 24
Finished Jul 27 04:50:04 PM PDT 24
Peak memory 207800 kb
Host smart-09e47b13-008f-4981-b281-0bd27aafdace
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560166525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.3560166525
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1520837506
Short name T88
Test name
Test status
Simulation time 44399651 ps
CPU time 1.02 seconds
Started Jul 27 04:50:01 PM PDT 24
Finished Jul 27 04:50:03 PM PDT 24
Peak memory 207444 kb
Host smart-7960a03d-3a13-4fbe-89b5-81e64a376079
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520837506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.1520837506
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.835597426
Short name T1143
Test name
Test status
Simulation time 63826879 ps
CPU time 1.79 seconds
Started Jul 27 04:49:51 PM PDT 24
Finished Jul 27 04:49:53 PM PDT 24
Peak memory 215784 kb
Host smart-1e46bd98-9519-4a45-84fd-ec2a37f9aa17
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835597426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.835597426
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.3586220417
Short name T1056
Test name
Test status
Simulation time 12633308 ps
CPU time 0.71 seconds
Started Jul 27 04:50:06 PM PDT 24
Finished Jul 27 04:50:07 PM PDT 24
Peak memory 204648 kb
Host smart-7762bda5-922b-41f1-83e2-86a63604cf2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586220417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.3
586220417
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.3580700130
Short name T139
Test name
Test status
Simulation time 151817059 ps
CPU time 1.22 seconds
Started Jul 27 04:50:05 PM PDT 24
Finished Jul 27 04:50:06 PM PDT 24
Peak memory 215840 kb
Host smart-4f55333d-9d03-4e84-9bec-264698bb8713
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580700130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.3580700130
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.102717187
Short name T1140
Test name
Test status
Simulation time 16968309 ps
CPU time 0.7 seconds
Started Jul 27 04:49:52 PM PDT 24
Finished Jul 27 04:49:52 PM PDT 24
Peak memory 204184 kb
Host smart-d3115b25-d5d8-4fbb-9ef2-3d2c3858383c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102717187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_mem
_walk.102717187
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.112825302
Short name T1134
Test name
Test status
Simulation time 59334561 ps
CPU time 1.83 seconds
Started Jul 27 04:50:14 PM PDT 24
Finished Jul 27 04:50:16 PM PDT 24
Peak memory 207672 kb
Host smart-c5d26936-2313-4f12-9d07-0e0a050323b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112825302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sp
i_device_same_csr_outstanding.112825302
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3004364549
Short name T112
Test name
Test status
Simulation time 307610206 ps
CPU time 3.11 seconds
Started Jul 27 04:49:54 PM PDT 24
Finished Jul 27 04:49:57 PM PDT 24
Peak memory 216040 kb
Host smart-16944131-6081-4719-845c-a6c4988efe12
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004364549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.3
004364549
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.3085668270
Short name T1101
Test name
Test status
Simulation time 2551450175 ps
CPU time 21.08 seconds
Started Jul 27 04:50:01 PM PDT 24
Finished Jul 27 04:50:22 PM PDT 24
Peak memory 215872 kb
Host smart-88d1edc9-2661-4aa2-b8f1-d3487621ce10
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085668270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.3085668270
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.153698498
Short name T1076
Test name
Test status
Simulation time 15671047 ps
CPU time 0.74 seconds
Started Jul 27 04:50:16 PM PDT 24
Finished Jul 27 04:50:17 PM PDT 24
Peak memory 204292 kb
Host smart-d5ddd773-e485-4d72-bb72-b07b0d35a26d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153698498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.153698498
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.2962273577
Short name T1055
Test name
Test status
Simulation time 25860096 ps
CPU time 0.75 seconds
Started Jul 27 04:50:20 PM PDT 24
Finished Jul 27 04:50:21 PM PDT 24
Peak memory 204280 kb
Host smart-5bc505f3-641d-4684-a141-f2e59d35be73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962273577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
2962273577
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.2288941000
Short name T1086
Test name
Test status
Simulation time 12930437 ps
CPU time 0.75 seconds
Started Jul 27 04:50:16 PM PDT 24
Finished Jul 27 04:50:17 PM PDT 24
Peak memory 204596 kb
Host smart-ab3a6288-b889-47ab-b901-7a170c8065c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288941000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
2288941000
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.570659162
Short name T1104
Test name
Test status
Simulation time 27457999 ps
CPU time 0.72 seconds
Started Jul 27 04:50:25 PM PDT 24
Finished Jul 27 04:50:26 PM PDT 24
Peak memory 204292 kb
Host smart-8f8f1982-0283-42e5-a2af-0062ec94c584
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570659162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.570659162
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.587306345
Short name T1080
Test name
Test status
Simulation time 11247330 ps
CPU time 0.69 seconds
Started Jul 27 04:50:18 PM PDT 24
Finished Jul 27 04:50:19 PM PDT 24
Peak memory 204296 kb
Host smart-8b9b77eb-9110-430d-a346-46a1163cd7b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587306345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.587306345
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.2521825001
Short name T1093
Test name
Test status
Simulation time 49871091 ps
CPU time 0.75 seconds
Started Jul 27 04:50:17 PM PDT 24
Finished Jul 27 04:50:17 PM PDT 24
Peak memory 204284 kb
Host smart-6b398707-a2aa-4cfe-a820-818505b9f94a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521825001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
2521825001
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.1229917800
Short name T1141
Test name
Test status
Simulation time 11940390 ps
CPU time 0.71 seconds
Started Jul 27 04:50:12 PM PDT 24
Finished Jul 27 04:50:13 PM PDT 24
Peak memory 204596 kb
Host smart-f2545a9e-abbb-441b-8575-c532f374ca10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229917800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
1229917800
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.4143587027
Short name T1063
Test name
Test status
Simulation time 11956686 ps
CPU time 0.67 seconds
Started Jul 27 04:50:31 PM PDT 24
Finished Jul 27 04:50:32 PM PDT 24
Peak memory 204376 kb
Host smart-da174291-020b-414e-9769-45cd85e126ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143587027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
4143587027
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.382535509
Short name T1138
Test name
Test status
Simulation time 22827074 ps
CPU time 0.71 seconds
Started Jul 27 04:50:24 PM PDT 24
Finished Jul 27 04:50:24 PM PDT 24
Peak memory 204296 kb
Host smart-4ccd0f38-1f7f-4450-9dfb-51849b1e4153
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382535509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.382535509
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.3158377771
Short name T1123
Test name
Test status
Simulation time 58306811 ps
CPU time 0.72 seconds
Started Jul 27 04:50:01 PM PDT 24
Finished Jul 27 04:50:01 PM PDT 24
Peak memory 204636 kb
Host smart-bbe052bf-bc4b-4e4e-a292-81235f0fbfc0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158377771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
3158377771
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.3449716691
Short name T1065
Test name
Test status
Simulation time 1671559651 ps
CPU time 8.81 seconds
Started Jul 27 04:50:30 PM PDT 24
Finished Jul 27 04:50:39 PM PDT 24
Peak memory 207672 kb
Host smart-a8e20fd6-27f3-41c2-9dff-11a85b43cbe8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449716691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.3449716691
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1378585920
Short name T140
Test name
Test status
Simulation time 735420025 ps
CPU time 21.7 seconds
Started Jul 27 04:50:10 PM PDT 24
Finished Jul 27 04:50:33 PM PDT 24
Peak memory 215792 kb
Host smart-a36549f9-a1c6-4348-8595-b9ad5c507076
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378585920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.1378585920
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.3679428798
Short name T89
Test name
Test status
Simulation time 127227082 ps
CPU time 1.19 seconds
Started Jul 27 04:50:16 PM PDT 24
Finished Jul 27 04:50:18 PM PDT 24
Peak memory 216840 kb
Host smart-99794355-9d8b-43ce-a0bd-92d945149cd8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679428798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.3679428798
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2758341923
Short name T1144
Test name
Test status
Simulation time 158053621 ps
CPU time 3.92 seconds
Started Jul 27 04:50:07 PM PDT 24
Finished Jul 27 04:50:11 PM PDT 24
Peak memory 217888 kb
Host smart-9cc52bc0-3e34-4334-9101-ef38a9f7be50
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758341923 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.2758341923
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.3618634313
Short name T1068
Test name
Test status
Simulation time 78796831 ps
CPU time 2.16 seconds
Started Jul 27 04:50:38 PM PDT 24
Finished Jul 27 04:50:40 PM PDT 24
Peak memory 215948 kb
Host smart-344a8fcf-90c0-408b-9b0e-ebb44319ec4e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618634313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.3
618634313
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.3700952809
Short name T1052
Test name
Test status
Simulation time 32734360 ps
CPU time 0.71 seconds
Started Jul 27 04:50:16 PM PDT 24
Finished Jul 27 04:50:17 PM PDT 24
Peak memory 204428 kb
Host smart-3d9675e3-05c1-4117-8c6d-24194da896fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700952809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.3
700952809
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.320720224
Short name T135
Test name
Test status
Simulation time 83094198 ps
CPU time 1.73 seconds
Started Jul 27 04:50:16 PM PDT 24
Finished Jul 27 04:50:18 PM PDT 24
Peak memory 215892 kb
Host smart-14126b7f-83a8-40c6-bafb-d685f15013bc
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320720224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_
device_mem_partial_access.320720224
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1010604796
Short name T1079
Test name
Test status
Simulation time 42605622 ps
CPU time 0.68 seconds
Started Jul 27 04:50:17 PM PDT 24
Finished Jul 27 04:50:18 PM PDT 24
Peak memory 204200 kb
Host smart-92b14c44-a21f-4d9b-aeef-fc3b73e1c57e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010604796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.1010604796
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.982868987
Short name T1075
Test name
Test status
Simulation time 264092763 ps
CPU time 2.95 seconds
Started Jul 27 04:50:17 PM PDT 24
Finished Jul 27 04:50:20 PM PDT 24
Peak memory 215912 kb
Host smart-355a0461-2853-4bdd-bfd7-0d880dfe0649
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982868987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sp
i_device_same_csr_outstanding.982868987
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.3250790291
Short name T1136
Test name
Test status
Simulation time 279519718 ps
CPU time 3.57 seconds
Started Jul 27 04:50:19 PM PDT 24
Finished Jul 27 04:50:23 PM PDT 24
Peak memory 216096 kb
Host smart-c7a3a041-b9bf-4e14-9337-7a6e42c0b455
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250790291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.3
250790291
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.3901660838
Short name T184
Test name
Test status
Simulation time 279718304 ps
CPU time 6.8 seconds
Started Jul 27 04:50:16 PM PDT 24
Finished Jul 27 04:50:23 PM PDT 24
Peak memory 215904 kb
Host smart-86d44528-07c2-4267-92e1-8bf6dfd233f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901660838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.3901660838
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.3437792818
Short name T1084
Test name
Test status
Simulation time 16038900 ps
CPU time 0.71 seconds
Started Jul 27 04:50:20 PM PDT 24
Finished Jul 27 04:50:21 PM PDT 24
Peak memory 204324 kb
Host smart-812b2cff-3dd7-4d58-a24c-3ab9076f64e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437792818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
3437792818
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.480668673
Short name T1059
Test name
Test status
Simulation time 12664556 ps
CPU time 0.71 seconds
Started Jul 27 04:50:28 PM PDT 24
Finished Jul 27 04:50:29 PM PDT 24
Peak memory 204336 kb
Host smart-bbe2fc23-f64b-4884-b9d5-c1279f433855
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480668673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.480668673
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.78605609
Short name T1053
Test name
Test status
Simulation time 65176078 ps
CPU time 0.74 seconds
Started Jul 27 04:50:42 PM PDT 24
Finished Jul 27 04:50:42 PM PDT 24
Peak memory 204740 kb
Host smart-20db9fe6-bcab-4ec1-8874-fe37b4b01a58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78605609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.78605609
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.849949332
Short name T1033
Test name
Test status
Simulation time 18728516 ps
CPU time 0.75 seconds
Started Jul 27 04:50:14 PM PDT 24
Finished Jul 27 04:50:15 PM PDT 24
Peak memory 204640 kb
Host smart-07c64a7b-5dd6-4dcd-9866-8f04ea5c8413
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849949332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.849949332
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.3103451698
Short name T1125
Test name
Test status
Simulation time 29975418 ps
CPU time 0.77 seconds
Started Jul 27 04:50:56 PM PDT 24
Finished Jul 27 04:50:57 PM PDT 24
Peak memory 204472 kb
Host smart-abccb3df-da15-4a86-94bd-61384b1e9b0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103451698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
3103451698
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.4210778045
Short name T1040
Test name
Test status
Simulation time 129051294 ps
CPU time 0.75 seconds
Started Jul 27 04:51:06 PM PDT 24
Finished Jul 27 04:51:07 PM PDT 24
Peak memory 204740 kb
Host smart-cfc72905-7e53-4841-bd39-135e383b1133
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210778045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
4210778045
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.4153413276
Short name T1072
Test name
Test status
Simulation time 16302961 ps
CPU time 0.73 seconds
Started Jul 27 04:50:43 PM PDT 24
Finished Jul 27 04:50:44 PM PDT 24
Peak memory 204392 kb
Host smart-3692b699-67b9-4848-97df-97df7bc76e37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153413276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
4153413276
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.962037286
Short name T1081
Test name
Test status
Simulation time 63719698 ps
CPU time 0.74 seconds
Started Jul 27 04:50:20 PM PDT 24
Finished Jul 27 04:50:21 PM PDT 24
Peak memory 204444 kb
Host smart-7bb4be22-5681-4f09-ae5c-5b76a5ff1243
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962037286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.962037286
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.1934956403
Short name T1133
Test name
Test status
Simulation time 20624542 ps
CPU time 0.75 seconds
Started Jul 27 04:50:15 PM PDT 24
Finished Jul 27 04:50:16 PM PDT 24
Peak memory 204420 kb
Host smart-466510b2-0f89-4782-9812-bf911658c497
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934956403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
1934956403
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.3933746435
Short name T1034
Test name
Test status
Simulation time 12587156 ps
CPU time 0.69 seconds
Started Jul 27 04:50:18 PM PDT 24
Finished Jul 27 04:50:19 PM PDT 24
Peak memory 204268 kb
Host smart-92795f7e-0198-4f71-afe0-4bdf9d722dbc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933746435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
3933746435
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3672434910
Short name T1130
Test name
Test status
Simulation time 302930491 ps
CPU time 21.2 seconds
Started Jul 27 04:50:13 PM PDT 24
Finished Jul 27 04:50:34 PM PDT 24
Peak memory 215900 kb
Host smart-08eeb406-73f9-40cd-8331-1185c2e4985e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672434910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.3672434910
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.2651846476
Short name T1051
Test name
Test status
Simulation time 3094403743 ps
CPU time 25.67 seconds
Started Jul 27 04:50:16 PM PDT 24
Finished Jul 27 04:50:42 PM PDT 24
Peak memory 207792 kb
Host smart-3a7867f5-aac5-4d2e-a4bc-8637895ac6f1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651846476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.2651846476
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.34873113
Short name T87
Test name
Test status
Simulation time 63857935 ps
CPU time 1.15 seconds
Started Jul 27 04:50:29 PM PDT 24
Finished Jul 27 04:50:30 PM PDT 24
Peak memory 207740 kb
Host smart-3059e299-7a78-4833-a183-c8c9193cafd0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34873113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_
hw_reset.34873113
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.2385707297
Short name T1119
Test name
Test status
Simulation time 372757174 ps
CPU time 2.59 seconds
Started Jul 27 04:50:16 PM PDT 24
Finished Jul 27 04:50:18 PM PDT 24
Peak memory 217412 kb
Host smart-32885012-7610-4fc9-903b-8631a31f1db3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385707297 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.2385707297
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.354255806
Short name T1149
Test name
Test status
Simulation time 41077668 ps
CPU time 1.73 seconds
Started Jul 27 04:50:19 PM PDT 24
Finished Jul 27 04:50:21 PM PDT 24
Peak memory 215808 kb
Host smart-c6d49a30-7e75-43b8-9879-fa1e052cfa3b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354255806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.354255806
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3909055845
Short name T1114
Test name
Test status
Simulation time 58312273 ps
CPU time 0.75 seconds
Started Jul 27 04:50:08 PM PDT 24
Finished Jul 27 04:50:09 PM PDT 24
Peak memory 204308 kb
Host smart-525635ea-7326-4aad-bfd2-c6f7463b2007
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909055845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.3
909055845
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1036882348
Short name T138
Test name
Test status
Simulation time 200805196 ps
CPU time 1.75 seconds
Started Jul 27 04:50:16 PM PDT 24
Finished Jul 27 04:50:18 PM PDT 24
Peak memory 215848 kb
Host smart-94a09c8d-e7bb-4ffb-b43e-6efba99b139d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036882348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.1036882348
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.2867876054
Short name T1036
Test name
Test status
Simulation time 80897186 ps
CPU time 0.65 seconds
Started Jul 27 04:50:18 PM PDT 24
Finished Jul 27 04:50:19 PM PDT 24
Peak memory 204172 kb
Host smart-64aa4433-a1bf-4b3a-b2a8-61d06048bbab
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867876054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.2867876054
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2764913471
Short name T158
Test name
Test status
Simulation time 75779642 ps
CPU time 1.95 seconds
Started Jul 27 04:50:21 PM PDT 24
Finished Jul 27 04:50:23 PM PDT 24
Peak memory 215796 kb
Host smart-5ef44131-0ae9-4028-b5de-38047df55b16
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764913471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.2764913471
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2220317760
Short name T1103
Test name
Test status
Simulation time 581769983 ps
CPU time 18.52 seconds
Started Jul 27 04:50:03 PM PDT 24
Finished Jul 27 04:50:21 PM PDT 24
Peak memory 215844 kb
Host smart-85b95629-4838-4d29-b656-d370b7b331dc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220317760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.2220317760
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.1045573657
Short name T1045
Test name
Test status
Simulation time 22681768 ps
CPU time 0.73 seconds
Started Jul 27 04:50:14 PM PDT 24
Finished Jul 27 04:50:15 PM PDT 24
Peak memory 204308 kb
Host smart-9e7af297-5ddc-4b81-af35-68016cf1d8f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045573657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
1045573657
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.1155999915
Short name T1083
Test name
Test status
Simulation time 31422422 ps
CPU time 0.73 seconds
Started Jul 27 04:50:12 PM PDT 24
Finished Jul 27 04:50:13 PM PDT 24
Peak memory 204372 kb
Host smart-a618ddd5-583d-4322-acc9-8ef213a3b32d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155999915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
1155999915
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.2872855611
Short name T1078
Test name
Test status
Simulation time 14921299 ps
CPU time 0.68 seconds
Started Jul 27 04:50:27 PM PDT 24
Finished Jul 27 04:50:28 PM PDT 24
Peak memory 204324 kb
Host smart-4a843789-ef5f-4118-b63d-2f0c97bfe21b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872855611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
2872855611
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.185503903
Short name T1106
Test name
Test status
Simulation time 174081120 ps
CPU time 0.75 seconds
Started Jul 27 04:50:30 PM PDT 24
Finished Jul 27 04:50:31 PM PDT 24
Peak memory 204364 kb
Host smart-06f14967-ac67-4c91-9fdb-ea60a2e1ec5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185503903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.185503903
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.453769560
Short name T1048
Test name
Test status
Simulation time 43313844 ps
CPU time 0.74 seconds
Started Jul 27 04:50:34 PM PDT 24
Finished Jul 27 04:50:35 PM PDT 24
Peak memory 204416 kb
Host smart-24c26998-fd5c-4a2d-a179-c00128d302f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453769560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.453769560
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3843279915
Short name T1071
Test name
Test status
Simulation time 150054564 ps
CPU time 0.81 seconds
Started Jul 27 04:50:30 PM PDT 24
Finished Jul 27 04:50:31 PM PDT 24
Peak memory 204324 kb
Host smart-79e841bd-79bc-4501-8d7c-c2e2414b04a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843279915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
3843279915
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.4071391852
Short name T1070
Test name
Test status
Simulation time 60965706 ps
CPU time 0.73 seconds
Started Jul 27 04:50:28 PM PDT 24
Finished Jul 27 04:50:29 PM PDT 24
Peak memory 204308 kb
Host smart-99fcfa96-f826-4d5f-869c-ca5e5b8537f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071391852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
4071391852
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.2957412580
Short name T1129
Test name
Test status
Simulation time 52507997 ps
CPU time 0.71 seconds
Started Jul 27 04:50:16 PM PDT 24
Finished Jul 27 04:50:17 PM PDT 24
Peak memory 204208 kb
Host smart-03b0afc0-fb11-4366-b2eb-4ecf582c4f68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957412580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
2957412580
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2183443276
Short name T1041
Test name
Test status
Simulation time 35801271 ps
CPU time 0.71 seconds
Started Jul 27 04:50:27 PM PDT 24
Finished Jul 27 04:50:28 PM PDT 24
Peak memory 204660 kb
Host smart-a37c88f6-4062-4a84-8f9e-f559f2b7ce8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183443276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
2183443276
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.3568369763
Short name T1058
Test name
Test status
Simulation time 14188998 ps
CPU time 0.72 seconds
Started Jul 27 04:50:25 PM PDT 24
Finished Jul 27 04:50:26 PM PDT 24
Peak memory 204276 kb
Host smart-15406841-8476-4b4a-bda0-fd87c3752e55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568369763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
3568369763
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1682151719
Short name T1102
Test name
Test status
Simulation time 702509380 ps
CPU time 1.68 seconds
Started Jul 27 04:50:16 PM PDT 24
Finished Jul 27 04:50:18 PM PDT 24
Peak memory 216984 kb
Host smart-e62cf307-2ce5-4881-8ce9-9eae806e947e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682151719 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.1682151719
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.3966150749
Short name T156
Test name
Test status
Simulation time 158166184 ps
CPU time 2.11 seconds
Started Jul 27 04:50:29 PM PDT 24
Finished Jul 27 04:50:31 PM PDT 24
Peak memory 207680 kb
Host smart-80372e5a-8358-4430-a8a5-df1e66433411
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966150749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.3
966150749
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.4146447606
Short name T1057
Test name
Test status
Simulation time 22967312 ps
CPU time 0.75 seconds
Started Jul 27 04:50:34 PM PDT 24
Finished Jul 27 04:50:35 PM PDT 24
Peak memory 204376 kb
Host smart-e198c756-f519-47e0-97af-4551a6a62b6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146447606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.4
146447606
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.818153572
Short name T1074
Test name
Test status
Simulation time 156397233 ps
CPU time 3.85 seconds
Started Jul 27 04:50:28 PM PDT 24
Finished Jul 27 04:50:32 PM PDT 24
Peak memory 215776 kb
Host smart-d29fa5d8-9724-4b3a-91b5-ae389fd0b516
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818153572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sp
i_device_same_csr_outstanding.818153572
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.3860990599
Short name T121
Test name
Test status
Simulation time 65262196 ps
CPU time 2.16 seconds
Started Jul 27 04:50:27 PM PDT 24
Finished Jul 27 04:50:29 PM PDT 24
Peak memory 216288 kb
Host smart-25303c89-4635-46d9-8874-7a206c52f079
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860990599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.3
860990599
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.1621987531
Short name T126
Test name
Test status
Simulation time 122729881 ps
CPU time 3.59 seconds
Started Jul 27 04:50:12 PM PDT 24
Finished Jul 27 04:50:16 PM PDT 24
Peak memory 217992 kb
Host smart-ff2d97c2-94fc-4b8b-a1d5-7da557fb3689
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621987531 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.1621987531
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1675214826
Short name T134
Test name
Test status
Simulation time 38929808 ps
CPU time 2.59 seconds
Started Jul 27 04:50:22 PM PDT 24
Finished Jul 27 04:50:25 PM PDT 24
Peak memory 215836 kb
Host smart-c488d5ed-6795-4006-914e-3de6852208c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675214826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.1
675214826
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.755746162
Short name T1090
Test name
Test status
Simulation time 14900473 ps
CPU time 0.73 seconds
Started Jul 27 04:50:23 PM PDT 24
Finished Jul 27 04:50:24 PM PDT 24
Peak memory 204572 kb
Host smart-fa32fe4a-c072-470a-992c-e0bf34ae8d18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755746162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.755746162
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.750920990
Short name T1107
Test name
Test status
Simulation time 265284092 ps
CPU time 1.79 seconds
Started Jul 27 04:50:16 PM PDT 24
Finished Jul 27 04:50:18 PM PDT 24
Peak memory 207684 kb
Host smart-e36b58ed-b26b-4164-a6d6-939596090b48
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750920990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sp
i_device_same_csr_outstanding.750920990
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.1317290011
Short name T1124
Test name
Test status
Simulation time 182424297 ps
CPU time 2.33 seconds
Started Jul 27 04:50:16 PM PDT 24
Finished Jul 27 04:50:18 PM PDT 24
Peak memory 216328 kb
Host smart-deee1815-ed2f-433c-a160-a857405489ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317290011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.1
317290011
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.3168711047
Short name T1064
Test name
Test status
Simulation time 1441198017 ps
CPU time 15.48 seconds
Started Jul 27 04:50:17 PM PDT 24
Finished Jul 27 04:50:33 PM PDT 24
Peak memory 215816 kb
Host smart-fba6df00-245c-462f-aca8-415b7444838e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168711047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.3168711047
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.230477206
Short name T1088
Test name
Test status
Simulation time 87798761 ps
CPU time 1.65 seconds
Started Jul 27 04:50:12 PM PDT 24
Finished Jul 27 04:50:13 PM PDT 24
Peak memory 215940 kb
Host smart-cf092df1-c724-4809-8658-10fd3ebf71f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230477206 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.230477206
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.2298969477
Short name T1087
Test name
Test status
Simulation time 56617583 ps
CPU time 1.73 seconds
Started Jul 27 04:50:18 PM PDT 24
Finished Jul 27 04:50:20 PM PDT 24
Peak memory 215880 kb
Host smart-24b0b4ec-0d8d-46a5-93d4-586e6ca0b219
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298969477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.2
298969477
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.1238386455
Short name T1046
Test name
Test status
Simulation time 14569343 ps
CPU time 0.73 seconds
Started Jul 27 04:50:16 PM PDT 24
Finished Jul 27 04:50:17 PM PDT 24
Peak memory 204252 kb
Host smart-157b698b-71c7-431c-b008-c5854629af69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238386455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.1
238386455
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.2009529829
Short name T1035
Test name
Test status
Simulation time 426186620 ps
CPU time 2.96 seconds
Started Jul 27 04:50:14 PM PDT 24
Finished Jul 27 04:50:17 PM PDT 24
Peak memory 215804 kb
Host smart-f0f0a6bd-ed0f-4da5-afd2-c58d31632af4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009529829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.2009529829
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.849052253
Short name T1142
Test name
Test status
Simulation time 82378878 ps
CPU time 3.79 seconds
Started Jul 27 04:50:19 PM PDT 24
Finished Jul 27 04:50:23 PM PDT 24
Peak memory 216360 kb
Host smart-aad5155e-3303-46dc-baf8-db6cdc37d636
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849052253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.849052253
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.1915613092
Short name T1066
Test name
Test status
Simulation time 434380422 ps
CPU time 6.89 seconds
Started Jul 27 04:50:27 PM PDT 24
Finished Jul 27 04:50:34 PM PDT 24
Peak memory 216412 kb
Host smart-89d7666d-cb2d-4e54-b792-03cb4c692b6a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915613092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.1915613092
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3724282337
Short name T130
Test name
Test status
Simulation time 67683320 ps
CPU time 1.79 seconds
Started Jul 27 04:50:23 PM PDT 24
Finished Jul 27 04:50:25 PM PDT 24
Peak memory 215948 kb
Host smart-9df6e889-58f9-41e5-a5a1-5aa8a7462bf3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724282337 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.3724282337
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.1060494865
Short name T1115
Test name
Test status
Simulation time 804816103 ps
CPU time 2 seconds
Started Jul 27 04:50:24 PM PDT 24
Finished Jul 27 04:50:26 PM PDT 24
Peak memory 215844 kb
Host smart-a09898d5-feb1-4142-be8d-5fa03c1a0180
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060494865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.1
060494865
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.4154549499
Short name T1061
Test name
Test status
Simulation time 32368474 ps
CPU time 0.76 seconds
Started Jul 27 04:50:11 PM PDT 24
Finished Jul 27 04:50:12 PM PDT 24
Peak memory 204640 kb
Host smart-337ed2f5-c0eb-417d-8cd3-83e69452d48c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154549499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.4
154549499
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.472726848
Short name T160
Test name
Test status
Simulation time 141153052 ps
CPU time 3.18 seconds
Started Jul 27 04:50:23 PM PDT 24
Finished Jul 27 04:50:26 PM PDT 24
Peak memory 215956 kb
Host smart-5436053b-1206-4c7d-a96f-eb2767952efa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472726848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sp
i_device_same_csr_outstanding.472726848
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.1860554495
Short name T122
Test name
Test status
Simulation time 67715179 ps
CPU time 4.43 seconds
Started Jul 27 04:50:16 PM PDT 24
Finished Jul 27 04:50:20 PM PDT 24
Peak memory 217416 kb
Host smart-c471cf03-0a6f-457f-b8e5-be313e5c82f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860554495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.1
860554495
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.1401071106
Short name T1135
Test name
Test status
Simulation time 515217039 ps
CPU time 13.13 seconds
Started Jul 27 04:50:14 PM PDT 24
Finished Jul 27 04:50:27 PM PDT 24
Peak memory 215876 kb
Host smart-f5acfd38-3a24-46e4-83a7-8c2590bfe8fe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401071106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.1401071106
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.314247014
Short name T128
Test name
Test status
Simulation time 111895449 ps
CPU time 2.81 seconds
Started Jul 27 04:50:13 PM PDT 24
Finished Jul 27 04:50:16 PM PDT 24
Peak memory 217704 kb
Host smart-42fe6ee5-8797-4492-aeac-f234e23eccb2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314247014 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.314247014
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.1340312197
Short name T136
Test name
Test status
Simulation time 30095181 ps
CPU time 1.94 seconds
Started Jul 27 04:50:41 PM PDT 24
Finished Jul 27 04:50:43 PM PDT 24
Peak memory 207620 kb
Host smart-5a14691a-796d-47f5-b79f-cb5a40a7b58f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340312197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.1
340312197
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2537880230
Short name T1091
Test name
Test status
Simulation time 22411520 ps
CPU time 0.7 seconds
Started Jul 27 04:50:41 PM PDT 24
Finished Jul 27 04:50:42 PM PDT 24
Peak memory 204800 kb
Host smart-d71d42d0-d6fd-4677-ac17-299f3c58bab2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537880230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.2
537880230
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2287781540
Short name T147
Test name
Test status
Simulation time 160387281 ps
CPU time 2.65 seconds
Started Jul 27 04:50:35 PM PDT 24
Finished Jul 27 04:50:38 PM PDT 24
Peak memory 215884 kb
Host smart-f9d7ce20-b308-4576-bfb0-9493049a2542
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287781540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.2287781540
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.1380240096
Short name T118
Test name
Test status
Simulation time 612143777 ps
CPU time 2.39 seconds
Started Jul 27 04:50:21 PM PDT 24
Finished Jul 27 04:50:24 PM PDT 24
Peak memory 216224 kb
Host smart-ac8b725a-1bc7-4af3-9918-d635a4dab079
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380240096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.1
380240096
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.173246128
Short name T129
Test name
Test status
Simulation time 308873395 ps
CPU time 19.49 seconds
Started Jul 27 04:50:25 PM PDT 24
Finished Jul 27 04:50:44 PM PDT 24
Peak memory 215760 kb
Host smart-b0e08e17-07d5-46fc-964b-ec5037ba473a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173246128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_
tl_intg_err.173246128
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.733806124
Short name T273
Test name
Test status
Simulation time 467487503 ps
CPU time 3.63 seconds
Started Jul 27 04:52:02 PM PDT 24
Finished Jul 27 04:52:05 PM PDT 24
Peak memory 233532 kb
Host smart-9725ec26-288f-49f7-b366-b8f142d2fe5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733806124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.733806124
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.3360749070
Short name T374
Test name
Test status
Simulation time 53128324 ps
CPU time 0.77 seconds
Started Jul 27 04:51:52 PM PDT 24
Finished Jul 27 04:51:53 PM PDT 24
Peak memory 207484 kb
Host smart-c57e9f68-3212-4797-a483-06eddf36b98f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360749070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.3360749070
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.3307255756
Short name T1005
Test name
Test status
Simulation time 3224111046 ps
CPU time 35.31 seconds
Started Jul 27 04:51:59 PM PDT 24
Finished Jul 27 04:52:35 PM PDT 24
Peak memory 256068 kb
Host smart-91897ca1-4a19-43ff-90e6-8b1d90c2238c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307255756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.3307255756
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.474154355
Short name T210
Test name
Test status
Simulation time 20153413639 ps
CPU time 47.82 seconds
Started Jul 27 04:52:03 PM PDT 24
Finished Jul 27 04:52:51 PM PDT 24
Peak memory 250648 kb
Host smart-ce8d1c66-7f9d-4a8a-b7e6-0c3df12f5a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474154355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle.
474154355
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.2235422736
Short name T512
Test name
Test status
Simulation time 446869497 ps
CPU time 3.5 seconds
Started Jul 27 04:51:51 PM PDT 24
Finished Jul 27 04:51:55 PM PDT 24
Peak memory 225348 kb
Host smart-39113e0d-1818-440f-a6d9-ebba3d5bd765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235422736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.2235422736
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.700426730
Short name T610
Test name
Test status
Simulation time 23633754141 ps
CPU time 165.7 seconds
Started Jul 27 04:52:01 PM PDT 24
Finished Jul 27 04:54:47 PM PDT 24
Peak memory 250028 kb
Host smart-1c07df1e-5795-4759-aaf3-6fce6586018b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700426730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds.
700426730
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_intercept.2358059444
Short name T191
Test name
Test status
Simulation time 8919623010 ps
CPU time 16.63 seconds
Started Jul 27 04:51:56 PM PDT 24
Finished Jul 27 04:52:13 PM PDT 24
Peak memory 233552 kb
Host smart-e6799390-8116-467c-bc86-dc04bb31944a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358059444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.2358059444
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.764995145
Short name T770
Test name
Test status
Simulation time 852793738 ps
CPU time 15.87 seconds
Started Jul 27 04:52:03 PM PDT 24
Finished Jul 27 04:52:19 PM PDT 24
Peak memory 229464 kb
Host smart-c6deb954-70de-4961-8f0f-d081e023b4b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764995145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.764995145
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.3603919291
Short name T1017
Test name
Test status
Simulation time 50408104 ps
CPU time 1.03 seconds
Started Jul 27 04:52:03 PM PDT 24
Finished Jul 27 04:52:04 PM PDT 24
Peak memory 218452 kb
Host smart-a18a1adf-d65b-46f1-901c-e2f22f5b5b1d
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603919291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.spi_device_mem_parity.3603919291
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.2895064239
Short name T755
Test name
Test status
Simulation time 9309781793 ps
CPU time 8.98 seconds
Started Jul 27 04:52:03 PM PDT 24
Finished Jul 27 04:52:12 PM PDT 24
Peak memory 241260 kb
Host smart-dfaf45c1-d072-4ced-ac63-c8e95ee7f7e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895064239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.2895064239
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.2324062822
Short name T478
Test name
Test status
Simulation time 660385159 ps
CPU time 3.17 seconds
Started Jul 27 04:52:05 PM PDT 24
Finished Jul 27 04:52:08 PM PDT 24
Peak memory 233500 kb
Host smart-6edbbc8c-5d58-4bb9-991d-33823a3ecd37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324062822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.2324062822
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.3577048701
Short name T460
Test name
Test status
Simulation time 1327931755 ps
CPU time 7.76 seconds
Started Jul 27 04:52:08 PM PDT 24
Finished Jul 27 04:52:16 PM PDT 24
Peak memory 223676 kb
Host smart-86ec0d3a-3800-4da0-95e4-af066a8715b9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3577048701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.3577048701
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.3978000023
Short name T78
Test name
Test status
Simulation time 161710357 ps
CPU time 1.15 seconds
Started Jul 27 04:52:00 PM PDT 24
Finished Jul 27 04:52:01 PM PDT 24
Peak memory 235804 kb
Host smart-5da23df8-c4d3-4ed8-ac1e-c05b46b483e9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978000023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.3978000023
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.1638919722
Short name T171
Test name
Test status
Simulation time 3071168590 ps
CPU time 19.33 seconds
Started Jul 27 04:52:05 PM PDT 24
Finished Jul 27 04:52:25 PM PDT 24
Peak memory 217016 kb
Host smart-20612e69-2d7d-41b2-811d-c5b818fe058b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638919722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.1638919722
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.1766471803
Short name T472
Test name
Test status
Simulation time 1096065639 ps
CPU time 6.03 seconds
Started Jul 27 04:52:07 PM PDT 24
Finished Jul 27 04:52:13 PM PDT 24
Peak memory 217020 kb
Host smart-189b3122-9823-41ce-88b1-e1052b6b1a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766471803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.1766471803
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.77760019
Short name T744
Test name
Test status
Simulation time 28801548 ps
CPU time 1.17 seconds
Started Jul 27 04:52:03 PM PDT 24
Finished Jul 27 04:52:04 PM PDT 24
Peak memory 208564 kb
Host smart-707f7d78-1d77-40ee-9011-1527dd70815b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77760019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.77760019
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.3934857954
Short name T827
Test name
Test status
Simulation time 100330653 ps
CPU time 0.89 seconds
Started Jul 27 04:51:58 PM PDT 24
Finished Jul 27 04:51:59 PM PDT 24
Peak memory 206728 kb
Host smart-2b0d8e47-ee71-4640-aa71-27f3c66db199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934857954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.3934857954
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.4251494853
Short name T404
Test name
Test status
Simulation time 804416616 ps
CPU time 9.1 seconds
Started Jul 27 04:51:58 PM PDT 24
Finished Jul 27 04:52:07 PM PDT 24
Peak memory 241712 kb
Host smart-2cebe18d-27bd-4d23-a101-eeabca9011c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251494853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.4251494853
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.2585897647
Short name T614
Test name
Test status
Simulation time 33393992 ps
CPU time 0.74 seconds
Started Jul 27 04:51:58 PM PDT 24
Finished Jul 27 04:51:58 PM PDT 24
Peak memory 205952 kb
Host smart-8457979e-7ede-4287-bacc-3f7df4e76104
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585897647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.2
585897647
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.2935503271
Short name T948
Test name
Test status
Simulation time 2522942628 ps
CPU time 12.46 seconds
Started Jul 27 04:52:07 PM PDT 24
Finished Jul 27 04:52:24 PM PDT 24
Peak memory 225476 kb
Host smart-86b478c6-b139-4dd8-8dbf-b8b23ecea20c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935503271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.2935503271
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.2676281695
Short name T776
Test name
Test status
Simulation time 55306060 ps
CPU time 0.75 seconds
Started Jul 27 04:52:03 PM PDT 24
Finished Jul 27 04:52:04 PM PDT 24
Peak memory 206408 kb
Host smart-a5309c19-86e6-4d1e-a244-d357132fa427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676281695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.2676281695
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.3844337803
Short name T180
Test name
Test status
Simulation time 14205532618 ps
CPU time 106.6 seconds
Started Jul 27 04:51:49 PM PDT 24
Finished Jul 27 04:53:36 PM PDT 24
Peak memory 252172 kb
Host smart-5206cb5a-6a50-48e0-85a9-6382675cccae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844337803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.3844337803
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.1754690960
Short name T659
Test name
Test status
Simulation time 8315799872 ps
CPU time 76.6 seconds
Started Jul 27 04:52:04 PM PDT 24
Finished Jul 27 04:53:21 PM PDT 24
Peak memory 249992 kb
Host smart-929283f8-cc38-43c1-85c5-cf96e6fa7ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754690960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.1754690960
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.1214628314
Short name T729
Test name
Test status
Simulation time 8550820978 ps
CPU time 63.96 seconds
Started Jul 27 04:52:02 PM PDT 24
Finished Jul 27 04:53:07 PM PDT 24
Peak memory 250008 kb
Host smart-fcb0d5a2-67ad-422e-8a25-4c3d29a8f8f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214628314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.1214628314
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.636396006
Short name T911
Test name
Test status
Simulation time 813419826 ps
CPU time 8.43 seconds
Started Jul 27 04:52:05 PM PDT 24
Finished Jul 27 04:52:14 PM PDT 24
Peak memory 233432 kb
Host smart-92abd70c-1698-4e87-a6c4-bb9c4bf71866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636396006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.636396006
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.2487228631
Short name T893
Test name
Test status
Simulation time 4828766174 ps
CPU time 34.24 seconds
Started Jul 27 04:51:53 PM PDT 24
Finished Jul 27 04:52:28 PM PDT 24
Peak memory 234932 kb
Host smart-8075dbe8-848e-4dbe-9d61-ad1c6a541b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487228631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds
.2487228631
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/1.spi_device_intercept.2064568375
Short name T1010
Test name
Test status
Simulation time 1591030591 ps
CPU time 9.03 seconds
Started Jul 27 04:52:03 PM PDT 24
Finished Jul 27 04:52:12 PM PDT 24
Peak memory 225300 kb
Host smart-17f5c25a-3f78-494a-bf67-df6eea3ebf8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064568375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.2064568375
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.1734337746
Short name T567
Test name
Test status
Simulation time 3211289380 ps
CPU time 3.58 seconds
Started Jul 27 04:52:08 PM PDT 24
Finished Jul 27 04:52:12 PM PDT 24
Peak memory 225404 kb
Host smart-593fdc80-a41b-4d2b-8827-a9a59f741dd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734337746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.1734337746
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.2322106779
Short name T713
Test name
Test status
Simulation time 16758359 ps
CPU time 0.99 seconds
Started Jul 27 04:52:09 PM PDT 24
Finished Jul 27 04:52:10 PM PDT 24
Peak memory 218628 kb
Host smart-a321690f-e36a-40b7-b831-470a9d156cb1
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322106779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.spi_device_mem_parity.2322106779
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.3135380770
Short name T978
Test name
Test status
Simulation time 48697553516 ps
CPU time 29.27 seconds
Started Jul 27 04:52:03 PM PDT 24
Finished Jul 27 04:52:32 PM PDT 24
Peak memory 233452 kb
Host smart-2674ae21-bfe2-4205-b2ff-1c66f2516f14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135380770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.3135380770
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.1034116977
Short name T844
Test name
Test status
Simulation time 521174254 ps
CPU time 9.84 seconds
Started Jul 27 04:51:53 PM PDT 24
Finished Jul 27 04:52:03 PM PDT 24
Peak memory 233504 kb
Host smart-eef474db-664a-4fdc-925b-87c9a7854827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034116977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.1034116977
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.289554227
Short name T150
Test name
Test status
Simulation time 1953098827 ps
CPU time 5.86 seconds
Started Jul 27 04:52:10 PM PDT 24
Finished Jul 27 04:52:16 PM PDT 24
Peak memory 219692 kb
Host smart-f2411647-d376-4ddc-bbe8-3f106eb035af
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=289554227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_direc
t.289554227
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.2381908801
Short name T77
Test name
Test status
Simulation time 285894693 ps
CPU time 1.15 seconds
Started Jul 27 04:52:07 PM PDT 24
Finished Jul 27 04:52:08 PM PDT 24
Peak memory 235860 kb
Host smart-2a3b02e1-dae8-4aec-a052-366e6702708c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381908801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.2381908801
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.3028676014
Short name T1002
Test name
Test status
Simulation time 5336010751 ps
CPU time 110.41 seconds
Started Jul 27 04:52:03 PM PDT 24
Finished Jul 27 04:53:54 PM PDT 24
Peak memory 253292 kb
Host smart-4e2c80fd-fa92-4c74-9543-9112c7a02b23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028676014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.3028676014
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.2025783190
Short name T399
Test name
Test status
Simulation time 3635617106 ps
CPU time 10.03 seconds
Started Jul 27 04:52:01 PM PDT 24
Finished Jul 27 04:52:11 PM PDT 24
Peak memory 220800 kb
Host smart-9a223632-2b34-4bc9-840e-413a1f3ad97e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025783190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.2025783190
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.1326284330
Short name T364
Test name
Test status
Simulation time 645135609 ps
CPU time 4.32 seconds
Started Jul 27 04:52:02 PM PDT 24
Finished Jul 27 04:52:07 PM PDT 24
Peak memory 216976 kb
Host smart-98ce5e57-9ece-46fc-92cb-3eead41daa2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326284330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.1326284330
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.785355177
Short name T560
Test name
Test status
Simulation time 1404882338 ps
CPU time 10.87 seconds
Started Jul 27 04:51:54 PM PDT 24
Finished Jul 27 04:52:05 PM PDT 24
Peak memory 217112 kb
Host smart-f4dff247-1eef-4420-b7c7-2d57232df5e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785355177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.785355177
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.1872256567
Short name T599
Test name
Test status
Simulation time 45581096 ps
CPU time 0.81 seconds
Started Jul 27 04:51:49 PM PDT 24
Finished Jul 27 04:51:50 PM PDT 24
Peak memory 206664 kb
Host smart-71698799-043d-485e-a825-ec4add3aeafa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872256567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.1872256567
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.212878819
Short name T842
Test name
Test status
Simulation time 46683685514 ps
CPU time 31.31 seconds
Started Jul 27 04:51:55 PM PDT 24
Finished Jul 27 04:52:26 PM PDT 24
Peak memory 239752 kb
Host smart-047e8bdf-57da-4082-8fc8-0ccdf50a5d99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212878819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.212878819
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.772444599
Short name T820
Test name
Test status
Simulation time 37415259 ps
CPU time 0.73 seconds
Started Jul 27 04:52:42 PM PDT 24
Finished Jul 27 04:52:42 PM PDT 24
Peak memory 205996 kb
Host smart-db70bb7a-195e-4d47-991e-68bf415bedc2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772444599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.772444599
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.3157079850
Short name T860
Test name
Test status
Simulation time 249695438 ps
CPU time 2.39 seconds
Started Jul 27 04:52:29 PM PDT 24
Finished Jul 27 04:52:32 PM PDT 24
Peak memory 233452 kb
Host smart-70ae23a5-cabc-422f-8769-3787bcd281c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157079850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.3157079850
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.3713677680
Short name T343
Test name
Test status
Simulation time 72356386 ps
CPU time 0.78 seconds
Started Jul 27 04:52:33 PM PDT 24
Finished Jul 27 04:52:34 PM PDT 24
Peak memory 207132 kb
Host smart-99e02534-636e-4fc6-bb40-a3c01d137933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713677680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.3713677680
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.1768351110
Short name T833
Test name
Test status
Simulation time 1149960405 ps
CPU time 27.16 seconds
Started Jul 27 04:52:31 PM PDT 24
Finished Jul 27 04:52:58 PM PDT 24
Peak memory 241864 kb
Host smart-493591ca-6350-4756-bf84-f73aaa7a0ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768351110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.1768351110
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.3297017730
Short name T795
Test name
Test status
Simulation time 395222356812 ps
CPU time 247.37 seconds
Started Jul 27 04:52:30 PM PDT 24
Finished Jul 27 04:56:43 PM PDT 24
Peak memory 254336 kb
Host smart-2c2fa81d-cc0c-4a1e-b734-7f2c6a897ca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297017730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmd
s.3297017730
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/10.spi_device_intercept.1453533717
Short name T582
Test name
Test status
Simulation time 461852479 ps
CPU time 5.41 seconds
Started Jul 27 04:52:31 PM PDT 24
Finished Jul 27 04:52:37 PM PDT 24
Peak memory 233536 kb
Host smart-376b7656-ec6b-47ad-88a7-77c709295605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453533717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.1453533717
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.1593181654
Short name T613
Test name
Test status
Simulation time 2065962125 ps
CPU time 27.7 seconds
Started Jul 27 04:52:43 PM PDT 24
Finished Jul 27 04:53:11 PM PDT 24
Peak memory 225420 kb
Host smart-b5e59995-e060-453d-bb30-6ea4945fffb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593181654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.1593181654
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.2831776135
Short name T857
Test name
Test status
Simulation time 19256879 ps
CPU time 1.01 seconds
Started Jul 27 04:52:16 PM PDT 24
Finished Jul 27 04:52:17 PM PDT 24
Peak memory 218600 kb
Host smart-871e31c5-2af2-42f3-bf5f-00fd8b56dc64
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831776135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.spi_device_mem_parity.2831776135
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.917108984
Short name T572
Test name
Test status
Simulation time 2872240925 ps
CPU time 10.02 seconds
Started Jul 27 04:52:39 PM PDT 24
Finished Jul 27 04:52:49 PM PDT 24
Peak memory 225472 kb
Host smart-b0abfaeb-7e06-4117-9d98-d20a88649d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917108984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swap
.917108984
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.2273048336
Short name T386
Test name
Test status
Simulation time 1665005880 ps
CPU time 6.22 seconds
Started Jul 27 04:52:42 PM PDT 24
Finished Jul 27 04:52:49 PM PDT 24
Peak memory 225380 kb
Host smart-8c8fc8e5-4263-4a8d-aafb-e491339d348d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273048336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.2273048336
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.946614787
Short name T722
Test name
Test status
Simulation time 1335645812 ps
CPU time 10.59 seconds
Started Jul 27 04:52:32 PM PDT 24
Finished Jul 27 04:52:43 PM PDT 24
Peak memory 219452 kb
Host smart-52239fca-9166-4f34-8ac0-d1e1b1133c1d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=946614787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dire
ct.946614787
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.489466822
Short name T952
Test name
Test status
Simulation time 28162883483 ps
CPU time 258.12 seconds
Started Jul 27 04:52:30 PM PDT 24
Finished Jul 27 04:56:48 PM PDT 24
Peak memory 257724 kb
Host smart-a76fa19d-918e-40ad-b143-2e944b802932
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489466822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stres
s_all.489466822
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.2232808847
Short name T709
Test name
Test status
Simulation time 8369256042 ps
CPU time 24.43 seconds
Started Jul 27 04:52:19 PM PDT 24
Finished Jul 27 04:52:43 PM PDT 24
Peak memory 220956 kb
Host smart-5bb3e500-cda4-4569-9d98-d54634ea66fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232808847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.2232808847
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.951471689
Short name T552
Test name
Test status
Simulation time 41194681879 ps
CPU time 14.33 seconds
Started Jul 27 04:52:32 PM PDT 24
Finished Jul 27 04:52:47 PM PDT 24
Peak memory 218248 kb
Host smart-832c622c-dc4b-4451-8f86-185de4f403ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951471689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.951471689
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.3762007573
Short name T909
Test name
Test status
Simulation time 307179947 ps
CPU time 0.96 seconds
Started Jul 27 04:52:30 PM PDT 24
Finished Jul 27 04:52:31 PM PDT 24
Peak memory 208200 kb
Host smart-9be69350-3a42-4b7d-9abd-1cfbbb12569b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762007573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.3762007573
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.2674372497
Short name T390
Test name
Test status
Simulation time 21350691 ps
CPU time 0.72 seconds
Started Jul 27 04:52:36 PM PDT 24
Finished Jul 27 04:52:37 PM PDT 24
Peak memory 206340 kb
Host smart-ba1bf1ed-97a8-4eaf-afbb-c2dbc3979fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674372497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.2674372497
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.1491813374
Short name T785
Test name
Test status
Simulation time 449970740 ps
CPU time 5.83 seconds
Started Jul 27 04:52:31 PM PDT 24
Finished Jul 27 04:52:37 PM PDT 24
Peak memory 240328 kb
Host smart-6ab4d3c6-e88d-4ce8-a547-abea79ff944b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491813374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.1491813374
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.112252966
Short name T847
Test name
Test status
Simulation time 12979154 ps
CPU time 0.73 seconds
Started Jul 27 04:52:32 PM PDT 24
Finished Jul 27 04:52:33 PM PDT 24
Peak memory 206028 kb
Host smart-2fbc4db5-c729-4aac-b3d4-167de9b0056a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112252966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.112252966
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.1248344608
Short name T734
Test name
Test status
Simulation time 120212855 ps
CPU time 2.79 seconds
Started Jul 27 04:52:50 PM PDT 24
Finished Jul 27 04:52:53 PM PDT 24
Peak memory 225276 kb
Host smart-2771315c-0f6e-40f1-af58-ee66754cc256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248344608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.1248344608
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.3986876319
Short name T504
Test name
Test status
Simulation time 23041544 ps
CPU time 0.78 seconds
Started Jul 27 04:52:33 PM PDT 24
Finished Jul 27 04:52:34 PM PDT 24
Peak memory 207552 kb
Host smart-53ce0149-0129-4541-b0a2-8e33e0e147f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986876319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.3986876319
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.2319568224
Short name T807
Test name
Test status
Simulation time 3271199566 ps
CPU time 66.58 seconds
Started Jul 27 04:52:41 PM PDT 24
Finished Jul 27 04:53:47 PM PDT 24
Peak memory 266388 kb
Host smart-cff8c5ea-dbb7-4a2d-a1a3-711d913290d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319568224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.2319568224
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.3859269211
Short name T202
Test name
Test status
Simulation time 14777626487 ps
CPU time 119.41 seconds
Started Jul 27 04:52:49 PM PDT 24
Finished Jul 27 04:54:48 PM PDT 24
Peak memory 236472 kb
Host smart-bb0fea4f-96d1-46ab-83a7-a60cccde9a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859269211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.3859269211
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.616343595
Short name T433
Test name
Test status
Simulation time 10239460823 ps
CPU time 64 seconds
Started Jul 27 04:52:42 PM PDT 24
Finished Jul 27 04:53:47 PM PDT 24
Peak memory 266864 kb
Host smart-83526af0-5d17-4165-ba0f-3b69a83a6c27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616343595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idle
.616343595
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.1133613289
Short name T346
Test name
Test status
Simulation time 602954678 ps
CPU time 4.39 seconds
Started Jul 27 04:52:33 PM PDT 24
Finished Jul 27 04:52:37 PM PDT 24
Peak memory 241732 kb
Host smart-9690b86d-1563-41ed-be0e-a80b7c19e6b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133613289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.1133613289
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.2883521946
Short name T745
Test name
Test status
Simulation time 8569785083 ps
CPU time 39.79 seconds
Started Jul 27 04:52:38 PM PDT 24
Finished Jul 27 04:53:18 PM PDT 24
Peak memory 251264 kb
Host smart-cc2ae3ed-9ebe-4ae2-b922-5e23523995de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883521946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmd
s.2883521946
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_intercept.894387206
Short name T255
Test name
Test status
Simulation time 588385289 ps
CPU time 4.81 seconds
Started Jul 27 04:52:31 PM PDT 24
Finished Jul 27 04:52:36 PM PDT 24
Peak memory 233504 kb
Host smart-bf4e48b8-fa14-4860-bbda-3d081baf524b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894387206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.894387206
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.1911699519
Short name T211
Test name
Test status
Simulation time 3775122311 ps
CPU time 11.6 seconds
Started Jul 27 04:52:33 PM PDT 24
Finished Jul 27 04:52:45 PM PDT 24
Peak memory 228892 kb
Host smart-62fbb588-b301-4441-887e-bcde8400398d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911699519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.1911699519
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.1693933842
Short name T228
Test name
Test status
Simulation time 8453457880 ps
CPU time 21.31 seconds
Started Jul 27 04:52:31 PM PDT 24
Finished Jul 27 04:52:52 PM PDT 24
Peak memory 225412 kb
Host smart-fb2bdefc-f845-4c61-90f6-0495fed6713c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693933842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.1693933842
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.1028169112
Short name T214
Test name
Test status
Simulation time 35290193990 ps
CPU time 18.01 seconds
Started Jul 27 04:52:36 PM PDT 24
Finished Jul 27 04:52:55 PM PDT 24
Peak memory 241824 kb
Host smart-e4c9f2a2-764c-401a-ad68-baac2329ed9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028169112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.1028169112
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.2796767291
Short name T498
Test name
Test status
Simulation time 859737966 ps
CPU time 5.51 seconds
Started Jul 27 04:52:29 PM PDT 24
Finished Jul 27 04:52:34 PM PDT 24
Peak memory 221716 kb
Host smart-b980dc1e-aa27-4fd4-b929-792a123a9c36
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2796767291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.2796767291
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.999594569
Short name T42
Test name
Test status
Simulation time 90593196178 ps
CPU time 99.26 seconds
Started Jul 27 04:52:27 PM PDT 24
Finished Jul 27 04:54:06 PM PDT 24
Peak memory 250168 kb
Host smart-01c85f35-8749-4a81-b754-348ef9369893
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999594569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stres
s_all.999594569
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.2205323862
Short name T525
Test name
Test status
Simulation time 20271164 ps
CPU time 0.74 seconds
Started Jul 27 04:52:41 PM PDT 24
Finished Jul 27 04:52:43 PM PDT 24
Peak memory 206564 kb
Host smart-540a8dbc-cb6d-4186-b540-7de56cc3ee93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205323862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.2205323862
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.1354452031
Short name T812
Test name
Test status
Simulation time 6426234611 ps
CPU time 16.59 seconds
Started Jul 27 04:52:30 PM PDT 24
Finished Jul 27 04:52:47 PM PDT 24
Peak memory 217152 kb
Host smart-7b4bb125-50d9-4a27-a941-3b94edbf4198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354452031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.1354452031
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.2344111043
Short name T426
Test name
Test status
Simulation time 28476668 ps
CPU time 1.03 seconds
Started Jul 27 04:52:31 PM PDT 24
Finished Jul 27 04:52:32 PM PDT 24
Peak memory 208980 kb
Host smart-a7cae9dc-6185-4062-8511-cafb13258970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344111043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.2344111043
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.2481919839
Short name T60
Test name
Test status
Simulation time 41527924 ps
CPU time 0.78 seconds
Started Jul 27 04:52:36 PM PDT 24
Finished Jul 27 04:52:37 PM PDT 24
Peak memory 206640 kb
Host smart-8b6e7684-eddf-4644-acb5-1fdaa562c156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481919839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.2481919839
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.4103211892
Short name T229
Test name
Test status
Simulation time 1568987506 ps
CPU time 8.59 seconds
Started Jul 27 04:52:42 PM PDT 24
Finished Jul 27 04:52:51 PM PDT 24
Peak memory 233516 kb
Host smart-2deca958-3a7a-4b7b-8929-53160d1ab276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103211892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.4103211892
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.3516598764
Short name T500
Test name
Test status
Simulation time 73445700 ps
CPU time 0.77 seconds
Started Jul 27 04:52:55 PM PDT 24
Finished Jul 27 04:52:56 PM PDT 24
Peak memory 206324 kb
Host smart-43334666-f649-4451-b613-8ff8f891cab9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516598764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
3516598764
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.4164922226
Short name T65
Test name
Test status
Simulation time 1666771002 ps
CPU time 5.81 seconds
Started Jul 27 04:52:34 PM PDT 24
Finished Jul 27 04:52:40 PM PDT 24
Peak memory 225396 kb
Host smart-6d6d82e2-a736-4590-a747-455cb755a2dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164922226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.4164922226
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.1803937776
Short name T369
Test name
Test status
Simulation time 19018294 ps
CPU time 0.78 seconds
Started Jul 27 04:52:32 PM PDT 24
Finished Jul 27 04:52:33 PM PDT 24
Peak memory 206136 kb
Host smart-90747448-8b22-40a5-b138-fa855068b586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803937776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.1803937776
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.1807383218
Short name T684
Test name
Test status
Simulation time 11911587485 ps
CPU time 38.84 seconds
Started Jul 27 04:52:40 PM PDT 24
Finished Jul 27 04:53:19 PM PDT 24
Peak memory 250044 kb
Host smart-d0dd39dd-f766-4f6e-adba-073833c484db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807383218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.1807383218
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.20404447
Short name T999
Test name
Test status
Simulation time 560826404 ps
CPU time 4.39 seconds
Started Jul 27 04:52:37 PM PDT 24
Finished Jul 27 04:52:41 PM PDT 24
Peak memory 218352 kb
Host smart-774097c0-0277-444d-8012-9baf545278fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20404447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.20404447
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.2973230251
Short name T491
Test name
Test status
Simulation time 10440865503 ps
CPU time 109.47 seconds
Started Jul 27 04:52:30 PM PDT 24
Finished Jul 27 04:54:19 PM PDT 24
Peak memory 265848 kb
Host smart-b03a16e9-5aa7-4317-b819-91c34adf49e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973230251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.2973230251
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.2538672249
Short name T816
Test name
Test status
Simulation time 1826722606 ps
CPU time 10.34 seconds
Started Jul 27 04:52:33 PM PDT 24
Finished Jul 27 04:52:43 PM PDT 24
Peak memory 238904 kb
Host smart-c4c91444-095f-47f5-b8a0-e7e90c3c7df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538672249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmd
s.2538672249
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_intercept.2338752765
Short name T675
Test name
Test status
Simulation time 130778961 ps
CPU time 2.67 seconds
Started Jul 27 04:52:32 PM PDT 24
Finished Jul 27 04:52:35 PM PDT 24
Peak memory 233608 kb
Host smart-1a4abf7e-560c-441e-87c5-13b9392b75f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338752765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.2338752765
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.773826462
Short name T271
Test name
Test status
Simulation time 3877462747 ps
CPU time 17.25 seconds
Started Jul 27 04:52:58 PM PDT 24
Finished Jul 27 04:53:16 PM PDT 24
Peak memory 240068 kb
Host smart-79d36fca-894a-4248-93b5-3a038027e9ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773826462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.773826462
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.2539774192
Short name T988
Test name
Test status
Simulation time 28535081 ps
CPU time 1.04 seconds
Started Jul 27 04:52:34 PM PDT 24
Finished Jul 27 04:52:35 PM PDT 24
Peak memory 217316 kb
Host smart-de2d2062-386e-4545-9bf8-025cd43c85a1
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539774192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.spi_device_mem_parity.2539774192
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.2003503930
Short name T835
Test name
Test status
Simulation time 27810710213 ps
CPU time 26.95 seconds
Started Jul 27 04:52:58 PM PDT 24
Finished Jul 27 04:53:26 PM PDT 24
Peak memory 250508 kb
Host smart-d08403fe-88e4-4408-ace0-22bf776d1052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003503930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.2003503930
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.2974061896
Short name T389
Test name
Test status
Simulation time 79854688093 ps
CPU time 22.12 seconds
Started Jul 27 04:52:40 PM PDT 24
Finished Jul 27 04:53:02 PM PDT 24
Peak memory 233688 kb
Host smart-79559658-c235-43be-988c-91d11541744c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974061896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.2974061896
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.2682842090
Short name T720
Test name
Test status
Simulation time 5090077362 ps
CPU time 15.07 seconds
Started Jul 27 04:52:34 PM PDT 24
Finished Jul 27 04:52:49 PM PDT 24
Peak memory 222916 kb
Host smart-0470a733-33f0-49a4-bb24-e883ccee9685
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2682842090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.2682842090
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.348573127
Short name T161
Test name
Test status
Simulation time 3615465044 ps
CPU time 36.65 seconds
Started Jul 27 04:52:38 PM PDT 24
Finished Jul 27 04:53:15 PM PDT 24
Peak memory 251080 kb
Host smart-ab10a012-08e1-4c37-a8a5-6bbb8c3128d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348573127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stres
s_all.348573127
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.2234887707
Short name T318
Test name
Test status
Simulation time 661158276 ps
CPU time 10.38 seconds
Started Jul 27 04:52:41 PM PDT 24
Finished Jul 27 04:52:52 PM PDT 24
Peak memory 217316 kb
Host smart-6c8f922e-25be-4654-a368-5ae5acf8ccbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234887707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.2234887707
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.2363207107
Short name T815
Test name
Test status
Simulation time 7357741070 ps
CPU time 19.26 seconds
Started Jul 27 04:52:31 PM PDT 24
Finished Jul 27 04:52:50 PM PDT 24
Peak memory 217232 kb
Host smart-d5374947-1a69-48be-b2b6-bea0a12cc730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363207107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.2363207107
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.2593566547
Short name T425
Test name
Test status
Simulation time 178240070 ps
CPU time 2.56 seconds
Started Jul 27 04:52:48 PM PDT 24
Finished Jul 27 04:52:50 PM PDT 24
Peak memory 217136 kb
Host smart-99e31b21-abf1-4506-82bc-7b8737e105e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593566547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.2593566547
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.2307744207
Short name T764
Test name
Test status
Simulation time 196145511 ps
CPU time 0.87 seconds
Started Jul 27 04:52:31 PM PDT 24
Finished Jul 27 04:52:32 PM PDT 24
Peak memory 206756 kb
Host smart-3e089fa1-6845-40a0-943d-4cfc233399f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307744207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.2307744207
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.2133923121
Short name T246
Test name
Test status
Simulation time 140721113 ps
CPU time 2.82 seconds
Started Jul 27 04:52:38 PM PDT 24
Finished Jul 27 04:52:41 PM PDT 24
Peak memory 233576 kb
Host smart-33ed3bc8-8a68-4f52-9e7a-f053beea3c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133923121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.2133923121
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.4263631191
Short name T711
Test name
Test status
Simulation time 38732660 ps
CPU time 0.67 seconds
Started Jul 27 04:52:33 PM PDT 24
Finished Jul 27 04:52:34 PM PDT 24
Peak memory 206384 kb
Host smart-fd31d443-3c5e-4de5-948f-61f2c6ddac1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263631191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
4263631191
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.2635337013
Short name T742
Test name
Test status
Simulation time 5626342691 ps
CPU time 6.66 seconds
Started Jul 27 04:52:39 PM PDT 24
Finished Jul 27 04:52:46 PM PDT 24
Peak memory 225484 kb
Host smart-275a5728-c4e5-4100-ba6b-2e43c72236f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635337013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.2635337013
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.4176959860
Short name T625
Test name
Test status
Simulation time 16572615 ps
CPU time 0.75 seconds
Started Jul 27 04:52:40 PM PDT 24
Finished Jul 27 04:52:41 PM PDT 24
Peak memory 206132 kb
Host smart-82d6c21f-498b-4e3a-80b9-06b1927d86c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176959860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.4176959860
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.2745010486
Short name T438
Test name
Test status
Simulation time 9131875440 ps
CPU time 72.66 seconds
Started Jul 27 04:52:40 PM PDT 24
Finished Jul 27 04:53:53 PM PDT 24
Peak memory 249976 kb
Host smart-1145ec14-e2b0-45cb-afcb-8410454fff84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745010486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.2745010486
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.2446690861
Short name T322
Test name
Test status
Simulation time 3050733610 ps
CPU time 22.85 seconds
Started Jul 27 04:52:31 PM PDT 24
Finished Jul 27 04:52:54 PM PDT 24
Peak memory 233700 kb
Host smart-7933f6a0-1856-4c1f-8b78-8648f39492c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446690861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.2446690861
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.2962151080
Short name T779
Test name
Test status
Simulation time 118222704 ps
CPU time 3.2 seconds
Started Jul 27 04:52:35 PM PDT 24
Finished Jul 27 04:52:38 PM PDT 24
Peak memory 225400 kb
Host smart-733b235d-6d68-4ab9-b4e5-8d5b9c536b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962151080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.2962151080
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.2134664137
Short name T85
Test name
Test status
Simulation time 161194404492 ps
CPU time 245.61 seconds
Started Jul 27 04:52:31 PM PDT 24
Finished Jul 27 04:56:37 PM PDT 24
Peak memory 254732 kb
Host smart-cf4f050e-1987-4c1a-9891-3623c39ed3f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134664137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmd
s.2134664137
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/13.spi_device_intercept.4034172654
Short name T540
Test name
Test status
Simulation time 3700833922 ps
CPU time 10.07 seconds
Started Jul 27 04:52:29 PM PDT 24
Finished Jul 27 04:52:39 PM PDT 24
Peak memory 225448 kb
Host smart-7c255735-675f-45eb-a6d0-f9aaf75b9c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034172654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.4034172654
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.242788135
Short name T458
Test name
Test status
Simulation time 8340292959 ps
CPU time 44.41 seconds
Started Jul 27 04:52:39 PM PDT 24
Finished Jul 27 04:53:24 PM PDT 24
Peak memory 233560 kb
Host smart-968fe0d5-468f-47fb-8b9e-9cd1b13030dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242788135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.242788135
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.2531760778
Short name T651
Test name
Test status
Simulation time 128898712 ps
CPU time 1.08 seconds
Started Jul 27 04:52:33 PM PDT 24
Finished Jul 27 04:52:34 PM PDT 24
Peak memory 217360 kb
Host smart-e9a49d45-d675-481f-b8a4-c9d6434bb4f1
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531760778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.spi_device_mem_parity.2531760778
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.2605527403
Short name T1009
Test name
Test status
Simulation time 144192646 ps
CPU time 3.45 seconds
Started Jul 27 04:52:33 PM PDT 24
Finished Jul 27 04:52:37 PM PDT 24
Peak memory 233600 kb
Host smart-f3fe2d3e-8232-48ba-8271-2c3ea30b55ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605527403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.2605527403
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.3570610796
Short name T977
Test name
Test status
Simulation time 120446642 ps
CPU time 2.51 seconds
Started Jul 27 04:52:34 PM PDT 24
Finished Jul 27 04:52:37 PM PDT 24
Peak memory 233168 kb
Host smart-cbb3f2af-cee0-4ca9-8213-aa30bef91bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570610796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.3570610796
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.3933743252
Short name T153
Test name
Test status
Simulation time 2073092400 ps
CPU time 7.01 seconds
Started Jul 27 04:52:45 PM PDT 24
Finished Jul 27 04:52:52 PM PDT 24
Peak memory 223212 kb
Host smart-e99234a4-cdf4-46f8-bc1f-17ae889e1d1d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3933743252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.3933743252
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.1228197403
Short name T723
Test name
Test status
Simulation time 130628461 ps
CPU time 0.91 seconds
Started Jul 27 04:52:33 PM PDT 24
Finished Jul 27 04:52:34 PM PDT 24
Peak memory 207232 kb
Host smart-d574c7c2-7378-46b9-b138-7aa3b49d89a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228197403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.1228197403
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.1714110943
Short name T316
Test name
Test status
Simulation time 2564613093 ps
CPU time 5.22 seconds
Started Jul 27 04:52:42 PM PDT 24
Finished Jul 27 04:52:47 PM PDT 24
Peak memory 217384 kb
Host smart-254757ca-9100-4020-90a6-bfa8aae69e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714110943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.1714110943
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.623169744
Short name T537
Test name
Test status
Simulation time 22010004537 ps
CPU time 6.68 seconds
Started Jul 27 04:52:31 PM PDT 24
Finished Jul 27 04:52:38 PM PDT 24
Peak memory 217136 kb
Host smart-b5e2d855-a3ef-462a-abf3-864890eb2008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623169744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.623169744
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.2573725568
Short name T878
Test name
Test status
Simulation time 15607354 ps
CPU time 0.88 seconds
Started Jul 27 04:52:30 PM PDT 24
Finished Jul 27 04:52:31 PM PDT 24
Peak memory 207708 kb
Host smart-91a4ef27-9186-431c-8680-c537d5dddf29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573725568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.2573725568
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.4046454299
Short name T940
Test name
Test status
Simulation time 90584537 ps
CPU time 0.84 seconds
Started Jul 27 04:52:41 PM PDT 24
Finished Jul 27 04:52:42 PM PDT 24
Peak memory 206716 kb
Host smart-3a6ddc6c-215f-4bd2-b782-ba20738e10e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046454299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.4046454299
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.86690465
Short name T763
Test name
Test status
Simulation time 2682115283 ps
CPU time 4.12 seconds
Started Jul 27 04:52:41 PM PDT 24
Finished Jul 27 04:52:45 PM PDT 24
Peak memory 233636 kb
Host smart-86ce372f-4590-40de-bc07-0b77e4cd75d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86690465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.86690465
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.2584297057
Short name T954
Test name
Test status
Simulation time 11813335 ps
CPU time 0.75 seconds
Started Jul 27 04:52:33 PM PDT 24
Finished Jul 27 04:52:34 PM PDT 24
Peak memory 205328 kb
Host smart-58dc6350-9aec-408a-8d4d-613946128fce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584297057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
2584297057
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.1134777161
Short name T92
Test name
Test status
Simulation time 1890301799 ps
CPU time 5.91 seconds
Started Jul 27 04:52:48 PM PDT 24
Finished Jul 27 04:52:54 PM PDT 24
Peak memory 233604 kb
Host smart-3f959395-43ef-475d-8dc3-8090ab341449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134777161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.1134777161
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.3182537088
Short name T370
Test name
Test status
Simulation time 35853979 ps
CPU time 0.76 seconds
Started Jul 27 04:52:32 PM PDT 24
Finished Jul 27 04:52:33 PM PDT 24
Peak memory 206248 kb
Host smart-e1b4c446-d60c-48e6-8483-86e9894eb6dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182537088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.3182537088
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.2246429728
Short name T607
Test name
Test status
Simulation time 5453863337 ps
CPU time 20.44 seconds
Started Jul 27 04:53:01 PM PDT 24
Finished Jul 27 04:53:21 PM PDT 24
Peak memory 225532 kb
Host smart-3a045a2d-2f32-467b-9b39-d440af99d81c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246429728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.2246429728
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.2770607639
Short name T79
Test name
Test status
Simulation time 19346271665 ps
CPU time 191.97 seconds
Started Jul 27 04:52:36 PM PDT 24
Finished Jul 27 04:55:48 PM PDT 24
Peak memory 257256 kb
Host smart-b5eb6ccd-7034-4a98-b6e2-e37938955db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770607639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.2770607639
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.4032660607
Short name T580
Test name
Test status
Simulation time 5663116916 ps
CPU time 37.07 seconds
Started Jul 27 04:52:42 PM PDT 24
Finished Jul 27 04:53:19 PM PDT 24
Peak memory 218432 kb
Host smart-fdae6eac-2c5c-4845-9f53-35f48bf8bf18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032660607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.4032660607
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.3498932593
Short name T178
Test name
Test status
Simulation time 83967332540 ps
CPU time 152.97 seconds
Started Jul 27 04:52:50 PM PDT 24
Finished Jul 27 04:55:23 PM PDT 24
Peak memory 250876 kb
Host smart-1b632509-90e1-42ac-99d3-a8c957cedab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498932593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmd
s.3498932593
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_intercept.2608781659
Short name T646
Test name
Test status
Simulation time 1859976804 ps
CPU time 21.49 seconds
Started Jul 27 04:52:34 PM PDT 24
Finished Jul 27 04:52:56 PM PDT 24
Peak memory 225392 kb
Host smart-6a0e76bb-7197-4616-aca7-6c186fdaee3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608781659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.2608781659
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.3163551476
Short name T269
Test name
Test status
Simulation time 5859774016 ps
CPU time 16.42 seconds
Started Jul 27 04:52:31 PM PDT 24
Finished Jul 27 04:52:48 PM PDT 24
Peak memory 233716 kb
Host smart-bcf67ea6-366d-4a8f-b2e4-2569664b9ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163551476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.3163551476
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.2772439558
Short name T416
Test name
Test status
Simulation time 56040683 ps
CPU time 1.07 seconds
Started Jul 27 04:52:52 PM PDT 24
Finished Jul 27 04:52:54 PM PDT 24
Peak memory 217416 kb
Host smart-ab71553c-39f9-42b4-9f3f-3c82cfde4c28
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772439558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.spi_device_mem_parity.2772439558
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.2553159033
Short name T302
Test name
Test status
Simulation time 9895480467 ps
CPU time 12.37 seconds
Started Jul 27 04:52:34 PM PDT 24
Finished Jul 27 04:52:46 PM PDT 24
Peak memory 233560 kb
Host smart-107a2196-5e52-415f-8157-94f51fc12105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553159033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.2553159033
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.4088763043
Short name T248
Test name
Test status
Simulation time 13135422279 ps
CPU time 21.33 seconds
Started Jul 27 04:52:55 PM PDT 24
Finished Jul 27 04:53:17 PM PDT 24
Peak memory 240664 kb
Host smart-6c368700-6448-48d8-8d01-2ab20ba8c354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088763043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.4088763043
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.526311605
Short name T597
Test name
Test status
Simulation time 990054867 ps
CPU time 5.52 seconds
Started Jul 27 04:52:35 PM PDT 24
Finished Jul 27 04:52:41 PM PDT 24
Peak memory 221044 kb
Host smart-9d3ebac2-7657-43a2-85af-eb941d028ba0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=526311605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dire
ct.526311605
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.780377033
Short name T674
Test name
Test status
Simulation time 11008604892 ps
CPU time 93.94 seconds
Started Jul 27 04:52:34 PM PDT 24
Finished Jul 27 04:54:08 PM PDT 24
Peak memory 250148 kb
Host smart-a592e26a-667e-4f40-922f-8f13576fa65f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780377033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stres
s_all.780377033
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.2175030667
Short name T393
Test name
Test status
Simulation time 12187341 ps
CPU time 0.7 seconds
Started Jul 27 04:52:42 PM PDT 24
Finished Jul 27 04:52:43 PM PDT 24
Peak memory 206420 kb
Host smart-d37bdd46-3139-434d-a15b-dad00b382254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175030667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.2175030667
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.3065102345
Short name T407
Test name
Test status
Simulation time 2251196595 ps
CPU time 6.58 seconds
Started Jul 27 04:52:44 PM PDT 24
Finished Jul 27 04:52:50 PM PDT 24
Peak memory 217220 kb
Host smart-d3476452-d211-4d48-aa49-51363d8da620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065102345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.3065102345
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.609076690
Short name T951
Test name
Test status
Simulation time 11836512 ps
CPU time 0.69 seconds
Started Jul 27 04:52:31 PM PDT 24
Finished Jul 27 04:52:31 PM PDT 24
Peak memory 206292 kb
Host smart-3e67f803-f553-44a6-b713-8716ca9e23e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609076690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.609076690
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.795136004
Short name T905
Test name
Test status
Simulation time 40000528 ps
CPU time 0.84 seconds
Started Jul 27 04:52:32 PM PDT 24
Finished Jul 27 04:52:34 PM PDT 24
Peak memory 206744 kb
Host smart-91400031-f5be-4f99-99dd-73d2352dfa62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795136004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.795136004
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.1140260895
Short name T681
Test name
Test status
Simulation time 2055938158 ps
CPU time 3.79 seconds
Started Jul 27 04:52:49 PM PDT 24
Finished Jul 27 04:52:53 PM PDT 24
Peak memory 233596 kb
Host smart-020ab52c-3c85-4c86-96d3-78f9152ccd96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140260895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.1140260895
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.1568813754
Short name T72
Test name
Test status
Simulation time 34064314 ps
CPU time 0.72 seconds
Started Jul 27 04:52:53 PM PDT 24
Finished Jul 27 04:52:54 PM PDT 24
Peak memory 206332 kb
Host smart-f91fbd05-19f7-4ccd-965d-61c8df928d19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568813754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
1568813754
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.1056254800
Short name T8
Test name
Test status
Simulation time 154509258 ps
CPU time 3.08 seconds
Started Jul 27 04:52:49 PM PDT 24
Finished Jul 27 04:52:52 PM PDT 24
Peak memory 225376 kb
Host smart-b2771c20-6f11-4c8f-a808-1806e9e2ed44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056254800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.1056254800
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.3599656435
Short name T27
Test name
Test status
Simulation time 39133653 ps
CPU time 0.77 seconds
Started Jul 27 04:52:44 PM PDT 24
Finished Jul 27 04:52:45 PM PDT 24
Peak memory 207224 kb
Host smart-409ae34d-cfcb-4994-8a4b-a9cd25812e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599656435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.3599656435
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.2999163100
Short name T262
Test name
Test status
Simulation time 2438544785 ps
CPU time 40.41 seconds
Started Jul 27 04:52:59 PM PDT 24
Finished Jul 27 04:53:40 PM PDT 24
Peak memory 252832 kb
Host smart-32fa994d-3157-45ec-8fc6-1225475398cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999163100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.2999163100
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.756090968
Short name T826
Test name
Test status
Simulation time 28651442414 ps
CPU time 247.21 seconds
Started Jul 27 04:52:48 PM PDT 24
Finished Jul 27 04:56:55 PM PDT 24
Peak memory 256256 kb
Host smart-76a961af-a121-4596-aa9a-51f5a776debc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756090968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.756090968
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.1813890696
Short name T877
Test name
Test status
Simulation time 367877533272 ps
CPU time 295.55 seconds
Started Jul 27 04:52:53 PM PDT 24
Finished Jul 27 04:57:49 PM PDT 24
Peak memory 251984 kb
Host smart-4183317d-da16-4834-ae15-a0ac88be7aab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813890696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.1813890696
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.1070243891
Short name T870
Test name
Test status
Simulation time 1610497585 ps
CPU time 22.36 seconds
Started Jul 27 04:52:55 PM PDT 24
Finished Jul 27 04:53:17 PM PDT 24
Peak memory 233624 kb
Host smart-a3db0560-b89a-482a-9be5-eeb61789e6ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070243891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.1070243891
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.1990078167
Short name T241
Test name
Test status
Simulation time 3841103644 ps
CPU time 28 seconds
Started Jul 27 04:52:44 PM PDT 24
Finished Jul 27 04:53:12 PM PDT 24
Peak memory 239424 kb
Host smart-84ec8544-66c2-43b6-9207-ed444953fde9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990078167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmd
s.1990078167
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/15.spi_device_intercept.1306998219
Short name T685
Test name
Test status
Simulation time 249399524 ps
CPU time 2.64 seconds
Started Jul 27 04:52:55 PM PDT 24
Finished Jul 27 04:52:58 PM PDT 24
Peak memory 225376 kb
Host smart-decf2958-075f-48ae-a951-8d75c4cacd52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306998219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.1306998219
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.2887436325
Short name T665
Test name
Test status
Simulation time 464328987 ps
CPU time 3.95 seconds
Started Jul 27 04:52:56 PM PDT 24
Finished Jul 27 04:53:00 PM PDT 24
Peak memory 233484 kb
Host smart-43982fb7-3ef1-4d9d-910b-5b19c8eae005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887436325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.2887436325
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.2629399774
Short name T546
Test name
Test status
Simulation time 30936540 ps
CPU time 1 seconds
Started Jul 27 04:52:39 PM PDT 24
Finished Jul 27 04:52:40 PM PDT 24
Peak memory 218572 kb
Host smart-617e081d-416b-4a58-8001-021d1fc82a16
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629399774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.2629399774
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.3206949424
Short name T919
Test name
Test status
Simulation time 1494045468 ps
CPU time 12.43 seconds
Started Jul 27 04:52:46 PM PDT 24
Finished Jul 27 04:52:59 PM PDT 24
Peak memory 225276 kb
Host smart-740aeb15-0198-4dba-867e-7ae027c20805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206949424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.3206949424
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.1187029893
Short name T249
Test name
Test status
Simulation time 902494415 ps
CPU time 3.8 seconds
Started Jul 27 04:52:54 PM PDT 24
Finished Jul 27 04:52:58 PM PDT 24
Peak memory 225260 kb
Host smart-8d3f7dfd-4a4d-409e-a2df-9a9025e997a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187029893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.1187029893
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.449643230
Short name T152
Test name
Test status
Simulation time 1012329297 ps
CPU time 7.92 seconds
Started Jul 27 04:53:09 PM PDT 24
Finished Jul 27 04:53:17 PM PDT 24
Peak memory 222888 kb
Host smart-20de0b72-7b84-435a-b1b5-dc2ab646082b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=449643230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dire
ct.449643230
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.425493701
Short name T164
Test name
Test status
Simulation time 13605789226 ps
CPU time 131.56 seconds
Started Jul 27 04:52:57 PM PDT 24
Finished Jul 27 04:55:09 PM PDT 24
Peak memory 257388 kb
Host smart-7a3f1ae7-04a4-40fc-a321-9efc02580bca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425493701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stres
s_all.425493701
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.3621149512
Short name T868
Test name
Test status
Simulation time 37841578 ps
CPU time 0.73 seconds
Started Jul 27 04:52:55 PM PDT 24
Finished Jul 27 04:52:56 PM PDT 24
Peak memory 206296 kb
Host smart-9a3fc9d9-2973-40fc-86c3-8f9474d84ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621149512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.3621149512
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.1335076776
Short name T347
Test name
Test status
Simulation time 29237242297 ps
CPU time 17.11 seconds
Started Jul 27 04:52:50 PM PDT 24
Finished Jul 27 04:53:07 PM PDT 24
Peak memory 217228 kb
Host smart-bbb9a050-b578-448b-a9ee-f08ed4f5fe16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335076776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.1335076776
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.590760445
Short name T688
Test name
Test status
Simulation time 190123338 ps
CPU time 1.17 seconds
Started Jul 27 04:53:02 PM PDT 24
Finished Jul 27 04:53:03 PM PDT 24
Peak memory 208636 kb
Host smart-467dc107-1e7f-425a-a1ea-36875cfe31f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590760445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.590760445
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.3992586112
Short name T397
Test name
Test status
Simulation time 60033971 ps
CPU time 0.84 seconds
Started Jul 27 04:52:50 PM PDT 24
Finished Jul 27 04:52:51 PM PDT 24
Peak memory 207756 kb
Host smart-4136c0be-50cd-4364-b2c3-f5c2ecfbcd99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992586112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.3992586112
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.3689620808
Short name T672
Test name
Test status
Simulation time 85640280 ps
CPU time 2.32 seconds
Started Jul 27 04:52:55 PM PDT 24
Finished Jul 27 04:52:57 PM PDT 24
Peak memory 224948 kb
Host smart-c2b9dd27-e105-4c50-825e-204bfe5e8894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689620808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.3689620808
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.893863164
Short name T383
Test name
Test status
Simulation time 32257541 ps
CPU time 0.73 seconds
Started Jul 27 04:52:43 PM PDT 24
Finished Jul 27 04:52:44 PM PDT 24
Peak memory 205420 kb
Host smart-4046a946-5fc8-453e-9631-82f6a0ea5eb6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893863164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.893863164
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.578542849
Short name T329
Test name
Test status
Simulation time 167352161 ps
CPU time 3.8 seconds
Started Jul 27 04:52:51 PM PDT 24
Finished Jul 27 04:52:55 PM PDT 24
Peak memory 233552 kb
Host smart-5c0c4da2-b796-4d8e-ab14-0f5c09f10b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578542849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.578542849
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.2693534339
Short name T414
Test name
Test status
Simulation time 40031919 ps
CPU time 0.83 seconds
Started Jul 27 04:52:54 PM PDT 24
Finished Jul 27 04:52:55 PM PDT 24
Peak memory 206156 kb
Host smart-c466253c-17e8-42c8-bca2-763f8306521c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693534339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.2693534339
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.1989875037
Short name T843
Test name
Test status
Simulation time 79924962527 ps
CPU time 334.04 seconds
Started Jul 27 04:52:59 PM PDT 24
Finished Jul 27 04:58:34 PM PDT 24
Peak memory 274608 kb
Host smart-5639772f-0926-4572-898d-795f82c5cb54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989875037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.1989875037
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.4142990566
Short name T216
Test name
Test status
Simulation time 2706528063 ps
CPU time 57.59 seconds
Started Jul 27 04:52:50 PM PDT 24
Finished Jul 27 04:53:47 PM PDT 24
Peak memory 233600 kb
Host smart-40c7bac9-07dc-4f06-aa62-881d39302e45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142990566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.4142990566
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.2800078220
Short name T145
Test name
Test status
Simulation time 5900251929 ps
CPU time 100.81 seconds
Started Jul 27 04:52:49 PM PDT 24
Finished Jul 27 04:54:30 PM PDT 24
Peak memory 264044 kb
Host smart-74c00650-08b4-4c38-b3d1-c6b111c8bac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800078220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.2800078220
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.1832782780
Short name T957
Test name
Test status
Simulation time 963850536 ps
CPU time 8.84 seconds
Started Jul 27 04:52:50 PM PDT 24
Finished Jul 27 04:52:59 PM PDT 24
Peak memory 234744 kb
Host smart-15bc9653-8760-4305-8892-25368d5b910d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832782780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.1832782780
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.2753248553
Short name T96
Test name
Test status
Simulation time 2634098700 ps
CPU time 59 seconds
Started Jul 27 04:52:48 PM PDT 24
Finished Jul 27 04:53:47 PM PDT 24
Peak memory 249980 kb
Host smart-ec9be427-0c06-410f-a964-817803843d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753248553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmd
s.2753248553
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/16.spi_device_intercept.1440666292
Short name T591
Test name
Test status
Simulation time 497378522 ps
CPU time 3.72 seconds
Started Jul 27 04:52:45 PM PDT 24
Finished Jul 27 04:52:49 PM PDT 24
Peak memory 233432 kb
Host smart-2fa5ec71-d873-4d45-b5c2-ebd3be6a7075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440666292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.1440666292
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.1169073395
Short name T655
Test name
Test status
Simulation time 17872234827 ps
CPU time 31.02 seconds
Started Jul 27 04:52:46 PM PDT 24
Finished Jul 27 04:53:18 PM PDT 24
Peak memory 239460 kb
Host smart-8942344d-4f02-4492-b42e-22614dc14133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169073395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.1169073395
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.188125467
Short name T488
Test name
Test status
Simulation time 29399098 ps
CPU time 0.98 seconds
Started Jul 27 04:52:52 PM PDT 24
Finished Jul 27 04:52:53 PM PDT 24
Peak memory 217352 kb
Host smart-eb6107af-fbba-427d-9444-01a58a17e683
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188125467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.spi_device_mem_parity.188125467
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.3036721032
Short name T377
Test name
Test status
Simulation time 1718420321 ps
CPU time 6.66 seconds
Started Jul 27 04:52:53 PM PDT 24
Finished Jul 27 04:53:00 PM PDT 24
Peak memory 233612 kb
Host smart-8cb4fe6d-6201-4835-978d-f0975fe52222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036721032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.3036721032
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.189166467
Short name T645
Test name
Test status
Simulation time 2629519350 ps
CPU time 4.21 seconds
Started Jul 27 04:53:01 PM PDT 24
Finished Jul 27 04:53:06 PM PDT 24
Peak memory 225380 kb
Host smart-4fe78f77-f39d-48b8-84da-9b5344a68590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189166467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.189166467
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.2474873544
Short name T701
Test name
Test status
Simulation time 4712014616 ps
CPU time 14.18 seconds
Started Jul 27 04:52:47 PM PDT 24
Finished Jul 27 04:53:01 PM PDT 24
Peak memory 219892 kb
Host smart-57e2e4d4-d589-4190-becc-f4c7ec7e2c42
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2474873544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.2474873544
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.2468533043
Short name T169
Test name
Test status
Simulation time 151390117867 ps
CPU time 331.57 seconds
Started Jul 27 04:53:13 PM PDT 24
Finished Jul 27 04:58:45 PM PDT 24
Peak memory 282572 kb
Host smart-82e87067-05f5-4dc0-99a0-99a61a426a42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468533043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.2468533043
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.2999098372
Short name T869
Test name
Test status
Simulation time 7753353340 ps
CPU time 24.16 seconds
Started Jul 27 04:53:10 PM PDT 24
Finished Jul 27 04:53:34 PM PDT 24
Peak memory 217264 kb
Host smart-42bcf527-80a3-4e81-9c76-54c071e46556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999098372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.2999098372
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.2578578930
Short name T345
Test name
Test status
Simulation time 9309749357 ps
CPU time 26.67 seconds
Started Jul 27 04:52:56 PM PDT 24
Finished Jul 27 04:53:23 PM PDT 24
Peak memory 217164 kb
Host smart-d9073968-c02d-4b13-8b0c-2d6e777ed339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578578930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.2578578930
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.2561728993
Short name T565
Test name
Test status
Simulation time 67106642 ps
CPU time 1.59 seconds
Started Jul 27 04:52:59 PM PDT 24
Finished Jul 27 04:53:01 PM PDT 24
Peak memory 217120 kb
Host smart-22fd7ac0-6e0e-44a2-a203-fa1e5f55062a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561728993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.2561728993
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.4177900372
Short name T340
Test name
Test status
Simulation time 16187872 ps
CPU time 0.74 seconds
Started Jul 27 04:52:51 PM PDT 24
Finished Jul 27 04:52:52 PM PDT 24
Peak memory 206676 kb
Host smart-ce56a4d5-3200-4831-8b16-c2bdfe8c0931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177900372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.4177900372
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.3299458104
Short name T517
Test name
Test status
Simulation time 123332284 ps
CPU time 2.25 seconds
Started Jul 27 04:52:51 PM PDT 24
Finished Jul 27 04:52:53 PM PDT 24
Peak memory 225288 kb
Host smart-4992e118-406d-4ddf-a6f0-3462eddfc03d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299458104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.3299458104
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.3706653040
Short name T609
Test name
Test status
Simulation time 11514768 ps
CPU time 0.7 seconds
Started Jul 27 04:52:52 PM PDT 24
Finished Jul 27 04:52:54 PM PDT 24
Peak memory 205476 kb
Host smart-290a33a2-3a6d-41b0-8c13-74f0f128923c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706653040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
3706653040
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.3974176164
Short name T811
Test name
Test status
Simulation time 8942694652 ps
CPU time 6.24 seconds
Started Jul 27 04:52:50 PM PDT 24
Finished Jul 27 04:52:57 PM PDT 24
Peak memory 233596 kb
Host smart-64f14ce8-a86a-4e2d-badb-ab6f013fbb9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974176164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.3974176164
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.659054388
Short name T774
Test name
Test status
Simulation time 70416929 ps
CPU time 0.78 seconds
Started Jul 27 04:52:47 PM PDT 24
Finished Jul 27 04:52:48 PM PDT 24
Peak memory 207448 kb
Host smart-f2ab4012-bf17-4579-b7c9-901c533ec89e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659054388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.659054388
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.1058160113
Short name T982
Test name
Test status
Simulation time 12644240 ps
CPU time 0.73 seconds
Started Jul 27 04:52:42 PM PDT 24
Finished Jul 27 04:52:43 PM PDT 24
Peak memory 216552 kb
Host smart-493c3b48-db38-427a-b6c8-4185d2fb45cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058160113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.1058160113
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.1498874204
Short name T395
Test name
Test status
Simulation time 3337134945 ps
CPU time 14.98 seconds
Started Jul 27 04:52:55 PM PDT 24
Finished Jul 27 04:53:11 PM PDT 24
Peak memory 225512 kb
Host smart-0e7361a0-3b7a-4944-9653-e7b930ebd82f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498874204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.1498874204
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.484077630
Short name T792
Test name
Test status
Simulation time 12696127657 ps
CPU time 44.17 seconds
Started Jul 27 04:53:16 PM PDT 24
Finished Jul 27 04:54:00 PM PDT 24
Peak memory 250076 kb
Host smart-ef82086d-9d48-4115-b743-d0ae8b8d3d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484077630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.484077630
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.4120815512
Short name T781
Test name
Test status
Simulation time 22726100 ps
CPU time 0.77 seconds
Started Jul 27 04:52:54 PM PDT 24
Finished Jul 27 04:52:54 PM PDT 24
Peak memory 216548 kb
Host smart-eceee2d1-7eaa-46e7-a8b6-2c5ca5c83cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120815512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmd
s.4120815512
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/17.spi_device_intercept.377518966
Short name T598
Test name
Test status
Simulation time 3824898280 ps
CPU time 12.16 seconds
Started Jul 27 04:52:56 PM PDT 24
Finished Jul 27 04:53:08 PM PDT 24
Peak memory 233560 kb
Host smart-3952ab94-40ee-4f2a-8e3a-5f53b614b8be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377518966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.377518966
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.1617824654
Short name T280
Test name
Test status
Simulation time 6063841286 ps
CPU time 10.06 seconds
Started Jul 27 04:52:42 PM PDT 24
Finished Jul 27 04:52:52 PM PDT 24
Peak memory 241536 kb
Host smart-92bff519-e152-4924-9a51-d4bd5ead95eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617824654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.1617824654
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.3431460097
Short name T46
Test name
Test status
Simulation time 124371148 ps
CPU time 1.05 seconds
Started Jul 27 04:52:57 PM PDT 24
Finished Jul 27 04:52:58 PM PDT 24
Peak memory 218560 kb
Host smart-be0879da-51d9-4832-aff1-5105a46f8e31
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431460097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.spi_device_mem_parity.3431460097
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.3230300479
Short name T264
Test name
Test status
Simulation time 8167637602 ps
CPU time 4.25 seconds
Started Jul 27 04:52:56 PM PDT 24
Finished Jul 27 04:53:00 PM PDT 24
Peak memory 233544 kb
Host smart-9fa03ad3-acce-4aae-bcea-9a56506f83db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230300479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.3230300479
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.3484005248
Short name T256
Test name
Test status
Simulation time 309219601 ps
CPU time 3.32 seconds
Started Jul 27 04:52:52 PM PDT 24
Finished Jul 27 04:52:55 PM PDT 24
Peak memory 233508 kb
Host smart-03828790-11c3-4607-b8b8-b9b62665f614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484005248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.3484005248
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.3378749843
Short name T586
Test name
Test status
Simulation time 303574711 ps
CPU time 3.49 seconds
Started Jul 27 04:52:52 PM PDT 24
Finished Jul 27 04:52:56 PM PDT 24
Peak memory 221176 kb
Host smart-05329f42-e81a-432b-817d-3fbfa31956e9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3378749843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.3378749843
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.1597825067
Short name T736
Test name
Test status
Simulation time 20792637631 ps
CPU time 218.32 seconds
Started Jul 27 04:52:41 PM PDT 24
Finished Jul 27 04:56:20 PM PDT 24
Peak memory 261400 kb
Host smart-cbf4673f-8227-4009-a93b-cbadaaff8589
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597825067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.1597825067
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.2791620683
Short name T483
Test name
Test status
Simulation time 18416966100 ps
CPU time 21.81 seconds
Started Jul 27 04:52:54 PM PDT 24
Finished Jul 27 04:53:16 PM PDT 24
Peak memory 217216 kb
Host smart-e3790770-9261-46a4-8ec2-8128b70e0af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791620683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.2791620683
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.4281092746
Short name T590
Test name
Test status
Simulation time 4201187241 ps
CPU time 8.16 seconds
Started Jul 27 04:52:53 PM PDT 24
Finished Jul 27 04:53:01 PM PDT 24
Peak memory 217108 kb
Host smart-16a55a07-daa2-463a-898f-cb15b93d14bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281092746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.4281092746
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.97397247
Short name T814
Test name
Test status
Simulation time 69584118 ps
CPU time 1.6 seconds
Started Jul 27 04:52:51 PM PDT 24
Finished Jul 27 04:52:52 PM PDT 24
Peak memory 217016 kb
Host smart-bfbb1c55-13d1-4e8d-a649-e5a3ee4a55d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97397247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.97397247
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.654163524
Short name T516
Test name
Test status
Simulation time 84158719 ps
CPU time 0.74 seconds
Started Jul 27 04:52:58 PM PDT 24
Finished Jul 27 04:52:59 PM PDT 24
Peak memory 206724 kb
Host smart-43425b63-c028-429d-9a8b-d77eadeb2cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654163524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.654163524
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.4180877174
Short name T809
Test name
Test status
Simulation time 32894649 ps
CPU time 2.42 seconds
Started Jul 27 04:52:49 PM PDT 24
Finished Jul 27 04:52:52 PM PDT 24
Peak memory 233624 kb
Host smart-40384b07-4ff2-4de3-8fb0-7f7fdc8a5fc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180877174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.4180877174
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.3287193589
Short name T775
Test name
Test status
Simulation time 23245640 ps
CPU time 0.73 seconds
Started Jul 27 04:52:56 PM PDT 24
Finished Jul 27 04:52:57 PM PDT 24
Peak memory 205984 kb
Host smart-95ed8bc1-fcae-4e63-8632-5e5314002a3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287193589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
3287193589
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.3571592821
Short name T350
Test name
Test status
Simulation time 122054756 ps
CPU time 2.47 seconds
Started Jul 27 04:53:02 PM PDT 24
Finished Jul 27 04:53:05 PM PDT 24
Peak memory 233492 kb
Host smart-018522fa-456e-45e0-a664-4311bed5b9a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571592821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.3571592821
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.1541892293
Short name T656
Test name
Test status
Simulation time 12868873 ps
CPU time 0.76 seconds
Started Jul 27 04:52:51 PM PDT 24
Finished Jul 27 04:52:52 PM PDT 24
Peak memory 206116 kb
Host smart-bd122d2c-6e00-477a-9e6f-d6782ac3e2d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541892293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.1541892293
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.1778838706
Short name T969
Test name
Test status
Simulation time 19432467189 ps
CPU time 155.52 seconds
Started Jul 27 04:52:56 PM PDT 24
Finished Jul 27 04:55:31 PM PDT 24
Peak memory 258164 kb
Host smart-d9aebc89-d42c-43b8-ae9a-433e8ad93907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778838706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.1778838706
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.16813388
Short name T227
Test name
Test status
Simulation time 4060004311 ps
CPU time 27.55 seconds
Started Jul 27 04:52:55 PM PDT 24
Finished Jul 27 04:53:23 PM PDT 24
Peak memory 250168 kb
Host smart-baf8d3e1-4a63-4135-bbb1-7ae3839dcafe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16813388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.16813388
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.1652650012
Short name T922
Test name
Test status
Simulation time 4177151314 ps
CPU time 56.32 seconds
Started Jul 27 04:52:57 PM PDT 24
Finished Jul 27 04:53:53 PM PDT 24
Peak memory 241860 kb
Host smart-348accfb-1ea3-42e3-a227-f84454cdd3a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652650012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.1652650012
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.160865282
Short name T712
Test name
Test status
Simulation time 701960805 ps
CPU time 10 seconds
Started Jul 27 04:53:07 PM PDT 24
Finished Jul 27 04:53:17 PM PDT 24
Peak memory 225364 kb
Host smart-3e85694a-09de-479b-b87f-097935f584a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160865282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.160865282
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.2227638686
Short name T492
Test name
Test status
Simulation time 42730141 ps
CPU time 0.74 seconds
Started Jul 27 04:53:09 PM PDT 24
Finished Jul 27 04:53:10 PM PDT 24
Peak memory 216512 kb
Host smart-7590520c-dd12-48dc-923f-de6dff7355d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227638686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmd
s.2227638686
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/18.spi_device_intercept.346222323
Short name T802
Test name
Test status
Simulation time 464416248 ps
CPU time 4.04 seconds
Started Jul 27 04:53:02 PM PDT 24
Finished Jul 27 04:53:06 PM PDT 24
Peak memory 233536 kb
Host smart-07e3eee3-545e-4ed2-a421-f79aa9054954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346222323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.346222323
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.343597301
Short name T285
Test name
Test status
Simulation time 1688191004 ps
CPU time 24.27 seconds
Started Jul 27 04:52:52 PM PDT 24
Finished Jul 27 04:53:16 PM PDT 24
Peak memory 225436 kb
Host smart-afecbc3e-e8cf-4e5a-b2fa-bf27e8228847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343597301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.343597301
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.2057269254
Short name T459
Test name
Test status
Simulation time 33469507 ps
CPU time 1.05 seconds
Started Jul 27 04:52:54 PM PDT 24
Finished Jul 27 04:52:55 PM PDT 24
Peak memory 217328 kb
Host smart-8d097571-993a-4380-8106-c85a8477ce8c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057269254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.spi_device_mem_parity.2057269254
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.1169266258
Short name T291
Test name
Test status
Simulation time 11724132741 ps
CPU time 12.53 seconds
Started Jul 27 04:52:54 PM PDT 24
Finished Jul 27 04:53:06 PM PDT 24
Peak memory 240952 kb
Host smart-9a326955-e52a-4fde-be97-e4e0ff374d59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169266258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.1169266258
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.2818224925
Short name T950
Test name
Test status
Simulation time 394833145 ps
CPU time 6.44 seconds
Started Jul 27 04:52:57 PM PDT 24
Finished Jul 27 04:53:03 PM PDT 24
Peak memory 233512 kb
Host smart-0feadb8b-9a69-403e-96ae-2e08bd345e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818224925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.2818224925
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.2980736790
Short name T797
Test name
Test status
Simulation time 7657910403 ps
CPU time 7.7 seconds
Started Jul 27 04:52:51 PM PDT 24
Finished Jul 27 04:52:59 PM PDT 24
Peak memory 221356 kb
Host smart-aac48fc5-9f8f-4533-8a2c-0764bc1ea7ca
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2980736790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.2980736790
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.643856668
Short name T188
Test name
Test status
Simulation time 4016885751 ps
CPU time 83.32 seconds
Started Jul 27 04:52:49 PM PDT 24
Finished Jul 27 04:54:13 PM PDT 24
Peak memory 258116 kb
Host smart-75e15d63-56cd-491a-b1a7-f2ae8f31e3a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643856668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stres
s_all.643856668
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.3126644482
Short name T1026
Test name
Test status
Simulation time 11981484784 ps
CPU time 33.82 seconds
Started Jul 27 04:52:47 PM PDT 24
Finished Jul 27 04:53:21 PM PDT 24
Peak memory 218712 kb
Host smart-aa9c7a83-e516-4a61-bf1f-240ea861e800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126644482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.3126644482
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.3510825463
Short name T615
Test name
Test status
Simulation time 2337685020 ps
CPU time 6.99 seconds
Started Jul 27 04:52:50 PM PDT 24
Finished Jul 27 04:52:58 PM PDT 24
Peak memory 217200 kb
Host smart-408c1c74-6a14-42e8-b452-97a82f669c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510825463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.3510825463
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.596586147
Short name T424
Test name
Test status
Simulation time 40268311 ps
CPU time 0.85 seconds
Started Jul 27 04:53:02 PM PDT 24
Finished Jul 27 04:53:03 PM PDT 24
Peak memory 207848 kb
Host smart-30aa7aaa-c1ac-4a5a-983f-3a72bb6f6ecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596586147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.596586147
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.2387703817
Short name T798
Test name
Test status
Simulation time 92126680 ps
CPU time 0.93 seconds
Started Jul 27 04:52:55 PM PDT 24
Finished Jul 27 04:52:56 PM PDT 24
Peak memory 207780 kb
Host smart-61b84064-f715-4c5e-bb5b-a59d269532b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387703817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.2387703817
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.85883441
Short name T427
Test name
Test status
Simulation time 70129946 ps
CPU time 2.11 seconds
Started Jul 27 04:52:57 PM PDT 24
Finished Jul 27 04:53:00 PM PDT 24
Peak memory 225352 kb
Host smart-584a7cf1-ce58-4f07-94da-3d7692185457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85883441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.85883441
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.3929404271
Short name T434
Test name
Test status
Simulation time 13669324 ps
CPU time 0.73 seconds
Started Jul 27 04:52:55 PM PDT 24
Finished Jul 27 04:52:56 PM PDT 24
Peak memory 205888 kb
Host smart-2546757b-b35f-423a-99a2-aeeb67768ce1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929404271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
3929404271
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.157322764
Short name T1016
Test name
Test status
Simulation time 91124682 ps
CPU time 2.92 seconds
Started Jul 27 04:52:57 PM PDT 24
Finished Jul 27 04:53:00 PM PDT 24
Peak memory 233552 kb
Host smart-e2e8c5c2-876e-4b9e-be60-502e2f831c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157322764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.157322764
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.391261242
Short name T70
Test name
Test status
Simulation time 29284400 ps
CPU time 0.73 seconds
Started Jul 27 04:52:49 PM PDT 24
Finished Jul 27 04:52:49 PM PDT 24
Peak memory 207220 kb
Host smart-aa6e30da-8adf-4774-aa5e-3554c81e3421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391261242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.391261242
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.1635131412
Short name T196
Test name
Test status
Simulation time 6350783189 ps
CPU time 44.06 seconds
Started Jul 27 04:52:51 PM PDT 24
Finished Jul 27 04:53:35 PM PDT 24
Peak memory 239248 kb
Host smart-a5668fc9-4a4a-4f8c-9874-bb35de875e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635131412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.1635131412
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.1142190243
Short name T612
Test name
Test status
Simulation time 99692548 ps
CPU time 0.85 seconds
Started Jul 27 04:52:51 PM PDT 24
Finished Jul 27 04:52:52 PM PDT 24
Peak memory 218736 kb
Host smart-a2507f01-50b5-4479-9fcf-527b8c4d9205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142190243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.1142190243
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.4240543730
Short name T747
Test name
Test status
Simulation time 83554398 ps
CPU time 2.54 seconds
Started Jul 27 04:52:46 PM PDT 24
Finished Jul 27 04:52:48 PM PDT 24
Peak memory 233652 kb
Host smart-97f8fb0e-5b79-4245-9544-3082db24c361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240543730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.4240543730
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.244532838
Short name T966
Test name
Test status
Simulation time 2425153148 ps
CPU time 42.06 seconds
Started Jul 27 04:53:01 PM PDT 24
Finished Jul 27 04:53:43 PM PDT 24
Peak memory 254064 kb
Host smart-b98e78dc-a3cf-421f-b99a-002897e40b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244532838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmds
.244532838
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_intercept.3572655282
Short name T420
Test name
Test status
Simulation time 2144454416 ps
CPU time 6 seconds
Started Jul 27 04:53:01 PM PDT 24
Finished Jul 27 04:53:07 PM PDT 24
Peak memory 233560 kb
Host smart-dd8dcf93-2eb9-442e-bfd4-de21d72bb986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572655282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.3572655282
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.383306048
Short name T109
Test name
Test status
Simulation time 737959688 ps
CPU time 11.15 seconds
Started Jul 27 04:52:48 PM PDT 24
Finished Jul 27 04:52:59 PM PDT 24
Peak memory 237976 kb
Host smart-1993c42e-270a-46b7-928a-cde27686ff7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383306048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.383306048
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.132798595
Short name T45
Test name
Test status
Simulation time 16796247 ps
CPU time 0.95 seconds
Started Jul 27 04:52:50 PM PDT 24
Finished Jul 27 04:52:51 PM PDT 24
Peak memory 218584 kb
Host smart-c86a44d7-36a1-45f3-afdb-4b036b31dac7
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132798595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.spi_device_mem_parity.132798595
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.3403143385
Short name T634
Test name
Test status
Simulation time 589653605 ps
CPU time 4.34 seconds
Started Jul 27 04:52:58 PM PDT 24
Finished Jul 27 04:53:03 PM PDT 24
Peak memory 233628 kb
Host smart-3a05a351-328a-4e23-9cda-46617771733c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403143385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.3403143385
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.3191107296
Short name T859
Test name
Test status
Simulation time 25496933900 ps
CPU time 20.21 seconds
Started Jul 27 04:52:52 PM PDT 24
Finished Jul 27 04:53:13 PM PDT 24
Peak memory 233648 kb
Host smart-64fc0ede-a64e-4e90-baac-e9f318156ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191107296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.3191107296
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.262228507
Short name T730
Test name
Test status
Simulation time 572970721 ps
CPU time 8.19 seconds
Started Jul 27 04:52:57 PM PDT 24
Finished Jul 27 04:53:06 PM PDT 24
Peak memory 221348 kb
Host smart-6da8b7af-2a15-45b2-bdee-9b82975bbb49
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=262228507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dire
ct.262228507
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.1601645194
Short name T638
Test name
Test status
Simulation time 138997403809 ps
CPU time 332.32 seconds
Started Jul 27 04:52:53 PM PDT 24
Finished Jul 27 04:58:25 PM PDT 24
Peak memory 265716 kb
Host smart-6004d601-a516-4096-8f34-227d1ef44001
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601645194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.1601645194
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.1193564211
Short name T796
Test name
Test status
Simulation time 24698667786 ps
CPU time 33.81 seconds
Started Jul 27 04:52:51 PM PDT 24
Finished Jul 27 04:53:26 PM PDT 24
Peak memory 217112 kb
Host smart-1924c880-f75b-4a69-86d3-20e9a3cd1017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193564211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.1193564211
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.643160296
Short name T753
Test name
Test status
Simulation time 1165639639 ps
CPU time 5.83 seconds
Started Jul 27 04:52:50 PM PDT 24
Finished Jul 27 04:52:56 PM PDT 24
Peak memory 217128 kb
Host smart-5e6fddf6-c571-450c-ae57-9d23c0929731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643160296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.643160296
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.763872861
Short name T503
Test name
Test status
Simulation time 33156489 ps
CPU time 1.07 seconds
Started Jul 27 04:52:57 PM PDT 24
Finished Jul 27 04:52:58 PM PDT 24
Peak memory 216860 kb
Host smart-976cec0f-93f8-4ca2-8c79-70cdcdac3fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763872861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.763872861
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.2244007625
Short name T505
Test name
Test status
Simulation time 26862792 ps
CPU time 0.77 seconds
Started Jul 27 04:53:01 PM PDT 24
Finished Jul 27 04:53:02 PM PDT 24
Peak memory 206676 kb
Host smart-4e2561f1-16e2-40df-b6ca-68992c06ec08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244007625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.2244007625
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.2259930343
Short name T479
Test name
Test status
Simulation time 12369568081 ps
CPU time 16.36 seconds
Started Jul 27 04:53:11 PM PDT 24
Finished Jul 27 04:53:27 PM PDT 24
Peak memory 233588 kb
Host smart-d966769e-98c7-4b8f-859f-d4b3576dd5e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259930343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.2259930343
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.1092680229
Short name T874
Test name
Test status
Simulation time 28938264 ps
CPU time 0.71 seconds
Started Jul 27 04:52:03 PM PDT 24
Finished Jul 27 04:52:04 PM PDT 24
Peak memory 205984 kb
Host smart-0a842b50-c5c1-4a90-94b0-3620a34a4fae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092680229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.1
092680229
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.3001881338
Short name T772
Test name
Test status
Simulation time 2366540741 ps
CPU time 8.76 seconds
Started Jul 27 04:52:08 PM PDT 24
Finished Jul 27 04:52:16 PM PDT 24
Peak memory 225436 kb
Host smart-273b85af-4184-4be7-a6d6-8e3edc06325e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001881338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.3001881338
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.1813652988
Short name T394
Test name
Test status
Simulation time 26007870 ps
CPU time 0.74 seconds
Started Jul 27 04:51:52 PM PDT 24
Finished Jul 27 04:51:53 PM PDT 24
Peak memory 206140 kb
Host smart-0c32d581-9e71-4fd0-8b64-1b20559d12a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813652988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.1813652988
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.154648865
Short name T578
Test name
Test status
Simulation time 12435921219 ps
CPU time 104.36 seconds
Started Jul 27 04:52:07 PM PDT 24
Finished Jul 27 04:53:52 PM PDT 24
Peak memory 250012 kb
Host smart-9a143c64-ec78-4194-a65b-1beb20f10f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154648865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.154648865
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.1036518723
Short name T980
Test name
Test status
Simulation time 5244546630 ps
CPU time 47.89 seconds
Started Jul 27 04:52:08 PM PDT 24
Finished Jul 27 04:52:56 PM PDT 24
Peak memory 250408 kb
Host smart-bf390b8d-5e5e-4e42-bae6-eb7a218256eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036518723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.1036518723
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.221545756
Short name T536
Test name
Test status
Simulation time 121813513092 ps
CPU time 145.06 seconds
Started Jul 27 04:52:07 PM PDT 24
Finished Jul 27 04:54:32 PM PDT 24
Peak memory 255928 kb
Host smart-1436dea0-05fd-4b44-bfd9-5c6228c49838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221545756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle.
221545756
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.918642685
Short name T784
Test name
Test status
Simulation time 4736437095 ps
CPU time 9.58 seconds
Started Jul 27 04:52:02 PM PDT 24
Finished Jul 27 04:52:12 PM PDT 24
Peak memory 233656 kb
Host smart-e6c3c5cc-d721-4261-8175-9de425369541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918642685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.918642685
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.4012411291
Short name T825
Test name
Test status
Simulation time 41943333516 ps
CPU time 152.3 seconds
Started Jul 27 04:52:08 PM PDT 24
Finished Jul 27 04:54:41 PM PDT 24
Peak memory 250084 kb
Host smart-d78b9278-b577-4f0b-90fa-5b08b7517bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012411291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds
.4012411291
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_intercept.1118939543
Short name T388
Test name
Test status
Simulation time 6502796306 ps
CPU time 43.71 seconds
Started Jul 27 04:51:56 PM PDT 24
Finished Jul 27 04:52:40 PM PDT 24
Peak memory 233636 kb
Host smart-e790ae42-9538-4813-ae59-c2ce1ff72682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118939543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.1118939543
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.2660508750
Short name T465
Test name
Test status
Simulation time 12892393667 ps
CPU time 99.43 seconds
Started Jul 27 04:52:01 PM PDT 24
Finished Jul 27 04:53:40 PM PDT 24
Peak memory 250048 kb
Host smart-b356ac09-01aa-4aab-842a-4974447cddbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660508750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.2660508750
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.3215266764
Short name T469
Test name
Test status
Simulation time 45453801 ps
CPU time 0.96 seconds
Started Jul 27 04:51:54 PM PDT 24
Finished Jul 27 04:51:55 PM PDT 24
Peak memory 218692 kb
Host smart-3478b37e-6b47-4273-b1e4-96d1dc25942b
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215266764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.spi_device_mem_parity.3215266764
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.2328690925
Short name T289
Test name
Test status
Simulation time 1313576726 ps
CPU time 4.44 seconds
Started Jul 27 04:52:05 PM PDT 24
Finished Jul 27 04:52:10 PM PDT 24
Peak memory 233520 kb
Host smart-89a983d0-4615-43d2-bb56-c7c1187d89a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328690925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.2328690925
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.1771562461
Short name T480
Test name
Test status
Simulation time 5991427577 ps
CPU time 8.34 seconds
Started Jul 27 04:52:02 PM PDT 24
Finished Jul 27 04:52:11 PM PDT 24
Peak memory 233712 kb
Host smart-17224727-0a7e-4100-ab16-63b9336b4ba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771562461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.1771562461
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.2533717135
Short name T50
Test name
Test status
Simulation time 1188568383 ps
CPU time 12.15 seconds
Started Jul 27 04:52:04 PM PDT 24
Finished Jul 27 04:52:16 PM PDT 24
Peak memory 222612 kb
Host smart-5d4ead1d-394c-408a-85a9-cd52a6a5e274
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2533717135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.2533717135
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.3283547542
Short name T146
Test name
Test status
Simulation time 73854298650 ps
CPU time 376.66 seconds
Started Jul 27 04:52:05 PM PDT 24
Finished Jul 27 04:58:22 PM PDT 24
Peak memory 266116 kb
Host smart-5e28d68d-831c-4094-a773-ea55030ebc44
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283547542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.3283547542
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.3524414463
Short name T428
Test name
Test status
Simulation time 20238693192 ps
CPU time 17.7 seconds
Started Jul 27 04:52:03 PM PDT 24
Finished Jul 27 04:52:20 PM PDT 24
Peak memory 217212 kb
Host smart-daae1536-384f-4585-8ab2-f6f664614faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524414463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.3524414463
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.2933801622
Short name T172
Test name
Test status
Simulation time 953818915 ps
CPU time 5.2 seconds
Started Jul 27 04:52:04 PM PDT 24
Finished Jul 27 04:52:10 PM PDT 24
Peak memory 217060 kb
Host smart-1de624b2-44fb-4b7b-8381-0815d88d039a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933801622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.2933801622
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.358945948
Short name T632
Test name
Test status
Simulation time 768361867 ps
CPU time 2.71 seconds
Started Jul 27 04:52:07 PM PDT 24
Finished Jul 27 04:52:10 PM PDT 24
Peak memory 217056 kb
Host smart-3e6fe39e-3457-4a61-8368-74a0a612fc7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358945948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.358945948
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.2066814611
Short name T652
Test name
Test status
Simulation time 230187013 ps
CPU time 0.9 seconds
Started Jul 27 04:52:09 PM PDT 24
Finished Jul 27 04:52:10 PM PDT 24
Peak memory 207232 kb
Host smart-625520ad-51d8-4ada-a6fe-3fc17f4b0207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066814611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.2066814611
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.3511949117
Short name T561
Test name
Test status
Simulation time 2715983331 ps
CPU time 10.25 seconds
Started Jul 27 04:52:07 PM PDT 24
Finished Jul 27 04:52:18 PM PDT 24
Peak memory 225324 kb
Host smart-f12c8753-a0ae-4766-8b3d-ddf98ee7df1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511949117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.3511949117
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.1954531803
Short name T577
Test name
Test status
Simulation time 61557945 ps
CPU time 0.69 seconds
Started Jul 27 04:53:00 PM PDT 24
Finished Jul 27 04:53:01 PM PDT 24
Peak memory 205928 kb
Host smart-3e1dcfdc-d975-4abc-a407-50f312fd6869
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954531803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
1954531803
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.2283338406
Short name T581
Test name
Test status
Simulation time 68428336 ps
CPU time 2.51 seconds
Started Jul 27 04:52:57 PM PDT 24
Finished Jul 27 04:53:00 PM PDT 24
Peak memory 233612 kb
Host smart-4798af2f-6471-4d57-b74d-acc59c2f21a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283338406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.2283338406
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.3322355919
Short name T813
Test name
Test status
Simulation time 17565474 ps
CPU time 0.79 seconds
Started Jul 27 04:53:02 PM PDT 24
Finished Jul 27 04:53:03 PM PDT 24
Peak memory 207132 kb
Host smart-2a3ab53f-ea33-4d60-94d8-fe1a10b5096c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322355919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.3322355919
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.2331624857
Short name T267
Test name
Test status
Simulation time 34307637073 ps
CPU time 148.73 seconds
Started Jul 27 04:53:03 PM PDT 24
Finished Jul 27 04:55:31 PM PDT 24
Peak memory 238116 kb
Host smart-f640466a-e640-443c-8963-33e67bbb35cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331624857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.2331624857
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.3624219009
Short name T309
Test name
Test status
Simulation time 11212939521 ps
CPU time 42.09 seconds
Started Jul 27 04:52:55 PM PDT 24
Finished Jul 27 04:53:37 PM PDT 24
Peak memory 233584 kb
Host smart-fc8dfd20-848d-43e7-b728-3f01e5ff23fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624219009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.3624219009
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_intercept.2158650874
Short name T682
Test name
Test status
Simulation time 944996204 ps
CPU time 3.51 seconds
Started Jul 27 04:52:58 PM PDT 24
Finished Jul 27 04:53:02 PM PDT 24
Peak memory 225396 kb
Host smart-a17cbed3-b67f-4776-983a-8f9b8c62e2e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158650874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.2158650874
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.1376065468
Short name T239
Test name
Test status
Simulation time 2795252896 ps
CPU time 18.35 seconds
Started Jul 27 04:52:55 PM PDT 24
Finished Jul 27 04:53:13 PM PDT 24
Peak memory 233600 kb
Host smart-22ca5e2f-dc2b-426f-8447-ee670c02cc04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376065468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.1376065468
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.3000061235
Short name T890
Test name
Test status
Simulation time 10141121532 ps
CPU time 15.19 seconds
Started Jul 27 04:52:48 PM PDT 24
Finished Jul 27 04:53:03 PM PDT 24
Peak memory 241728 kb
Host smart-dbb9f674-ac70-449a-81ba-5b1e92016360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000061235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.3000061235
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.2870003083
Short name T822
Test name
Test status
Simulation time 669768040 ps
CPU time 2.86 seconds
Started Jul 27 04:52:56 PM PDT 24
Finished Jul 27 04:52:59 PM PDT 24
Peak memory 225372 kb
Host smart-921aacd5-b4a5-4015-bcc0-ecb28e018202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870003083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.2870003083
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.352359069
Short name T353
Test name
Test status
Simulation time 251316157 ps
CPU time 4.27 seconds
Started Jul 27 04:52:59 PM PDT 24
Finished Jul 27 04:53:04 PM PDT 24
Peak memory 221036 kb
Host smart-367fb3d7-4c8d-4e22-8b9c-639f287af730
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=352359069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dire
ct.352359069
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.556543392
Short name T710
Test name
Test status
Simulation time 89506356981 ps
CPU time 546.98 seconds
Started Jul 27 04:52:59 PM PDT 24
Finished Jul 27 05:02:06 PM PDT 24
Peak memory 282788 kb
Host smart-42f712b0-3cb0-48f2-a2d6-ac7a36d5e53c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556543392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stres
s_all.556543392
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.1337838093
Short name T319
Test name
Test status
Simulation time 5193379904 ps
CPU time 28.36 seconds
Started Jul 27 04:52:51 PM PDT 24
Finished Jul 27 04:53:25 PM PDT 24
Peak memory 217232 kb
Host smart-b1347d96-1e4b-4789-9353-077307340b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337838093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.1337838093
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.3418009190
Short name T606
Test name
Test status
Simulation time 1485147846 ps
CPU time 7.73 seconds
Started Jul 27 04:52:56 PM PDT 24
Finished Jul 27 04:53:04 PM PDT 24
Peak memory 217024 kb
Host smart-69c5f881-a251-49b5-ad06-5f3186641b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418009190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.3418009190
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.252446315
Short name T380
Test name
Test status
Simulation time 63792301 ps
CPU time 1.5 seconds
Started Jul 27 04:52:51 PM PDT 24
Finished Jul 27 04:52:53 PM PDT 24
Peak memory 217156 kb
Host smart-b1299c51-6531-488f-9adf-bf12ce31277f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252446315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.252446315
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.3479012464
Short name T493
Test name
Test status
Simulation time 126805500 ps
CPU time 0.89 seconds
Started Jul 27 04:52:58 PM PDT 24
Finished Jul 27 04:52:59 PM PDT 24
Peak memory 206660 kb
Host smart-1dabff6a-e7d2-4d95-96cd-7949da68d627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479012464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.3479012464
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.789056225
Short name T1012
Test name
Test status
Simulation time 2187796435 ps
CPU time 3.07 seconds
Started Jul 27 04:52:55 PM PDT 24
Finished Jul 27 04:52:58 PM PDT 24
Peak memory 225344 kb
Host smart-44464523-8b5b-4c3c-8d56-6b83a418caf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789056225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.789056225
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.3667914951
Short name T398
Test name
Test status
Simulation time 48559862 ps
CPU time 0.74 seconds
Started Jul 27 04:53:00 PM PDT 24
Finished Jul 27 04:53:02 PM PDT 24
Peak memory 205944 kb
Host smart-f1b052a1-49d1-4345-98d9-55a1173b50e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667914951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
3667914951
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.2366155532
Short name T259
Test name
Test status
Simulation time 56384489 ps
CPU time 2.89 seconds
Started Jul 27 04:53:05 PM PDT 24
Finished Jul 27 04:53:08 PM PDT 24
Peak memory 233496 kb
Host smart-c1f6707b-2343-4810-b2c7-aaecabc1db38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366155532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.2366155532
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.1032790706
Short name T733
Test name
Test status
Simulation time 19201558 ps
CPU time 0.76 seconds
Started Jul 27 04:52:53 PM PDT 24
Finished Jul 27 04:52:54 PM PDT 24
Peak memory 207112 kb
Host smart-289d6d29-4f74-479c-8fc5-363b404770ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032790706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.1032790706
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.494416310
Short name T600
Test name
Test status
Simulation time 35295844299 ps
CPU time 77.32 seconds
Started Jul 27 04:52:54 PM PDT 24
Finished Jul 27 04:54:11 PM PDT 24
Peak memory 249968 kb
Host smart-db881d47-c79e-463a-8427-75d20ab9f906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494416310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.494416310
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.986241495
Short name T83
Test name
Test status
Simulation time 25968219063 ps
CPU time 256.59 seconds
Started Jul 27 04:53:03 PM PDT 24
Finished Jul 27 04:57:19 PM PDT 24
Peak memory 256788 kb
Host smart-20130183-1355-4dd9-8a87-a5fbdd9a1fcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986241495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.986241495
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.1325979296
Short name T544
Test name
Test status
Simulation time 13091232271 ps
CPU time 45.41 seconds
Started Jul 27 04:53:01 PM PDT 24
Finished Jul 27 04:53:46 PM PDT 24
Peak memory 250036 kb
Host smart-8b9f8599-d295-472e-87c1-4722fb8e969c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325979296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.1325979296
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.3145358121
Short name T773
Test name
Test status
Simulation time 921513523 ps
CPU time 7.6 seconds
Started Jul 27 04:52:58 PM PDT 24
Finished Jul 27 04:53:06 PM PDT 24
Peak memory 233616 kb
Host smart-7b119b19-67ca-4790-94f3-cfdcd622094b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145358121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.3145358121
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_intercept.1925751626
Short name T283
Test name
Test status
Simulation time 474138838 ps
CPU time 2.11 seconds
Started Jul 27 04:52:58 PM PDT 24
Finished Jul 27 04:53:01 PM PDT 24
Peak memory 225388 kb
Host smart-4e1efd41-9a21-405d-986f-546175035ed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925751626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.1925751626
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.36858449
Short name T432
Test name
Test status
Simulation time 1258187863 ps
CPU time 7.53 seconds
Started Jul 27 04:53:01 PM PDT 24
Finished Jul 27 04:53:08 PM PDT 24
Peak memory 233612 kb
Host smart-8febfbc8-3327-4874-8389-9b82490ffe01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36858449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.36858449
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.1416759149
Short name T649
Test name
Test status
Simulation time 2212061668 ps
CPU time 7.61 seconds
Started Jul 27 04:53:00 PM PDT 24
Finished Jul 27 04:53:07 PM PDT 24
Peak memory 225336 kb
Host smart-ae639ae7-cc7e-4c9c-8bbb-505ded1b2cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416759149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.1416759149
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.2675117948
Short name T839
Test name
Test status
Simulation time 31503006176 ps
CPU time 40.09 seconds
Started Jul 27 04:52:59 PM PDT 24
Finished Jul 27 04:53:39 PM PDT 24
Peak memory 233596 kb
Host smart-0c3ab2a0-b6cf-43cd-a9f8-283f176f12eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675117948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.2675117948
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.2876420874
Short name T25
Test name
Test status
Simulation time 3451673408 ps
CPU time 11.01 seconds
Started Jul 27 04:53:09 PM PDT 24
Finished Jul 27 04:53:20 PM PDT 24
Peak memory 222364 kb
Host smart-90e38bd9-a830-445c-aaaa-2df04628931a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2876420874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.2876420874
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.768932335
Short name T661
Test name
Test status
Simulation time 20720761 ps
CPU time 0.72 seconds
Started Jul 27 04:52:57 PM PDT 24
Finished Jul 27 04:52:58 PM PDT 24
Peak memory 206228 kb
Host smart-4687e8d6-d1de-42a2-b1df-49b1a351b7b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768932335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.768932335
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.3908188507
Short name T573
Test name
Test status
Simulation time 933189212 ps
CPU time 3.94 seconds
Started Jul 27 04:53:02 PM PDT 24
Finished Jul 27 04:53:06 PM PDT 24
Peak memory 217024 kb
Host smart-cbc27bf7-1278-4f07-bc61-e0dd6ff83061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908188507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.3908188507
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.2741098471
Short name T320
Test name
Test status
Simulation time 173488201 ps
CPU time 1.64 seconds
Started Jul 27 04:53:04 PM PDT 24
Finished Jul 27 04:53:06 PM PDT 24
Peak memory 208792 kb
Host smart-6d07bc90-0b31-4ce9-bc1b-263f5903db76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741098471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.2741098471
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.2926076573
Short name T362
Test name
Test status
Simulation time 77983509 ps
CPU time 0.7 seconds
Started Jul 27 04:52:56 PM PDT 24
Finished Jul 27 04:52:57 PM PDT 24
Peak memory 206684 kb
Host smart-fd7e6af7-c017-4c1c-858c-22f79f728592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926076573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.2926076573
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.2537794480
Short name T252
Test name
Test status
Simulation time 165906701 ps
CPU time 2.64 seconds
Started Jul 27 04:52:58 PM PDT 24
Finished Jul 27 04:53:01 PM PDT 24
Peak memory 233432 kb
Host smart-1a83b890-10da-438d-8860-490fc7665340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537794480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.2537794480
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.3269383625
Short name T716
Test name
Test status
Simulation time 11768809 ps
CPU time 0.76 seconds
Started Jul 27 04:52:56 PM PDT 24
Finished Jul 27 04:52:57 PM PDT 24
Peak memory 206080 kb
Host smart-957b4c36-6593-4abc-ab81-ca9180abe67e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269383625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
3269383625
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.651043305
Short name T643
Test name
Test status
Simulation time 9237583428 ps
CPU time 10.98 seconds
Started Jul 27 04:53:22 PM PDT 24
Finished Jul 27 04:53:33 PM PDT 24
Peak memory 233680 kb
Host smart-fab292a6-5520-4839-b588-5a84c3352062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651043305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.651043305
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.1439171795
Short name T926
Test name
Test status
Simulation time 48625703 ps
CPU time 0.79 seconds
Started Jul 27 04:53:01 PM PDT 24
Finished Jul 27 04:53:02 PM PDT 24
Peak memory 206640 kb
Host smart-349e7307-cfe1-4705-adae-738b78880ca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439171795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.1439171795
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.4071907881
Short name T49
Test name
Test status
Simulation time 64391054976 ps
CPU time 116.41 seconds
Started Jul 27 04:52:59 PM PDT 24
Finished Jul 27 04:54:56 PM PDT 24
Peak memory 250080 kb
Host smart-59b08322-ea0d-48bf-9b69-54fe1fd51ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071907881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.4071907881
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.2086474888
Short name T631
Test name
Test status
Simulation time 34654941073 ps
CPU time 310.76 seconds
Started Jul 27 04:52:58 PM PDT 24
Finished Jul 27 04:58:10 PM PDT 24
Peak memory 257364 kb
Host smart-730a398a-f316-4607-aa81-57b5139dca1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086474888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.2086474888
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.636405943
Short name T270
Test name
Test status
Simulation time 127729381876 ps
CPU time 368.91 seconds
Started Jul 27 04:53:21 PM PDT 24
Finished Jul 27 04:59:35 PM PDT 24
Peak memory 274384 kb
Host smart-812f353a-53da-4cb4-b955-861197398f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636405943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idle
.636405943
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.1370473957
Short name T312
Test name
Test status
Simulation time 14099237625 ps
CPU time 23.82 seconds
Started Jul 27 04:53:15 PM PDT 24
Finished Jul 27 04:53:38 PM PDT 24
Peak memory 241876 kb
Host smart-2f4b0bd7-7aaa-44e7-97d5-f91f31b10033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370473957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.1370473957
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_intercept.3986483300
Short name T915
Test name
Test status
Simulation time 328882866 ps
CPU time 5.41 seconds
Started Jul 27 04:52:59 PM PDT 24
Finished Jul 27 04:53:05 PM PDT 24
Peak memory 233560 kb
Host smart-d27979b5-90f8-4d96-9f73-7b9293c31ac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986483300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.3986483300
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.2617533169
Short name T224
Test name
Test status
Simulation time 93104478 ps
CPU time 2.11 seconds
Started Jul 27 04:53:17 PM PDT 24
Finished Jul 27 04:53:19 PM PDT 24
Peak memory 219776 kb
Host smart-8ea7f9fa-d46e-4b48-bfad-cab021f09c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617533169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.2617533169
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.1539952563
Short name T410
Test name
Test status
Simulation time 182205081 ps
CPU time 3.09 seconds
Started Jul 27 04:53:20 PM PDT 24
Finished Jul 27 04:53:23 PM PDT 24
Peak memory 233516 kb
Host smart-06f2bbab-9fcf-4cda-8fa6-a6739849e314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539952563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.1539952563
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.1304830086
Short name T769
Test name
Test status
Simulation time 166380718 ps
CPU time 3.47 seconds
Started Jul 27 04:53:13 PM PDT 24
Finished Jul 27 04:53:17 PM PDT 24
Peak memory 225396 kb
Host smart-b682e904-ce33-4dcb-84bc-44e14e4e30c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304830086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.1304830086
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.299026596
Short name T714
Test name
Test status
Simulation time 878150846 ps
CPU time 11.17 seconds
Started Jul 27 04:53:05 PM PDT 24
Finished Jul 27 04:53:16 PM PDT 24
Peak memory 222756 kb
Host smart-111cf60b-2013-479b-9e91-ac5b3575aa46
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=299026596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dire
ct.299026596
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.4226762285
Short name T506
Test name
Test status
Simulation time 139701598172 ps
CPU time 302.72 seconds
Started Jul 27 04:53:21 PM PDT 24
Finished Jul 27 04:58:23 PM PDT 24
Peak memory 257336 kb
Host smart-10add1cb-79fa-468c-b4bb-9a618180daee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226762285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.4226762285
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.1285213450
Short name T601
Test name
Test status
Simulation time 5839582051 ps
CPU time 25.34 seconds
Started Jul 27 04:53:04 PM PDT 24
Finished Jul 27 04:53:29 PM PDT 24
Peak memory 221024 kb
Host smart-4b83670c-631f-42ed-858a-2a07f6497aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285213450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.1285213450
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.2426657903
Short name T497
Test name
Test status
Simulation time 1955736109 ps
CPU time 4.67 seconds
Started Jul 27 04:52:59 PM PDT 24
Finished Jul 27 04:53:04 PM PDT 24
Peak memory 216980 kb
Host smart-2abfe5e7-6956-4b7c-a755-473b8ba4dd51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426657903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.2426657903
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.2649053306
Short name T344
Test name
Test status
Simulation time 49429437 ps
CPU time 0.75 seconds
Started Jul 27 04:53:07 PM PDT 24
Finished Jul 27 04:53:08 PM PDT 24
Peak memory 206648 kb
Host smart-e99b0933-41a2-45c3-b938-97fcb48d4f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649053306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.2649053306
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.2078120775
Short name T418
Test name
Test status
Simulation time 397469845 ps
CPU time 0.87 seconds
Started Jul 27 04:53:04 PM PDT 24
Finished Jul 27 04:53:05 PM PDT 24
Peak memory 206652 kb
Host smart-2f6730e4-d5e6-4d67-b194-5d5950acc26c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078120775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.2078120775
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.69094389
Short name T258
Test name
Test status
Simulation time 1785509870 ps
CPU time 7.55 seconds
Started Jul 27 04:53:06 PM PDT 24
Finished Jul 27 04:53:14 PM PDT 24
Peak memory 233472 kb
Host smart-68dee9d7-65b8-42c5-b573-7e55986cbc91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69094389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.69094389
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.3968378647
Short name T415
Test name
Test status
Simulation time 37597794 ps
CPU time 0.69 seconds
Started Jul 27 04:53:03 PM PDT 24
Finished Jul 27 04:53:04 PM PDT 24
Peak memory 205452 kb
Host smart-05704729-bb5c-4fee-b980-812d3ea3c648
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968378647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
3968378647
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.3288571534
Short name T250
Test name
Test status
Simulation time 1066592941 ps
CPU time 3.53 seconds
Started Jul 27 04:52:58 PM PDT 24
Finished Jul 27 04:53:02 PM PDT 24
Peak memory 225180 kb
Host smart-d1e3a768-4328-4cb6-b4c9-2b67da1cec80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288571534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.3288571534
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.659193375
Short name T485
Test name
Test status
Simulation time 26968770 ps
CPU time 0.73 seconds
Started Jul 27 04:53:06 PM PDT 24
Finished Jul 27 04:53:07 PM PDT 24
Peak memory 206044 kb
Host smart-fd33dbc6-111a-47ea-90d7-c933a8d7c682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659193375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.659193375
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.242009587
Short name T741
Test name
Test status
Simulation time 75280387919 ps
CPU time 127.85 seconds
Started Jul 27 04:53:08 PM PDT 24
Finished Jul 27 04:55:16 PM PDT 24
Peak memory 254280 kb
Host smart-ff1b13fa-5ef3-4881-bfa4-c53bd32eda74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242009587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.242009587
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.2938804929
Short name T242
Test name
Test status
Simulation time 280949199886 ps
CPU time 551.78 seconds
Started Jul 27 04:53:15 PM PDT 24
Finished Jul 27 05:02:27 PM PDT 24
Peak memory 265028 kb
Host smart-146610a0-3507-4a3e-91ba-365b8be05d17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938804929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.2938804929
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.3089587859
Short name T317
Test name
Test status
Simulation time 2723346106 ps
CPU time 17.08 seconds
Started Jul 27 04:53:16 PM PDT 24
Finished Jul 27 04:53:33 PM PDT 24
Peak memory 225360 kb
Host smart-09272003-619c-4689-985b-854e69641cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089587859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.3089587859
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.1880366150
Short name T359
Test name
Test status
Simulation time 73294470 ps
CPU time 3.09 seconds
Started Jul 27 04:53:15 PM PDT 24
Finished Jul 27 04:53:18 PM PDT 24
Peak memory 233648 kb
Host smart-c9546b0b-6dcb-4a67-a420-f271bc4b4096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880366150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.1880366150
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.2595833803
Short name T611
Test name
Test status
Simulation time 39145941476 ps
CPU time 76.02 seconds
Started Jul 27 04:53:18 PM PDT 24
Finished Jul 27 04:54:35 PM PDT 24
Peak memory 241856 kb
Host smart-7dfada8b-07d6-4a64-8c25-19432a73e61f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595833803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmd
s.2595833803
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.1443373625
Short name T452
Test name
Test status
Simulation time 17985991851 ps
CPU time 36.1 seconds
Started Jul 27 04:53:17 PM PDT 24
Finished Jul 27 04:53:53 PM PDT 24
Peak memory 219784 kb
Host smart-419ff543-c3ed-4e84-8449-6099cd05a2c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443373625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.1443373625
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.209218534
Short name T192
Test name
Test status
Simulation time 5382507371 ps
CPU time 9.61 seconds
Started Jul 27 04:53:03 PM PDT 24
Finished Jul 27 04:53:12 PM PDT 24
Peak memory 241716 kb
Host smart-98b9ab99-8a13-4432-abf9-7ff2514897c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209218534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swap
.209218534
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.858691204
Short name T972
Test name
Test status
Simulation time 12270024089 ps
CPU time 9.66 seconds
Started Jul 27 04:53:06 PM PDT 24
Finished Jul 27 04:53:16 PM PDT 24
Peak memory 225360 kb
Host smart-e147b343-9cc0-46db-97e9-b41b5286310b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858691204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.858691204
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.1154825185
Short name T1027
Test name
Test status
Simulation time 408137172 ps
CPU time 4.42 seconds
Started Jul 27 04:53:05 PM PDT 24
Finished Jul 27 04:53:09 PM PDT 24
Peak memory 222988 kb
Host smart-9410e29b-7d70-475b-a5e0-8dfe8e7e0a47
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1154825185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.1154825185
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.4173084234
Short name T325
Test name
Test status
Simulation time 8875407668 ps
CPU time 18.08 seconds
Started Jul 27 04:53:05 PM PDT 24
Finished Jul 27 04:53:23 PM PDT 24
Peak memory 217312 kb
Host smart-25f55e81-1fe9-45b9-8eb0-b0248144549d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173084234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.4173084234
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.362146899
Short name T447
Test name
Test status
Simulation time 10807475944 ps
CPU time 12.66 seconds
Started Jul 27 04:52:58 PM PDT 24
Finished Jul 27 04:53:11 PM PDT 24
Peak memory 217072 kb
Host smart-ceea9b7d-863b-4506-88f5-41af6cbf4dea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362146899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.362146899
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.26146031
Short name T801
Test name
Test status
Simulation time 30600201 ps
CPU time 1.1 seconds
Started Jul 27 04:52:56 PM PDT 24
Finished Jul 27 04:52:57 PM PDT 24
Peak memory 217044 kb
Host smart-2b5c2ff7-df99-4e69-8321-f87298f10846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26146031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.26146031
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.3219238023
Short name T363
Test name
Test status
Simulation time 122593048 ps
CPU time 0.8 seconds
Started Jul 27 04:53:08 PM PDT 24
Finished Jul 27 04:53:09 PM PDT 24
Peak memory 206728 kb
Host smart-77c6421f-c339-4b9a-b7b4-483d0c79afef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219238023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.3219238023
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.1107190712
Short name T276
Test name
Test status
Simulation time 5119934519 ps
CPU time 7.57 seconds
Started Jul 27 04:53:04 PM PDT 24
Finished Jul 27 04:53:11 PM PDT 24
Peak memory 233624 kb
Host smart-d92a41e7-cdd1-445f-8ba5-82d88def09df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107190712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.1107190712
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.191036649
Short name T761
Test name
Test status
Simulation time 37786586 ps
CPU time 0.7 seconds
Started Jul 27 04:52:59 PM PDT 24
Finished Jul 27 04:53:00 PM PDT 24
Peak memory 206036 kb
Host smart-0ee9acaa-0668-4a59-adcb-f87d75053c26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191036649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.191036649
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.3291233398
Short name T496
Test name
Test status
Simulation time 283962454 ps
CPU time 2.27 seconds
Started Jul 27 04:52:57 PM PDT 24
Finished Jul 27 04:53:00 PM PDT 24
Peak memory 224636 kb
Host smart-5b7e6174-c589-43b5-a5ff-aaa1e2d1f7e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291233398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.3291233398
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.3839800034
Short name T662
Test name
Test status
Simulation time 52712084 ps
CPU time 0.8 seconds
Started Jul 27 04:53:02 PM PDT 24
Finished Jul 27 04:53:03 PM PDT 24
Peak memory 207160 kb
Host smart-774135ee-48c3-409b-b29f-7e9769f050c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839800034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.3839800034
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.2976574853
Short name T756
Test name
Test status
Simulation time 14108889412 ps
CPU time 85.97 seconds
Started Jul 27 04:53:17 PM PDT 24
Finished Jul 27 04:54:43 PM PDT 24
Peak memory 258144 kb
Host smart-755716a8-6a09-45a8-b92e-fb5dcbb6c8e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976574853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.2976574853
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.4157398700
Short name T200
Test name
Test status
Simulation time 23836846755 ps
CPU time 171.52 seconds
Started Jul 27 04:53:07 PM PDT 24
Finished Jul 27 04:55:59 PM PDT 24
Peak memory 257660 kb
Host smart-1ed3a891-db8b-4afc-863e-84d3deadd33e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157398700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.4157398700
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.3438931770
Short name T301
Test name
Test status
Simulation time 11497003845 ps
CPU time 104.2 seconds
Started Jul 27 04:52:59 PM PDT 24
Finished Jul 27 04:54:44 PM PDT 24
Peak memory 264608 kb
Host smart-f9cf5a51-4634-4d80-83e2-525c4c0ecbac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438931770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.3438931770
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.2162005115
Short name T782
Test name
Test status
Simulation time 910807894 ps
CPU time 16.7 seconds
Started Jul 27 04:53:16 PM PDT 24
Finished Jul 27 04:53:38 PM PDT 24
Peak memory 235136 kb
Host smart-1519cb1f-21ad-4ce6-8f5b-7f6dee9facf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162005115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.2162005115
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_intercept.1429788579
Short name T232
Test name
Test status
Simulation time 39097427 ps
CPU time 2.62 seconds
Started Jul 27 04:53:10 PM PDT 24
Finished Jul 27 04:53:13 PM PDT 24
Peak memory 233540 kb
Host smart-3cc10a4f-3799-43a3-ab73-58f503a4957f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429788579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.1429788579
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.2826499649
Short name T260
Test name
Test status
Simulation time 9235124984 ps
CPU time 30.65 seconds
Started Jul 27 04:53:20 PM PDT 24
Finished Jul 27 04:53:51 PM PDT 24
Peak memory 225484 kb
Host smart-2600763a-3f82-4704-975d-d3a7c55a89b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826499649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.2826499649
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.2784978269
Short name T206
Test name
Test status
Simulation time 505790997 ps
CPU time 5.34 seconds
Started Jul 27 04:52:59 PM PDT 24
Finished Jul 27 04:53:04 PM PDT 24
Peak memory 233600 kb
Host smart-b8c1ec3e-8488-48e9-9d8b-324e60e17af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784978269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.2784978269
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.1725878104
Short name T846
Test name
Test status
Simulation time 509148003 ps
CPU time 5.5 seconds
Started Jul 27 04:53:22 PM PDT 24
Finished Jul 27 04:53:27 PM PDT 24
Peak memory 233612 kb
Host smart-8d56255d-510f-44b2-83e0-4e0c5aec8709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725878104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.1725878104
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.456108379
Short name T690
Test name
Test status
Simulation time 2009816648 ps
CPU time 9.08 seconds
Started Jul 27 04:53:17 PM PDT 24
Finished Jul 27 04:53:26 PM PDT 24
Peak memory 222744 kb
Host smart-d75876f1-c6b7-40b3-bf3f-994352d0990c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=456108379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dire
ct.456108379
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.3953355014
Short name T1003
Test name
Test status
Simulation time 1572162771 ps
CPU time 32.85 seconds
Started Jul 27 04:53:06 PM PDT 24
Finished Jul 27 04:53:38 PM PDT 24
Peak memory 238004 kb
Host smart-063008c7-b566-4bb2-92a0-57e9adc177a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953355014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.3953355014
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.3793837682
Short name T765
Test name
Test status
Simulation time 1440243419 ps
CPU time 4.22 seconds
Started Jul 27 04:52:58 PM PDT 24
Finished Jul 27 04:53:03 PM PDT 24
Peak memory 217128 kb
Host smart-6c949ab0-076f-4f2f-b133-7a5b935eb327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793837682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.3793837682
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.1042912635
Short name T867
Test name
Test status
Simulation time 1426954941 ps
CPU time 7.14 seconds
Started Jul 27 04:53:20 PM PDT 24
Finished Jul 27 04:53:27 PM PDT 24
Peak memory 217048 kb
Host smart-03bc46f5-a169-41d9-92d2-0fad05ce8a3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042912635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.1042912635
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.540505764
Short name T527
Test name
Test status
Simulation time 269745375 ps
CPU time 5.64 seconds
Started Jul 27 04:53:04 PM PDT 24
Finished Jul 27 04:53:09 PM PDT 24
Peak memory 217092 kb
Host smart-0590ad36-a888-46dc-90cc-eb8775e5d8c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540505764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.540505764
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.432740223
Short name T387
Test name
Test status
Simulation time 354997693 ps
CPU time 1 seconds
Started Jul 27 04:53:12 PM PDT 24
Finished Jul 27 04:53:13 PM PDT 24
Peak memory 207128 kb
Host smart-457b3885-2daf-4d93-b73e-b3d2255c3bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432740223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.432740223
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.4259645811
Short name T226
Test name
Test status
Simulation time 75783306 ps
CPU time 2.58 seconds
Started Jul 27 04:52:58 PM PDT 24
Finished Jul 27 04:53:01 PM PDT 24
Peak memory 233488 kb
Host smart-7f2dd334-9480-4fbc-a238-ec13b19e37da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259645811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.4259645811
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.3336626869
Short name T514
Test name
Test status
Simulation time 15431762 ps
CPU time 0.71 seconds
Started Jul 27 04:53:24 PM PDT 24
Finished Jul 27 04:53:25 PM PDT 24
Peak memory 206252 kb
Host smart-a97eebfd-a591-468e-b29b-552078eab66a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336626869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
3336626869
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.2176555284
Short name T274
Test name
Test status
Simulation time 116112963 ps
CPU time 2.13 seconds
Started Jul 27 04:53:23 PM PDT 24
Finished Jul 27 04:53:25 PM PDT 24
Peak memory 225428 kb
Host smart-8d1c302b-edb4-4400-9bea-8cd910f9a688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176555284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.2176555284
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.3412452013
Short name T494
Test name
Test status
Simulation time 65583183 ps
CPU time 0.75 seconds
Started Jul 27 04:53:19 PM PDT 24
Finished Jul 27 04:53:20 PM PDT 24
Peak memory 206436 kb
Host smart-8dca1234-7f21-4f1a-808d-9cb208ae9a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412452013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.3412452013
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.632928471
Short name T1015
Test name
Test status
Simulation time 18059331393 ps
CPU time 79.83 seconds
Started Jul 27 04:53:10 PM PDT 24
Finished Jul 27 04:54:30 PM PDT 24
Peak memory 257820 kb
Host smart-1ab4f6c7-f20f-4749-8bee-4c069acf35d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632928471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.632928471
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.2654488887
Short name T689
Test name
Test status
Simulation time 46127146259 ps
CPU time 134.94 seconds
Started Jul 27 04:52:58 PM PDT 24
Finished Jul 27 04:55:13 PM PDT 24
Peak memory 254100 kb
Host smart-9da03cd2-7bd6-4917-bebf-7cee5600c6c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654488887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.2654488887
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.3623092573
Short name T315
Test name
Test status
Simulation time 51206275922 ps
CPU time 453.12 seconds
Started Jul 27 04:53:07 PM PDT 24
Finished Jul 27 05:00:40 PM PDT 24
Peak memory 253928 kb
Host smart-66416a90-5cc4-4f39-89fe-de4c58591da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623092573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.3623092573
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.4042667310
Short name T888
Test name
Test status
Simulation time 967227883 ps
CPU time 5.41 seconds
Started Jul 27 04:53:16 PM PDT 24
Finished Jul 27 04:53:21 PM PDT 24
Peak memory 235284 kb
Host smart-8e30abfb-3aef-4ba6-8f0f-4a86b0012496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042667310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.4042667310
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.3813774469
Short name T97
Test name
Test status
Simulation time 58231825765 ps
CPU time 211.73 seconds
Started Jul 27 04:53:07 PM PDT 24
Finished Jul 27 04:56:38 PM PDT 24
Peak memory 257476 kb
Host smart-e4ecc039-6b19-4d20-8578-96f9564bb618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813774469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmd
s.3813774469
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_intercept.3017551598
Short name T99
Test name
Test status
Simulation time 1551335457 ps
CPU time 8.54 seconds
Started Jul 27 04:53:07 PM PDT 24
Finished Jul 27 04:53:16 PM PDT 24
Peak memory 225388 kb
Host smart-cf3774cb-9e68-435f-9664-482fc401a3dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017551598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.3017551598
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.454422443
Short name T973
Test name
Test status
Simulation time 20095030288 ps
CPU time 58.14 seconds
Started Jul 27 04:53:00 PM PDT 24
Finished Jul 27 04:53:58 PM PDT 24
Peak memory 233560 kb
Host smart-796072fd-ebcd-4afc-8d98-b1a36047ef72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454422443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.454422443
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.4024048061
Short name T64
Test name
Test status
Simulation time 481759570 ps
CPU time 6.83 seconds
Started Jul 27 04:53:16 PM PDT 24
Finished Jul 27 04:53:23 PM PDT 24
Peak memory 233584 kb
Host smart-2948dade-12dd-4f5d-b6e0-e67b8bf4e64b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024048061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.4024048061
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.2046546325
Short name T791
Test name
Test status
Simulation time 893484592 ps
CPU time 12.15 seconds
Started Jul 27 04:53:14 PM PDT 24
Finished Jul 27 04:53:26 PM PDT 24
Peak memory 233576 kb
Host smart-9d0c3314-ee26-4d69-b399-e0297ecac922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046546325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.2046546325
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.3522875093
Short name T666
Test name
Test status
Simulation time 2382148883 ps
CPU time 25.77 seconds
Started Jul 27 04:53:14 PM PDT 24
Finished Jul 27 04:53:40 PM PDT 24
Peak memory 222568 kb
Host smart-eee12b79-cbf0-4757-ae87-a402ac023c75
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3522875093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.3522875093
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.3969424749
Short name T805
Test name
Test status
Simulation time 115204570603 ps
CPU time 250.53 seconds
Started Jul 27 04:53:04 PM PDT 24
Finished Jul 27 04:57:14 PM PDT 24
Peak memory 253344 kb
Host smart-c385f8a9-e0f2-43ef-b72d-c1a65a7eb424
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969424749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.3969424749
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.301624236
Short name T886
Test name
Test status
Simulation time 11709144 ps
CPU time 0.72 seconds
Started Jul 27 04:52:57 PM PDT 24
Finished Jul 27 04:52:58 PM PDT 24
Peak memory 206368 kb
Host smart-312eb0bf-1c57-4c75-b01d-df04cff4aa9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301624236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.301624236
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.1382578236
Short name T960
Test name
Test status
Simulation time 478903273 ps
CPU time 1.43 seconds
Started Jul 27 04:53:03 PM PDT 24
Finished Jul 27 04:53:05 PM PDT 24
Peak memory 208508 kb
Host smart-283b3c02-8d50-43a0-99c5-02a0f7bc5b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382578236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.1382578236
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.2439828240
Short name T914
Test name
Test status
Simulation time 14687108 ps
CPU time 0.72 seconds
Started Jul 27 04:52:58 PM PDT 24
Finished Jul 27 04:53:00 PM PDT 24
Peak memory 206512 kb
Host smart-00ce8cec-4dc8-4810-b433-24d1d43af32d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439828240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.2439828240
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.3337325927
Short name T849
Test name
Test status
Simulation time 781755127 ps
CPU time 1.03 seconds
Started Jul 27 04:53:01 PM PDT 24
Finished Jul 27 04:53:02 PM PDT 24
Peak memory 206344 kb
Host smart-488b673d-e701-462b-805e-3c02a858359b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337325927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.3337325927
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.2073351801
Short name T2
Test name
Test status
Simulation time 746380128 ps
CPU time 2.42 seconds
Started Jul 27 04:53:06 PM PDT 24
Finished Jul 27 04:53:09 PM PDT 24
Peak memory 225408 kb
Host smart-4ab64af5-b86f-4b36-bc8c-b9945bda61a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073351801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.2073351801
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.3444953154
Short name T746
Test name
Test status
Simulation time 20169563 ps
CPU time 0.69 seconds
Started Jul 27 04:53:07 PM PDT 24
Finished Jul 27 04:53:07 PM PDT 24
Peak memory 205956 kb
Host smart-b581d768-cfa2-43ff-b48c-6faf1fabcb67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444953154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
3444953154
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.1526359441
Short name T281
Test name
Test status
Simulation time 725475078 ps
CPU time 2.87 seconds
Started Jul 27 04:53:11 PM PDT 24
Finished Jul 27 04:53:14 PM PDT 24
Peak memory 225496 kb
Host smart-ecdbbfd1-6f39-43c6-b4d1-e5b20d2aff96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526359441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.1526359441
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.1931419542
Short name T680
Test name
Test status
Simulation time 46196963 ps
CPU time 0.76 seconds
Started Jul 27 04:53:29 PM PDT 24
Finished Jul 27 04:53:29 PM PDT 24
Peak memory 206084 kb
Host smart-a08450b7-b4c4-4b69-b9f8-44523d297dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931419542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.1931419542
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.1309416100
Short name T557
Test name
Test status
Simulation time 19493379372 ps
CPU time 73.6 seconds
Started Jul 27 04:53:16 PM PDT 24
Finished Jul 27 04:54:30 PM PDT 24
Peak memory 225516 kb
Host smart-6a0acdc4-c73b-4337-ba17-f72713c5a454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309416100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.1309416100
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.3086868973
Short name T44
Test name
Test status
Simulation time 20789225467 ps
CPU time 186.56 seconds
Started Jul 27 04:53:23 PM PDT 24
Finished Jul 27 04:56:29 PM PDT 24
Peak memory 250064 kb
Host smart-4b51499a-a45f-4fc7-984c-50bbaa70f229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086868973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.3086868973
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.467201330
Short name T448
Test name
Test status
Simulation time 15821447214 ps
CPU time 157.18 seconds
Started Jul 27 04:53:26 PM PDT 24
Finished Jul 27 04:56:03 PM PDT 24
Peak memory 250036 kb
Host smart-8f87dd9a-c2f0-4e70-8d2f-f297caa63a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467201330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idle
.467201330
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.2985795091
Short name T533
Test name
Test status
Simulation time 71735085 ps
CPU time 3.72 seconds
Started Jul 27 04:53:28 PM PDT 24
Finished Jul 27 04:53:31 PM PDT 24
Peak memory 233544 kb
Host smart-e2c4c30c-bf69-4302-8436-849ae790cc4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985795091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.2985795091
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.2405621985
Short name T617
Test name
Test status
Simulation time 15104171764 ps
CPU time 44.82 seconds
Started Jul 27 04:53:14 PM PDT 24
Finished Jul 27 04:53:59 PM PDT 24
Peak memory 250468 kb
Host smart-24a5cc6d-c790-4cbc-99cd-ec686a0c7f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405621985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmd
s.2405621985
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_intercept.358323072
Short name T1018
Test name
Test status
Simulation time 2607165398 ps
CPU time 6.36 seconds
Started Jul 27 04:53:23 PM PDT 24
Finished Jul 27 04:53:29 PM PDT 24
Peak memory 233584 kb
Host smart-5d20cb27-8b00-44e8-b6ae-0b3136094558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358323072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.358323072
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.3835850552
Short name T594
Test name
Test status
Simulation time 5790854640 ps
CPU time 41.42 seconds
Started Jul 27 04:53:20 PM PDT 24
Finished Jul 27 04:54:02 PM PDT 24
Peak memory 249940 kb
Host smart-96992c49-fd25-41f7-abe9-815b6eb5648e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835850552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.3835850552
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.4005295395
Short name T521
Test name
Test status
Simulation time 2945867450 ps
CPU time 12.36 seconds
Started Jul 27 04:53:14 PM PDT 24
Finished Jul 27 04:53:27 PM PDT 24
Peak memory 233560 kb
Host smart-8a1979a9-b531-478b-b113-b83b58d730c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005295395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.4005295395
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.188190450
Short name T783
Test name
Test status
Simulation time 25034817382 ps
CPU time 37.36 seconds
Started Jul 27 04:53:11 PM PDT 24
Finished Jul 27 04:53:48 PM PDT 24
Peak memory 253732 kb
Host smart-df4238fc-03bf-4af7-ae65-23cf1ae9d3a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188190450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.188190450
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.4099674585
Short name T508
Test name
Test status
Simulation time 136195212 ps
CPU time 4.53 seconds
Started Jul 27 04:53:14 PM PDT 24
Finished Jul 27 04:53:19 PM PDT 24
Peak memory 219864 kb
Host smart-641c438f-374e-4e62-842d-aabf7ebb6ea2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4099674585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.4099674585
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.1781698339
Short name T490
Test name
Test status
Simulation time 142007315937 ps
CPU time 269.11 seconds
Started Jul 27 04:53:11 PM PDT 24
Finished Jul 27 04:57:40 PM PDT 24
Peak memory 261580 kb
Host smart-da7bc49d-486d-4b86-8889-12067fc72c1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781698339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.1781698339
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.2413165713
Short name T378
Test name
Test status
Simulation time 11738992972 ps
CPU time 21.57 seconds
Started Jul 27 04:53:23 PM PDT 24
Finished Jul 27 04:53:50 PM PDT 24
Peak memory 217264 kb
Host smart-7f209250-d4c7-4e17-a7d1-60718ea1957c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413165713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.2413165713
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.1779271396
Short name T929
Test name
Test status
Simulation time 40516716 ps
CPU time 0.74 seconds
Started Jul 27 04:53:22 PM PDT 24
Finished Jul 27 04:53:23 PM PDT 24
Peak memory 206300 kb
Host smart-1aeed745-b77a-4b57-a927-c53b9478367e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779271396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.1779271396
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.495268473
Short name T446
Test name
Test status
Simulation time 375711991 ps
CPU time 3.96 seconds
Started Jul 27 04:53:13 PM PDT 24
Finished Jul 27 04:53:17 PM PDT 24
Peak memory 217028 kb
Host smart-23c20191-a5e9-4145-8ffb-57b2d0a8c6b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495268473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.495268473
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.2560877576
Short name T382
Test name
Test status
Simulation time 39587658 ps
CPU time 0.74 seconds
Started Jul 27 04:53:19 PM PDT 24
Finished Jul 27 04:53:20 PM PDT 24
Peak memory 206676 kb
Host smart-c94a8b74-1473-403b-851c-7e1077c06959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560877576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.2560877576
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.3171576883
Short name T695
Test name
Test status
Simulation time 57854422 ps
CPU time 2.1 seconds
Started Jul 27 04:53:24 PM PDT 24
Finished Jul 27 04:53:26 PM PDT 24
Peak memory 224984 kb
Host smart-4d19e3bf-c2f3-4150-9c62-4ddb473531de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171576883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.3171576883
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.3759460018
Short name T862
Test name
Test status
Simulation time 50474338 ps
CPU time 0.7 seconds
Started Jul 27 04:53:14 PM PDT 24
Finished Jul 27 04:53:15 PM PDT 24
Peak memory 205944 kb
Host smart-631379e4-b499-4c88-8d4b-313a6e5087db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759460018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
3759460018
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.1081016177
Short name T595
Test name
Test status
Simulation time 134637813 ps
CPU time 2.26 seconds
Started Jul 27 04:53:22 PM PDT 24
Finished Jul 27 04:53:24 PM PDT 24
Peak memory 225204 kb
Host smart-3e7fa6cd-dc34-40e0-8ee9-66620accb2e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081016177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.1081016177
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.1118744196
Short name T476
Test name
Test status
Simulation time 58293175 ps
CPU time 0.76 seconds
Started Jul 27 04:53:23 PM PDT 24
Finished Jul 27 04:53:24 PM PDT 24
Peak memory 207208 kb
Host smart-a88db980-b0b4-4427-b281-1ea1278dad21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118744196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.1118744196
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.2647575809
Short name T667
Test name
Test status
Simulation time 5317410502 ps
CPU time 56.72 seconds
Started Jul 27 04:53:26 PM PDT 24
Finished Jul 27 04:54:23 PM PDT 24
Peak memory 252096 kb
Host smart-a3ba2e12-fd27-4ed7-8268-dff05f8d4408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647575809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.2647575809
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.506002596
Short name T203
Test name
Test status
Simulation time 77714427533 ps
CPU time 116.85 seconds
Started Jul 27 04:53:08 PM PDT 24
Finished Jul 27 04:55:05 PM PDT 24
Peak memory 253756 kb
Host smart-898922e0-7018-46ac-b000-b2ad563b16a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506002596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.506002596
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.1395683941
Short name T636
Test name
Test status
Simulation time 30437068894 ps
CPU time 229.55 seconds
Started Jul 27 04:53:20 PM PDT 24
Finished Jul 27 04:57:09 PM PDT 24
Peak memory 250328 kb
Host smart-2b0bbdf0-b48d-4ad4-8df1-13bb0c856683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395683941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.1395683941
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.1782358976
Short name T155
Test name
Test status
Simulation time 4143131499 ps
CPU time 16.98 seconds
Started Jul 27 04:53:17 PM PDT 24
Finished Jul 27 04:53:34 PM PDT 24
Peak memory 235144 kb
Host smart-56602ad7-5e3c-409a-b7b5-470e01d40b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782358976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.1782358976
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.3520383626
Short name T26
Test name
Test status
Simulation time 3901794403 ps
CPU time 43.61 seconds
Started Jul 27 04:53:17 PM PDT 24
Finished Jul 27 04:54:01 PM PDT 24
Peak memory 251872 kb
Host smart-70e54fa3-2d75-418c-b87d-6477761a1517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520383626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmd
s.3520383626
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_intercept.4165716668
Short name T12
Test name
Test status
Simulation time 5747369993 ps
CPU time 26.11 seconds
Started Jul 27 04:53:27 PM PDT 24
Finished Jul 27 04:53:53 PM PDT 24
Peak memory 225456 kb
Host smart-191b0ebe-2ff6-48de-9e3c-85bfbed78f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165716668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.4165716668
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.2520292719
Short name T762
Test name
Test status
Simulation time 3852555640 ps
CPU time 34.11 seconds
Started Jul 27 04:53:10 PM PDT 24
Finished Jul 27 04:53:44 PM PDT 24
Peak memory 241420 kb
Host smart-a8aa692f-6961-43a7-871e-90e2681782be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520292719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.2520292719
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.3275122818
Short name T110
Test name
Test status
Simulation time 299958894 ps
CPU time 2.97 seconds
Started Jul 27 04:53:26 PM PDT 24
Finished Jul 27 04:53:29 PM PDT 24
Peak memory 233556 kb
Host smart-97d661af-bdcc-4f3f-adf4-bbedf8357fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275122818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.3275122818
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.1166017506
Short name T218
Test name
Test status
Simulation time 321670959 ps
CPU time 4.22 seconds
Started Jul 27 04:53:24 PM PDT 24
Finished Jul 27 04:53:28 PM PDT 24
Peak memory 233504 kb
Host smart-cca6204e-3618-451b-af94-7e1ec13f9be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166017506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.1166017506
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.1633936200
Short name T942
Test name
Test status
Simulation time 469463140 ps
CPU time 5.28 seconds
Started Jul 27 04:53:19 PM PDT 24
Finished Jul 27 04:53:24 PM PDT 24
Peak memory 222552 kb
Host smart-ba585fe8-f5c8-496c-9075-805cfce37f40
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1633936200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.1633936200
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.3871188045
Short name T167
Test name
Test status
Simulation time 35134997983 ps
CPU time 367.76 seconds
Started Jul 27 04:53:24 PM PDT 24
Finished Jul 27 04:59:37 PM PDT 24
Peak memory 271116 kb
Host smart-2231a5d2-c6f5-419a-9160-848936161714
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871188045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.3871188045
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.2495165857
Short name T894
Test name
Test status
Simulation time 4667969119 ps
CPU time 11.57 seconds
Started Jul 27 04:53:20 PM PDT 24
Finished Jul 27 04:53:31 PM PDT 24
Peak memory 220584 kb
Host smart-480214e4-81de-4904-8ed4-4c98dc977b5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495165857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.2495165857
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.1823307407
Short name T858
Test name
Test status
Simulation time 1431190801 ps
CPU time 4.04 seconds
Started Jul 27 04:53:15 PM PDT 24
Finished Jul 27 04:53:19 PM PDT 24
Peak memory 217112 kb
Host smart-8b66882b-d8bd-4a5c-9d4a-0b017a519553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823307407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.1823307407
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.54982973
Short name T693
Test name
Test status
Simulation time 202455636 ps
CPU time 2.13 seconds
Started Jul 27 04:53:28 PM PDT 24
Finished Jul 27 04:53:30 PM PDT 24
Peak memory 216984 kb
Host smart-82a7b469-aa87-4e62-8ebf-edac85ec2ef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54982973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.54982973
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.2977349315
Short name T717
Test name
Test status
Simulation time 19283033 ps
CPU time 0.74 seconds
Started Jul 27 04:53:26 PM PDT 24
Finished Jul 27 04:53:27 PM PDT 24
Peak memory 206684 kb
Host smart-a70eaeeb-7ef8-4850-9167-3a674f1e5dfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977349315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.2977349315
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.3565962648
Short name T526
Test name
Test status
Simulation time 288462428 ps
CPU time 5.86 seconds
Started Jul 27 04:53:21 PM PDT 24
Finished Jul 27 04:53:27 PM PDT 24
Peak memory 225372 kb
Host smart-215eddb0-747d-4f27-8ff3-f49a038336a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565962648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.3565962648
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.3350176041
Short name T727
Test name
Test status
Simulation time 16827721 ps
CPU time 0.76 seconds
Started Jul 27 04:53:14 PM PDT 24
Finished Jul 27 04:53:15 PM PDT 24
Peak memory 205416 kb
Host smart-638f9698-8600-463a-a02d-7e817cbdd376
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350176041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
3350176041
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.675897335
Short name T41
Test name
Test status
Simulation time 115470441 ps
CPU time 2.22 seconds
Started Jul 27 04:53:14 PM PDT 24
Finished Jul 27 04:53:17 PM PDT 24
Peak memory 233100 kb
Host smart-49a9bd5e-466b-4a98-b6dd-e9b7d56a6a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675897335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.675897335
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.1348394241
Short name T330
Test name
Test status
Simulation time 17585821 ps
CPU time 0.8 seconds
Started Jul 27 04:53:18 PM PDT 24
Finished Jul 27 04:53:19 PM PDT 24
Peak memory 207544 kb
Host smart-a3f1f9c7-cc3f-45af-891b-ee39919a97bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348394241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.1348394241
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.3606539800
Short name T194
Test name
Test status
Simulation time 12107271782 ps
CPU time 85.32 seconds
Started Jul 27 04:53:25 PM PDT 24
Finished Jul 27 04:54:51 PM PDT 24
Peak memory 258412 kb
Host smart-2ec9bb1e-09e3-4492-b450-7af668549810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606539800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.3606539800
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.2359866238
Short name T1030
Test name
Test status
Simulation time 42871418875 ps
CPU time 69.77 seconds
Started Jul 27 04:53:24 PM PDT 24
Finished Jul 27 04:54:34 PM PDT 24
Peak memory 256088 kb
Host smart-069e0c82-de67-4dd2-91ec-88e4a6528ed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359866238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.2359866238
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.2272696677
Short name T305
Test name
Test status
Simulation time 6609720361 ps
CPU time 39.07 seconds
Started Jul 27 04:53:25 PM PDT 24
Finished Jul 27 04:54:04 PM PDT 24
Peak memory 225424 kb
Host smart-d5367831-0410-45bd-a862-5240c4a003e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272696677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.2272696677
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.2088095616
Short name T545
Test name
Test status
Simulation time 391508383393 ps
CPU time 129.94 seconds
Started Jul 27 04:53:31 PM PDT 24
Finished Jul 27 04:55:41 PM PDT 24
Peak memory 250008 kb
Host smart-3eaaa426-96b9-41ea-9686-acdc3cfe8a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088095616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmd
s.2088095616
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_intercept.4077919096
Short name T223
Test name
Test status
Simulation time 1414878942 ps
CPU time 3.65 seconds
Started Jul 27 04:53:26 PM PDT 24
Finished Jul 27 04:53:29 PM PDT 24
Peak memory 228696 kb
Host smart-4e0d776a-f3b9-42d6-8c91-9e6053a128f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077919096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.4077919096
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.2032972573
Short name T748
Test name
Test status
Simulation time 2693683984 ps
CPU time 31.23 seconds
Started Jul 27 04:53:24 PM PDT 24
Finished Jul 27 04:53:55 PM PDT 24
Peak memory 241776 kb
Host smart-aa95d5d6-84f7-493b-9742-a51d8e1a54b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032972573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.2032972573
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.2508707957
Short name T542
Test name
Test status
Simulation time 411197911 ps
CPU time 6.55 seconds
Started Jul 27 04:53:24 PM PDT 24
Finished Jul 27 04:53:31 PM PDT 24
Peak memory 225300 kb
Host smart-b4e065e8-8646-4b6c-a83b-f4368aca797d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508707957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.2508707957
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.1806974592
Short name T240
Test name
Test status
Simulation time 3577750446 ps
CPU time 11.3 seconds
Started Jul 27 04:53:12 PM PDT 24
Finished Jul 27 04:53:23 PM PDT 24
Peak memory 233660 kb
Host smart-1504cd4f-31b0-48ee-b3b9-ba6f1abea08c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806974592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.1806974592
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.2717410392
Short name T985
Test name
Test status
Simulation time 923354850 ps
CPU time 4.3 seconds
Started Jul 27 04:53:14 PM PDT 24
Finished Jul 27 04:53:19 PM PDT 24
Peak memory 223736 kb
Host smart-3122974c-5dba-4f90-b4c1-84adcaed2489
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2717410392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.2717410392
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.2532672264
Short name T22
Test name
Test status
Simulation time 43736172829 ps
CPU time 134.13 seconds
Started Jul 27 04:53:12 PM PDT 24
Finished Jul 27 04:55:27 PM PDT 24
Peak memory 258256 kb
Host smart-54f67fe6-2d79-4e42-822f-b93cf06ccfa6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532672264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.2532672264
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.4012164425
Short name T323
Test name
Test status
Simulation time 545449500 ps
CPU time 5.75 seconds
Started Jul 27 04:53:24 PM PDT 24
Finished Jul 27 04:53:30 PM PDT 24
Peak memory 217300 kb
Host smart-09c0119e-69e7-4450-84d7-5f4a21892f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012164425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.4012164425
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.3997918574
Short name T916
Test name
Test status
Simulation time 295520273 ps
CPU time 2.58 seconds
Started Jul 27 04:53:28 PM PDT 24
Finished Jul 27 04:53:31 PM PDT 24
Peak memory 217024 kb
Host smart-5e55456c-6221-4646-9253-dc9b52698a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997918574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.3997918574
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.1827168097
Short name T790
Test name
Test status
Simulation time 129932907 ps
CPU time 1.68 seconds
Started Jul 27 04:53:23 PM PDT 24
Finished Jul 27 04:53:25 PM PDT 24
Peak memory 217028 kb
Host smart-2bb72502-04e2-4ee8-aba6-b9e39e5e87f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827168097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.1827168097
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.43060262
Short name T413
Test name
Test status
Simulation time 227731586 ps
CPU time 0.89 seconds
Started Jul 27 04:53:21 PM PDT 24
Finished Jul 27 04:53:22 PM PDT 24
Peak memory 207708 kb
Host smart-c47523b9-f40f-4997-8530-e5ed21241636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43060262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.43060262
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.1558065115
Short name T853
Test name
Test status
Simulation time 169452136 ps
CPU time 2.77 seconds
Started Jul 27 04:53:20 PM PDT 24
Finished Jul 27 04:53:23 PM PDT 24
Peak memory 233476 kb
Host smart-d9a12f76-8e1d-420f-87f7-13bab5a7f9c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558065115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.1558065115
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.1917356906
Short name T405
Test name
Test status
Simulation time 13065833 ps
CPU time 0.73 seconds
Started Jul 27 04:53:24 PM PDT 24
Finished Jul 27 04:53:25 PM PDT 24
Peak memory 206060 kb
Host smart-3628340c-be07-4920-83c6-ce460b610779
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917356906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
1917356906
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.2603259034
Short name T93
Test name
Test status
Simulation time 79500624 ps
CPU time 2.27 seconds
Started Jul 27 04:53:23 PM PDT 24
Finished Jul 27 04:53:25 PM PDT 24
Peak memory 225468 kb
Host smart-1a38943e-6299-429f-9938-07e067f4ef6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603259034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.2603259034
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.2257259049
Short name T935
Test name
Test status
Simulation time 38402255 ps
CPU time 0.76 seconds
Started Jul 27 04:53:15 PM PDT 24
Finished Jul 27 04:53:16 PM PDT 24
Peak memory 207520 kb
Host smart-11825ab7-2467-40ca-8438-d2ac30d33041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257259049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.2257259049
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.1876192349
Short name T253
Test name
Test status
Simulation time 13862803265 ps
CPU time 134.33 seconds
Started Jul 27 04:53:34 PM PDT 24
Finished Jul 27 04:55:49 PM PDT 24
Peak memory 252200 kb
Host smart-6a4e35f9-fd4e-4aba-a8c5-1b1fedd64979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876192349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.1876192349
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.2251559874
Short name T61
Test name
Test status
Simulation time 12916678333 ps
CPU time 79.76 seconds
Started Jul 27 04:53:17 PM PDT 24
Finished Jul 27 04:54:37 PM PDT 24
Peak memory 241824 kb
Host smart-de31f681-6a84-4b26-a9d6-58c0e3058f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251559874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.2251559874
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.3848738042
Short name T403
Test name
Test status
Simulation time 17069722063 ps
CPU time 61.86 seconds
Started Jul 27 04:53:24 PM PDT 24
Finished Jul 27 04:54:26 PM PDT 24
Peak memory 249088 kb
Host smart-5e441cf8-0297-42a7-acb0-905c8f5cc3b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848738042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.3848738042
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.3260772441
Short name T311
Test name
Test status
Simulation time 850034214 ps
CPU time 13.77 seconds
Started Jul 27 04:53:41 PM PDT 24
Finished Jul 27 04:53:55 PM PDT 24
Peak memory 233560 kb
Host smart-0cfecdd4-c968-43d0-8c4c-5d84ab2e289b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260772441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.3260772441
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.3427192651
Short name T579
Test name
Test status
Simulation time 876387340 ps
CPU time 8.63 seconds
Started Jul 27 04:53:31 PM PDT 24
Finished Jul 27 04:53:40 PM PDT 24
Peak memory 233572 kb
Host smart-31845242-733e-4b06-8431-08b344daef75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427192651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmd
s.3427192651
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_intercept.2084630385
Short name T24
Test name
Test status
Simulation time 12875878399 ps
CPU time 26.91 seconds
Started Jul 27 04:53:30 PM PDT 24
Finished Jul 27 04:53:57 PM PDT 24
Peak memory 225452 kb
Host smart-e1abaa8d-cc02-4ef5-8cc8-f58c8d04b5f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084630385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.2084630385
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.2449703393
Short name T443
Test name
Test status
Simulation time 20382952089 ps
CPU time 78.65 seconds
Started Jul 27 04:53:24 PM PDT 24
Finished Jul 27 04:54:43 PM PDT 24
Peak memory 252200 kb
Host smart-bb192996-e3f3-429f-b4c2-62883f42918d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449703393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.2449703393
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.753661408
Short name T199
Test name
Test status
Simulation time 5698377572 ps
CPU time 19.18 seconds
Started Jul 27 04:53:19 PM PDT 24
Finished Jul 27 04:53:38 PM PDT 24
Peak memory 225348 kb
Host smart-de60e074-964e-40f8-a21d-ebdbe05490eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753661408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swap
.753661408
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.3019041091
Short name T534
Test name
Test status
Simulation time 2085497044 ps
CPU time 7.71 seconds
Started Jul 27 04:53:08 PM PDT 24
Finished Jul 27 04:53:16 PM PDT 24
Peak memory 225328 kb
Host smart-2b844e93-1d94-4a7c-a683-e5ce78091dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019041091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.3019041091
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.904586848
Short name T151
Test name
Test status
Simulation time 1942958640 ps
CPU time 22.5 seconds
Started Jul 27 04:53:22 PM PDT 24
Finished Jul 27 04:53:45 PM PDT 24
Peak memory 223052 kb
Host smart-c0c605c3-4719-447b-90c0-e9c760602034
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=904586848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dire
ct.904586848
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.354366613
Short name T901
Test name
Test status
Simulation time 178502182427 ps
CPU time 96.55 seconds
Started Jul 27 04:53:25 PM PDT 24
Finished Jul 27 04:55:01 PM PDT 24
Peak memory 250164 kb
Host smart-fc68abf8-cd1c-483a-b305-0a30b47be91a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354366613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stres
s_all.354366613
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.3262880214
Short name T400
Test name
Test status
Simulation time 4915641316 ps
CPU time 12.41 seconds
Started Jul 27 04:53:14 PM PDT 24
Finished Jul 27 04:53:27 PM PDT 24
Peak memory 217172 kb
Host smart-f9e4a666-99ae-4985-801b-7a109cf1b914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262880214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.3262880214
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.3392168103
Short name T921
Test name
Test status
Simulation time 1393924429 ps
CPU time 4.37 seconds
Started Jul 27 04:53:17 PM PDT 24
Finished Jul 27 04:53:21 PM PDT 24
Peak memory 217044 kb
Host smart-39fa8bfe-b99e-4430-ad93-b71ea5eab8cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392168103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.3392168103
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.2405353532
Short name T352
Test name
Test status
Simulation time 58011130 ps
CPU time 1.06 seconds
Started Jul 27 04:53:20 PM PDT 24
Finished Jul 27 04:53:21 PM PDT 24
Peak memory 208912 kb
Host smart-52d3377d-e1f9-4620-8889-7f3a513ad12e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405353532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.2405353532
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.575792744
Short name T991
Test name
Test status
Simulation time 312455110 ps
CPU time 0.93 seconds
Started Jul 27 04:53:21 PM PDT 24
Finished Jul 27 04:53:22 PM PDT 24
Peak memory 207964 kb
Host smart-d4121add-c8e1-4cbe-8155-0d59a5ab0105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575792744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.575792744
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.2910060546
Short name T848
Test name
Test status
Simulation time 16433807118 ps
CPU time 11.88 seconds
Started Jul 27 04:53:23 PM PDT 24
Finished Jul 27 04:53:40 PM PDT 24
Peak memory 233696 kb
Host smart-0cf7e8d3-a5a6-4602-aece-6969ed8c9f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910060546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.2910060546
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.2357680689
Short name T71
Test name
Test status
Simulation time 37898984 ps
CPU time 0.74 seconds
Started Jul 27 04:52:03 PM PDT 24
Finished Jul 27 04:52:04 PM PDT 24
Peak memory 205372 kb
Host smart-6b1aa941-02b6-43fc-9023-59df2d2ba8ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357680689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.2
357680689
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.3356970222
Short name T670
Test name
Test status
Simulation time 37590648 ps
CPU time 2.32 seconds
Started Jul 27 04:52:12 PM PDT 24
Finished Jul 27 04:52:15 PM PDT 24
Peak memory 225304 kb
Host smart-97dc7bb8-c214-4aad-be0c-8459b0bfc403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356970222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.3356970222
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.1189040253
Short name T943
Test name
Test status
Simulation time 35719259 ps
CPU time 0.81 seconds
Started Jul 27 04:52:08 PM PDT 24
Finished Jul 27 04:52:09 PM PDT 24
Peak memory 206144 kb
Host smart-e5530963-04ea-49c4-b52f-ec33ea383f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189040253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.1189040253
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.1756403848
Short name T68
Test name
Test status
Simulation time 33496878192 ps
CPU time 105.77 seconds
Started Jul 27 04:52:01 PM PDT 24
Finished Jul 27 04:53:47 PM PDT 24
Peak memory 250116 kb
Host smart-8de96751-dab1-4d7a-8a50-3b22d219e124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756403848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.1756403848
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.1955651544
Short name T945
Test name
Test status
Simulation time 7504053281 ps
CPU time 50.9 seconds
Started Jul 27 04:52:20 PM PDT 24
Finished Jul 27 04:53:11 PM PDT 24
Peak memory 250060 kb
Host smart-1e5fc67b-de4d-45a4-bbf5-a57c19a675e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955651544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.1955651544
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.418267143
Short name T442
Test name
Test status
Simulation time 48220556 ps
CPU time 0.83 seconds
Started Jul 27 04:52:06 PM PDT 24
Finished Jul 27 04:52:07 PM PDT 24
Peak memory 217724 kb
Host smart-17829bc4-4236-4135-8c88-a2e4cef678ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418267143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle.
418267143
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.865304836
Short name T927
Test name
Test status
Simulation time 210219817 ps
CPU time 5.26 seconds
Started Jul 27 04:52:09 PM PDT 24
Finished Jul 27 04:52:14 PM PDT 24
Peak memory 233572 kb
Host smart-5b069f7e-023e-430e-8316-13c04b2df95b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865304836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.865304836
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.1259988826
Short name T303
Test name
Test status
Simulation time 11171413836 ps
CPU time 55.62 seconds
Started Jul 27 04:52:06 PM PDT 24
Finished Jul 27 04:53:01 PM PDT 24
Peak memory 250988 kb
Host smart-f7898aad-9277-4fb8-b7af-595ac56bd416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259988826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds
.1259988826
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_intercept.2687364925
Short name T707
Test name
Test status
Simulation time 935475801 ps
CPU time 5.2 seconds
Started Jul 27 04:52:10 PM PDT 24
Finished Jul 27 04:52:15 PM PDT 24
Peak memory 233540 kb
Host smart-8745645f-7bab-4f02-a38f-c7025ef5ecac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687364925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.2687364925
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.1396954498
Short name T749
Test name
Test status
Simulation time 1661928634 ps
CPU time 7.25 seconds
Started Jul 27 04:52:07 PM PDT 24
Finished Jul 27 04:52:15 PM PDT 24
Peak memory 233496 kb
Host smart-be5b169b-68a9-48c6-802a-27f828028077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396954498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.1396954498
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.1490107330
Short name T671
Test name
Test status
Simulation time 23875626 ps
CPU time 1.01 seconds
Started Jul 27 04:52:05 PM PDT 24
Finished Jul 27 04:52:07 PM PDT 24
Peak memory 217256 kb
Host smart-5946e2d8-949b-4476-bb2e-f73a688b660c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490107330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.spi_device_mem_parity.1490107330
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.2992099566
Short name T865
Test name
Test status
Simulation time 1925878159 ps
CPU time 3.27 seconds
Started Jul 27 04:52:12 PM PDT 24
Finished Jul 27 04:52:16 PM PDT 24
Peak memory 225368 kb
Host smart-9892da5d-1e90-4774-82ff-f2fbbad0826f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992099566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.2992099566
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.2060787265
Short name T551
Test name
Test status
Simulation time 8732968850 ps
CPU time 9.1 seconds
Started Jul 27 04:52:03 PM PDT 24
Finished Jul 27 04:52:12 PM PDT 24
Peak memory 233564 kb
Host smart-87adc052-57e8-4575-9834-eed4478f4d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060787265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.2060787265
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.1047441213
Short name T1031
Test name
Test status
Simulation time 445128424 ps
CPU time 3.18 seconds
Started Jul 27 04:52:10 PM PDT 24
Finished Jul 27 04:52:13 PM PDT 24
Peak memory 221564 kb
Host smart-8c6edd11-2a0b-43b8-9fff-a79393f51303
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1047441213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.1047441213
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.606040403
Short name T75
Test name
Test status
Simulation time 184431217 ps
CPU time 0.92 seconds
Started Jul 27 04:52:02 PM PDT 24
Finished Jul 27 04:52:03 PM PDT 24
Peak memory 235856 kb
Host smart-6818877f-559b-49bf-a075-7510f9048b09
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606040403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.606040403
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.1252657804
Short name T19
Test name
Test status
Simulation time 1307815724 ps
CPU time 8.8 seconds
Started Jul 27 04:52:03 PM PDT 24
Finished Jul 27 04:52:12 PM PDT 24
Peak memory 218480 kb
Host smart-0e61733b-16dd-4393-9cdc-3b006fd16947
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252657804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.1252657804
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.476726450
Short name T173
Test name
Test status
Simulation time 16336234201 ps
CPU time 9.62 seconds
Started Jul 27 04:52:09 PM PDT 24
Finished Jul 27 04:52:19 PM PDT 24
Peak memory 217152 kb
Host smart-0e773680-3269-4fd2-bfed-16e8ccf9fda9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476726450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.476726450
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.3294201419
Short name T518
Test name
Test status
Simulation time 38446117372 ps
CPU time 13.16 seconds
Started Jul 27 04:52:06 PM PDT 24
Finished Jul 27 04:52:19 PM PDT 24
Peak memory 217108 kb
Host smart-ca1cd013-3eb2-4499-947e-d53aa028449e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294201419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.3294201419
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.1858402767
Short name T933
Test name
Test status
Simulation time 61841150 ps
CPU time 1.41 seconds
Started Jul 27 04:52:06 PM PDT 24
Finished Jul 27 04:52:08 PM PDT 24
Peak memory 217052 kb
Host smart-34c134b1-632e-4174-8636-cbfb3567927a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858402767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.1858402767
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.1380391353
Short name T356
Test name
Test status
Simulation time 91213670 ps
CPU time 0.97 seconds
Started Jul 27 04:51:59 PM PDT 24
Finished Jul 27 04:52:00 PM PDT 24
Peak memory 206908 kb
Host smart-0e2e6c11-3e29-4663-a472-7eea7f14e29e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380391353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.1380391353
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.3770671889
Short name T895
Test name
Test status
Simulation time 18285644443 ps
CPU time 15.92 seconds
Started Jul 27 04:52:07 PM PDT 24
Finished Jul 27 04:52:23 PM PDT 24
Peak memory 225376 kb
Host smart-cb6eb0c9-a143-46cc-91e3-650f9249e155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770671889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.3770671889
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.1184635356
Short name T620
Test name
Test status
Simulation time 13836430 ps
CPU time 0.72 seconds
Started Jul 27 04:53:30 PM PDT 24
Finished Jul 27 04:53:30 PM PDT 24
Peak memory 205472 kb
Host smart-214621fd-250a-434f-9d58-6e4e49c9186b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184635356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
1184635356
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.3702502392
Short name T630
Test name
Test status
Simulation time 3061137458 ps
CPU time 12.2 seconds
Started Jul 27 04:53:33 PM PDT 24
Finished Jul 27 04:53:50 PM PDT 24
Peak memory 233636 kb
Host smart-7163f2a4-7f6f-4df9-aa65-0057f6663c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702502392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.3702502392
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.1463785208
Short name T758
Test name
Test status
Simulation time 19337284 ps
CPU time 0.79 seconds
Started Jul 27 04:53:26 PM PDT 24
Finished Jul 27 04:53:27 PM PDT 24
Peak memory 207452 kb
Host smart-0bca161b-d305-4776-941f-4437948edd13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463785208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.1463785208
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.2859366658
Short name T225
Test name
Test status
Simulation time 30916660228 ps
CPU time 242.29 seconds
Started Jul 27 04:53:25 PM PDT 24
Finished Jul 27 04:57:27 PM PDT 24
Peak memory 252560 kb
Host smart-10adcc0d-9185-46dc-84e9-e9522e66abcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859366658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.2859366658
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.2566041959
Short name T56
Test name
Test status
Simulation time 31841142468 ps
CPU time 49.61 seconds
Started Jul 27 04:53:27 PM PDT 24
Finished Jul 27 04:54:17 PM PDT 24
Peak memory 258332 kb
Host smart-c1fb0b18-5a2e-4ab2-bbfe-b740c438a003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566041959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.2566041959
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.1885049496
Short name T856
Test name
Test status
Simulation time 1751828788 ps
CPU time 9.3 seconds
Started Jul 27 04:53:26 PM PDT 24
Finished Jul 27 04:53:35 PM PDT 24
Peak memory 240524 kb
Host smart-1b3fdf0d-0438-4a91-9b30-e205cf093cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885049496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.1885049496
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.614364118
Short name T29
Test name
Test status
Simulation time 33820004850 ps
CPU time 40.68 seconds
Started Jul 27 04:53:22 PM PDT 24
Finished Jul 27 04:54:03 PM PDT 24
Peak memory 249944 kb
Host smart-c345d8ba-36c1-43e1-8186-97eab292b2f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614364118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmds
.614364118
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/30.spi_device_intercept.2653533200
Short name T284
Test name
Test status
Simulation time 293994008 ps
CPU time 3.26 seconds
Started Jul 27 04:53:24 PM PDT 24
Finished Jul 27 04:53:28 PM PDT 24
Peak memory 225392 kb
Host smart-2337c6b1-19af-4f36-8e92-6a09a4a789e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653533200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.2653533200
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.4062497393
Short name T131
Test name
Test status
Simulation time 3942668296 ps
CPU time 3.58 seconds
Started Jul 27 04:53:24 PM PDT 24
Finished Jul 27 04:53:27 PM PDT 24
Peak memory 233568 kb
Host smart-ab20207e-c2b3-4134-bc7a-c8c490bba706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062497393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.4062497393
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.3181338053
Short name T297
Test name
Test status
Simulation time 2053627056 ps
CPU time 7.97 seconds
Started Jul 27 04:53:28 PM PDT 24
Finished Jul 27 04:53:36 PM PDT 24
Peak memory 233476 kb
Host smart-a89d7bd4-580b-401a-8ed1-60bbc8cf528b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181338053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.3181338053
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.3029074341
Short name T98
Test name
Test status
Simulation time 51219311244 ps
CPU time 21.01 seconds
Started Jul 27 04:53:36 PM PDT 24
Finished Jul 27 04:53:57 PM PDT 24
Peak memory 233588 kb
Host smart-9702b60d-f5c2-4631-afad-1e32748cd15b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029074341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.3029074341
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.1634046309
Short name T549
Test name
Test status
Simulation time 194989242 ps
CPU time 4.52 seconds
Started Jul 27 04:53:27 PM PDT 24
Finished Jul 27 04:53:32 PM PDT 24
Peak memory 221324 kb
Host smart-2a46270d-17b8-4939-8935-ab7e29379b3a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1634046309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.1634046309
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.2082822906
Short name T166
Test name
Test status
Simulation time 158263436 ps
CPU time 0.99 seconds
Started Jul 27 04:53:25 PM PDT 24
Finished Jul 27 04:53:26 PM PDT 24
Peak memory 207576 kb
Host smart-8f161016-1725-40dc-be47-e55e4013e957
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082822906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.2082822906
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.327641791
Short name T619
Test name
Test status
Simulation time 4982911578 ps
CPU time 8.08 seconds
Started Jul 27 04:53:30 PM PDT 24
Finished Jul 27 04:53:39 PM PDT 24
Peak memory 217084 kb
Host smart-0816c29b-523f-437a-9734-463f7f5645b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327641791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.327641791
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.3844240105
Short name T473
Test name
Test status
Simulation time 1181582687 ps
CPU time 2.7 seconds
Started Jul 27 04:53:29 PM PDT 24
Finished Jul 27 04:53:32 PM PDT 24
Peak memory 216980 kb
Host smart-71ced567-ad17-4dc0-bbf9-19297919714e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844240105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.3844240105
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.4176794524
Short name T831
Test name
Test status
Simulation time 124913933 ps
CPU time 1 seconds
Started Jul 27 04:53:41 PM PDT 24
Finished Jul 27 04:53:42 PM PDT 24
Peak memory 208604 kb
Host smart-6aeefe02-c385-4309-a3d9-e3b344e14599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176794524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.4176794524
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.185077844
Short name T819
Test name
Test status
Simulation time 39025650 ps
CPU time 0.7 seconds
Started Jul 27 04:53:29 PM PDT 24
Finished Jul 27 04:53:30 PM PDT 24
Peak memory 206188 kb
Host smart-a562e511-a290-4c00-b374-567090b3d59d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185077844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.185077844
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.3330984713
Short name T445
Test name
Test status
Simulation time 116738936 ps
CPU time 2.38 seconds
Started Jul 27 04:53:23 PM PDT 24
Finished Jul 27 04:53:25 PM PDT 24
Peak memory 225408 kb
Host smart-d62b1ab7-2e03-4749-9ebe-32461b09c50e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330984713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.3330984713
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.3789044046
Short name T673
Test name
Test status
Simulation time 46995256 ps
CPU time 0.73 seconds
Started Jul 27 04:53:24 PM PDT 24
Finished Jul 27 04:53:25 PM PDT 24
Peak memory 205392 kb
Host smart-a5491328-ca5b-44a9-aeb3-84d11b0b6185
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789044046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
3789044046
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.579788165
Short name T495
Test name
Test status
Simulation time 371710785 ps
CPU time 2.06 seconds
Started Jul 27 04:53:28 PM PDT 24
Finished Jul 27 04:53:30 PM PDT 24
Peak memory 224552 kb
Host smart-a4e58cf6-398b-4a61-a8e9-e263aaddfa37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579788165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.579788165
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.2530396771
Short name T904
Test name
Test status
Simulation time 43208530 ps
CPU time 0.81 seconds
Started Jul 27 04:53:17 PM PDT 24
Finished Jul 27 04:53:18 PM PDT 24
Peak memory 207144 kb
Host smart-b3d7eb1f-8c7e-418b-b271-94ae363bbe73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530396771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.2530396771
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.3223559188
Short name T187
Test name
Test status
Simulation time 68177669839 ps
CPU time 55.19 seconds
Started Jul 27 04:53:22 PM PDT 24
Finished Jul 27 04:54:17 PM PDT 24
Peak memory 241452 kb
Host smart-cb21963b-41b3-472f-baf8-7efe9f74fab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223559188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.3223559188
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.2652230910
Short name T243
Test name
Test status
Simulation time 12464894956 ps
CPU time 79.65 seconds
Started Jul 27 04:53:24 PM PDT 24
Finished Jul 27 04:54:44 PM PDT 24
Peak memory 241912 kb
Host smart-0fafb7b9-c4b2-4734-a035-60f358a5fefd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652230910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.2652230910
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.2307846753
Short name T906
Test name
Test status
Simulation time 26633968931 ps
CPU time 58.26 seconds
Started Jul 27 04:53:23 PM PDT 24
Finished Jul 27 04:54:21 PM PDT 24
Peak memory 251672 kb
Host smart-c8c78a53-b01c-4b00-b567-362e5df00c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307846753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.2307846753
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.532173822
Short name T683
Test name
Test status
Simulation time 181174814 ps
CPU time 4.25 seconds
Started Jul 27 04:53:26 PM PDT 24
Finished Jul 27 04:53:31 PM PDT 24
Peak memory 225472 kb
Host smart-f3709d03-7b7d-47b5-9d3a-381db175e10a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532173822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.532173822
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.1790363864
Short name T621
Test name
Test status
Simulation time 544480413 ps
CPU time 3.42 seconds
Started Jul 27 04:53:27 PM PDT 24
Finished Jul 27 04:53:30 PM PDT 24
Peak memory 233540 kb
Host smart-9b7a4d4d-04d8-4312-86ef-530f1e3f1b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790363864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.1790363864
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.1684903976
Short name T338
Test name
Test status
Simulation time 650931367 ps
CPU time 2.41 seconds
Started Jul 27 04:53:21 PM PDT 24
Finished Jul 27 04:53:23 PM PDT 24
Peak memory 224824 kb
Host smart-75478c77-0f7e-4778-b1a4-f33320ece9e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684903976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.1684903976
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.872754188
Short name T477
Test name
Test status
Simulation time 56618506 ps
CPU time 1.94 seconds
Started Jul 27 04:53:25 PM PDT 24
Finished Jul 27 04:53:27 PM PDT 24
Peak memory 224192 kb
Host smart-c3f52a22-749f-4d02-8045-c314588f56dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872754188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swap
.872754188
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.2021042513
Short name T650
Test name
Test status
Simulation time 1878025933 ps
CPU time 5.35 seconds
Started Jul 27 04:53:24 PM PDT 24
Finished Jul 27 04:53:29 PM PDT 24
Peak memory 225380 kb
Host smart-3d978f9c-351e-4716-89d3-0a71d5c8c05f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021042513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.2021042513
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.1674623076
Short name T574
Test name
Test status
Simulation time 561516359 ps
CPU time 5.59 seconds
Started Jul 27 04:53:27 PM PDT 24
Finished Jul 27 04:53:38 PM PDT 24
Peak memory 219824 kb
Host smart-ba2ad6b9-6db1-4244-bd98-2ed08b3856c4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1674623076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.1674623076
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.1845581236
Short name T293
Test name
Test status
Simulation time 516617504703 ps
CPU time 975.8 seconds
Started Jul 27 04:53:29 PM PDT 24
Finished Jul 27 05:09:45 PM PDT 24
Peak memory 299964 kb
Host smart-5e8efe5a-443e-4707-b841-fa89c316510a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845581236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.1845581236
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.813800580
Short name T799
Test name
Test status
Simulation time 256745181 ps
CPU time 0.76 seconds
Started Jul 27 04:53:26 PM PDT 24
Finished Jul 27 04:53:27 PM PDT 24
Peak memory 206404 kb
Host smart-cab298f1-cfcd-4d8a-a7aa-8477909e8165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813800580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.813800580
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.1106901130
Short name T603
Test name
Test status
Simulation time 5977613678 ps
CPU time 10.22 seconds
Started Jul 27 04:53:41 PM PDT 24
Finished Jul 27 04:53:52 PM PDT 24
Peak memory 217236 kb
Host smart-348a7b05-bc7f-4f42-95f9-c3359919bc0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106901130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.1106901130
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.3244784438
Short name T596
Test name
Test status
Simulation time 161024295 ps
CPU time 1.14 seconds
Started Jul 27 04:53:29 PM PDT 24
Finished Jul 27 04:53:30 PM PDT 24
Peak memory 208596 kb
Host smart-716a1457-7436-4c0b-b5f7-84748c36a1c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244784438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.3244784438
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.1208502292
Short name T880
Test name
Test status
Simulation time 67359825 ps
CPU time 1 seconds
Started Jul 27 04:53:23 PM PDT 24
Finished Jul 27 04:53:24 PM PDT 24
Peak memory 206720 kb
Host smart-6aa59cd6-0ba4-4914-aa35-3b725fefc7a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208502292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.1208502292
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.782597391
Short name T278
Test name
Test status
Simulation time 820554353 ps
CPU time 5.12 seconds
Started Jul 27 04:53:25 PM PDT 24
Finished Jul 27 04:53:30 PM PDT 24
Peak memory 241788 kb
Host smart-55f21084-ad1c-48b8-81d1-124d769405ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782597391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.782597391
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.3691486041
Short name T457
Test name
Test status
Simulation time 29366940 ps
CPU time 0.75 seconds
Started Jul 27 04:53:45 PM PDT 24
Finished Jul 27 04:53:46 PM PDT 24
Peak memory 205484 kb
Host smart-a908e995-0ae4-449d-907f-033a2f103b5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691486041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
3691486041
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.4170797551
Short name T341
Test name
Test status
Simulation time 198451155 ps
CPU time 3.22 seconds
Started Jul 27 04:53:50 PM PDT 24
Finished Jul 27 04:53:53 PM PDT 24
Peak memory 233664 kb
Host smart-078c52e1-38de-48e3-b00d-b8a3d179ea9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170797551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.4170797551
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.1544621086
Short name T931
Test name
Test status
Simulation time 62573791 ps
CPU time 0.73 seconds
Started Jul 27 04:53:29 PM PDT 24
Finished Jul 27 04:53:29 PM PDT 24
Peak memory 207220 kb
Host smart-02fd3263-400f-4021-9bc0-c7a6087411ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544621086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.1544621086
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.2422010379
Short name T236
Test name
Test status
Simulation time 287254393237 ps
CPU time 404.86 seconds
Started Jul 27 04:53:31 PM PDT 24
Finished Jul 27 05:00:16 PM PDT 24
Peak memory 258188 kb
Host smart-684f7c23-5a70-4f1a-a759-b10962de57c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422010379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.2422010379
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.3291269822
Short name T759
Test name
Test status
Simulation time 39680543438 ps
CPU time 370.83 seconds
Started Jul 27 04:53:32 PM PDT 24
Finished Jul 27 04:59:43 PM PDT 24
Peak memory 262252 kb
Host smart-8b8368e0-4c64-4b62-b229-136fc3ad22d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291269822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.3291269822
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.3476986698
Short name T584
Test name
Test status
Simulation time 3847890048 ps
CPU time 54.22 seconds
Started Jul 27 04:53:32 PM PDT 24
Finished Jul 27 04:54:27 PM PDT 24
Peak memory 241132 kb
Host smart-d6763228-825b-4046-a034-bb019605a1b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476986698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.3476986698
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.167133698
Short name T654
Test name
Test status
Simulation time 3389779916 ps
CPU time 58.51 seconds
Started Jul 27 04:53:30 PM PDT 24
Finished Jul 27 04:54:28 PM PDT 24
Peak memory 251612 kb
Host smart-9e6b8c76-f512-4b27-b928-738bb1aafada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167133698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.167133698
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.3582987554
Short name T850
Test name
Test status
Simulation time 7319519612 ps
CPU time 44.23 seconds
Started Jul 27 04:53:41 PM PDT 24
Finished Jul 27 04:54:26 PM PDT 24
Peak memory 265452 kb
Host smart-b7da9107-0e0a-4a1a-bf41-dec36a475725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582987554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmd
s.3582987554
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_intercept.2990420403
Short name T235
Test name
Test status
Simulation time 1613469030 ps
CPU time 9.76 seconds
Started Jul 27 04:53:30 PM PDT 24
Finished Jul 27 04:53:40 PM PDT 24
Peak memory 233580 kb
Host smart-901e3d3e-1d6a-45b8-9993-69db3d7bf746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990420403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.2990420403
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.2546482478
Short name T523
Test name
Test status
Simulation time 28818117792 ps
CPU time 48.84 seconds
Started Jul 27 04:53:46 PM PDT 24
Finished Jul 27 04:54:35 PM PDT 24
Peak memory 241656 kb
Host smart-76faf616-796c-4c8c-a000-3bd7c5b83533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546482478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.2546482478
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.3987990775
Short name T882
Test name
Test status
Simulation time 402130354 ps
CPU time 3.54 seconds
Started Jul 27 04:53:37 PM PDT 24
Finished Jul 27 04:53:41 PM PDT 24
Peak memory 225300 kb
Host smart-d255fecf-7273-4620-8883-a8254a650ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987990775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.3987990775
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.2857952220
Short name T193
Test name
Test status
Simulation time 2715089388 ps
CPU time 8.01 seconds
Started Jul 27 04:53:38 PM PDT 24
Finished Jul 27 04:53:46 PM PDT 24
Peak memory 233864 kb
Host smart-01fef6ba-55f2-4dfe-8cbb-96af39eb81dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857952220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.2857952220
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.1759828868
Short name T735
Test name
Test status
Simulation time 7169018470 ps
CPU time 13.53 seconds
Started Jul 27 04:53:51 PM PDT 24
Finished Jul 27 04:54:05 PM PDT 24
Peak memory 219928 kb
Host smart-cdd7780c-0771-4702-8e90-295679713cf5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1759828868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.1759828868
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.2338983896
Short name T300
Test name
Test status
Simulation time 2510825946 ps
CPU time 43.64 seconds
Started Jul 27 04:53:44 PM PDT 24
Finished Jul 27 04:54:27 PM PDT 24
Peak memory 235520 kb
Host smart-b3f64bfe-a44a-4c0f-ae12-0e79d448c177
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338983896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.2338983896
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.3973401584
Short name T30
Test name
Test status
Simulation time 1389768188 ps
CPU time 7.37 seconds
Started Jul 27 04:53:27 PM PDT 24
Finished Jul 27 04:53:35 PM PDT 24
Peak memory 219656 kb
Host smart-321b23cf-8a1f-452b-94db-cf0733543ca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973401584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.3973401584
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.3682027682
Short name T371
Test name
Test status
Simulation time 1126852946 ps
CPU time 4.01 seconds
Started Jul 27 04:53:41 PM PDT 24
Finished Jul 27 04:53:45 PM PDT 24
Peak memory 217072 kb
Host smart-39816a89-a224-4647-80c4-4d95b8dccb46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682027682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.3682027682
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.3705142200
Short name T897
Test name
Test status
Simulation time 117062137 ps
CPU time 1.2 seconds
Started Jul 27 04:53:40 PM PDT 24
Finished Jul 27 04:53:41 PM PDT 24
Peak memory 208700 kb
Host smart-289d5e3e-b237-49ee-9930-83682506b585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705142200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.3705142200
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.3971601332
Short name T642
Test name
Test status
Simulation time 16550622 ps
CPU time 0.72 seconds
Started Jul 27 04:53:36 PM PDT 24
Finished Jul 27 04:53:37 PM PDT 24
Peak memory 206684 kb
Host smart-182b4ab8-191c-4c62-bf94-2ca6b7eb9ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971601332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.3971601332
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.4047624667
Short name T510
Test name
Test status
Simulation time 7919925812 ps
CPU time 21.78 seconds
Started Jul 27 04:53:27 PM PDT 24
Finished Jul 27 04:53:49 PM PDT 24
Peak memory 233656 kb
Host smart-2d21fe3c-79fd-4995-bbcc-cd0544ed7d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047624667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.4047624667
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.271767605
Short name T1022
Test name
Test status
Simulation time 13130939 ps
CPU time 0.7 seconds
Started Jul 27 04:53:29 PM PDT 24
Finished Jul 27 04:53:30 PM PDT 24
Peak memory 205388 kb
Host smart-169e4214-996d-40a7-948d-740d934b2cf5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271767605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.271767605
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.3393982956
Short name T970
Test name
Test status
Simulation time 191069233 ps
CPU time 4.96 seconds
Started Jul 27 04:53:45 PM PDT 24
Finished Jul 27 04:53:50 PM PDT 24
Peak memory 233532 kb
Host smart-ca654cd1-b927-48ce-a589-1c0ca574c5f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393982956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.3393982956
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.4156153223
Short name T965
Test name
Test status
Simulation time 29687198 ps
CPU time 0.81 seconds
Started Jul 27 04:53:43 PM PDT 24
Finished Jul 27 04:53:44 PM PDT 24
Peak memory 207472 kb
Host smart-6e90fd77-de0b-4998-82bb-2524cb11c2d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156153223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.4156153223
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.1100309877
Short name T59
Test name
Test status
Simulation time 167979777575 ps
CPU time 130.04 seconds
Started Jul 27 04:53:39 PM PDT 24
Finished Jul 27 04:55:49 PM PDT 24
Peak memory 253808 kb
Host smart-2f227854-066a-4c37-b523-a66888d17661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100309877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.1100309877
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.2018411565
Short name T215
Test name
Test status
Simulation time 154959585243 ps
CPU time 406.51 seconds
Started Jul 27 04:53:28 PM PDT 24
Finished Jul 27 05:00:14 PM PDT 24
Peak memory 270548 kb
Host smart-5b6db581-519a-4c83-9094-9700ff45084c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018411565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.2018411565
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.646825818
Short name T873
Test name
Test status
Simulation time 21542609313 ps
CPU time 24.73 seconds
Started Jul 27 04:53:50 PM PDT 24
Finished Jul 27 04:54:15 PM PDT 24
Peak memory 241396 kb
Host smart-1be1695f-fb61-4741-857e-c95d56f26cd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646825818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmds
.646825818
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_intercept.1528994104
Short name T995
Test name
Test status
Simulation time 1282018476 ps
CPU time 5.82 seconds
Started Jul 27 04:53:33 PM PDT 24
Finished Jul 27 04:53:39 PM PDT 24
Peak memory 233544 kb
Host smart-3c824b5b-188d-434e-982a-925dd08b3f54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528994104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.1528994104
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.219288115
Short name T481
Test name
Test status
Simulation time 825554328 ps
CPU time 15.17 seconds
Started Jul 27 04:53:45 PM PDT 24
Finished Jul 27 04:54:00 PM PDT 24
Peak memory 233624 kb
Host smart-15077747-53e6-4940-91f8-b772759971bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219288115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.219288115
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.1885257309
Short name T261
Test name
Test status
Simulation time 3303687206 ps
CPU time 11.26 seconds
Started Jul 27 04:53:46 PM PDT 24
Finished Jul 27 04:53:57 PM PDT 24
Peak memory 233672 kb
Host smart-63eeb555-66e6-43ec-9e6a-2544b26be552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885257309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.1885257309
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.3004889741
Short name T912
Test name
Test status
Simulation time 15829474104 ps
CPU time 16.18 seconds
Started Jul 27 04:53:37 PM PDT 24
Finished Jul 27 04:53:53 PM PDT 24
Peak memory 233492 kb
Host smart-eeb0e9ee-54a6-4660-8848-d3b0948c9a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004889741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.3004889741
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.2579239584
Short name T866
Test name
Test status
Simulation time 222809937 ps
CPU time 4.16 seconds
Started Jul 27 04:53:41 PM PDT 24
Finished Jul 27 04:53:45 PM PDT 24
Peak memory 221692 kb
Host smart-d1098e81-840e-42b1-aa88-22eb7b3ec5c1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2579239584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.2579239584
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.3101210894
Short name T513
Test name
Test status
Simulation time 12706346524 ps
CPU time 84.43 seconds
Started Jul 27 04:53:22 PM PDT 24
Finished Jul 27 04:54:47 PM PDT 24
Peak memory 252288 kb
Host smart-72835d15-c5bc-406d-be4e-0fbd431d60b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101210894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.3101210894
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.2740095610
Short name T321
Test name
Test status
Simulation time 57315720669 ps
CPU time 33.89 seconds
Started Jul 27 04:53:24 PM PDT 24
Finished Jul 27 04:53:58 PM PDT 24
Peak memory 217376 kb
Host smart-0467d770-3d97-467b-aba9-bbfb5441db46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740095610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.2740095610
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.1916865940
Short name T605
Test name
Test status
Simulation time 27616149740 ps
CPU time 15.83 seconds
Started Jul 27 04:53:24 PM PDT 24
Finished Jul 27 04:53:40 PM PDT 24
Peak memory 218364 kb
Host smart-1660fe9a-a8df-4c0d-9517-f04bc4d501e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916865940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.1916865940
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.1888488146
Short name T35
Test name
Test status
Simulation time 116594770 ps
CPU time 1.79 seconds
Started Jul 27 04:53:48 PM PDT 24
Finished Jul 27 04:53:50 PM PDT 24
Peak memory 217004 kb
Host smart-0f722439-ea09-4ea7-8033-75d332e019bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888488146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.1888488146
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.2684429574
Short name T885
Test name
Test status
Simulation time 56261894 ps
CPU time 0.78 seconds
Started Jul 27 04:53:26 PM PDT 24
Finished Jul 27 04:53:27 PM PDT 24
Peak memory 206732 kb
Host smart-6df1a345-3cc5-4096-88e4-7d7e5438d332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684429574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.2684429574
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.1090405273
Short name T468
Test name
Test status
Simulation time 5280121433 ps
CPU time 7.96 seconds
Started Jul 27 04:53:29 PM PDT 24
Finished Jul 27 04:53:37 PM PDT 24
Peak memory 233552 kb
Host smart-ad86fc63-3e1e-4db0-a3e9-f93b97148c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090405273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.1090405273
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.2169853165
Short name T691
Test name
Test status
Simulation time 44300343 ps
CPU time 0.79 seconds
Started Jul 27 04:53:44 PM PDT 24
Finished Jul 27 04:53:45 PM PDT 24
Peak memory 206036 kb
Host smart-635c41ad-e130-439d-bc2d-4cada1da9032
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169853165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
2169853165
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.38059740
Short name T372
Test name
Test status
Simulation time 962541121 ps
CPU time 2.17 seconds
Started Jul 27 04:53:47 PM PDT 24
Finished Jul 27 04:53:49 PM PDT 24
Peak memory 225464 kb
Host smart-8f776ae5-3e8b-4088-8336-2e0e54e874c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38059740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.38059740
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.2906576857
Short name T339
Test name
Test status
Simulation time 20385883 ps
CPU time 0.83 seconds
Started Jul 27 04:53:33 PM PDT 24
Finished Jul 27 04:53:34 PM PDT 24
Peak memory 207156 kb
Host smart-de158861-a8d6-441c-a22a-f37aecf67a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906576857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.2906576857
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.1288798803
Short name T265
Test name
Test status
Simulation time 7416378830 ps
CPU time 66.27 seconds
Started Jul 27 04:53:36 PM PDT 24
Finished Jul 27 04:54:42 PM PDT 24
Peak memory 256640 kb
Host smart-cb069989-20f9-426b-8e24-3501b790f651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288798803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.1288798803
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.3505089347
Short name T608
Test name
Test status
Simulation time 21319911108 ps
CPU time 214.12 seconds
Started Jul 27 04:53:42 PM PDT 24
Finished Jul 27 04:57:16 PM PDT 24
Peak memory 255148 kb
Host smart-a7e8a3e1-1224-47e5-b36c-1efe134414b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505089347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.3505089347
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.1773699649
Short name T623
Test name
Test status
Simulation time 20200573369 ps
CPU time 169.53 seconds
Started Jul 27 04:53:30 PM PDT 24
Finished Jul 27 04:56:19 PM PDT 24
Peak memory 250028 kb
Host smart-c980912f-d82b-4c24-a8b1-019a4cafa089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773699649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.1773699649
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.4182775892
Short name T937
Test name
Test status
Simulation time 143301150 ps
CPU time 4.55 seconds
Started Jul 27 04:53:29 PM PDT 24
Finished Jul 27 04:53:34 PM PDT 24
Peak memory 235744 kb
Host smart-ece4b96d-024e-49fa-a0dd-12363af762c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182775892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.4182775892
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_intercept.2388856236
Short name T828
Test name
Test status
Simulation time 5635944337 ps
CPU time 23.54 seconds
Started Jul 27 04:53:49 PM PDT 24
Finished Jul 27 04:54:13 PM PDT 24
Peak memory 233628 kb
Host smart-7dec5fe0-a7fb-4f0e-8e84-50a53cf5ae42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388856236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.2388856236
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.463861144
Short name T668
Test name
Test status
Simulation time 4563898951 ps
CPU time 27.55 seconds
Started Jul 27 04:53:38 PM PDT 24
Finished Jul 27 04:54:05 PM PDT 24
Peak memory 225336 kb
Host smart-2722b0ad-8e5c-43a4-99f9-7f0f9760215d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463861144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.463861144
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.1136713246
Short name T998
Test name
Test status
Simulation time 1872726756 ps
CPU time 7.71 seconds
Started Jul 27 04:53:36 PM PDT 24
Finished Jul 27 04:53:43 PM PDT 24
Peak memory 233604 kb
Host smart-623afa58-b319-4d33-b10c-9c1d90fd4788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136713246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.1136713246
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.2725743367
Short name T891
Test name
Test status
Simulation time 274114263 ps
CPU time 2.15 seconds
Started Jul 27 04:53:28 PM PDT 24
Finished Jul 27 04:53:31 PM PDT 24
Peak memory 225332 kb
Host smart-ae446bf1-4f0b-4380-aa07-d5c4fa220036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725743367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.2725743367
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.3446468233
Short name T696
Test name
Test status
Simulation time 4128244106 ps
CPU time 10.19 seconds
Started Jul 27 04:53:47 PM PDT 24
Finished Jul 27 04:53:57 PM PDT 24
Peak memory 223048 kb
Host smart-56f6b839-ece0-46cf-93cc-3248e3e4a5cb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3446468233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.3446468233
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.2148809695
Short name T57
Test name
Test status
Simulation time 13514288401 ps
CPU time 75.63 seconds
Started Jul 27 04:53:52 PM PDT 24
Finished Jul 27 04:55:08 PM PDT 24
Peak memory 258320 kb
Host smart-7d883713-97cf-48fb-ad35-3448685d33e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148809695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.2148809695
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.4240865446
Short name T838
Test name
Test status
Simulation time 508943739 ps
CPU time 8.2 seconds
Started Jul 27 04:53:28 PM PDT 24
Finished Jul 27 04:53:37 PM PDT 24
Peak memory 217064 kb
Host smart-54c5decc-a866-4dd8-8a44-d357fd60465e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240865446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.4240865446
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.245250943
Short name T752
Test name
Test status
Simulation time 5761852731 ps
CPU time 16.73 seconds
Started Jul 27 04:53:37 PM PDT 24
Finished Jul 27 04:53:54 PM PDT 24
Peak memory 217088 kb
Host smart-d9db6eac-ac80-4be0-86cc-f33cb0385ce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245250943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.245250943
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.2130476684
Short name T768
Test name
Test status
Simulation time 261586324 ps
CPU time 1.75 seconds
Started Jul 27 04:53:36 PM PDT 24
Finished Jul 27 04:53:38 PM PDT 24
Peak memory 217104 kb
Host smart-ea2df579-c80d-4892-bf4f-8cec34fc900b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130476684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.2130476684
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.1293604520
Short name T6
Test name
Test status
Simulation time 68434099 ps
CPU time 0.85 seconds
Started Jul 27 04:53:38 PM PDT 24
Finished Jul 27 04:53:39 PM PDT 24
Peak memory 206752 kb
Host smart-8d2b7898-1096-4ea9-ab38-729e17241ded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293604520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.1293604520
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.3900570380
Short name T658
Test name
Test status
Simulation time 522225791 ps
CPU time 11.37 seconds
Started Jul 27 04:53:32 PM PDT 24
Finished Jul 27 04:53:49 PM PDT 24
Peak memory 239048 kb
Host smart-327f648f-919f-47d6-ab59-1d6a8ecdb288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900570380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.3900570380
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.2284814890
Short name T543
Test name
Test status
Simulation time 22660087 ps
CPU time 0.72 seconds
Started Jul 27 04:53:49 PM PDT 24
Finished Jul 27 04:53:50 PM PDT 24
Peak memory 205372 kb
Host smart-6a7ff0a3-45d2-4b6b-82f3-505144af6a9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284814890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
2284814890
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.2131506856
Short name T336
Test name
Test status
Simulation time 55252759 ps
CPU time 2.08 seconds
Started Jul 27 04:53:50 PM PDT 24
Finished Jul 27 04:53:53 PM PDT 24
Peak memory 224836 kb
Host smart-7863dea4-c3fd-42ee-8f32-d1a6d706e2d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131506856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.2131506856
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.2938290862
Short name T342
Test name
Test status
Simulation time 17811227 ps
CPU time 0.79 seconds
Started Jul 27 04:53:32 PM PDT 24
Finished Jul 27 04:53:33 PM PDT 24
Peak memory 206128 kb
Host smart-196fd6b2-e02b-44ac-a878-0002982eb0ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938290862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.2938290862
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.3632474620
Short name T678
Test name
Test status
Simulation time 46187762140 ps
CPU time 140.57 seconds
Started Jul 27 04:53:41 PM PDT 24
Finished Jul 27 04:56:02 PM PDT 24
Peak memory 242240 kb
Host smart-e368a894-de75-49ee-afcd-6fdeb924335d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632474620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.3632474620
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.4117182499
Short name T687
Test name
Test status
Simulation time 123150493 ps
CPU time 2.6 seconds
Started Jul 27 04:53:46 PM PDT 24
Finished Jul 27 04:53:49 PM PDT 24
Peak memory 233508 kb
Host smart-27e8376f-1227-4ce0-bf94-157c7494be24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117182499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.4117182499
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.661810762
Short name T818
Test name
Test status
Simulation time 4762629409 ps
CPU time 48.24 seconds
Started Jul 27 04:53:44 PM PDT 24
Finished Jul 27 04:54:33 PM PDT 24
Peak memory 250080 kb
Host smart-9004187c-169d-44d1-9655-5cdf32848782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661810762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmds
.661810762
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/35.spi_device_intercept.2795632220
Short name T766
Test name
Test status
Simulation time 3329519522 ps
CPU time 17.21 seconds
Started Jul 27 04:53:41 PM PDT 24
Finished Jul 27 04:53:59 PM PDT 24
Peak memory 225416 kb
Host smart-2a07eed2-298e-4a30-aceb-457d3fadbacd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795632220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.2795632220
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.1474477982
Short name T592
Test name
Test status
Simulation time 497505795 ps
CPU time 7.84 seconds
Started Jul 27 04:53:53 PM PDT 24
Finished Jul 27 04:54:01 PM PDT 24
Peak memory 233536 kb
Host smart-700d0ed6-c039-4e85-8bb3-0d8aa7e14c1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474477982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.1474477982
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.1618506615
Short name T808
Test name
Test status
Simulation time 435097418 ps
CPU time 4.43 seconds
Started Jul 27 04:53:40 PM PDT 24
Finished Jul 27 04:53:44 PM PDT 24
Peak memory 233632 kb
Host smart-ff4fd12a-cbd0-4f71-991e-1897bc485d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618506615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.1618506615
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.652088926
Short name T917
Test name
Test status
Simulation time 319207787 ps
CPU time 2.71 seconds
Started Jul 27 04:53:23 PM PDT 24
Finished Jul 27 04:53:25 PM PDT 24
Peak memory 233616 kb
Host smart-50f621fd-93a6-4074-8d44-a561c36404ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652088926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.652088926
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.2126371867
Short name T588
Test name
Test status
Simulation time 353728344 ps
CPU time 3.84 seconds
Started Jul 27 04:53:49 PM PDT 24
Finished Jul 27 04:53:53 PM PDT 24
Peak memory 223180 kb
Host smart-edb07395-7ad4-44a5-b7cb-20218630ecc6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2126371867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.2126371867
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.2566972665
Short name T899
Test name
Test status
Simulation time 8968017023 ps
CPU time 72.92 seconds
Started Jul 27 04:53:48 PM PDT 24
Finished Jul 27 04:55:01 PM PDT 24
Peak memory 239476 kb
Host smart-7b73039b-c7c2-4988-b69b-2807a368c8ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566972665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.2566972665
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.1444031715
Short name T1014
Test name
Test status
Simulation time 10997788054 ps
CPU time 15.28 seconds
Started Jul 27 04:53:44 PM PDT 24
Finished Jul 27 04:53:59 PM PDT 24
Peak memory 217264 kb
Host smart-062c3164-cccd-4343-8919-a6647a7b1df8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444031715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.1444031715
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.1176104567
Short name T676
Test name
Test status
Simulation time 1948703230 ps
CPU time 9.4 seconds
Started Jul 27 04:53:33 PM PDT 24
Finished Jul 27 04:53:42 PM PDT 24
Peak memory 216952 kb
Host smart-d3eb847b-ac4e-4fad-bab3-1819ff273ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176104567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.1176104567
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.3975740308
Short name T974
Test name
Test status
Simulation time 113262688 ps
CPU time 1.98 seconds
Started Jul 27 04:53:46 PM PDT 24
Finished Jul 27 04:53:48 PM PDT 24
Peak memory 217180 kb
Host smart-06767322-f73b-43cb-a9c7-f05b99cbb9fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975740308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.3975740308
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.925793318
Short name T946
Test name
Test status
Simulation time 35817769 ps
CPU time 0.79 seconds
Started Jul 27 04:53:36 PM PDT 24
Finished Jul 27 04:53:37 PM PDT 24
Peak memory 206636 kb
Host smart-52a7bd07-849a-4cbf-9ed5-d1bd6cbdec53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925793318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.925793318
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.2682063298
Short name T964
Test name
Test status
Simulation time 359230154 ps
CPU time 4.06 seconds
Started Jul 27 04:53:49 PM PDT 24
Finished Jul 27 04:53:53 PM PDT 24
Peak memory 237800 kb
Host smart-05a8710e-f2c5-4251-8dde-c5af3385adcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682063298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.2682063298
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.18785192
Short name T836
Test name
Test status
Simulation time 11662148 ps
CPU time 0.73 seconds
Started Jul 27 04:53:44 PM PDT 24
Finished Jul 27 04:53:45 PM PDT 24
Peak memory 205928 kb
Host smart-1db8a992-d62e-4ada-bcf1-f53c18043a37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18785192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.18785192
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.786600154
Short name T189
Test name
Test status
Simulation time 928952697 ps
CPU time 2.29 seconds
Started Jul 27 04:53:45 PM PDT 24
Finished Jul 27 04:53:47 PM PDT 24
Peak memory 225280 kb
Host smart-1544d80c-fae6-43a1-b6b7-676043676592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786600154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.786600154
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.1775233031
Short name T564
Test name
Test status
Simulation time 18824588 ps
CPU time 0.81 seconds
Started Jul 27 04:53:52 PM PDT 24
Finished Jul 27 04:53:53 PM PDT 24
Peak memory 206448 kb
Host smart-93952b5f-4d42-4672-8b24-fb0428f8a000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775233031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.1775233031
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.2962514464
Short name T704
Test name
Test status
Simulation time 11476693457 ps
CPU time 50.93 seconds
Started Jul 27 04:53:44 PM PDT 24
Finished Jul 27 04:54:35 PM PDT 24
Peak memory 233632 kb
Host smart-47debb41-7e04-47c7-b624-1272a6cf9213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962514464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.2962514464
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.2556748191
Short name T37
Test name
Test status
Simulation time 22406973110 ps
CPU time 199.13 seconds
Started Jul 27 04:53:51 PM PDT 24
Finished Jul 27 04:57:10 PM PDT 24
Peak memory 258164 kb
Host smart-956e6692-b789-446d-845c-ec960b59b950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556748191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.2556748191
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.263857230
Short name T1024
Test name
Test status
Simulation time 2952950126 ps
CPU time 21.65 seconds
Started Jul 27 04:53:35 PM PDT 24
Finished Jul 27 04:53:56 PM PDT 24
Peak memory 233648 kb
Host smart-31da81f1-bed8-407a-a1c8-f8ba40166f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263857230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.263857230
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.87192987
Short name T179
Test name
Test status
Simulation time 14904526832 ps
CPU time 115.85 seconds
Started Jul 27 04:53:53 PM PDT 24
Finished Jul 27 04:55:49 PM PDT 24
Peak memory 257940 kb
Host smart-2663d16a-7b1d-4e7f-bd8e-412e85af6856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87192987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmds.87192987
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_intercept.900261456
Short name T509
Test name
Test status
Simulation time 76813835 ps
CPU time 2.35 seconds
Started Jul 27 04:53:53 PM PDT 24
Finished Jul 27 04:53:55 PM PDT 24
Peak memory 232784 kb
Host smart-5b976cc1-617d-4eca-98f4-57caec76d0bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900261456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.900261456
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.893614632
Short name T221
Test name
Test status
Simulation time 6134962477 ps
CPU time 7.53 seconds
Started Jul 27 04:53:47 PM PDT 24
Finished Jul 27 04:53:55 PM PDT 24
Peak memory 225416 kb
Host smart-137ad6d1-3194-4db3-bd6d-1b93d17cdb24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893614632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.893614632
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.3951627534
Short name T287
Test name
Test status
Simulation time 348085134 ps
CPU time 4.37 seconds
Started Jul 27 04:53:53 PM PDT 24
Finished Jul 27 04:53:57 PM PDT 24
Peak memory 233516 kb
Host smart-907931db-d06e-4032-89fa-7c2e60d9aee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951627534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.3951627534
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.972524961
Short name T757
Test name
Test status
Simulation time 2943448661 ps
CPU time 8.1 seconds
Started Jul 27 04:53:47 PM PDT 24
Finished Jul 27 04:53:55 PM PDT 24
Peak memory 233664 kb
Host smart-3fcab8df-4d87-4072-b99e-5098cb285bd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972524961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.972524961
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.847163728
Short name T9
Test name
Test status
Simulation time 693539812 ps
CPU time 6.08 seconds
Started Jul 27 04:53:51 PM PDT 24
Finished Jul 27 04:53:57 PM PDT 24
Peak memory 219964 kb
Host smart-6ede8ef5-5a7f-46e0-bc19-d1a02dab7a5b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=847163728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dire
ct.847163728
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.2630830603
Short name T165
Test name
Test status
Simulation time 4424357361 ps
CPU time 79.22 seconds
Started Jul 27 04:53:49 PM PDT 24
Finished Jul 27 04:55:08 PM PDT 24
Peak memory 252144 kb
Host smart-ccf5eb9d-7182-4f1a-8a41-702201503478
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630830603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.2630830603
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.1913211540
Short name T963
Test name
Test status
Simulation time 18649299115 ps
CPU time 26.37 seconds
Started Jul 27 04:53:43 PM PDT 24
Finished Jul 27 04:54:09 PM PDT 24
Peak memory 220712 kb
Host smart-dbd79d42-6065-4094-b3b0-d3961f0bf11e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913211540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.1913211540
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.3621847987
Short name T732
Test name
Test status
Simulation time 82427515 ps
CPU time 1.35 seconds
Started Jul 27 04:53:44 PM PDT 24
Finished Jul 27 04:53:45 PM PDT 24
Peak memory 208684 kb
Host smart-992e92ee-62a6-45f9-8ef5-50a5e3b52284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621847987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.3621847987
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.4127711644
Short name T953
Test name
Test status
Simulation time 61921875 ps
CPU time 0.91 seconds
Started Jul 27 04:53:54 PM PDT 24
Finished Jul 27 04:53:55 PM PDT 24
Peak memory 208136 kb
Host smart-70efb499-239a-474b-b696-258481e3fbfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127711644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.4127711644
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.232493161
Short name T467
Test name
Test status
Simulation time 32328737 ps
CPU time 0.79 seconds
Started Jul 27 04:53:52 PM PDT 24
Finished Jul 27 04:53:53 PM PDT 24
Peak memory 206640 kb
Host smart-3dfd2be1-4e9f-4573-94b8-eb6cc4e5969e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232493161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.232493161
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.2563158077
Short name T834
Test name
Test status
Simulation time 4717214720 ps
CPU time 9.64 seconds
Started Jul 27 04:53:42 PM PDT 24
Finished Jul 27 04:53:51 PM PDT 24
Peak memory 225320 kb
Host smart-4c56946c-c650-405c-9475-df0b28c39ba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563158077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.2563158077
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.610130921
Short name T73
Test name
Test status
Simulation time 19399153 ps
CPU time 0.72 seconds
Started Jul 27 04:53:55 PM PDT 24
Finished Jul 27 04:53:55 PM PDT 24
Peak memory 206332 kb
Host smart-59433c12-b349-4d83-b5c7-e4504120287d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610130921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.610130921
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.2764834207
Short name T810
Test name
Test status
Simulation time 360584254 ps
CPU time 4.17 seconds
Started Jul 27 04:53:38 PM PDT 24
Finished Jul 27 04:53:43 PM PDT 24
Peak memory 233556 kb
Host smart-4268b413-fa7b-496b-a743-0a801a4e0468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764834207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.2764834207
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.4181279692
Short name T531
Test name
Test status
Simulation time 22811557 ps
CPU time 0.79 seconds
Started Jul 27 04:53:41 PM PDT 24
Finished Jul 27 04:53:42 PM PDT 24
Peak memory 207196 kb
Host smart-1e0ab484-d1c3-46b1-b07b-a3eb0a13b37b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181279692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.4181279692
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.3231333805
Short name T52
Test name
Test status
Simulation time 86724974814 ps
CPU time 193.12 seconds
Started Jul 27 04:53:42 PM PDT 24
Finished Jul 27 04:56:55 PM PDT 24
Peak memory 255056 kb
Host smart-9f22c93e-70d5-4de2-8dc3-8fa596c53055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231333805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.3231333805
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.4197414187
Short name T854
Test name
Test status
Simulation time 16563920986 ps
CPU time 32.24 seconds
Started Jul 27 04:53:44 PM PDT 24
Finished Jul 27 04:54:16 PM PDT 24
Peak memory 232248 kb
Host smart-6531f6ba-173b-4eab-bd8e-b1a056b84a0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197414187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.4197414187
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.4066863999
Short name T417
Test name
Test status
Simulation time 7901039714 ps
CPU time 56.82 seconds
Started Jul 27 04:53:41 PM PDT 24
Finished Jul 27 04:54:38 PM PDT 24
Peak memory 241900 kb
Host smart-bd67a752-3a6e-4ad3-a897-01f08b561a86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066863999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmd
s.4066863999
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/37.spi_device_intercept.4094187442
Short name T275
Test name
Test status
Simulation time 296322466 ps
CPU time 2.26 seconds
Started Jul 27 04:53:48 PM PDT 24
Finished Jul 27 04:53:50 PM PDT 24
Peak memory 225404 kb
Host smart-79ab03fc-3e57-476a-b415-bf239eb78361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094187442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.4094187442
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.586664954
Short name T829
Test name
Test status
Simulation time 1751642555 ps
CPU time 16.24 seconds
Started Jul 27 04:53:35 PM PDT 24
Finished Jul 27 04:53:52 PM PDT 24
Peak memory 233616 kb
Host smart-d4e31e72-72e9-4cf2-8f72-c396f8d45244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586664954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.586664954
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.972693446
Short name T845
Test name
Test status
Simulation time 210988024 ps
CPU time 4.43 seconds
Started Jul 27 04:53:49 PM PDT 24
Finished Jul 27 04:53:53 PM PDT 24
Peak memory 233476 kb
Host smart-1251664e-47e4-4360-b40c-cac2a35bdbbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972693446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swap
.972693446
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.384801039
Short name T198
Test name
Test status
Simulation time 4493011299 ps
CPU time 18.37 seconds
Started Jul 27 04:53:46 PM PDT 24
Finished Jul 27 04:54:04 PM PDT 24
Peak memory 249580 kb
Host smart-65009714-0999-4fa8-9df0-1e902fc6f990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384801039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.384801039
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.264501795
Short name T821
Test name
Test status
Simulation time 240741292 ps
CPU time 5.08 seconds
Started Jul 27 04:53:37 PM PDT 24
Finished Jul 27 04:53:42 PM PDT 24
Peak memory 220808 kb
Host smart-ba01fe2d-6ace-43b6-8936-a20469e814ea
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=264501795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dire
ct.264501795
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.4031147688
Short name T562
Test name
Test status
Simulation time 6945923501 ps
CPU time 20.29 seconds
Started Jul 27 04:53:43 PM PDT 24
Finished Jul 27 04:54:03 PM PDT 24
Peak memory 217492 kb
Host smart-e8652db8-53ee-46bc-87da-0d6a9c6fabbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031147688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.4031147688
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.914649868
Short name T334
Test name
Test status
Simulation time 1078249398 ps
CPU time 2.84 seconds
Started Jul 27 04:53:33 PM PDT 24
Finished Jul 27 04:53:36 PM PDT 24
Peak memory 217100 kb
Host smart-47cd881c-3d9e-4830-8caa-b3d9c90433ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914649868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.914649868
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.58934770
Short name T979
Test name
Test status
Simulation time 204511196 ps
CPU time 1.27 seconds
Started Jul 27 04:53:47 PM PDT 24
Finished Jul 27 04:53:48 PM PDT 24
Peak memory 217164 kb
Host smart-515a5a34-95d5-44fa-9e30-a4bc9b12b39c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58934770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.58934770
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.4023991666
Short name T955
Test name
Test status
Simulation time 17346784 ps
CPU time 0.77 seconds
Started Jul 27 04:53:49 PM PDT 24
Finished Jul 27 04:53:50 PM PDT 24
Peak memory 206652 kb
Host smart-c0ae07c6-2274-443c-81ad-36e92816dc75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023991666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.4023991666
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.1089041318
Short name T354
Test name
Test status
Simulation time 91893728 ps
CPU time 2.6 seconds
Started Jul 27 04:53:49 PM PDT 24
Finished Jul 27 04:53:52 PM PDT 24
Peak memory 233280 kb
Host smart-7d95fdd7-d499-42d9-b836-e8e5a39124ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089041318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.1089041318
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.3536420843
Short name T968
Test name
Test status
Simulation time 50428324 ps
CPU time 0.72 seconds
Started Jul 27 04:53:43 PM PDT 24
Finished Jul 27 04:53:44 PM PDT 24
Peak memory 205944 kb
Host smart-8732e805-12f4-476c-a707-5d3794faf436
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536420843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
3536420843
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.662239650
Short name T898
Test name
Test status
Simulation time 151800719 ps
CPU time 2.76 seconds
Started Jul 27 04:53:58 PM PDT 24
Finished Jul 27 04:54:01 PM PDT 24
Peak memory 225280 kb
Host smart-ea6917e7-330e-488f-a2f0-5b7357e34c4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662239650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.662239650
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.4005616891
Short name T855
Test name
Test status
Simulation time 42552497 ps
CPU time 0.82 seconds
Started Jul 27 04:53:49 PM PDT 24
Finished Jul 27 04:53:50 PM PDT 24
Peak memory 207224 kb
Host smart-4f5e02c2-d3c8-4a4c-80ad-4441a5760295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005616891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.4005616891
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.3693733832
Short name T637
Test name
Test status
Simulation time 23630325 ps
CPU time 0.74 seconds
Started Jul 27 04:53:56 PM PDT 24
Finished Jul 27 04:53:56 PM PDT 24
Peak memory 216620 kb
Host smart-f6248b0f-6d2a-4019-8de9-9140f5679c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693733832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.3693733832
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.3036566338
Short name T725
Test name
Test status
Simulation time 7758949786 ps
CPU time 60.14 seconds
Started Jul 27 04:53:58 PM PDT 24
Finished Jul 27 04:54:58 PM PDT 24
Peak memory 236900 kb
Host smart-9732e3e9-2790-47a9-bbf2-a3e2a492bdda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036566338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.3036566338
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.442320335
Short name T290
Test name
Test status
Simulation time 3057051745 ps
CPU time 43.3 seconds
Started Jul 27 04:53:50 PM PDT 24
Finished Jul 27 04:54:34 PM PDT 24
Peak memory 250012 kb
Host smart-8764c6b6-fe89-40a8-9043-043e29f541bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442320335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idle
.442320335
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.342323005
Short name T437
Test name
Test status
Simulation time 9767727947 ps
CPU time 11.28 seconds
Started Jul 27 04:53:51 PM PDT 24
Finished Jul 27 04:54:02 PM PDT 24
Peak memory 233680 kb
Host smart-7b1edfcd-ec19-43aa-b907-cafa5198ddaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342323005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.342323005
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.4266085013
Short name T622
Test name
Test status
Simulation time 43511646741 ps
CPU time 162.65 seconds
Started Jul 27 04:53:57 PM PDT 24
Finished Jul 27 04:56:39 PM PDT 24
Peak memory 258196 kb
Host smart-62a7c25f-7f1c-4709-b332-2156473e9f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266085013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmd
s.4266085013
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/38.spi_device_intercept.1788769337
Short name T95
Test name
Test status
Simulation time 99127410 ps
CPU time 2.47 seconds
Started Jul 27 04:54:19 PM PDT 24
Finished Jul 27 04:54:22 PM PDT 24
Peak memory 225360 kb
Host smart-ed42bfcb-d517-4940-8d8b-dbab25f10f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788769337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.1788769337
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.222918456
Short name T230
Test name
Test status
Simulation time 32651032945 ps
CPU time 36.7 seconds
Started Jul 27 04:53:52 PM PDT 24
Finished Jul 27 04:54:28 PM PDT 24
Peak memory 225476 kb
Host smart-c0238bf3-89a6-4971-a51c-1b3062206db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222918456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.222918456
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.2099959188
Short name T175
Test name
Test status
Simulation time 30338871 ps
CPU time 2.11 seconds
Started Jul 27 04:53:48 PM PDT 24
Finished Jul 27 04:53:50 PM PDT 24
Peak memory 224604 kb
Host smart-0cd77601-ebc3-4a9e-ba62-5bc72a3350b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099959188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.2099959188
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.2705263566
Short name T244
Test name
Test status
Simulation time 16759129010 ps
CPU time 14.98 seconds
Started Jul 27 04:53:54 PM PDT 24
Finished Jul 27 04:54:10 PM PDT 24
Peak memory 233596 kb
Host smart-2fa1f21b-bc88-46b9-8f1d-17a91c1bb240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705263566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.2705263566
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.737555719
Short name T430
Test name
Test status
Simulation time 874686144 ps
CPU time 6.92 seconds
Started Jul 27 04:53:54 PM PDT 24
Finished Jul 27 04:54:01 PM PDT 24
Peak memory 219544 kb
Host smart-2945c6f5-da12-4dcf-844f-79ba2c85b89f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=737555719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dire
ct.737555719
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.3863383652
Short name T1007
Test name
Test status
Simulation time 61605750614 ps
CPU time 550.09 seconds
Started Jul 27 04:53:51 PM PDT 24
Finished Jul 27 05:03:01 PM PDT 24
Peak memory 274564 kb
Host smart-12c0621c-2861-4c3d-bcf9-faa7412bebbf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863383652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.3863383652
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.322677922
Short name T314
Test name
Test status
Simulation time 1648043809 ps
CPU time 5.37 seconds
Started Jul 27 04:53:50 PM PDT 24
Finished Jul 27 04:53:55 PM PDT 24
Peak memory 218816 kb
Host smart-09fdaaf2-a73b-4100-925b-40dd4fd8158a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322677922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.322677922
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.1867780514
Short name T794
Test name
Test status
Simulation time 233583318 ps
CPU time 2.36 seconds
Started Jul 27 04:53:41 PM PDT 24
Finished Jul 27 04:53:44 PM PDT 24
Peak memory 217168 kb
Host smart-39a3fd18-8dba-4d16-b141-079a6c294904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867780514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.1867780514
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.3696523159
Short name T357
Test name
Test status
Simulation time 286819068 ps
CPU time 3.02 seconds
Started Jul 27 04:53:50 PM PDT 24
Finished Jul 27 04:53:53 PM PDT 24
Peak memory 217064 kb
Host smart-eaa76f3e-64c0-4bb0-bd89-924d6d62b23e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696523159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.3696523159
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.3936534993
Short name T925
Test name
Test status
Simulation time 47907529 ps
CPU time 0.86 seconds
Started Jul 27 04:53:51 PM PDT 24
Finished Jul 27 04:53:52 PM PDT 24
Peak memory 207824 kb
Host smart-9cdd12bc-7b88-4d19-b3e1-12b7b44ae00f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936534993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.3936534993
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.2347042482
Short name T1020
Test name
Test status
Simulation time 8408846781 ps
CPU time 8.67 seconds
Started Jul 27 04:53:53 PM PDT 24
Finished Jul 27 04:54:01 PM PDT 24
Peak memory 233588 kb
Host smart-71e713ff-6d86-46a0-8050-e656862319cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347042482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.2347042482
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.662860098
Short name T384
Test name
Test status
Simulation time 15266030 ps
CPU time 0.76 seconds
Started Jul 27 04:53:50 PM PDT 24
Finished Jul 27 04:53:51 PM PDT 24
Peak memory 205480 kb
Host smart-e2da0c4a-3c91-41e4-a7ba-85960141a790
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662860098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.662860098
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.646982508
Short name T3
Test name
Test status
Simulation time 125751883 ps
CPU time 2.43 seconds
Started Jul 27 04:53:52 PM PDT 24
Finished Jul 27 04:53:55 PM PDT 24
Peak memory 233184 kb
Host smart-26da02cf-2807-4267-9672-88e7595fe180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646982508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.646982508
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.2162805692
Short name T436
Test name
Test status
Simulation time 19523780 ps
CPU time 0.73 seconds
Started Jul 27 04:53:52 PM PDT 24
Finished Jul 27 04:53:53 PM PDT 24
Peak memory 206156 kb
Host smart-350a840a-92fd-4cac-ad92-065394dd63b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162805692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.2162805692
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.4180832319
Short name T967
Test name
Test status
Simulation time 2592656026 ps
CPU time 4 seconds
Started Jul 27 04:53:55 PM PDT 24
Finished Jul 27 04:53:59 PM PDT 24
Peak memory 218452 kb
Host smart-50a310c8-d42c-4287-bf54-bb400bf6b075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180832319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.4180832319
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.3611203442
Short name T288
Test name
Test status
Simulation time 4682997422 ps
CPU time 110.9 seconds
Started Jul 27 04:53:52 PM PDT 24
Finished Jul 27 04:55:43 PM PDT 24
Peak memory 258248 kb
Host smart-462c5297-c05d-40d0-b07d-26abfee07095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611203442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.3611203442
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.3536027778
Short name T435
Test name
Test status
Simulation time 83607091 ps
CPU time 2.8 seconds
Started Jul 27 04:53:57 PM PDT 24
Finished Jul 27 04:54:00 PM PDT 24
Peak memory 233468 kb
Host smart-e8144ce9-c3c1-4c36-a630-cf10ef1a96e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536027778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.3536027778
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.586727284
Short name T923
Test name
Test status
Simulation time 10556207057 ps
CPU time 145.22 seconds
Started Jul 27 04:53:54 PM PDT 24
Finished Jul 27 04:56:19 PM PDT 24
Peak memory 256568 kb
Host smart-b4b350a7-ff97-4ab6-8469-f5dc94e61764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586727284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmds
.586727284
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/39.spi_device_intercept.1680597759
Short name T381
Test name
Test status
Simulation time 9109407677 ps
CPU time 36.87 seconds
Started Jul 27 04:53:52 PM PDT 24
Finished Jul 27 04:54:34 PM PDT 24
Peak memory 225384 kb
Host smart-75337f32-4603-4bf8-aebc-6bcb67bd2e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680597759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.1680597759
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.1021504429
Short name T892
Test name
Test status
Simulation time 126315079 ps
CPU time 2.54 seconds
Started Jul 27 04:53:51 PM PDT 24
Finished Jul 27 04:53:54 PM PDT 24
Peak memory 233128 kb
Host smart-911f18ad-b33f-4742-b1af-51c9d17b4139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021504429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.1021504429
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.204283000
Short name T913
Test name
Test status
Simulation time 46055230348 ps
CPU time 13.74 seconds
Started Jul 27 04:53:53 PM PDT 24
Finished Jul 27 04:54:07 PM PDT 24
Peak memory 233620 kb
Host smart-7e51f3c3-daa6-4623-a669-28e10561d827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204283000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swap
.204283000
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.1956082979
Short name T971
Test name
Test status
Simulation time 12848076470 ps
CPU time 11.75 seconds
Started Jul 27 04:53:53 PM PDT 24
Finished Jul 27 04:54:05 PM PDT 24
Peak memory 233640 kb
Host smart-290198e3-2b17-4dc6-a17a-c118a7c6d9b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956082979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.1956082979
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.3690120980
Short name T767
Test name
Test status
Simulation time 517514514 ps
CPU time 3.97 seconds
Started Jul 27 04:53:53 PM PDT 24
Finished Jul 27 04:53:57 PM PDT 24
Peak memory 223240 kb
Host smart-6489fdb1-56fa-4be3-a849-8430d69eace6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3690120980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.3690120980
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.609223498
Short name T780
Test name
Test status
Simulation time 4276066740 ps
CPU time 35.52 seconds
Started Jul 27 04:53:44 PM PDT 24
Finished Jul 27 04:54:20 PM PDT 24
Peak memory 240804 kb
Host smart-12b3b926-1182-4667-b951-a4e5f7470bda
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609223498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stres
s_all.609223498
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.708135902
Short name T724
Test name
Test status
Simulation time 3023582298 ps
CPU time 8.55 seconds
Started Jul 27 04:53:56 PM PDT 24
Finished Jul 27 04:54:05 PM PDT 24
Peak memory 217248 kb
Host smart-ba6e3283-c0c7-4466-bc7d-197eccd7dd08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708135902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.708135902
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.1783793060
Short name T444
Test name
Test status
Simulation time 6878471979 ps
CPU time 21.78 seconds
Started Jul 27 04:53:57 PM PDT 24
Finished Jul 27 04:54:19 PM PDT 24
Peak memory 217128 kb
Host smart-ebde9dbf-b1d8-408f-b44a-f5a289bd01b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783793060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.1783793060
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.3667073522
Short name T778
Test name
Test status
Simulation time 16664906 ps
CPU time 0.76 seconds
Started Jul 27 04:53:53 PM PDT 24
Finished Jul 27 04:53:54 PM PDT 24
Peak memory 207024 kb
Host smart-3640cf8e-7c99-42a9-b034-02e3c501afa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667073522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.3667073522
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.168927169
Short name T824
Test name
Test status
Simulation time 147481723 ps
CPU time 0.95 seconds
Started Jul 27 04:53:53 PM PDT 24
Finished Jul 27 04:53:54 PM PDT 24
Peak memory 206564 kb
Host smart-f6558111-d425-4348-ade9-1b41767710f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168927169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.168927169
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.4253208180
Short name T938
Test name
Test status
Simulation time 1906049435 ps
CPU time 7.91 seconds
Started Jul 27 04:53:55 PM PDT 24
Finished Jul 27 04:54:03 PM PDT 24
Peak memory 233500 kb
Host smart-c3844b41-6a4b-47ad-8ceb-f413d3e87a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253208180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.4253208180
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.1856241865
Short name T361
Test name
Test status
Simulation time 13956555 ps
CPU time 0.71 seconds
Started Jul 27 04:52:06 PM PDT 24
Finished Jul 27 04:52:07 PM PDT 24
Peak memory 205452 kb
Host smart-12337ada-6bb2-4ace-a8c3-8d2434aac985
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856241865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.1
856241865
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.14315772
Short name T624
Test name
Test status
Simulation time 137545454 ps
CPU time 2.19 seconds
Started Jul 27 04:52:04 PM PDT 24
Finished Jul 27 04:52:06 PM PDT 24
Peak memory 233504 kb
Host smart-abca0e5e-6ced-415d-8930-d604a97e0a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14315772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.14315772
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.2875362387
Short name T396
Test name
Test status
Simulation time 61690012 ps
CPU time 0.84 seconds
Started Jul 27 04:52:03 PM PDT 24
Finished Jul 27 04:52:04 PM PDT 24
Peak memory 207604 kb
Host smart-4daab64b-81c7-4dab-b69a-7e9056313bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875362387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.2875362387
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.975837874
Short name T4
Test name
Test status
Simulation time 3815166632 ps
CPU time 82.2 seconds
Started Jul 27 04:52:03 PM PDT 24
Finished Jul 27 04:53:25 PM PDT 24
Peak memory 258176 kb
Host smart-fcae6861-df49-4e08-ab31-caea82687426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975837874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.975837874
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.2322314983
Short name T628
Test name
Test status
Simulation time 29953179328 ps
CPU time 78.95 seconds
Started Jul 27 04:52:10 PM PDT 24
Finished Jul 27 04:53:29 PM PDT 24
Peak memory 251032 kb
Host smart-57bf9e9e-d737-41e3-9ec7-cfe6ce92da33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322314983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.2322314983
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.3786976974
Short name T219
Test name
Test status
Simulation time 58125727576 ps
CPU time 304.84 seconds
Started Jul 27 04:52:01 PM PDT 24
Finished Jul 27 04:57:06 PM PDT 24
Peak memory 266056 kb
Host smart-0500efc8-ee30-495a-a948-165ca66f8c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786976974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.3786976974
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.3852654672
Short name T308
Test name
Test status
Simulation time 2730608663 ps
CPU time 45.14 seconds
Started Jul 27 04:52:03 PM PDT 24
Finished Jul 27 04:52:48 PM PDT 24
Peak memory 233572 kb
Host smart-7dc3648a-e4bc-4795-a4aa-5e75281851ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852654672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.3852654672
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.2635586843
Short name T482
Test name
Test status
Simulation time 23124258290 ps
CPU time 45.46 seconds
Started Jul 27 04:51:59 PM PDT 24
Finished Jul 27 04:52:45 PM PDT 24
Peak memory 237568 kb
Host smart-c1463069-0418-481c-a327-9c2edef102fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635586843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds
.2635586843
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/4.spi_device_intercept.1022409955
Short name T837
Test name
Test status
Simulation time 214563043 ps
CPU time 3.07 seconds
Started Jul 27 04:52:05 PM PDT 24
Finished Jul 27 04:52:08 PM PDT 24
Peak memory 224996 kb
Host smart-0898166a-cbfa-44f5-a8d4-e81b4bee9282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022409955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.1022409955
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.2937519522
Short name T575
Test name
Test status
Simulation time 7746118049 ps
CPU time 60.76 seconds
Started Jul 27 04:52:11 PM PDT 24
Finished Jul 27 04:53:12 PM PDT 24
Peak memory 233740 kb
Host smart-11947f25-cd9c-4ea1-aec9-15ce74685fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937519522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.2937519522
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.182693488
Short name T558
Test name
Test status
Simulation time 16332917 ps
CPU time 1.07 seconds
Started Jul 27 04:52:07 PM PDT 24
Finished Jul 27 04:52:09 PM PDT 24
Peak memory 218556 kb
Host smart-fb21b86c-f875-440b-9099-746d955227ea
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182693488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.spi_device_mem_parity.182693488
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.971387401
Short name T176
Test name
Test status
Simulation time 115616432 ps
CPU time 2.34 seconds
Started Jul 27 04:52:09 PM PDT 24
Finished Jul 27 04:52:11 PM PDT 24
Peak memory 225356 kb
Host smart-63eb3db8-4cf3-49a3-bfd6-23af89d6f5e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971387401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap.
971387401
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.3657657158
Short name T62
Test name
Test status
Simulation time 1340446258 ps
CPU time 3.19 seconds
Started Jul 27 04:52:02 PM PDT 24
Finished Jul 27 04:52:05 PM PDT 24
Peak memory 233552 kb
Host smart-8345795a-e719-48a6-b5e8-efc3c28b6bcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657657158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.3657657158
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.1539801563
Short name T368
Test name
Test status
Simulation time 1689549947 ps
CPU time 7.86 seconds
Started Jul 27 04:52:08 PM PDT 24
Finished Jul 27 04:52:16 PM PDT 24
Peak memory 223244 kb
Host smart-8fbb1a3f-e763-4bb5-8d41-903dc239650a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1539801563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.1539801563
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.318781313
Short name T76
Test name
Test status
Simulation time 87532285 ps
CPU time 1.19 seconds
Started Jul 27 04:52:07 PM PDT 24
Finished Jul 27 04:52:09 PM PDT 24
Peak memory 236300 kb
Host smart-8bfb79df-5789-4e43-9aad-65b477d8e2a0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318781313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.318781313
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.3541285841
Short name T669
Test name
Test status
Simulation time 32594928581 ps
CPU time 43.56 seconds
Started Jul 27 04:52:07 PM PDT 24
Finished Jul 27 04:52:55 PM PDT 24
Peak memory 217488 kb
Host smart-9f2c8652-af90-489b-af23-4f22820ca5fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541285841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.3541285841
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.4184168179
Short name T872
Test name
Test status
Simulation time 636811505 ps
CPU time 2.1 seconds
Started Jul 27 04:52:04 PM PDT 24
Finished Jul 27 04:52:06 PM PDT 24
Peak memory 217020 kb
Host smart-b8bcdc6f-fd9b-4c68-9c4e-ee21edc556d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184168179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.4184168179
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.1514999409
Short name T851
Test name
Test status
Simulation time 133868014 ps
CPU time 2.04 seconds
Started Jul 27 04:52:03 PM PDT 24
Finished Jul 27 04:52:05 PM PDT 24
Peak memory 216972 kb
Host smart-6df950ad-99ce-4b9e-b7bf-4bd6e269f6b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514999409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.1514999409
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.2121185843
Short name T31
Test name
Test status
Simulation time 73278161 ps
CPU time 0.92 seconds
Started Jul 27 04:52:10 PM PDT 24
Finished Jul 27 04:52:11 PM PDT 24
Peak memory 206712 kb
Host smart-045d8d0c-0877-4a66-a221-f7691d3d1476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121185843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.2121185843
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.1208390163
Short name T539
Test name
Test status
Simulation time 4442558631 ps
CPU time 16.87 seconds
Started Jul 27 04:52:08 PM PDT 24
Finished Jul 27 04:52:25 PM PDT 24
Peak memory 225480 kb
Host smart-0c9fbe38-6fe0-4974-bf90-baa30161ca4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208390163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.1208390163
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.1026874481
Short name T449
Test name
Test status
Simulation time 34506246 ps
CPU time 0.7 seconds
Started Jul 27 04:53:50 PM PDT 24
Finished Jul 27 04:53:51 PM PDT 24
Peak memory 206076 kb
Host smart-d870cadb-efda-4341-8f7e-6a7d25ef9065
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026874481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
1026874481
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.3111624524
Short name T463
Test name
Test status
Simulation time 769812406 ps
CPU time 2.35 seconds
Started Jul 27 04:53:55 PM PDT 24
Finished Jul 27 04:53:58 PM PDT 24
Peak memory 225328 kb
Host smart-ecf86768-aa33-4afd-a7c8-17424eaed019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111624524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.3111624524
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.2174089296
Short name T392
Test name
Test status
Simulation time 72201722 ps
CPU time 0.8 seconds
Started Jul 27 04:53:57 PM PDT 24
Finished Jul 27 04:53:58 PM PDT 24
Peak memory 207212 kb
Host smart-21f2f75d-e4c9-4f48-90f9-79a2cc57f796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174089296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.2174089296
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.3006012012
Short name T299
Test name
Test status
Simulation time 53140854911 ps
CPU time 187.71 seconds
Started Jul 27 04:53:52 PM PDT 24
Finished Jul 27 04:57:00 PM PDT 24
Peak memory 250048 kb
Host smart-f73797fb-4bb4-4479-aa5e-33a98508a030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006012012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.3006012012
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.322771211
Short name T355
Test name
Test status
Simulation time 1728783837 ps
CPU time 25.11 seconds
Started Jul 27 04:53:48 PM PDT 24
Finished Jul 27 04:54:13 PM PDT 24
Peak memory 233600 kb
Host smart-5d85daa8-f0b7-49ee-aa03-285e348b8584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322771211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.322771211
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.3353538020
Short name T771
Test name
Test status
Simulation time 137993533054 ps
CPU time 104.64 seconds
Started Jul 27 04:53:50 PM PDT 24
Finished Jul 27 04:55:35 PM PDT 24
Peak memory 248540 kb
Host smart-430f144b-5caa-45ad-95b1-132f4523849a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353538020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.3353538020
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.2558536684
Short name T501
Test name
Test status
Simulation time 1864563617 ps
CPU time 11.95 seconds
Started Jul 27 04:54:20 PM PDT 24
Finished Jul 27 04:54:32 PM PDT 24
Peak memory 249884 kb
Host smart-b9413eb2-6539-4251-821e-064974cb4412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558536684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.2558536684
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.1406074871
Short name T266
Test name
Test status
Simulation time 1266972087 ps
CPU time 15.93 seconds
Started Jul 27 04:53:54 PM PDT 24
Finished Jul 27 04:54:10 PM PDT 24
Peak memory 225256 kb
Host smart-fc2e122e-bbc8-4d86-9ff1-e6137c11a1bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406074871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmd
s.1406074871
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/40.spi_device_intercept.803806289
Short name T881
Test name
Test status
Simulation time 3878128190 ps
CPU time 10.44 seconds
Started Jul 27 04:53:53 PM PDT 24
Finished Jul 27 04:54:04 PM PDT 24
Peak memory 225452 kb
Host smart-170b0384-34a3-4288-be18-c54120bdbe16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803806289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.803806289
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.3237080470
Short name T515
Test name
Test status
Simulation time 298536624 ps
CPU time 6.84 seconds
Started Jul 27 04:53:49 PM PDT 24
Finished Jul 27 04:53:56 PM PDT 24
Peak memory 233580 kb
Host smart-0525bcbc-7aeb-4dec-b316-48dce5213b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237080470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.3237080470
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.107734396
Short name T604
Test name
Test status
Simulation time 6259935553 ps
CPU time 11.37 seconds
Started Jul 27 04:53:57 PM PDT 24
Finished Jul 27 04:54:09 PM PDT 24
Peak memory 225420 kb
Host smart-a097283a-6eb9-45c2-902b-57c4d56dbd0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107734396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swap
.107734396
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.1050652874
Short name T251
Test name
Test status
Simulation time 12147797897 ps
CPU time 12.49 seconds
Started Jul 27 04:53:56 PM PDT 24
Finished Jul 27 04:54:13 PM PDT 24
Peak memory 225480 kb
Host smart-eedc677b-db28-465d-8e69-7fac628bde36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050652874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.1050652874
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.3412386657
Short name T629
Test name
Test status
Simulation time 995861730 ps
CPU time 4.27 seconds
Started Jul 27 04:53:54 PM PDT 24
Finished Jul 27 04:53:58 PM PDT 24
Peak memory 219784 kb
Host smart-38618065-cc76-4023-b4ee-8260931e9fc4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3412386657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.3412386657
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.1906128052
Short name T660
Test name
Test status
Simulation time 77872880254 ps
CPU time 190.21 seconds
Started Jul 27 04:53:50 PM PDT 24
Finished Jul 27 04:57:00 PM PDT 24
Peak memory 253704 kb
Host smart-9c882356-b1c1-4cfb-a7f4-913af5aa51ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906128052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.1906128052
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.721727969
Short name T803
Test name
Test status
Simulation time 1627033933 ps
CPU time 22.17 seconds
Started Jul 27 04:53:54 PM PDT 24
Finished Jul 27 04:54:16 PM PDT 24
Peak memory 217368 kb
Host smart-5f949019-d25a-49b8-855b-a9974995e2ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721727969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.721727969
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.2308925356
Short name T640
Test name
Test status
Simulation time 9236933186 ps
CPU time 14.81 seconds
Started Jul 27 04:53:54 PM PDT 24
Finished Jul 27 04:54:09 PM PDT 24
Peak memory 217156 kb
Host smart-5bd0552b-5361-413b-b4c0-df3a92ed18d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308925356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.2308925356
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.4114112502
Short name T647
Test name
Test status
Simulation time 44966913 ps
CPU time 0.66 seconds
Started Jul 27 04:53:50 PM PDT 24
Finished Jul 27 04:53:51 PM PDT 24
Peak memory 206248 kb
Host smart-7b594986-ed6e-4ca8-883b-5004fe6fc7e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114112502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.4114112502
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.4075722410
Short name T475
Test name
Test status
Simulation time 73223332 ps
CPU time 0.96 seconds
Started Jul 27 04:53:52 PM PDT 24
Finished Jul 27 04:53:53 PM PDT 24
Peak memory 207160 kb
Host smart-e176902b-a070-4750-9117-b494028ad175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075722410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.4075722410
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.2267349640
Short name T576
Test name
Test status
Simulation time 601890495 ps
CPU time 5.43 seconds
Started Jul 27 04:53:48 PM PDT 24
Finished Jul 27 04:53:54 PM PDT 24
Peak memory 233512 kb
Host smart-4aa2fd5e-3b0f-431c-9780-321537780ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267349640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.2267349640
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.1532683702
Short name T706
Test name
Test status
Simulation time 49178462 ps
CPU time 0.69 seconds
Started Jul 27 04:53:50 PM PDT 24
Finished Jul 27 04:53:51 PM PDT 24
Peak memory 206272 kb
Host smart-3be1d67b-7225-4bdb-b5b7-89266ed971f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532683702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
1532683702
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.298945069
Short name T583
Test name
Test status
Simulation time 496290652 ps
CPU time 5.46 seconds
Started Jul 27 04:53:54 PM PDT 24
Finished Jul 27 04:54:00 PM PDT 24
Peak memory 225388 kb
Host smart-a168037d-b284-496f-a2bf-7852aa461555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298945069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.298945069
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.3931679296
Short name T700
Test name
Test status
Simulation time 36771682 ps
CPU time 0.78 seconds
Started Jul 27 04:53:51 PM PDT 24
Finished Jul 27 04:53:51 PM PDT 24
Peak memory 207104 kb
Host smart-9c12842e-5fbe-4318-a509-2f687c99795d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931679296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.3931679296
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.2912074139
Short name T48
Test name
Test status
Simulation time 9622119285 ps
CPU time 61.06 seconds
Started Jul 27 04:53:56 PM PDT 24
Finished Jul 27 04:54:57 PM PDT 24
Peak memory 257264 kb
Host smart-f1bad203-07c8-47e2-bb40-ba7a448df9ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912074139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.2912074139
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.40088001
Short name T439
Test name
Test status
Simulation time 3520917945 ps
CPU time 36.22 seconds
Started Jul 27 04:53:48 PM PDT 24
Finished Jul 27 04:54:24 PM PDT 24
Peak memory 251900 kb
Host smart-696bfcfe-6a55-4221-bba2-399f5edff8b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40088001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.40088001
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.3158224934
Short name T304
Test name
Test status
Simulation time 7758283369 ps
CPU time 100.8 seconds
Started Jul 27 04:54:04 PM PDT 24
Finished Jul 27 04:55:45 PM PDT 24
Peak memory 266408 kb
Host smart-9e4b1fd7-3412-46ff-9819-8d4e6f6a7553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158224934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.3158224934
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.3935978399
Short name T548
Test name
Test status
Simulation time 4065452719 ps
CPU time 12.13 seconds
Started Jul 27 04:53:50 PM PDT 24
Finished Jul 27 04:54:02 PM PDT 24
Peak memory 225480 kb
Host smart-c8de6fb0-2525-429b-afe8-d9dff4ffecf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935978399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.3935978399
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_intercept.3010372886
Short name T466
Test name
Test status
Simulation time 890781680 ps
CPU time 9.14 seconds
Started Jul 27 04:53:55 PM PDT 24
Finished Jul 27 04:54:04 PM PDT 24
Peak memory 225348 kb
Host smart-1e1d9f38-6984-4dcb-a42a-317f470cff0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010372886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.3010372886
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.3710024839
Short name T277
Test name
Test status
Simulation time 1039447088 ps
CPU time 14.37 seconds
Started Jul 27 04:53:49 PM PDT 24
Finished Jul 27 04:54:03 PM PDT 24
Peak memory 241644 kb
Host smart-ce9c7dc1-8336-458a-892b-7e868e8e1606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710024839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.3710024839
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.1016977959
Short name T975
Test name
Test status
Simulation time 18330905362 ps
CPU time 26.53 seconds
Started Jul 27 04:53:44 PM PDT 24
Finished Jul 27 04:54:11 PM PDT 24
Peak memory 233540 kb
Host smart-15d898d8-d6dc-4e62-ad40-64079e712b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016977959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.1016977959
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.174099769
Short name T841
Test name
Test status
Simulation time 1017588414 ps
CPU time 4.39 seconds
Started Jul 27 04:53:50 PM PDT 24
Finished Jul 27 04:53:55 PM PDT 24
Peak memory 225404 kb
Host smart-b17d360e-0f03-4ec6-9032-f75c25909517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174099769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.174099769
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.3169500368
Short name T484
Test name
Test status
Simulation time 2316898386 ps
CPU time 7.54 seconds
Started Jul 27 04:53:52 PM PDT 24
Finished Jul 27 04:53:59 PM PDT 24
Peak memory 223856 kb
Host smart-4831a9c0-4e56-4308-98d9-5819dbc91856
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3169500368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.3169500368
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.629131707
Short name T162
Test name
Test status
Simulation time 76423794 ps
CPU time 1.28 seconds
Started Jul 27 04:54:05 PM PDT 24
Finished Jul 27 04:54:06 PM PDT 24
Peak memory 207836 kb
Host smart-006211d1-4b8a-49ab-afc8-065387a6bde1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629131707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stres
s_all.629131707
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.1037872221
Short name T54
Test name
Test status
Simulation time 547038838 ps
CPU time 9.2 seconds
Started Jul 27 04:53:50 PM PDT 24
Finished Jul 27 04:53:59 PM PDT 24
Peak memory 216480 kb
Host smart-e0358059-9599-41f0-80aa-a850f083e051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037872221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.1037872221
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.4113271123
Short name T451
Test name
Test status
Simulation time 19869101679 ps
CPU time 7.56 seconds
Started Jul 27 04:53:49 PM PDT 24
Finished Jul 27 04:53:57 PM PDT 24
Peak memory 218560 kb
Host smart-b95b06b0-2e5f-4b41-b821-f00043bd67e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113271123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.4113271123
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.4249352102
Short name T743
Test name
Test status
Simulation time 79989045 ps
CPU time 1.53 seconds
Started Jul 27 04:53:56 PM PDT 24
Finished Jul 27 04:53:58 PM PDT 24
Peak memory 208936 kb
Host smart-597d533a-2c4c-48a7-b65d-458ced212b96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249352102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.4249352102
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.1435246592
Short name T924
Test name
Test status
Simulation time 142371659 ps
CPU time 0.85 seconds
Started Jul 27 04:53:57 PM PDT 24
Finished Jul 27 04:53:58 PM PDT 24
Peak memory 206700 kb
Host smart-35c5a809-7383-4adf-962c-91bc8f53e3a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435246592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.1435246592
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.1186569303
Short name T535
Test name
Test status
Simulation time 700108130 ps
CPU time 2.25 seconds
Started Jul 27 04:53:47 PM PDT 24
Finished Jul 27 04:53:49 PM PDT 24
Peak memory 224508 kb
Host smart-3d856098-0aa9-45a5-a0f6-bf0de7059e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186569303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.1186569303
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.1867877102
Short name T806
Test name
Test status
Simulation time 35873457 ps
CPU time 0.73 seconds
Started Jul 27 04:54:03 PM PDT 24
Finished Jul 27 04:54:04 PM PDT 24
Peak memory 205940 kb
Host smart-f5e98b28-698d-4549-b9a9-a570de30d28a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867877102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
1867877102
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.3408781007
Short name T247
Test name
Test status
Simulation time 356611729 ps
CPU time 3.35 seconds
Started Jul 27 04:54:17 PM PDT 24
Finished Jul 27 04:54:20 PM PDT 24
Peak memory 225340 kb
Host smart-3599dbcc-3247-4029-bcaf-f3aa9eb89e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408781007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.3408781007
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.3962471901
Short name T993
Test name
Test status
Simulation time 52792168 ps
CPU time 0.73 seconds
Started Jul 27 04:53:55 PM PDT 24
Finished Jul 27 04:53:55 PM PDT 24
Peak memory 207460 kb
Host smart-b3e43198-1f80-433c-9de2-cc520168bf5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962471901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.3962471901
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.99807809
Short name T454
Test name
Test status
Simulation time 702919537 ps
CPU time 14.19 seconds
Started Jul 27 04:53:52 PM PDT 24
Finished Jul 27 04:54:07 PM PDT 24
Peak memory 238984 kb
Host smart-ac6bf83b-65bf-412d-b1ef-05ef31379c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99807809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.99807809
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.1007850615
Short name T1021
Test name
Test status
Simulation time 6029583845 ps
CPU time 30.81 seconds
Started Jul 27 04:53:55 PM PDT 24
Finished Jul 27 04:54:26 PM PDT 24
Peak memory 250092 kb
Host smart-95176d98-98b5-49f0-9c88-b06601b3cb40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007850615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.1007850615
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.2950294593
Short name T195
Test name
Test status
Simulation time 5239938570 ps
CPU time 56.78 seconds
Started Jul 27 04:54:04 PM PDT 24
Finished Jul 27 04:55:01 PM PDT 24
Peak memory 257204 kb
Host smart-425a3031-cef9-44c6-8447-2508900e2ae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950294593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.2950294593
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.4165863545
Short name T530
Test name
Test status
Simulation time 199996197 ps
CPU time 5.44 seconds
Started Jul 27 04:54:05 PM PDT 24
Finished Jul 27 04:54:10 PM PDT 24
Peak memory 241780 kb
Host smart-134408d2-c708-42e3-83e3-26523508f7e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165863545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.4165863545
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.3303558759
Short name T930
Test name
Test status
Simulation time 27191190558 ps
CPU time 58.13 seconds
Started Jul 27 04:54:17 PM PDT 24
Finished Jul 27 04:55:15 PM PDT 24
Peak memory 225348 kb
Host smart-2d8db12f-5a5e-413f-aebe-2464b0386a40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303558759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmd
s.3303558759
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_intercept.2165795786
Short name T550
Test name
Test status
Simulation time 1526365818 ps
CPU time 3.77 seconds
Started Jul 27 04:53:56 PM PDT 24
Finished Jul 27 04:54:00 PM PDT 24
Peak memory 225336 kb
Host smart-59b09ea2-7696-48db-b8af-0676434d4203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165795786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.2165795786
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.3947541485
Short name T789
Test name
Test status
Simulation time 1141797447 ps
CPU time 19.84 seconds
Started Jul 27 04:53:51 PM PDT 24
Finished Jul 27 04:54:11 PM PDT 24
Peak memory 233524 kb
Host smart-9c5766b8-e154-4933-a12c-ceb9ed3b9a56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947541485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.3947541485
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.3822097941
Short name T726
Test name
Test status
Simulation time 1893658833 ps
CPU time 3.47 seconds
Started Jul 27 04:53:44 PM PDT 24
Finished Jul 27 04:53:48 PM PDT 24
Peak memory 233572 kb
Host smart-c87a2a61-8b0e-4d52-aeee-52530be4b25d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822097941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.3822097941
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.1112736358
Short name T932
Test name
Test status
Simulation time 5890573067 ps
CPU time 6.02 seconds
Started Jul 27 04:53:51 PM PDT 24
Finished Jul 27 04:53:57 PM PDT 24
Peak memory 233520 kb
Host smart-b9be3e83-de54-4fa4-8681-28546b959e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112736358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.1112736358
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.2047469749
Short name T385
Test name
Test status
Simulation time 3517619591 ps
CPU time 6.77 seconds
Started Jul 27 04:53:54 PM PDT 24
Finished Jul 27 04:54:01 PM PDT 24
Peak memory 221464 kb
Host smart-6c0a5393-e041-465d-a4c6-a60417ba5aef
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2047469749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.2047469749
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.2234361838
Short name T760
Test name
Test status
Simulation time 51093518870 ps
CPU time 142.23 seconds
Started Jul 27 04:54:18 PM PDT 24
Finished Jul 27 04:56:40 PM PDT 24
Peak memory 249816 kb
Host smart-6b805895-754d-484a-a8ec-bda196f4ac9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234361838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.2234361838
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.3047885876
Short name T896
Test name
Test status
Simulation time 6680718896 ps
CPU time 7.8 seconds
Started Jul 27 04:53:49 PM PDT 24
Finished Jul 27 04:53:57 PM PDT 24
Peak memory 217044 kb
Host smart-b8c9f8b4-2d69-47a6-8973-2c8bd6421f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047885876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.3047885876
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.3667114740
Short name T507
Test name
Test status
Simulation time 209741439 ps
CPU time 1.6 seconds
Started Jul 27 04:53:53 PM PDT 24
Finished Jul 27 04:53:55 PM PDT 24
Peak memory 208592 kb
Host smart-576f5bfb-efe7-49d3-b650-c3c80834bbad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667114740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.3667114740
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.1189364357
Short name T324
Test name
Test status
Simulation time 142220694 ps
CPU time 2.29 seconds
Started Jul 27 04:54:13 PM PDT 24
Finished Jul 27 04:54:15 PM PDT 24
Peak memory 217028 kb
Host smart-08544fe3-e0f3-483f-b699-600ae3749697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189364357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.1189364357
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.3675686112
Short name T411
Test name
Test status
Simulation time 418531167 ps
CPU time 0.83 seconds
Started Jul 27 04:53:47 PM PDT 24
Finished Jul 27 04:53:48 PM PDT 24
Peak memory 206620 kb
Host smart-b2568ee3-f05c-42a9-a9b4-ec09653a9463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675686112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.3675686112
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.2603236468
Short name T237
Test name
Test status
Simulation time 21661225839 ps
CPU time 18.09 seconds
Started Jul 27 04:53:58 PM PDT 24
Finished Jul 27 04:54:16 PM PDT 24
Peak memory 225436 kb
Host smart-d7060b4d-6533-4c35-b2bb-dcab3c290148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603236468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.2603236468
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.1065897909
Short name T639
Test name
Test status
Simulation time 15769543 ps
CPU time 0.74 seconds
Started Jul 27 04:53:55 PM PDT 24
Finished Jul 27 04:53:56 PM PDT 24
Peak memory 205364 kb
Host smart-4589e249-87d6-4b69-84f6-6b861938d029
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065897909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
1065897909
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.3252497931
Short name T692
Test name
Test status
Simulation time 198033255 ps
CPU time 2.47 seconds
Started Jul 27 04:54:05 PM PDT 24
Finished Jul 27 04:54:07 PM PDT 24
Peak memory 225288 kb
Host smart-0a0c7f43-629e-4fa8-8e70-47ce6a1dcf1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252497931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.3252497931
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.3706253165
Short name T69
Test name
Test status
Simulation time 16699270 ps
CPU time 0.76 seconds
Started Jul 27 04:53:59 PM PDT 24
Finished Jul 27 04:54:00 PM PDT 24
Peak memory 207108 kb
Host smart-aa8e379c-75d8-4466-a04b-4e5111505033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706253165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.3706253165
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.3575028850
Short name T750
Test name
Test status
Simulation time 24835803439 ps
CPU time 183.07 seconds
Started Jul 27 04:53:52 PM PDT 24
Finished Jul 27 04:56:55 PM PDT 24
Peak memory 255552 kb
Host smart-41ebdf84-f970-4d06-8490-bb8e100dba67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575028850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.3575028850
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.2498931265
Short name T220
Test name
Test status
Simulation time 2392538505 ps
CPU time 47.56 seconds
Started Jul 27 04:54:07 PM PDT 24
Finished Jul 27 04:54:55 PM PDT 24
Peak memory 256224 kb
Host smart-775f85ac-fade-4a13-b843-fd9c8da47044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498931265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.2498931265
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.4253595553
Short name T111
Test name
Test status
Simulation time 20446154364 ps
CPU time 161.89 seconds
Started Jul 27 04:54:05 PM PDT 24
Finished Jul 27 04:56:47 PM PDT 24
Peak memory 249788 kb
Host smart-617eb4d8-fa6c-49e2-abdd-39e6e0f6230b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253595553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.4253595553
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.3894139345
Short name T310
Test name
Test status
Simulation time 380784295 ps
CPU time 7.76 seconds
Started Jul 27 04:54:01 PM PDT 24
Finished Jul 27 04:54:09 PM PDT 24
Peak memory 233556 kb
Host smart-b132bdc4-a79f-4ccf-804a-f329704b5624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894139345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.3894139345
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.1134937752
Short name T1028
Test name
Test status
Simulation time 30679330748 ps
CPU time 125.46 seconds
Started Jul 27 04:54:05 PM PDT 24
Finished Jul 27 04:56:11 PM PDT 24
Peak memory 250812 kb
Host smart-e1738472-9266-463d-a83d-6725acf978e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134937752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmd
s.1134937752
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_intercept.3076762896
Short name T754
Test name
Test status
Simulation time 1338854394 ps
CPU time 11.38 seconds
Started Jul 27 04:53:57 PM PDT 24
Finished Jul 27 04:54:08 PM PDT 24
Peak memory 225336 kb
Host smart-4ee7e240-8f4f-4dca-908b-076924af087a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076762896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.3076762896
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.3253326344
Short name T553
Test name
Test status
Simulation time 7306824417 ps
CPU time 37.34 seconds
Started Jul 27 04:54:00 PM PDT 24
Finished Jul 27 04:54:37 PM PDT 24
Peak memory 233608 kb
Host smart-6250da04-fb21-4a3b-9286-1587ec2536d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253326344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.3253326344
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.3457376494
Short name T994
Test name
Test status
Simulation time 4947548424 ps
CPU time 15.33 seconds
Started Jul 27 04:54:00 PM PDT 24
Finished Jul 27 04:54:15 PM PDT 24
Peak memory 233568 kb
Host smart-9784de5f-ed28-4c25-a960-47f1531cb4fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457376494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.3457376494
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.868583479
Short name T28
Test name
Test status
Simulation time 521480501 ps
CPU time 2.72 seconds
Started Jul 27 04:53:58 PM PDT 24
Finished Jul 27 04:54:01 PM PDT 24
Peak memory 225436 kb
Host smart-d62407bc-dbce-4013-8a59-d7e71b49ec01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868583479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.868583479
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.866710354
Short name T910
Test name
Test status
Simulation time 4960897402 ps
CPU time 8.5 seconds
Started Jul 27 04:53:57 PM PDT 24
Finished Jul 27 04:54:10 PM PDT 24
Peak memory 220148 kb
Host smart-c2c816bc-85d2-4713-80cf-7db756693e31
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=866710354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dire
ct.866710354
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.345652313
Short name T990
Test name
Test status
Simulation time 66042273 ps
CPU time 1.12 seconds
Started Jul 27 04:54:09 PM PDT 24
Finished Jul 27 04:54:10 PM PDT 24
Peak memory 208304 kb
Host smart-4cd4bebe-d3cb-4a25-a430-e2eb1e1c7d0f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345652313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stres
s_all.345652313
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.2643017388
Short name T618
Test name
Test status
Simulation time 502562472 ps
CPU time 4.56 seconds
Started Jul 27 04:53:56 PM PDT 24
Finished Jul 27 04:54:00 PM PDT 24
Peak memory 217228 kb
Host smart-f0ec9ed3-ccd7-4000-8ed4-188fc1e6db09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643017388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.2643017388
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.404890652
Short name T91
Test name
Test status
Simulation time 2783149537 ps
CPU time 5.46 seconds
Started Jul 27 04:53:57 PM PDT 24
Finished Jul 27 04:54:03 PM PDT 24
Peak memory 217252 kb
Host smart-535c2936-a953-489f-862c-34638feb8a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404890652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.404890652
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.2169066894
Short name T462
Test name
Test status
Simulation time 35776721 ps
CPU time 0.71 seconds
Started Jul 27 04:53:58 PM PDT 24
Finished Jul 27 04:53:59 PM PDT 24
Peak memory 206660 kb
Host smart-d9a3f64f-0209-41ae-9ec5-5144f731197a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169066894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.2169066894
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.3880962384
Short name T375
Test name
Test status
Simulation time 452983382 ps
CPU time 0.84 seconds
Started Jul 27 04:54:00 PM PDT 24
Finished Jul 27 04:54:01 PM PDT 24
Peak memory 206636 kb
Host smart-9b267836-c53a-4d23-a9eb-0c17ea66e99c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880962384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.3880962384
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.4286768805
Short name T698
Test name
Test status
Simulation time 315853177 ps
CPU time 2.25 seconds
Started Jul 27 04:53:55 PM PDT 24
Finished Jul 27 04:53:57 PM PDT 24
Peak memory 224952 kb
Host smart-e1d0e3d8-e9a1-4241-9535-eaaa70e8859b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286768805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.4286768805
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.3700893116
Short name T348
Test name
Test status
Simulation time 15545599 ps
CPU time 0.71 seconds
Started Jul 27 04:54:09 PM PDT 24
Finished Jul 27 04:54:10 PM PDT 24
Peak memory 206052 kb
Host smart-66015dff-fb84-4b5a-8ab7-abecd542d628
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700893116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
3700893116
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.1213870769
Short name T412
Test name
Test status
Simulation time 6633902459 ps
CPU time 11.42 seconds
Started Jul 27 04:54:16 PM PDT 24
Finished Jul 27 04:54:28 PM PDT 24
Peak memory 233720 kb
Host smart-42c972f3-a4d6-460e-89fc-f3b25e83deac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213870769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.1213870769
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.3962139898
Short name T633
Test name
Test status
Simulation time 14450880 ps
CPU time 0.77 seconds
Started Jul 27 04:54:17 PM PDT 24
Finished Jul 27 04:54:18 PM PDT 24
Peak memory 207448 kb
Host smart-9d349686-0bb3-4914-942d-b5d50610c5e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962139898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.3962139898
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.1938187299
Short name T958
Test name
Test status
Simulation time 6851534385 ps
CPU time 58.78 seconds
Started Jul 27 04:53:56 PM PDT 24
Finished Jul 27 04:54:55 PM PDT 24
Peak memory 241864 kb
Host smart-80cb290e-8641-4760-b321-74dfae2800f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938187299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.1938187299
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.648720607
Short name T987
Test name
Test status
Simulation time 5466091102 ps
CPU time 57.89 seconds
Started Jul 27 04:54:15 PM PDT 24
Finished Jul 27 04:55:13 PM PDT 24
Peak memory 250024 kb
Host smart-4f0181df-f467-413e-9563-4ba506ec36d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648720607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idle
.648720607
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.2515230130
Short name T718
Test name
Test status
Simulation time 180221889 ps
CPU time 5.74 seconds
Started Jul 27 04:53:54 PM PDT 24
Finished Jul 27 04:54:00 PM PDT 24
Peak memory 238676 kb
Host smart-e9182e3a-0b34-4861-a4ec-ef8dc19de9c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515230130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.2515230130
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.3622066863
Short name T817
Test name
Test status
Simulation time 1604312092 ps
CPU time 36.09 seconds
Started Jul 27 04:54:00 PM PDT 24
Finished Jul 27 04:54:36 PM PDT 24
Peak memory 253088 kb
Host smart-dd5cecfc-24e1-44c4-bd7f-d3584830e180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622066863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmd
s.3622066863
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/44.spi_device_intercept.2056629415
Short name T556
Test name
Test status
Simulation time 185651118 ps
CPU time 5.38 seconds
Started Jul 27 04:53:57 PM PDT 24
Finished Jul 27 04:54:02 PM PDT 24
Peak memory 233600 kb
Host smart-c7c96d6d-736a-4aa2-a233-8f03c7a6cffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056629415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.2056629415
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.1071846542
Short name T956
Test name
Test status
Simulation time 12947510719 ps
CPU time 26.93 seconds
Started Jul 27 04:53:56 PM PDT 24
Finished Jul 27 04:54:23 PM PDT 24
Peak memory 233640 kb
Host smart-95282635-7524-4610-a7ea-6da388ddcddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071846542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.1071846542
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.1693422
Short name T863
Test name
Test status
Simulation time 23678086787 ps
CPU time 11.51 seconds
Started Jul 27 04:53:59 PM PDT 24
Finished Jul 27 04:54:11 PM PDT 24
Peak memory 233568 kb
Host smart-193ade4e-895d-483f-a120-4cdc6c6a0e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swap.1693422
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.3280536018
Short name T419
Test name
Test status
Simulation time 728265264 ps
CPU time 7.08 seconds
Started Jul 27 04:53:59 PM PDT 24
Finished Jul 27 04:54:06 PM PDT 24
Peak memory 241776 kb
Host smart-77afc788-392b-481a-8283-88ffd6db3d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280536018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.3280536018
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.3482665051
Short name T5
Test name
Test status
Simulation time 2006843174 ps
CPU time 7.66 seconds
Started Jul 27 04:53:58 PM PDT 24
Finished Jul 27 04:54:06 PM PDT 24
Peak memory 222880 kb
Host smart-07c66668-0862-49ba-aca1-c3973c25a708
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3482665051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.3482665051
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.1053278939
Short name T168
Test name
Test status
Simulation time 51453149297 ps
CPU time 154.61 seconds
Started Jul 27 04:54:12 PM PDT 24
Finished Jul 27 04:56:47 PM PDT 24
Peak memory 254592 kb
Host smart-66b50591-7eff-4040-8e83-efd09ca6a1cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053278939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.1053278939
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.3147673795
Short name T571
Test name
Test status
Simulation time 3346632558 ps
CPU time 10.18 seconds
Started Jul 27 04:54:04 PM PDT 24
Finished Jul 27 04:54:14 PM PDT 24
Peak memory 217296 kb
Host smart-a42b0a3e-96c5-47e4-98ec-41a7f5571ec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147673795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.3147673795
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.3893417918
Short name T379
Test name
Test status
Simulation time 28720046588 ps
CPU time 11.43 seconds
Started Jul 27 04:54:16 PM PDT 24
Finished Jul 27 04:54:27 PM PDT 24
Peak memory 217140 kb
Host smart-c4e70ce1-6b9a-42da-8006-908bc586f705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893417918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.3893417918
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.1145440959
Short name T653
Test name
Test status
Simulation time 105607036 ps
CPU time 1.49 seconds
Started Jul 27 04:53:56 PM PDT 24
Finished Jul 27 04:53:57 PM PDT 24
Peak memory 217056 kb
Host smart-1a8c5be7-633d-4068-a5e2-07ca802b5108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145440959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.1145440959
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.1362612892
Short name T976
Test name
Test status
Simulation time 268615167 ps
CPU time 0.85 seconds
Started Jul 27 04:53:56 PM PDT 24
Finished Jul 27 04:53:57 PM PDT 24
Peak memory 206616 kb
Host smart-b69c626f-090b-44f1-ba3a-de69aeb4134f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362612892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.1362612892
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.1462467796
Short name T787
Test name
Test status
Simulation time 275905412 ps
CPU time 2.54 seconds
Started Jul 27 04:54:16 PM PDT 24
Finished Jul 27 04:54:19 PM PDT 24
Peak memory 225304 kb
Host smart-7d8e0c35-3784-46e8-a502-e8519a008ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462467796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.1462467796
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.2416417976
Short name T777
Test name
Test status
Simulation time 15096074 ps
CPU time 0.74 seconds
Started Jul 27 04:54:11 PM PDT 24
Finished Jul 27 04:54:12 PM PDT 24
Peak memory 205992 kb
Host smart-532dbadc-9d7e-4efa-89ef-bc21e19a7170
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416417976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
2416417976
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.4151482187
Short name T996
Test name
Test status
Simulation time 132793637 ps
CPU time 2.73 seconds
Started Jul 27 04:54:13 PM PDT 24
Finished Jul 27 04:54:15 PM PDT 24
Peak memory 225300 kb
Host smart-479aa1d9-e6fb-4fee-a7d5-6c94018375ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151482187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.4151482187
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.105345077
Short name T66
Test name
Test status
Simulation time 46488236 ps
CPU time 0.78 seconds
Started Jul 27 04:54:16 PM PDT 24
Finished Jul 27 04:54:16 PM PDT 24
Peak memory 207220 kb
Host smart-f87f2921-1ef2-451d-ba89-7c625cb0dd23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105345077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.105345077
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.3154430277
Short name T170
Test name
Test status
Simulation time 137454771665 ps
CPU time 160.96 seconds
Started Jul 27 04:54:09 PM PDT 24
Finished Jul 27 04:56:50 PM PDT 24
Peak memory 256196 kb
Host smart-51b12513-e67a-4348-863a-3d62a156bbe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154430277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.3154430277
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.2916358201
Short name T234
Test name
Test status
Simulation time 186122226440 ps
CPU time 429.89 seconds
Started Jul 27 04:54:18 PM PDT 24
Finished Jul 27 05:01:29 PM PDT 24
Peak memory 257340 kb
Host smart-ee5bedad-be90-4f05-b723-68876567d2dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916358201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.2916358201
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.4057797261
Short name T222
Test name
Test status
Simulation time 2230219771 ps
CPU time 43.62 seconds
Started Jul 27 04:54:16 PM PDT 24
Finished Jul 27 04:54:59 PM PDT 24
Peak memory 250272 kb
Host smart-d68ecd7a-5b19-42fa-8055-36959e10b995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057797261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.4057797261
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.2274763588
Short name T358
Test name
Test status
Simulation time 193819086 ps
CPU time 6.31 seconds
Started Jul 27 04:54:10 PM PDT 24
Finished Jul 27 04:54:16 PM PDT 24
Peak memory 249060 kb
Host smart-47a80544-ca9b-4bf8-be38-d471e695fa58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274763588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.2274763588
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.2501981680
Short name T367
Test name
Test status
Simulation time 2187526336 ps
CPU time 26.39 seconds
Started Jul 27 04:54:12 PM PDT 24
Finished Jul 27 04:54:39 PM PDT 24
Peak memory 239184 kb
Host smart-acce6e1a-b2ad-4d04-83c8-e6e963feded3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501981680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmd
s.2501981680
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_intercept.386934446
Short name T635
Test name
Test status
Simulation time 5452006908 ps
CPU time 5.6 seconds
Started Jul 27 04:54:17 PM PDT 24
Finished Jul 27 04:54:28 PM PDT 24
Peak memory 225500 kb
Host smart-d19104cf-98cf-43c4-9d7c-5ff8faaf99d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386934446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.386934446
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.1827197879
Short name T852
Test name
Test status
Simulation time 2445111325 ps
CPU time 18.44 seconds
Started Jul 27 04:54:18 PM PDT 24
Finished Jul 27 04:54:37 PM PDT 24
Peak memory 233612 kb
Host smart-b49ad7d1-9141-439b-bffe-0ac8cb3ef3e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827197879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.1827197879
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.3401285307
Short name T616
Test name
Test status
Simulation time 39593062035 ps
CPU time 21.9 seconds
Started Jul 27 04:54:18 PM PDT 24
Finished Jul 27 04:54:40 PM PDT 24
Peak memory 233508 kb
Host smart-54e9f7fb-648d-4c66-8263-e7832484720e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401285307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.3401285307
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.3935698621
Short name T1011
Test name
Test status
Simulation time 5732260353 ps
CPU time 11.38 seconds
Started Jul 27 04:54:15 PM PDT 24
Finished Jul 27 04:54:27 PM PDT 24
Peak memory 225516 kb
Host smart-7f353522-c5a2-4eb9-a905-774091217ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935698621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.3935698621
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.2087376633
Short name T455
Test name
Test status
Simulation time 3118842832 ps
CPU time 9.03 seconds
Started Jul 27 04:54:08 PM PDT 24
Finished Jul 27 04:54:17 PM PDT 24
Peak memory 222892 kb
Host smart-bc2145ce-3ec1-4eea-ad7c-4ff2f2f1ac75
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2087376633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.2087376633
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.1363711357
Short name T879
Test name
Test status
Simulation time 56777317969 ps
CPU time 486.27 seconds
Started Jul 27 04:54:19 PM PDT 24
Finished Jul 27 05:02:26 PM PDT 24
Peak memory 272988 kb
Host smart-edc5328f-18ba-4265-99eb-0f8ef816e7c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363711357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.1363711357
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.3657208290
Short name T593
Test name
Test status
Simulation time 19531023 ps
CPU time 0.79 seconds
Started Jul 27 04:54:11 PM PDT 24
Finished Jul 27 04:54:12 PM PDT 24
Peak memory 206360 kb
Host smart-213af678-c47e-4037-b8e8-624384e11355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657208290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.3657208290
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.3472090767
Short name T983
Test name
Test status
Simulation time 146344017 ps
CPU time 1.65 seconds
Started Jul 27 04:54:13 PM PDT 24
Finished Jul 27 04:54:15 PM PDT 24
Peak memory 208612 kb
Host smart-3b3670bc-ad67-4bae-8173-d2d424be69d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472090767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.3472090767
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.2920197866
Short name T986
Test name
Test status
Simulation time 157498903 ps
CPU time 1.67 seconds
Started Jul 27 04:54:15 PM PDT 24
Finished Jul 27 04:54:17 PM PDT 24
Peak memory 217096 kb
Host smart-e6c89774-6d22-479f-b798-9237ee4943f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920197866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.2920197866
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.3293076434
Short name T33
Test name
Test status
Simulation time 41963277 ps
CPU time 0.85 seconds
Started Jul 27 04:54:19 PM PDT 24
Finished Jul 27 04:54:20 PM PDT 24
Peak memory 206692 kb
Host smart-eee268cd-8929-447b-b9d2-c33c7abbbe6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293076434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.3293076434
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.3103231564
Short name T737
Test name
Test status
Simulation time 708032484 ps
CPU time 2.31 seconds
Started Jul 27 04:54:16 PM PDT 24
Finished Jul 27 04:54:19 PM PDT 24
Peak memory 224460 kb
Host smart-91f6ab5a-186f-4695-a492-b2a97962f3ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103231564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.3103231564
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.1252100153
Short name T949
Test name
Test status
Simulation time 14524987 ps
CPU time 0.71 seconds
Started Jul 27 04:54:15 PM PDT 24
Finished Jul 27 04:54:16 PM PDT 24
Peak memory 205944 kb
Host smart-46bf3c28-49f2-41ea-b6b8-9b538cae6c10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252100153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
1252100153
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.1685894355
Short name T989
Test name
Test status
Simulation time 1422654582 ps
CPU time 9.17 seconds
Started Jul 27 04:54:19 PM PDT 24
Finished Jul 27 04:54:28 PM PDT 24
Peak memory 225368 kb
Host smart-bda03de8-415f-4d74-81f0-75990f39ffb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685894355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.1685894355
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.14347848
Short name T431
Test name
Test status
Simulation time 63584728 ps
CPU time 0.82 seconds
Started Jul 27 04:54:17 PM PDT 24
Finished Jul 27 04:54:18 PM PDT 24
Peak memory 207452 kb
Host smart-9e5c6c98-bda2-4c3f-9e00-e6f74325f62a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14347848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.14347848
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.2257637887
Short name T541
Test name
Test status
Simulation time 27729507143 ps
CPU time 90.87 seconds
Started Jul 27 04:54:11 PM PDT 24
Finished Jul 27 04:55:42 PM PDT 24
Peak memory 252900 kb
Host smart-fb258df1-7e7f-4151-8896-1897202dbb9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257637887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.2257637887
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.2988175801
Short name T1004
Test name
Test status
Simulation time 13878852576 ps
CPU time 35.2 seconds
Started Jul 27 04:54:18 PM PDT 24
Finished Jul 27 04:54:53 PM PDT 24
Peak memory 241756 kb
Host smart-f4c05bd5-dc49-41eb-9c83-c10ba9e18406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988175801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.2988175801
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.3637576163
Short name T861
Test name
Test status
Simulation time 893139645 ps
CPU time 14.72 seconds
Started Jul 27 04:54:18 PM PDT 24
Finished Jul 27 04:54:33 PM PDT 24
Peak memory 225440 kb
Host smart-75942500-5ff5-41dd-827c-14f5720de318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637576163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.3637576163
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.1856443562
Short name T1019
Test name
Test status
Simulation time 19105386408 ps
CPU time 100.14 seconds
Started Jul 27 04:54:12 PM PDT 24
Finished Jul 27 04:55:53 PM PDT 24
Peak memory 242028 kb
Host smart-88e849f0-62fc-4b02-95c0-5de6e99927ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856443562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmd
s.1856443562
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_intercept.1767203278
Short name T528
Test name
Test status
Simulation time 370417651 ps
CPU time 5.6 seconds
Started Jul 27 04:54:11 PM PDT 24
Finished Jul 27 04:54:17 PM PDT 24
Peak memory 220540 kb
Host smart-a5f313a7-3236-42e9-9636-c0e19fe5af46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767203278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.1767203278
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.1454193984
Short name T920
Test name
Test status
Simulation time 10310191092 ps
CPU time 94.81 seconds
Started Jul 27 04:54:13 PM PDT 24
Finished Jul 27 04:55:48 PM PDT 24
Peak memory 233744 kb
Host smart-ef09399e-fc06-4540-8e0d-8f96fa7b11d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454193984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.1454193984
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.3054051138
Short name T366
Test name
Test status
Simulation time 133398330 ps
CPU time 2.44 seconds
Started Jul 27 04:54:15 PM PDT 24
Finished Jul 27 04:54:18 PM PDT 24
Peak memory 233088 kb
Host smart-a0339503-a4a3-4ca9-99dd-2a9337ee9cf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054051138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.3054051138
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.1437467199
Short name T257
Test name
Test status
Simulation time 1124584391 ps
CPU time 3.52 seconds
Started Jul 27 04:54:17 PM PDT 24
Finished Jul 27 04:54:20 PM PDT 24
Peak memory 233480 kb
Host smart-046b03ec-32a0-431a-bd74-6041ed699a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437467199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.1437467199
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.1266224754
Short name T677
Test name
Test status
Simulation time 2679598483 ps
CPU time 13.79 seconds
Started Jul 27 04:54:09 PM PDT 24
Finished Jul 27 04:54:23 PM PDT 24
Peak memory 220204 kb
Host smart-b19a8879-a21d-4738-8967-7a75cbfde6d6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1266224754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.1266224754
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.1356876031
Short name T471
Test name
Test status
Simulation time 105433188 ps
CPU time 0.99 seconds
Started Jul 27 04:54:18 PM PDT 24
Finished Jul 27 04:54:19 PM PDT 24
Peak memory 207392 kb
Host smart-fa397dd2-ffaf-4e06-b098-444dfc782f99
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356876031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.1356876031
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.3066248164
Short name T402
Test name
Test status
Simulation time 180022931 ps
CPU time 2.94 seconds
Started Jul 27 04:54:17 PM PDT 24
Finished Jul 27 04:54:20 PM PDT 24
Peak memory 217028 kb
Host smart-bb11d7f4-bf9c-4881-9109-6d5709106bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066248164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.3066248164
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.3729787765
Short name T519
Test name
Test status
Simulation time 6740982500 ps
CPU time 4.13 seconds
Started Jul 27 04:54:12 PM PDT 24
Finished Jul 27 04:54:17 PM PDT 24
Peak memory 217100 kb
Host smart-1f850d1b-7367-40ae-a5da-24f59ade6a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729787765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.3729787765
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.2952694830
Short name T520
Test name
Test status
Simulation time 26179952 ps
CPU time 0.91 seconds
Started Jul 27 04:54:19 PM PDT 24
Finished Jul 27 04:54:20 PM PDT 24
Peak memory 207824 kb
Host smart-03b2cf91-ee58-452c-80dc-308c701a4779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952694830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.2952694830
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.4285073956
Short name T349
Test name
Test status
Simulation time 398941378 ps
CPU time 0.87 seconds
Started Jul 27 04:54:13 PM PDT 24
Finished Jul 27 04:54:14 PM PDT 24
Peak memory 206660 kb
Host smart-3ac329d1-842a-4693-9a72-6044d0c0537c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285073956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.4285073956
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.2125453622
Short name T174
Test name
Test status
Simulation time 1188838519 ps
CPU time 3.05 seconds
Started Jul 27 04:54:18 PM PDT 24
Finished Jul 27 04:54:21 PM PDT 24
Peak memory 233640 kb
Host smart-97de82c3-70a1-4e50-afa9-589c4bd9c762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125453622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.2125453622
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.38208996
Short name T900
Test name
Test status
Simulation time 22383698 ps
CPU time 0.72 seconds
Started Jul 27 04:54:20 PM PDT 24
Finished Jul 27 04:54:21 PM PDT 24
Peak memory 206016 kb
Host smart-0045bf1b-94bb-4792-9e60-26c7baf9ef90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38208996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.38208996
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.2410960011
Short name T489
Test name
Test status
Simulation time 76322869 ps
CPU time 2.22 seconds
Started Jul 27 04:54:12 PM PDT 24
Finished Jul 27 04:54:15 PM PDT 24
Peak memory 225340 kb
Host smart-05e13be2-ed5b-4622-8125-d206d7795dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410960011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.2410960011
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.1799246354
Short name T360
Test name
Test status
Simulation time 22955699 ps
CPU time 0.71 seconds
Started Jul 27 04:54:09 PM PDT 24
Finished Jul 27 04:54:10 PM PDT 24
Peak memory 206376 kb
Host smart-6363c302-9617-4f24-b044-f2c3b722a91b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799246354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.1799246354
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.925204606
Short name T907
Test name
Test status
Simulation time 21258879721 ps
CPU time 63.76 seconds
Started Jul 27 04:54:16 PM PDT 24
Finished Jul 27 04:55:20 PM PDT 24
Peak memory 241864 kb
Host smart-786e5564-3934-4237-8e0c-edd911642d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925204606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.925204606
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.1096465815
Short name T208
Test name
Test status
Simulation time 6586903926 ps
CPU time 70.72 seconds
Started Jul 27 04:54:18 PM PDT 24
Finished Jul 27 04:55:29 PM PDT 24
Peak memory 253616 kb
Host smart-02bf47d8-168a-4bf9-b4d4-6e77bc496a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096465815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.1096465815
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.2767045316
Short name T738
Test name
Test status
Simulation time 49967554630 ps
CPU time 31.38 seconds
Started Jul 27 04:54:17 PM PDT 24
Finished Jul 27 04:54:49 PM PDT 24
Peak memory 225392 kb
Host smart-19121ff6-4074-4a23-ab02-b9f40c25d44c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767045316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.2767045316
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.2176282572
Short name T307
Test name
Test status
Simulation time 30071974277 ps
CPU time 50.48 seconds
Started Jul 27 04:54:18 PM PDT 24
Finished Jul 27 04:55:09 PM PDT 24
Peak memory 250128 kb
Host smart-9e4dafea-e781-4dc0-80ac-4e25d783523c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176282572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.2176282572
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.2075315139
Short name T245
Test name
Test status
Simulation time 5815182141 ps
CPU time 82.91 seconds
Started Jul 27 04:54:16 PM PDT 24
Finished Jul 27 04:55:39 PM PDT 24
Peak memory 261740 kb
Host smart-31b99334-18e6-40e4-9a56-0a25203bd478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075315139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmd
s.2075315139
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_intercept.1001561344
Short name T391
Test name
Test status
Simulation time 31239437 ps
CPU time 2.47 seconds
Started Jul 27 04:54:13 PM PDT 24
Finished Jul 27 04:54:16 PM PDT 24
Peak memory 233120 kb
Host smart-34cf8527-e8f1-4f41-ad1d-1f16c098f877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001561344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.1001561344
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.663500956
Short name T272
Test name
Test status
Simulation time 2035989648 ps
CPU time 12.97 seconds
Started Jul 27 04:54:11 PM PDT 24
Finished Jul 27 04:54:25 PM PDT 24
Peak memory 224392 kb
Host smart-715c6d65-a32f-42c6-9f72-47826d075104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663500956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.663500956
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.4209225856
Short name T563
Test name
Test status
Simulation time 27317682 ps
CPU time 2.09 seconds
Started Jul 27 04:54:02 PM PDT 24
Finished Jul 27 04:54:04 PM PDT 24
Peak memory 224576 kb
Host smart-e8143135-d2b3-47ae-9677-7c412396b948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209225856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.4209225856
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.2458011353
Short name T928
Test name
Test status
Simulation time 550080361 ps
CPU time 9.52 seconds
Started Jul 27 04:54:13 PM PDT 24
Finished Jul 27 04:54:23 PM PDT 24
Peak memory 239836 kb
Host smart-fc7cf5bb-f069-431d-b0ac-b84d5667784b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458011353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.2458011353
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.2776670488
Short name T962
Test name
Test status
Simulation time 122614582 ps
CPU time 3.02 seconds
Started Jul 27 04:54:12 PM PDT 24
Finished Jul 27 04:54:16 PM PDT 24
Peak memory 220056 kb
Host smart-92b57bc7-4dfc-488a-a119-794a4343395b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2776670488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.2776670488
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.200110139
Short name T934
Test name
Test status
Simulation time 148510915934 ps
CPU time 326.43 seconds
Started Jul 27 04:54:18 PM PDT 24
Finished Jul 27 04:59:45 PM PDT 24
Peak memory 266648 kb
Host smart-be7b812b-06b5-455f-ba52-8ebc1ae5cbc5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200110139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stres
s_all.200110139
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.2231213691
Short name T440
Test name
Test status
Simulation time 15280910427 ps
CPU time 31.2 seconds
Started Jul 27 04:54:18 PM PDT 24
Finished Jul 27 04:54:49 PM PDT 24
Peak memory 217288 kb
Host smart-c666888c-925f-42bc-bd7b-b95fdf1bb91a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231213691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.2231213691
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.3712750479
Short name T34
Test name
Test status
Simulation time 1141814353 ps
CPU time 5.8 seconds
Started Jul 27 04:54:13 PM PDT 24
Finished Jul 27 04:54:19 PM PDT 24
Peak memory 217100 kb
Host smart-52d344d4-34a1-4f77-a2f0-5974e2a08e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712750479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.3712750479
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.2121302173
Short name T1023
Test name
Test status
Simulation time 1410537308 ps
CPU time 4.56 seconds
Started Jul 27 04:54:16 PM PDT 24
Finished Jul 27 04:54:21 PM PDT 24
Peak memory 217108 kb
Host smart-7ee3b6db-84a0-4f12-88b0-4734f8f7a6e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121302173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.2121302173
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.3677726100
Short name T90
Test name
Test status
Simulation time 148472950 ps
CPU time 0.99 seconds
Started Jul 27 04:54:14 PM PDT 24
Finished Jul 27 04:54:16 PM PDT 24
Peak memory 206812 kb
Host smart-adb60b83-61ed-4d46-806c-984a6d64920e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677726100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.3677726100
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.3865122212
Short name T840
Test name
Test status
Simulation time 1438630923 ps
CPU time 8.23 seconds
Started Jul 27 04:54:10 PM PDT 24
Finished Jul 27 04:54:18 PM PDT 24
Peak memory 233488 kb
Host smart-6991cd67-f947-457c-a41f-bacf7c8a3e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865122212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.3865122212
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.3008824934
Short name T487
Test name
Test status
Simulation time 11271914 ps
CPU time 0.7 seconds
Started Jul 27 04:54:18 PM PDT 24
Finished Jul 27 04:54:19 PM PDT 24
Peak memory 206344 kb
Host smart-3de34216-7546-465c-b6f8-644fc1affbb3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008824934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
3008824934
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.812100066
Short name T686
Test name
Test status
Simulation time 312615256 ps
CPU time 6.7 seconds
Started Jul 27 04:54:16 PM PDT 24
Finished Jul 27 04:54:22 PM PDT 24
Peak memory 225416 kb
Host smart-befa6b72-4278-487c-a513-683ce608a230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812100066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.812100066
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.3350227139
Short name T522
Test name
Test status
Simulation time 16169901 ps
CPU time 0.77 seconds
Started Jul 27 04:54:11 PM PDT 24
Finished Jul 27 04:54:12 PM PDT 24
Peak memory 206464 kb
Host smart-66973907-f755-4922-bf96-d8100cde3c54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350227139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.3350227139
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.1503769784
Short name T529
Test name
Test status
Simulation time 1076059881 ps
CPU time 10.25 seconds
Started Jul 27 04:54:22 PM PDT 24
Finished Jul 27 04:54:33 PM PDT 24
Peak memory 225352 kb
Host smart-a49e3922-8897-4220-91bc-9def855f40f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503769784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.1503769784
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.2339695413
Short name T213
Test name
Test status
Simulation time 1610108622 ps
CPU time 21.57 seconds
Started Jul 27 04:54:15 PM PDT 24
Finished Jul 27 04:54:37 PM PDT 24
Peak memory 233536 kb
Host smart-8226c448-1b3c-45b5-ac06-43fbdce3e18b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339695413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.2339695413
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.3630397740
Short name T279
Test name
Test status
Simulation time 25601320369 ps
CPU time 233.86 seconds
Started Jul 27 04:54:14 PM PDT 24
Finished Jul 27 04:58:08 PM PDT 24
Peak memory 254444 kb
Host smart-c624a10d-dc8e-4cee-b031-a861c6ae4202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630397740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.3630397740
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.2668572075
Short name T63
Test name
Test status
Simulation time 19252460417 ps
CPU time 67.91 seconds
Started Jul 27 04:54:25 PM PDT 24
Finished Jul 27 04:55:33 PM PDT 24
Peak memory 249992 kb
Host smart-ff15fe9c-ec87-4179-b6d3-5de67e798837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668572075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.2668572075
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_intercept.3598755220
Short name T456
Test name
Test status
Simulation time 330812603 ps
CPU time 3.76 seconds
Started Jul 27 04:54:17 PM PDT 24
Finished Jul 27 04:54:26 PM PDT 24
Peak memory 233596 kb
Host smart-3de698a9-6229-43b3-82f7-6e1b77d0aa09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598755220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.3598755220
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.3305980422
Short name T705
Test name
Test status
Simulation time 792340715 ps
CPU time 13.69 seconds
Started Jul 27 04:54:19 PM PDT 24
Finished Jul 27 04:54:33 PM PDT 24
Peak memory 239412 kb
Host smart-74898b0d-e5f2-4f31-bd3f-237dd782deb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305980422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.3305980422
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.3646270755
Short name T268
Test name
Test status
Simulation time 435876969 ps
CPU time 3.57 seconds
Started Jul 27 04:54:53 PM PDT 24
Finished Jul 27 04:54:57 PM PDT 24
Peak memory 233592 kb
Host smart-0c52eff4-e238-47a5-a4ff-71edf00e3e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646270755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.3646270755
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.3461607849
Short name T992
Test name
Test status
Simulation time 637388105 ps
CPU time 5.69 seconds
Started Jul 27 04:54:14 PM PDT 24
Finished Jul 27 04:54:20 PM PDT 24
Peak memory 225440 kb
Host smart-75505878-9f89-45a5-aab7-abb30001c46d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461607849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.3461607849
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.4050612398
Short name T602
Test name
Test status
Simulation time 103367436 ps
CPU time 3.75 seconds
Started Jul 27 04:54:27 PM PDT 24
Finished Jul 27 04:54:31 PM PDT 24
Peak memory 223416 kb
Host smart-c7513609-e3d3-4c78-88c0-935101585807
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4050612398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.4050612398
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.1991177688
Short name T657
Test name
Test status
Simulation time 21294381746 ps
CPU time 31.58 seconds
Started Jul 27 04:54:16 PM PDT 24
Finished Jul 27 04:54:48 PM PDT 24
Peak memory 217208 kb
Host smart-3732b77c-16f6-4791-bcf9-b292417909d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991177688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.1991177688
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.2952104490
Short name T627
Test name
Test status
Simulation time 96311262024 ps
CPU time 14.78 seconds
Started Jul 27 04:54:06 PM PDT 24
Finished Jul 27 04:54:21 PM PDT 24
Peak memory 217204 kb
Host smart-96daad7b-ae90-4900-893c-e4e3e69af85d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952104490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.2952104490
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.919758472
Short name T1013
Test name
Test status
Simulation time 22078426 ps
CPU time 0.7 seconds
Started Jul 27 04:54:17 PM PDT 24
Finished Jul 27 04:54:18 PM PDT 24
Peak memory 206304 kb
Host smart-25746345-86d2-453f-98a9-4b06302f1b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919758472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.919758472
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.1330057871
Short name T823
Test name
Test status
Simulation time 121215451 ps
CPU time 0.85 seconds
Started Jul 27 04:54:12 PM PDT 24
Finished Jul 27 04:54:13 PM PDT 24
Peak memory 206684 kb
Host smart-dcee2d23-473c-4fc3-93b5-1105c751b879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330057871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.1330057871
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.976921744
Short name T1001
Test name
Test status
Simulation time 7803486238 ps
CPU time 15.98 seconds
Started Jul 27 04:54:24 PM PDT 24
Finished Jul 27 04:54:40 PM PDT 24
Peak memory 241236 kb
Host smart-ae1020cd-fab6-43a4-be6f-f6e0a62b4f10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976921744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.976921744
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.480479924
Short name T67
Test name
Test status
Simulation time 12476255 ps
CPU time 0.73 seconds
Started Jul 27 04:54:19 PM PDT 24
Finished Jul 27 04:54:20 PM PDT 24
Peak memory 205352 kb
Host smart-5501c8b0-0733-4fe7-aeab-1cff784a5a5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480479924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.480479924
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.355838904
Short name T499
Test name
Test status
Simulation time 203493783 ps
CPU time 2.6 seconds
Started Jul 27 04:54:31 PM PDT 24
Finished Jul 27 04:54:33 PM PDT 24
Peak memory 233524 kb
Host smart-e7857a6a-e6e8-4c33-9b30-414aa46169d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355838904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.355838904
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.2882410689
Short name T331
Test name
Test status
Simulation time 21662942 ps
CPU time 0.76 seconds
Started Jul 27 04:54:20 PM PDT 24
Finished Jul 27 04:54:21 PM PDT 24
Peak memory 206196 kb
Host smart-aa111592-5218-47fc-85ca-f8b2d2309c8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882410689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.2882410689
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.2475665128
Short name T702
Test name
Test status
Simulation time 1538411459 ps
CPU time 17.14 seconds
Started Jul 27 04:54:28 PM PDT 24
Finished Jul 27 04:54:45 PM PDT 24
Peak memory 251208 kb
Host smart-40e23daa-7680-4428-ae46-cfd97ac84c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475665128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.2475665128
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.3282339665
Short name T830
Test name
Test status
Simulation time 46741134 ps
CPU time 2.57 seconds
Started Jul 27 04:54:13 PM PDT 24
Finished Jul 27 04:54:16 PM PDT 24
Peak memory 225332 kb
Host smart-97a6e09f-db06-4a2a-afbe-4d96c548b35f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282339665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.3282339665
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.1634142189
Short name T298
Test name
Test status
Simulation time 173735802878 ps
CPU time 297.32 seconds
Started Jul 27 04:54:16 PM PDT 24
Finished Jul 27 04:59:13 PM PDT 24
Peak memory 265340 kb
Host smart-f8090f78-bb85-4a23-a899-aaebbf6a2d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634142189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmd
s.1634142189
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/49.spi_device_intercept.621179080
Short name T205
Test name
Test status
Simulation time 451391118 ps
CPU time 3.52 seconds
Started Jul 27 04:54:14 PM PDT 24
Finished Jul 27 04:54:19 PM PDT 24
Peak memory 233512 kb
Host smart-d0b6d192-c506-4b60-a855-adacea936fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621179080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.621179080
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.617494745
Short name T751
Test name
Test status
Simulation time 15048924746 ps
CPU time 23.93 seconds
Started Jul 27 04:54:24 PM PDT 24
Finished Jul 27 04:54:48 PM PDT 24
Peak memory 240184 kb
Host smart-b47cc273-1ddf-4d33-8b7f-137fbceb3b98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617494745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.617494745
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.1400443720
Short name T663
Test name
Test status
Simulation time 4187309733 ps
CPU time 15.81 seconds
Started Jul 27 04:54:26 PM PDT 24
Finished Jul 27 04:54:41 PM PDT 24
Peak memory 225324 kb
Host smart-0ffa5535-e6e0-4f54-ba73-620ab387bc27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400443720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.1400443720
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.3836983206
Short name T876
Test name
Test status
Simulation time 2940265432 ps
CPU time 7.03 seconds
Started Jul 27 04:54:12 PM PDT 24
Finished Jul 27 04:54:20 PM PDT 24
Peak memory 225448 kb
Host smart-0c2497b2-5d36-4ec8-8665-64e900d7b41d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836983206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.3836983206
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.3109887656
Short name T664
Test name
Test status
Simulation time 885062329 ps
CPU time 11 seconds
Started Jul 27 04:54:49 PM PDT 24
Finished Jul 27 04:55:00 PM PDT 24
Peak memory 223232 kb
Host smart-bfb007a0-f4b0-4869-a68e-ae4530130c46
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3109887656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.3109887656
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.875535719
Short name T728
Test name
Test status
Simulation time 23721117169 ps
CPU time 15.72 seconds
Started Jul 27 04:54:28 PM PDT 24
Finished Jul 27 04:54:44 PM PDT 24
Peak memory 217252 kb
Host smart-e8f7ad76-b079-4313-8192-6e3bccc32a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875535719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.875535719
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.52032388
Short name T959
Test name
Test status
Simulation time 4464365029 ps
CPU time 11.1 seconds
Started Jul 27 04:54:14 PM PDT 24
Finished Jul 27 04:54:25 PM PDT 24
Peak memory 217180 kb
Host smart-d0d7fafa-3a1b-40a3-b150-bbf75f145960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52032388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.52032388
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.4240302310
Short name T941
Test name
Test status
Simulation time 114838275 ps
CPU time 1.1 seconds
Started Jul 27 04:54:19 PM PDT 24
Finished Jul 27 04:54:21 PM PDT 24
Peak memory 208296 kb
Host smart-24483dbf-3fb1-4bc4-ab2f-e5bd288ea9ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240302310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.4240302310
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.3963584769
Short name T585
Test name
Test status
Simulation time 344446037 ps
CPU time 0.88 seconds
Started Jul 27 04:54:28 PM PDT 24
Finished Jul 27 04:54:29 PM PDT 24
Peak memory 206644 kb
Host smart-35a6db88-8cf9-45bf-af1a-e30e3ae760c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963584769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.3963584769
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.2675796965
Short name T421
Test name
Test status
Simulation time 6021986046 ps
CPU time 21.25 seconds
Started Jul 27 04:54:20 PM PDT 24
Finished Jul 27 04:54:41 PM PDT 24
Peak memory 238092 kb
Host smart-e6ca50d1-9592-4f15-8c14-7e1c6b44144f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675796965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.2675796965
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.3457794946
Short name T902
Test name
Test status
Simulation time 18382122 ps
CPU time 0.7 seconds
Started Jul 27 04:52:12 PM PDT 24
Finished Jul 27 04:52:13 PM PDT 24
Peak memory 205460 kb
Host smart-038ac2cd-7897-451b-b973-867891be976b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457794946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.3
457794946
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.3500858057
Short name T731
Test name
Test status
Simulation time 3392244384 ps
CPU time 15.85 seconds
Started Jul 27 04:52:07 PM PDT 24
Finished Jul 27 04:52:23 PM PDT 24
Peak memory 225336 kb
Host smart-7cdbbe7c-e097-493a-841f-bb92ff210998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500858057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.3500858057
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.1079731126
Short name T36
Test name
Test status
Simulation time 14734910 ps
CPU time 0.75 seconds
Started Jul 27 04:52:07 PM PDT 24
Finished Jul 27 04:52:08 PM PDT 24
Peak memory 206204 kb
Host smart-bd0ab697-b5a6-473d-84ac-fd626ca333db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079731126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.1079731126
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.3456996624
Short name T871
Test name
Test status
Simulation time 16060287420 ps
CPU time 117.47 seconds
Started Jul 27 04:52:08 PM PDT 24
Finished Jul 27 04:54:06 PM PDT 24
Peak memory 250020 kb
Host smart-61209501-740a-41d7-82a3-ab7add18165e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456996624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.3456996624
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.4154892333
Short name T80
Test name
Test status
Simulation time 34451591479 ps
CPU time 255.33 seconds
Started Jul 27 04:52:10 PM PDT 24
Finished Jul 27 04:56:25 PM PDT 24
Peak memory 262332 kb
Host smart-febcfeb5-19aa-4957-9544-1eaa05e1b846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154892333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.4154892333
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.3666111291
Short name T422
Test name
Test status
Simulation time 22468066742 ps
CPU time 203.76 seconds
Started Jul 27 04:52:08 PM PDT 24
Finished Jul 27 04:55:32 PM PDT 24
Peak memory 250092 kb
Host smart-ac9fc5cd-4fc0-48d1-9643-34c25918cd06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666111291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.3666111291
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.2675367431
Short name T11
Test name
Test status
Simulation time 880930422 ps
CPU time 3.31 seconds
Started Jul 27 04:52:26 PM PDT 24
Finished Jul 27 04:52:30 PM PDT 24
Peak memory 233524 kb
Host smart-5f580640-31ad-4bcd-a249-988009a1c2f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675367431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.2675367431
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.3986060238
Short name T295
Test name
Test status
Simulation time 16617109334 ps
CPU time 53.36 seconds
Started Jul 27 04:52:27 PM PDT 24
Finished Jul 27 04:53:21 PM PDT 24
Peak memory 250476 kb
Host smart-5c2af83b-3429-4b93-b6a3-1d3e9a66458f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986060238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds
.3986060238
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/5.spi_device_intercept.1689503426
Short name T566
Test name
Test status
Simulation time 33714641 ps
CPU time 2.27 seconds
Started Jul 27 04:52:19 PM PDT 24
Finished Jul 27 04:52:22 PM PDT 24
Peak memory 233160 kb
Host smart-75d1d2a0-cc07-47b7-a35c-88d994b104ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689503426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.1689503426
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.935666692
Short name T832
Test name
Test status
Simulation time 2099963530 ps
CPU time 7.77 seconds
Started Jul 27 04:52:11 PM PDT 24
Finished Jul 27 04:52:19 PM PDT 24
Peak memory 233572 kb
Host smart-abf694d9-ba61-4914-b382-5da6cf5b55ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935666692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.935666692
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.2645677053
Short name T511
Test name
Test status
Simulation time 59856883 ps
CPU time 1.07 seconds
Started Jul 27 04:52:18 PM PDT 24
Finished Jul 27 04:52:19 PM PDT 24
Peak memory 217300 kb
Host smart-c6b23ac1-17ae-42e9-aecb-28bdebf93ba2
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645677053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.spi_device_mem_parity.2645677053
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.474068198
Short name T788
Test name
Test status
Simulation time 577513003 ps
CPU time 6.2 seconds
Started Jul 27 04:52:10 PM PDT 24
Finished Jul 27 04:52:21 PM PDT 24
Peak memory 240464 kb
Host smart-7ac6c696-a4cc-4930-89cf-92869afc1c85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474068198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap.
474068198
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.1332319797
Short name T532
Test name
Test status
Simulation time 218859839 ps
CPU time 2.6 seconds
Started Jul 27 04:52:11 PM PDT 24
Finished Jul 27 04:52:14 PM PDT 24
Peak memory 225284 kb
Host smart-54b6b97b-f8f4-4fc0-af43-ec29ca53cfb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332319797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.1332319797
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.3987564827
Short name T944
Test name
Test status
Simulation time 1105656343 ps
CPU time 9.93 seconds
Started Jul 27 04:52:14 PM PDT 24
Finished Jul 27 04:52:24 PM PDT 24
Peak memory 222804 kb
Host smart-c0ce094d-134f-43b1-958d-773a3a9662bf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3987564827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.3987564827
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.4174371854
Short name T1000
Test name
Test status
Simulation time 86344073649 ps
CPU time 293.35 seconds
Started Jul 27 04:52:19 PM PDT 24
Finished Jul 27 04:57:12 PM PDT 24
Peak memory 251724 kb
Host smart-55d77bc6-730d-4db9-8c0d-e5cd6cde400e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174371854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.4174371854
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.4063769791
Short name T502
Test name
Test status
Simulation time 2549561151 ps
CPU time 10.94 seconds
Started Jul 27 04:52:07 PM PDT 24
Finished Jul 27 04:52:18 PM PDT 24
Peak memory 217584 kb
Host smart-96f57ad1-bfe9-4101-b79e-f64535c0f97c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063769791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.4063769791
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.3026845639
Short name T333
Test name
Test status
Simulation time 914001853 ps
CPU time 7.56 seconds
Started Jul 27 04:52:32 PM PDT 24
Finished Jul 27 04:52:39 PM PDT 24
Peak memory 217100 kb
Host smart-f13364b4-a613-4dde-b8ea-e7e257652452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026845639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.3026845639
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.2533854280
Short name T699
Test name
Test status
Simulation time 15095882 ps
CPU time 0.71 seconds
Started Jul 27 04:52:30 PM PDT 24
Finished Jul 27 04:52:31 PM PDT 24
Peak memory 206300 kb
Host smart-92b6a794-16bc-4767-bd59-bb6b5cb5b2f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533854280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.2533854280
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.2797388167
Short name T981
Test name
Test status
Simulation time 194208121 ps
CPU time 0.87 seconds
Started Jul 27 04:52:12 PM PDT 24
Finished Jul 27 04:52:13 PM PDT 24
Peak memory 206740 kb
Host smart-09e8f482-f84d-421d-b8b2-1d2df3339bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797388167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.2797388167
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.4038521625
Short name T547
Test name
Test status
Simulation time 1022875969 ps
CPU time 6.09 seconds
Started Jul 27 04:52:07 PM PDT 24
Finished Jul 27 04:52:14 PM PDT 24
Peak memory 233496 kb
Host smart-a537d949-045a-4ade-8059-05ef9d9773bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038521625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.4038521625
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.866856882
Short name T373
Test name
Test status
Simulation time 26554727 ps
CPU time 0.79 seconds
Started Jul 27 04:52:08 PM PDT 24
Finished Jul 27 04:52:09 PM PDT 24
Peak memory 205440 kb
Host smart-7541dcff-d593-4366-bb9d-ea3119680a93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866856882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.866856882
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.3195404685
Short name T559
Test name
Test status
Simulation time 1661075239 ps
CPU time 12.06 seconds
Started Jul 27 04:52:12 PM PDT 24
Finished Jul 27 04:52:30 PM PDT 24
Peak memory 225372 kb
Host smart-fb252e64-2d7b-4cae-8b85-d4a6feba9c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195404685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.3195404685
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.1602368933
Short name T786
Test name
Test status
Simulation time 30299242 ps
CPU time 0.75 seconds
Started Jul 27 04:52:11 PM PDT 24
Finished Jul 27 04:52:12 PM PDT 24
Peak memory 206192 kb
Host smart-7fee2d20-28c0-40c5-a66e-fa5c49fc69d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602368933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.1602368933
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.2123399375
Short name T694
Test name
Test status
Simulation time 18931455484 ps
CPU time 149.06 seconds
Started Jul 27 04:52:11 PM PDT 24
Finished Jul 27 04:54:40 PM PDT 24
Peak memory 253136 kb
Host smart-34e70f73-739d-4dc6-b8e7-b7b4a6083609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123399375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.2123399375
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.1350785989
Short name T464
Test name
Test status
Simulation time 31501596887 ps
CPU time 268.63 seconds
Started Jul 27 04:52:07 PM PDT 24
Finished Jul 27 04:56:36 PM PDT 24
Peak memory 253452 kb
Host smart-0d6a8f7c-8a5e-4a8b-a1fe-4618c4e0d002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350785989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.1350785989
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.3710287324
Short name T296
Test name
Test status
Simulation time 36968253441 ps
CPU time 121.59 seconds
Started Jul 27 04:52:15 PM PDT 24
Finished Jul 27 04:54:17 PM PDT 24
Peak memory 258116 kb
Host smart-46b7664c-8712-4fb5-ab27-1d7776d2f66f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710287324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.3710287324
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.327661567
Short name T332
Test name
Test status
Simulation time 251580467 ps
CPU time 3.01 seconds
Started Jul 27 04:52:13 PM PDT 24
Finished Jul 27 04:52:16 PM PDT 24
Peak memory 233508 kb
Host smart-89303957-0e2e-472c-a627-379eb8f03326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327661567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.327661567
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.2802428025
Short name T555
Test name
Test status
Simulation time 32024762767 ps
CPU time 111.94 seconds
Started Jul 27 04:52:32 PM PDT 24
Finished Jul 27 04:54:24 PM PDT 24
Peak memory 249968 kb
Host smart-cda3dc11-5a35-4151-b04b-18257ad5f5f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802428025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds
.2802428025
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/6.spi_device_intercept.1700208411
Short name T337
Test name
Test status
Simulation time 29852531 ps
CPU time 2.13 seconds
Started Jul 27 04:52:14 PM PDT 24
Finished Jul 27 04:52:16 PM PDT 24
Peak memory 224008 kb
Host smart-e6ff5858-2896-43b5-89fa-b570b5509331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700208411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.1700208411
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.2076666985
Short name T947
Test name
Test status
Simulation time 2836644339 ps
CPU time 10.98 seconds
Started Jul 27 04:52:10 PM PDT 24
Finished Jul 27 04:52:21 PM PDT 24
Peak memory 225360 kb
Host smart-0e24ab0a-1bb6-4fa4-ae33-d4ffb60beb03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076666985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.2076666985
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.794279959
Short name T47
Test name
Test status
Simulation time 106144630 ps
CPU time 1.06 seconds
Started Jul 27 04:52:35 PM PDT 24
Finished Jul 27 04:52:36 PM PDT 24
Peak memory 217260 kb
Host smart-023e9236-82be-4fef-afb3-50ad2fe3f6f1
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794279959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.spi_device_mem_parity.794279959
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.3583281657
Short name T679
Test name
Test status
Simulation time 3050549874 ps
CPU time 7.04 seconds
Started Jul 27 04:52:07 PM PDT 24
Finished Jul 27 04:52:14 PM PDT 24
Peak memory 233648 kb
Host smart-cc161e19-e898-4a8f-84c5-c71fd26a8119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583281657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.3583281657
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.1525844812
Short name T409
Test name
Test status
Simulation time 1234874875 ps
CPU time 9.61 seconds
Started Jul 27 04:52:15 PM PDT 24
Finished Jul 27 04:52:24 PM PDT 24
Peak memory 233620 kb
Host smart-ace8d681-4a32-4052-939e-4d9a4e339e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525844812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.1525844812
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.1806761900
Short name T568
Test name
Test status
Simulation time 1493486762 ps
CPU time 7.16 seconds
Started Jul 27 04:52:11 PM PDT 24
Finished Jul 27 04:52:18 PM PDT 24
Peak memory 221424 kb
Host smart-1a0e840b-0d08-4750-a35a-f164791a749d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1806761900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.1806761900
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.1998977432
Short name T450
Test name
Test status
Simulation time 53493605 ps
CPU time 1.12 seconds
Started Jul 27 04:52:23 PM PDT 24
Finished Jul 27 04:52:25 PM PDT 24
Peak memory 207620 kb
Host smart-80e4d292-888c-4ba2-8402-426667c85cda
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998977432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.1998977432
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.3369937093
Short name T715
Test name
Test status
Simulation time 9856688038 ps
CPU time 40.28 seconds
Started Jul 27 04:52:09 PM PDT 24
Finished Jul 27 04:52:49 PM PDT 24
Peak memory 217212 kb
Host smart-7458b1ca-50f9-42db-9469-56d0a1399966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369937093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.3369937093
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.762438575
Short name T703
Test name
Test status
Simulation time 779107891 ps
CPU time 1.33 seconds
Started Jul 27 04:52:18 PM PDT 24
Finished Jul 27 04:52:19 PM PDT 24
Peak memory 207320 kb
Host smart-e5cb221b-9ada-4dbd-9617-b682b07e93c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762438575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.762438575
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.877936233
Short name T570
Test name
Test status
Simulation time 863953545 ps
CPU time 7 seconds
Started Jul 27 04:52:18 PM PDT 24
Finished Jul 27 04:52:25 PM PDT 24
Peak memory 217044 kb
Host smart-14c61f34-81be-42b6-b0e5-6c5667530d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877936233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.877936233
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.2792860215
Short name T406
Test name
Test status
Simulation time 20602895 ps
CPU time 0.77 seconds
Started Jul 27 04:52:13 PM PDT 24
Finished Jul 27 04:52:14 PM PDT 24
Peak memory 206664 kb
Host smart-fc54d104-dbbb-4e44-9c71-dd6831479ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792860215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.2792860215
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.746247840
Short name T721
Test name
Test status
Simulation time 4086648068 ps
CPU time 5.8 seconds
Started Jul 27 04:52:30 PM PDT 24
Finished Jul 27 04:52:35 PM PDT 24
Peak memory 225452 kb
Host smart-10959a64-5b1b-4333-908d-a727926c1f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746247840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.746247840
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.3462554572
Short name T441
Test name
Test status
Simulation time 113640913 ps
CPU time 0.71 seconds
Started Jul 27 04:52:26 PM PDT 24
Finished Jul 27 04:52:27 PM PDT 24
Peak memory 205676 kb
Host smart-903cb65a-6f21-4d58-b5fd-82030c68e2fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462554572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.3
462554572
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.2580590061
Short name T1008
Test name
Test status
Simulation time 1115649014 ps
CPU time 9.18 seconds
Started Jul 27 04:52:35 PM PDT 24
Finished Jul 27 04:52:44 PM PDT 24
Peak memory 233512 kb
Host smart-38d2775a-0aa3-4bb9-9073-09cc8e7792a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580590061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.2580590061
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.1909021278
Short name T554
Test name
Test status
Simulation time 37467897 ps
CPU time 0.81 seconds
Started Jul 27 04:52:15 PM PDT 24
Finished Jul 27 04:52:16 PM PDT 24
Peak memory 207540 kb
Host smart-5c9cf3db-491a-4c5c-8d44-54ef52e523ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909021278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.1909021278
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.3088232070
Short name T648
Test name
Test status
Simulation time 135707019640 ps
CPU time 138.12 seconds
Started Jul 27 04:52:25 PM PDT 24
Finished Jul 27 04:54:43 PM PDT 24
Peak memory 254764 kb
Host smart-93b33e54-663f-401a-8666-75f25aead453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088232070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.3088232070
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.1486323052
Short name T190
Test name
Test status
Simulation time 15123650586 ps
CPU time 94.9 seconds
Started Jul 27 04:52:15 PM PDT 24
Finished Jul 27 04:53:50 PM PDT 24
Peak memory 254552 kb
Host smart-6a2d7fcd-d82a-4305-ad5b-da4ae53fe659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486323052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.1486323052
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.3249761283
Short name T328
Test name
Test status
Simulation time 73562198891 ps
CPU time 367.3 seconds
Started Jul 27 04:52:25 PM PDT 24
Finished Jul 27 04:58:32 PM PDT 24
Peak memory 268996 kb
Host smart-72e62e80-1bb9-4630-8e04-d822af8d804a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249761283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.3249761283
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.761580081
Short name T939
Test name
Test status
Simulation time 7869560767 ps
CPU time 33.1 seconds
Started Jul 27 04:52:24 PM PDT 24
Finished Jul 27 04:53:02 PM PDT 24
Peak memory 250068 kb
Host smart-a4bab230-60be-425e-86cd-bfbb3d3a9bc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761580081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.761580081
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.80863993
Short name T82
Test name
Test status
Simulation time 26773980285 ps
CPU time 68.38 seconds
Started Jul 27 04:52:30 PM PDT 24
Finished Jul 27 04:53:39 PM PDT 24
Peak memory 250064 kb
Host smart-6cb1f2ae-3918-45c2-8d82-c4d0b7cc5a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80863993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds.80863993
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_intercept.486749779
Short name T524
Test name
Test status
Simulation time 148367471 ps
CPU time 2.4 seconds
Started Jul 27 04:52:09 PM PDT 24
Finished Jul 27 04:52:11 PM PDT 24
Peak memory 233220 kb
Host smart-10a312a2-d459-4d74-b809-bef624b8acbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486749779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.486749779
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.2644456033
Short name T1025
Test name
Test status
Simulation time 332683746 ps
CPU time 8.87 seconds
Started Jul 27 04:52:15 PM PDT 24
Finished Jul 27 04:52:24 PM PDT 24
Peak memory 225444 kb
Host smart-bbb72be8-325a-440d-90f0-754fded59c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644456033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.2644456033
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.3615097976
Short name T793
Test name
Test status
Simulation time 183875894 ps
CPU time 1.1 seconds
Started Jul 27 04:52:13 PM PDT 24
Finished Jul 27 04:52:15 PM PDT 24
Peak memory 217308 kb
Host smart-f359c65c-a63a-4a67-a7bc-a0488fe0ba5b
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615097976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.spi_device_mem_parity.3615097976
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.3917329632
Short name T626
Test name
Test status
Simulation time 3749172415 ps
CPU time 12.36 seconds
Started Jul 27 04:52:09 PM PDT 24
Finished Jul 27 04:52:21 PM PDT 24
Peak memory 233564 kb
Host smart-15d33b5a-66f6-475f-be3a-03b09859a3ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917329632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.3917329632
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.223796313
Short name T209
Test name
Test status
Simulation time 255961874 ps
CPU time 4.56 seconds
Started Jul 27 04:52:33 PM PDT 24
Finished Jul 27 04:52:38 PM PDT 24
Peak memory 233524 kb
Host smart-77e407d0-e62a-431e-a1d1-5c3f077dbee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223796313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.223796313
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.1769418165
Short name T903
Test name
Test status
Simulation time 3905909812 ps
CPU time 6.06 seconds
Started Jul 27 04:52:36 PM PDT 24
Finished Jul 27 04:52:42 PM PDT 24
Peak memory 220128 kb
Host smart-083e4b35-899a-47d7-9d8d-fb58a17bc9b3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1769418165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.1769418165
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.1747253335
Short name T538
Test name
Test status
Simulation time 6397506052 ps
CPU time 18.06 seconds
Started Jul 27 04:52:11 PM PDT 24
Finished Jul 27 04:52:29 PM PDT 24
Peak memory 217200 kb
Host smart-e1737620-24f9-41b9-8bb0-da5084f46c01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747253335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.1747253335
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.1120916579
Short name T875
Test name
Test status
Simulation time 5879419078 ps
CPU time 17.7 seconds
Started Jul 27 04:52:17 PM PDT 24
Finished Jul 27 04:52:35 PM PDT 24
Peak memory 217108 kb
Host smart-7d01094c-d57a-4f68-b5b0-e4d80a36ca5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120916579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.1120916579
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.3479798482
Short name T326
Test name
Test status
Simulation time 37450891 ps
CPU time 1.56 seconds
Started Jul 27 04:52:26 PM PDT 24
Finished Jul 27 04:52:27 PM PDT 24
Peak memory 217132 kb
Host smart-823216ee-4542-47a4-b3a3-03b29c1e6f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479798482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.3479798482
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.1333125955
Short name T351
Test name
Test status
Simulation time 420582484 ps
CPU time 0.89 seconds
Started Jul 27 04:52:22 PM PDT 24
Finished Jul 27 04:52:23 PM PDT 24
Peak memory 206976 kb
Host smart-067d747e-299c-49d5-ab2b-e6ae2538eff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333125955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.1333125955
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.2672998654
Short name T474
Test name
Test status
Simulation time 917911800 ps
CPU time 7.38 seconds
Started Jul 27 04:52:28 PM PDT 24
Finished Jul 27 04:52:36 PM PDT 24
Peak memory 225400 kb
Host smart-f73ef669-93f5-4449-af42-0a31dbb4aef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672998654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.2672998654
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.504848775
Short name T376
Test name
Test status
Simulation time 19495245 ps
CPU time 0.74 seconds
Started Jul 27 04:52:15 PM PDT 24
Finished Jul 27 04:52:16 PM PDT 24
Peak memory 206032 kb
Host smart-df083ec9-97b6-4c6c-a18e-fb1257c90e37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504848775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.504848775
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.1290051168
Short name T800
Test name
Test status
Simulation time 297781734 ps
CPU time 2.28 seconds
Started Jul 27 04:52:33 PM PDT 24
Finished Jul 27 04:52:35 PM PDT 24
Peak memory 225356 kb
Host smart-47aabd9c-87ec-4c61-9a5d-e8f19fe0f5fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290051168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.1290051168
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.3336322288
Short name T641
Test name
Test status
Simulation time 15068818 ps
CPU time 0.72 seconds
Started Jul 27 04:52:23 PM PDT 24
Finished Jul 27 04:52:24 PM PDT 24
Peak memory 206128 kb
Host smart-7fac1e7f-a857-4994-a987-cd979c63d380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336322288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.3336322288
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.3572195613
Short name T461
Test name
Test status
Simulation time 78885899 ps
CPU time 0.82 seconds
Started Jul 27 04:52:16 PM PDT 24
Finished Jul 27 04:52:17 PM PDT 24
Peak memory 216496 kb
Host smart-573dd042-3882-460d-b2a3-ca99481dc39d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572195613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.3572195613
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.3170757577
Short name T38
Test name
Test status
Simulation time 6312193443 ps
CPU time 62.03 seconds
Started Jul 27 04:52:33 PM PDT 24
Finished Jul 27 04:53:35 PM PDT 24
Peak memory 269132 kb
Host smart-1bd3a5c4-b1c6-4172-b4b8-1ba7f451b069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170757577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.3170757577
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.2385576524
Short name T286
Test name
Test status
Simulation time 19931748959 ps
CPU time 193.59 seconds
Started Jul 27 04:52:26 PM PDT 24
Finished Jul 27 04:55:40 PM PDT 24
Peak memory 267336 kb
Host smart-3641135d-76b2-4143-9dec-78ac88224932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385576524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.2385576524
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.1821151108
Short name T233
Test name
Test status
Simulation time 457293339 ps
CPU time 4.43 seconds
Started Jul 27 04:52:30 PM PDT 24
Finished Jul 27 04:52:35 PM PDT 24
Peak memory 233600 kb
Host smart-ca7671a3-fd90-424c-81ac-388ce27db2c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821151108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.1821151108
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.817150465
Short name T282
Test name
Test status
Simulation time 45903156071 ps
CPU time 82.54 seconds
Started Jul 27 04:52:31 PM PDT 24
Finished Jul 27 04:53:54 PM PDT 24
Peak memory 265048 kb
Host smart-645cec30-1e6b-422a-a270-851ccf79df63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817150465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds.
817150465
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/8.spi_device_intercept.2839009953
Short name T217
Test name
Test status
Simulation time 1813769675 ps
CPU time 14.22 seconds
Started Jul 27 04:52:31 PM PDT 24
Finished Jul 27 04:52:46 PM PDT 24
Peak memory 233584 kb
Host smart-9bb1c704-9e38-499e-af82-a386671f86ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839009953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.2839009953
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.117051687
Short name T10
Test name
Test status
Simulation time 38195882159 ps
CPU time 30.78 seconds
Started Jul 27 04:52:32 PM PDT 24
Finished Jul 27 04:53:03 PM PDT 24
Peak memory 241484 kb
Host smart-e933aeb6-afa6-4478-a154-4de6bde0979d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117051687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.117051687
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.1922657931
Short name T936
Test name
Test status
Simulation time 147215926 ps
CPU time 1.02 seconds
Started Jul 27 04:52:17 PM PDT 24
Finished Jul 27 04:52:18 PM PDT 24
Peak memory 218528 kb
Host smart-1ac46c9d-7b9a-492c-b225-5bce7599df9f
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922657931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.spi_device_mem_parity.1922657931
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.1407288447
Short name T429
Test name
Test status
Simulation time 22074176231 ps
CPU time 16.67 seconds
Started Jul 27 04:52:40 PM PDT 24
Finished Jul 27 04:52:56 PM PDT 24
Peak memory 233504 kb
Host smart-5db88f81-b0dc-4dda-a94e-b73cc4f84982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407288447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.1407288447
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.3384918341
Short name T1006
Test name
Test status
Simulation time 567711306 ps
CPU time 7.41 seconds
Started Jul 27 04:52:27 PM PDT 24
Finished Jul 27 04:52:34 PM PDT 24
Peak memory 233684 kb
Host smart-448149cd-ec6f-4415-be6b-29b942c4ff89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384918341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.3384918341
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.2420848265
Short name T569
Test name
Test status
Simulation time 3846980702 ps
CPU time 23.14 seconds
Started Jul 27 04:52:27 PM PDT 24
Finished Jul 27 04:52:50 PM PDT 24
Peak memory 222812 kb
Host smart-357f3d08-68b4-4675-a380-383bc64942cb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2420848265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.2420848265
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.3931277492
Short name T18
Test name
Test status
Simulation time 155962452 ps
CPU time 0.93 seconds
Started Jul 27 04:52:31 PM PDT 24
Finished Jul 27 04:52:32 PM PDT 24
Peak memory 208160 kb
Host smart-2068f5a0-9539-4e37-9a67-c423681acbe5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931277492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.3931277492
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.3780305123
Short name T1029
Test name
Test status
Simulation time 18021273739 ps
CPU time 15.7 seconds
Started Jul 27 04:52:29 PM PDT 24
Finished Jul 27 04:52:44 PM PDT 24
Peak memory 220908 kb
Host smart-2887af20-b74b-429b-bcdf-7bcfdf8c1538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780305123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.3780305123
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.909292489
Short name T401
Test name
Test status
Simulation time 2545537315 ps
CPU time 7.88 seconds
Started Jul 27 04:52:17 PM PDT 24
Finished Jul 27 04:52:25 PM PDT 24
Peak memory 217104 kb
Host smart-decd4a5e-211a-4c0d-b001-c4d013c54085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909292489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.909292489
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.3618488756
Short name T918
Test name
Test status
Simulation time 81101595 ps
CPU time 1.07 seconds
Started Jul 27 04:52:19 PM PDT 24
Finished Jul 27 04:52:20 PM PDT 24
Peak memory 207744 kb
Host smart-48cd654e-112e-4e0e-9a33-7c4a0afe818d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618488756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.3618488756
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.1985588006
Short name T327
Test name
Test status
Simulation time 65295093 ps
CPU time 0.97 seconds
Started Jul 27 04:52:18 PM PDT 24
Finished Jul 27 04:52:19 PM PDT 24
Peak memory 206928 kb
Host smart-ed3abab8-e6f2-4948-a02a-e579b536fc4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985588006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.1985588006
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.2477229952
Short name T408
Test name
Test status
Simulation time 13117269801 ps
CPU time 10.6 seconds
Started Jul 27 04:52:14 PM PDT 24
Finished Jul 27 04:52:25 PM PDT 24
Peak memory 233572 kb
Host smart-931fdc34-600b-458d-8080-dafe02cab89d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477229952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.2477229952
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.1736449387
Short name T889
Test name
Test status
Simulation time 17453880 ps
CPU time 0.72 seconds
Started Jul 27 04:52:27 PM PDT 24
Finished Jul 27 04:52:27 PM PDT 24
Peak memory 205412 kb
Host smart-6172077f-58f8-4f17-8dd3-33a79689654d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736449387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.1
736449387
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.1318768286
Short name T719
Test name
Test status
Simulation time 601077335 ps
CPU time 3.95 seconds
Started Jul 27 04:52:29 PM PDT 24
Finished Jul 27 04:52:33 PM PDT 24
Peak memory 233700 kb
Host smart-ce015ea0-f2a1-4172-97bc-fca2413cd4ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318768286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.1318768286
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.71110588
Short name T365
Test name
Test status
Simulation time 24512097 ps
CPU time 0.8 seconds
Started Jul 27 04:52:27 PM PDT 24
Finished Jul 27 04:52:28 PM PDT 24
Peak memory 206088 kb
Host smart-144edc96-e524-47d2-a6f6-285c1676c633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71110588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.71110588
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.1111043813
Short name T335
Test name
Test status
Simulation time 17307686 ps
CPU time 0.87 seconds
Started Jul 27 04:52:36 PM PDT 24
Finished Jul 27 04:52:38 PM PDT 24
Peak memory 216260 kb
Host smart-efa4e1ac-1d6f-4894-b1ed-40aaa2e4f5ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111043813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.1111043813
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.3385789887
Short name T961
Test name
Test status
Simulation time 9338156328 ps
CPU time 142.93 seconds
Started Jul 27 04:52:39 PM PDT 24
Finished Jul 27 04:55:02 PM PDT 24
Peak memory 273836 kb
Host smart-20a6c567-1c44-440d-bbf8-858489438b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385789887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.3385789887
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.3452693676
Short name T883
Test name
Test status
Simulation time 42004398766 ps
CPU time 384.24 seconds
Started Jul 27 04:52:28 PM PDT 24
Finished Jul 27 04:58:52 PM PDT 24
Peak memory 259724 kb
Host smart-7346c112-0cd8-4fd2-a533-b67a962b8a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452693676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.3452693676
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.2361510009
Short name T887
Test name
Test status
Simulation time 2567370556 ps
CPU time 5.8 seconds
Started Jul 27 04:52:25 PM PDT 24
Finished Jul 27 04:52:31 PM PDT 24
Peak memory 233720 kb
Host smart-e4cc8d86-59ae-4015-9f00-dfc84047f227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361510009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.2361510009
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.1148934579
Short name T864
Test name
Test status
Simulation time 466263023692 ps
CPU time 340.88 seconds
Started Jul 27 04:52:23 PM PDT 24
Finished Jul 27 04:58:04 PM PDT 24
Peak memory 255552 kb
Host smart-a6e10205-8b8f-418a-a09e-d741cd11f035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148934579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds
.1148934579
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_intercept.1326550181
Short name T740
Test name
Test status
Simulation time 1393553362 ps
CPU time 8.3 seconds
Started Jul 27 04:52:28 PM PDT 24
Finished Jul 27 04:52:36 PM PDT 24
Peak memory 233528 kb
Host smart-8914b230-b037-4b1e-8262-d3d23d07e2e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326550181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.1326550181
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.2578332743
Short name T453
Test name
Test status
Simulation time 4609495918 ps
CPU time 50.03 seconds
Started Jul 27 04:52:23 PM PDT 24
Finished Jul 27 04:53:13 PM PDT 24
Peak memory 233652 kb
Host smart-06eeae8a-7396-42ad-bc1f-b47a533be8b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578332743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.2578332743
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.3883297702
Short name T470
Test name
Test status
Simulation time 106948339 ps
CPU time 1.04 seconds
Started Jul 27 04:52:29 PM PDT 24
Finished Jul 27 04:52:30 PM PDT 24
Peak memory 218576 kb
Host smart-6ef13137-48e7-49be-ac49-9fb73c5445b2
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883297702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.spi_device_mem_parity.3883297702
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.2262673093
Short name T804
Test name
Test status
Simulation time 1130590683 ps
CPU time 4.89 seconds
Started Jul 27 04:52:30 PM PDT 24
Finished Jul 27 04:52:35 PM PDT 24
Peak memory 225328 kb
Host smart-3a4b9019-a4d1-44c1-af7f-1f78d1890f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262673093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.2262673093
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.2287812246
Short name T697
Test name
Test status
Simulation time 73495825 ps
CPU time 2.35 seconds
Started Jul 27 04:52:36 PM PDT 24
Finished Jul 27 04:52:39 PM PDT 24
Peak memory 233544 kb
Host smart-f80863ae-2197-443a-a70a-1b5d8643ece0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287812246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.2287812246
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.1879334366
Short name T884
Test name
Test status
Simulation time 3628586588 ps
CPU time 7.53 seconds
Started Jul 27 04:52:31 PM PDT 24
Finished Jul 27 04:52:39 PM PDT 24
Peak memory 222284 kb
Host smart-5f151e64-8d60-45e2-8a0a-1ee179f9b29c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1879334366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.1879334366
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.3487989876
Short name T587
Test name
Test status
Simulation time 38431713 ps
CPU time 0.97 seconds
Started Jul 27 04:52:28 PM PDT 24
Finished Jul 27 04:52:30 PM PDT 24
Peak memory 207276 kb
Host smart-81da6da5-0458-48e7-bed6-3f62f7a815f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487989876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.3487989876
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.658923374
Short name T644
Test name
Test status
Simulation time 3191375152 ps
CPU time 6.02 seconds
Started Jul 27 04:52:15 PM PDT 24
Finished Jul 27 04:52:21 PM PDT 24
Peak memory 217156 kb
Host smart-84687405-172f-4eb5-b0e1-bc917a49d1b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658923374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.658923374
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.2362700363
Short name T423
Test name
Test status
Simulation time 18409364 ps
CPU time 0.7 seconds
Started Jul 27 04:52:20 PM PDT 24
Finished Jul 27 04:52:20 PM PDT 24
Peak memory 206208 kb
Host smart-c75d11a5-6136-44b2-8b25-95122987f3e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362700363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.2362700363
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.3294198078
Short name T589
Test name
Test status
Simulation time 5560301500 ps
CPU time 8.09 seconds
Started Jul 27 04:52:26 PM PDT 24
Finished Jul 27 04:52:35 PM PDT 24
Peak memory 217104 kb
Host smart-7df30079-5594-473f-b209-84d0595e7639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294198078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.3294198078
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.375416448
Short name T739
Test name
Test status
Simulation time 174762120 ps
CPU time 0.86 seconds
Started Jul 27 04:52:36 PM PDT 24
Finished Jul 27 04:52:38 PM PDT 24
Peak memory 207000 kb
Host smart-f2e1061f-2c65-460e-94d3-b727bbe3ab2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375416448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.375416448
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.420211926
Short name T908
Test name
Test status
Simulation time 3992386556 ps
CPU time 13.96 seconds
Started Jul 27 04:52:27 PM PDT 24
Finished Jul 27 04:52:41 PM PDT 24
Peak memory 233644 kb
Host smart-dc6b841e-36fe-4350-927b-4ef82bf3671c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420211926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.420211926
Directory /workspace/9.spi_device_upload/latest
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