Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2959892	1			T1	1		T2	1		T3	297
all_values[1]	2959892	1			T1	1		T2	1		T3	297
all_values[2]	2959892	1			T1	1		T2	1		T3	297
all_values[3]	2959892	1			T1	1		T2	1		T3	297
all_values[4]	2959892	1			T1	1		T2	1		T3	297
all_values[5]	2959892	1			T1	1		T2	1		T3	297
all_values[6]	2959892	1			T1	1		T2	1		T3	297
all_values[7]	2959892	1			T1	1		T2	1		T3	297

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23407020

1

T1

8

T2

8

T3

2376

auto[1]

272116

1

T17

31

T18

36

T20

1214

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23647298

1

T1

8

T2

8

T3

2376

auto[1]

31838

1

T12

209

T14

6

T33

161

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2909661	1			T1	1		T2	1		T3	297
all_values[0]	auto[0]	auto[1]	15638	1			T12	102		T14	2		T33	82
all_values[0]	auto[1]	auto[0]	34301	1			T17	3		T18	2		T20	235
all_values[0]	auto[1]	auto[1]	292	1			T17	2		T18	1		T20	2
all_values[1]	auto[0]	auto[0]	2938502	1			T1	1		T2	1		T3	297
all_values[1]	auto[0]	auto[1]	10195	1			T12	86		T14	2		T33	59
all_values[1]	auto[1]	auto[0]	11011	1			T17	3		T18	1		T20	5
all_values[1]	auto[1]	auto[1]	184	1			T17	2		T20	4		T21	6
all_values[2]	auto[0]	auto[0]	2924633	1			T1	1		T2	1		T3	297
all_values[2]	auto[0]	auto[1]	3434	1			T12	21		T14	2		T33	20
all_values[2]	auto[1]	auto[0]	31626	1			T18	3		T20	233		T21	6
all_values[2]	auto[1]	auto[1]	199	1			T17	1		T18	2		T20	6
all_values[3]	auto[0]	auto[0]	2926877	1			T1	1		T2	1		T3	297
all_values[3]	auto[0]	auto[1]	201	1			T17	5		T18	1		T20	3
all_values[3]	auto[1]	auto[0]	32649	1			T18	4		T20	234		T21	4
all_values[3]	auto[1]	auto[1]	165	1			T17	1		T18	3		T20	3
all_values[4]	auto[0]	auto[0]	2927734	1			T1	1		T2	1		T3	297
all_values[4]	auto[0]	auto[1]	220	1			T17	3		T18	2		T20	1
all_values[4]	auto[1]	auto[0]	31742	1			T17	3		T18	2		T20	5
all_values[4]	auto[1]	auto[1]	196	1			T17	1		T18	4		T20	4
all_values[5]	auto[0]	auto[0]	2890103	1			T1	1		T2	1		T3	297
all_values[5]	auto[0]	auto[1]	184	1			T17	1		T18	3		T20	4
all_values[5]	auto[1]	auto[0]	69442	1			T17	3		T18	5		T20	233
all_values[5]	auto[1]	auto[1]	163	1			T17	2		T20	3		T21	4
all_values[6]	auto[0]	auto[0]	2925456	1			T1	1		T2	1		T3	297
all_values[6]	auto[0]	auto[1]	184	1			T18	1		T20	3		T21	3
all_values[6]	auto[1]	auto[0]	34048	1			T17	2		T18	2		T20	7
all_values[6]	auto[1]	auto[1]	204	1			T17	4		T18	2		T20	2
all_values[7]	auto[0]	auto[0]	2933798	1			T1	1		T2	1		T3	297
all_values[7]	auto[0]	auto[1]	200	1			T17	2		T20	1		T21	1
all_values[7]	auto[1]	auto[0]	25715	1			T17	1		T18	5		T20	234
all_values[7]	auto[1]	auto[1]	179	1			T17	3		T20	4		T21	6