Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	33993	1			T1	4		T12	111		T14	166
auto[SpiFlashAddrCfg]	7989	1			T2	4		T3	2		T12	23
auto[SpiFlashAddr3b]	9423	1			T1	8		T2	4		T3	8
auto[SpiFlashAddr4b]	7772	1			T1	8		T2	4		T3	4

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33375

1

T3

14

T12

110

T13

5

auto[1]

25802

1

T1

20

T2

12

T12

74

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32061

1

T1

8

T2

8

T3

10

auto[1]

27116

1

T1

12

T2

4

T3

4

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	38829	1			T1	8		T2	2		T12	116
values[1]	1113	1			T2	4		T3	2		T12	7
values[2]	1587	1			T12	3		T13	1		T14	1
values[3]	1573	1			T1	2		T12	2		T14	3
values[4]	1567	1			T1	6		T12	5		T13	4
values[5]	1560	1			T3	2		T12	3		T14	2
values[6]	1370	1			T1	4		T12	8		T14	8
values[7]	1618	1			T3	8		T12	6		T14	2
values[8]	9960	1			T2	6		T3	2		T12	34

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32532

1

T1

20

T2

12

T3

14

auto[1]

26645

1

T12

184

T13

5

T38

80

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

55801

1

T1

20

T2

10

T3

14

write

3376

1

T2

2

T12

12

T14

11

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

19802

1

T1

10

T2

2

T3

8

valids[0x1]

39375

1

T1

10

T2

10

T3

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1587	1			T12	10		T14	1		T38	3
internal_process_ops[0x5a]	1560	1			T1	4		T3	4		T12	5
internal_process_ops[0x05]	19704	1			T1	4		T12	52		T14	143
internal_process_ops[0x35]	1645	1			T12	5		T14	3		T38	2
internal_process_ops[0x15]	1625	1			T12	2		T14	3		T38	2
internal_process_ops[0x03]	1108	1			T14	1		T38	2		T33	3
internal_process_ops[0x0b]	1131	1			T2	4		T12	1		T38	2
internal_process_ops[0x3b]	1087	1			T12	2		T13	1		T14	3
internal_process_ops[0x6b]	1135	1			T1	4		T12	2		T14	1
internal_process_ops[0xbb]	1161	1			T1	6		T12	3		T13	2
internal_process_ops[0xeb]	1090	1			T12	2		T13	2		T14	3

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

57519

1

T1

20

T2

10

T3

14

auto[1]

1658

1

T2

2

T12

9

T14

5

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

56679

1

T1

20

T2

12

T3

14

auto[1]

2498

1

T12

10

T14

6

T38

8

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10325

1

T14

155

T49

8

T33

18

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6933

1

T1

4

T14

8

T33

17

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2284

1

T3

2

T14

12

T49

2

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

2019

1

T2

4

T14

7

T33

13

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2640

1

T3

8

T14

5

T49

6

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2338

1

T1

8

T2

4

T14

8

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2158

1

T3

4

T14

12

T49

4

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

2005

1

T1

8

T2

2

T14

4

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

136

1

T178

2

T179

2

T50

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

106

1

T14

2

T52

3

T21

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

86

1

T16

3

T19

1

T50

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

118

1

T14

1

T48

1

T50

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

101

1

T14

1

T28

4

T50

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

110

1

T14

1

T48

2

T50

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

137

1

T33

5

T26

1

T16

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

134

1

T14

1

T48

3

T50

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

143

1

T14

5

T33

2

T180

6

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

97

1

T16

1

T48

2

T57

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

99

1

T33

3

T48

5

T50

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

128

1

T52

1

T21

1

T181

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

118

1

T16

1

T178

4

T50

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

93

1

T33

1

T16

3

T21

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

119

1

T16

4

T48

2

T19

4

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

105

1

T2

2

T16

2

T51

4

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9682

1

T12

65

T38

27

T15

158

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6215

1

T12

38

T38

6

T15

193

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1389

1

T12

13

T13

3

T38

4

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1423

1

T12

9

T38

10

T15

30

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1807

1

T12

15

T13

2

T38

6

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1795

1

T12

14

T38

11

T15

25

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1409

1

T12

7

T38

3

T15

29

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1379

1

T12

11

T38

5

T15

18

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

86

1

T12

1

T38

4

T16

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

123

1

T12

7

T15

1

T16

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

101

1

T15

1

T16

2

T17

7

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

82

1

T15

1

T16

2

T91

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

85

1

T16

9

T17

1

T48

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

104

1

T12

1

T15

4

T17

4

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

110

1

T38

1

T16

1

T17

5

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

93

1

T38

2

T90

2

T19

4

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

94

1

T15

2

T16

1

T17

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

97

1

T12

1

T15

2

T16

4

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

97

1

T12

1

T15

2

T16

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

88

1

T17

2

T90

2

T182

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

108

1

T16

2

T17

2

T18

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

80

1

T15

1

T16

1

T17

4

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

98

1

T12

1

T15

7

T16

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

100

1

T38

1

T15

1

T16

4

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	4162	1			T14	6		T33	10		T26	12
auto[0]	values[0]	valids[0x1]	16404	1			T1	8		T2	2		T14	165
auto[0]	values[1]	valids[0x1]	587	1			T2	4		T3	2		T14	2
auto[0]	values[2]	valids[0x0]	620	1			T33	3		T16	2		T51	6
auto[0]	values[2]	valids[0x1]	344	1			T14	1		T33	2		T16	1
auto[0]	values[3]	valids[0x0]	655	1			T14	2		T26	5		T183	4
auto[0]	values[3]	valids[0x1]	298	1			T1	2		T14	1		T33	1
auto[0]	values[4]	valids[0x0]	632	1			T1	6		T14	3		T33	7
auto[0]	values[4]	valids[0x1]	346	1			T14	4		T49	2		T102	4
auto[0]	values[5]	valids[0x0]	616	1			T3	2		T14	1		T49	4
auto[0]	values[5]	valids[0x1]	293	1			T14	1		T33	3		T180	2
auto[0]	values[6]	valids[0x0]	501	1			T1	4		T14	8		T49	4
auto[0]	values[6]	valids[0x1]	257	1			T25	2		T26	1		T184	2
auto[0]	values[7]	valids[0x0]	601	1			T3	4		T33	1		T26	3
auto[0]	values[7]	valids[0x1]	332	1			T3	4		T14	2		T25	4
auto[0]	values[8]	valids[0x0]	3711	1			T2	2		T3	2		T14	22
auto[0]	values[8]	valids[0x1]	2173	1			T2	4		T14	4		T49	6
auto[1]	values[0]	valids[0x0]	3771	1			T12	25		T38	26		T15	65
auto[1]	values[0]	valids[0x1]	14492	1			T12	91		T38	20		T15	331
auto[1]	values[1]	valids[0x1]	526	1			T12	7		T38	5		T15	19
auto[1]	values[2]	valids[0x0]	383	1			T12	3		T13	1		T38	1
auto[1]	values[2]	valids[0x1]	240	1			T15	8		T16	5		T17	3
auto[1]	values[3]	valids[0x0]	337	1			T12	1		T38	1		T15	8
auto[1]	values[3]	valids[0x1]	283	1			T12	1		T38	2		T15	2
auto[1]	values[4]	valids[0x0]	355	1			T12	5		T13	4		T38	1
auto[1]	values[4]	valids[0x1]	234	1			T38	2		T15	7		T16	7
auto[1]	values[5]	valids[0x0]	363	1			T38	3		T16	9		T17	8
auto[1]	values[5]	valids[0x1]	288	1			T12	3		T38	2		T15	6
auto[1]	values[6]	valids[0x0]	377	1			T12	7		T38	1		T15	3
auto[1]	values[6]	valids[0x1]	235	1			T12	1		T15	2		T17	8
auto[1]	values[7]	valids[0x0]	385	1			T12	6		T15	4		T16	1
auto[1]	values[7]	valids[0x1]	300	1			T15	2		T24	1		T16	6
auto[1]	values[8]	valids[0x0]	2333	1			T12	16		T38	12		T15	26
auto[1]	values[8]	valids[0x1]	1743	1			T12	18		T38	4		T15	31