Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3556365

1

T1

1

T2

1

T3

1

auto[1]

31821

1

T12

44

T14

144

T38

124

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

888620

1

T1

1

T2

1

T3

1

auto[1]

2699566

1

T12

6539

T14

2285

T38

1387

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	644593	1			T1	1		T2	1		T3	1
auto[524288:1048575]	428044	1			T5	2128		T12	539		T13	3
auto[1048576:1572863]	438780	1			T5	217		T13	4		T14	787
auto[1572864:2097151]	377418	1			T5	4		T12	259		T13	17
auto[2097152:2621439]	409870	1			T5	1365		T12	134		T45	2
auto[2621440:3145727]	427170	1			T5	399		T7	1		T12	1208
auto[3145728:3670015]	432362	1			T5	1255		T12	3420		T14	130
auto[3670016:4194303]	429949	1			T5	1348		T12	10		T13	230

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2735386

1

T1

1

T2

1

T3

1

auto[1]

852800

1

T5

6817

T13

455

T14

2

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3107910

1

T1

1

T2

1

T3

1

auto[1]

480276

1

T12

1276

T14

11

T38

454

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	154322	1			T1	1		T2	1		T3	1
auto[0]	auto[0]	auto[0:524287]	auto[1]	415107	1			T12	1		T14	1374		T49	5870
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	98890	1			T5	2128		T12	3		T13	3
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	276588	1			T12	258		T38	128		T33	1929
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	102559	1			T5	217		T13	4		T14	5
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	272173	1			T14	646		T38	4		T33	1
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	83678	1			T5	4		T12	1		T13	17
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	224523	1			T12	257		T15	593		T16	2685
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	103399	1			T5	1365		T12	3		T45	2
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	261229	1			T12	129		T33	256		T15	2257
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	123463	1			T5	399		T7	1		T12	11
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	244721	1			T12	1177		T33	2		T15	263
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	127328	1			T5	1255		T12	3		T14	2
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	231140	1			T12	3415		T14	128		T38	871
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	85067	1			T5	1348		T12	5		T13	230
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	277022	1			T12	1		T15	768		T26	128
auto[0]	auto[1]	auto[0:524287]	auto[0]	955	1			T12	1		T14	4		T33	1
auto[0]	auto[1]	auto[0:524287]	auto[1]	68898	1			T12	1007		T33	1		T15	149
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	456	1			T12	5		T38	7		T15	1
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	48695	1			T12	260		T15	1664		T17	257
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	553	1			T38	4		T15	1		T16	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	60277	1			T15	24		T17	1		T18	128
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	1495	1			T12	1		T38	12		T33	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	62444	1			T38	128		T16	518		T48	2599
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	560	1			T38	3		T33	1		T15	5
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	41168	1			T15	1582		T16	2835		T17	1629
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	569	1			T38	11		T29	2		T16	1
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	53638	1			T38	161		T16	517		T17	130
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	446	1			T15	4		T16	2		T17	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	69800	1			T15	1345		T16	512		T17	2492
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	719	1			T14	3		T38	16		T15	3
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	64483	1			T14	1		T15	644		T16	2325
auto[1]	auto[0]	auto[0:524287]	auto[0]	495	1			T12	1		T14	1		T33	1
auto[1]	auto[0]	auto[0:524287]	auto[1]	4479	1			T12	2		T14	4		T33	2
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	426	1			T12	2		T33	1		T26	1
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	2688	1			T12	9		T33	1		T26	2
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	392	1			T14	6		T33	1		T15	2
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2298	1			T14	130		T15	12		T16	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	420	1			T15	1		T16	1		T17	3
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	3822	1			T15	8		T16	1		T17	37
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	429	1			T12	1		T16	6		T17	5
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2671	1			T12	1		T16	14		T17	82
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	431	1			T12	3		T38	3		T33	2
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	2803	1			T12	17		T33	1		T15	4
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	418	1			T12	1		T38	3		T15	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	2749	1			T12	1		T15	46		T17	57
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	480	1			T12	1		T38	6		T16	4
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	1700	1			T12	3		T16	10		T17	11
auto[1]	auto[1]	auto[0:524287]	auto[0]	90	1			T33	1		T16	1		T17	2
auto[1]	auto[1]	auto[0:524287]	auto[1]	247	1			T16	2		T17	12		T48	1
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	54	1			T12	1		T17	1		T91	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	247	1			T12	1		T17	2		T91	19
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	90	1			T15	1		T17	1		T48	2
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	438	1			T15	1		T17	16		T48	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	115	1			T38	3		T16	1		T48	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	921	1			T16	3		T48	10		T20	17
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	84	1			T15	1		T16	2		T17	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	330	1			T15	2		T19	20		T223	35
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	96	1			T38	9		T16	1		T17	2
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	1449	1			T38	95		T16	15		T17	14
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	70	1			T38	2		T15	1		T100	2
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	411	1			T15	4		T100	60		T35	4
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	71	1			T14	1		T38	3		T15	4
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	407	1			T14	2		T15	71		T16	1

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	2230026	1			T1	1		T2	1		T3	1
auto[0]	auto[0]	auto[1]	851183	1			T5	6817		T13	455		T14	2
auto[0]	auto[1]	auto[0]	474221	1			T12	1274		T14	8		T38	342
auto[0]	auto[1]	auto[1]	935	1			T29	6		T17	3		T97	1
auto[1]	auto[0]	auto[0]	26139	1			T12	42		T14	141		T38	9
auto[1]	auto[0]	auto[1]	562	1			T38	3		T28	3		T16	1
auto[1]	auto[1]	auto[0]	5000	1			T12	2		T14	3		T38	109
auto[1]	auto[1]	auto[1]	120	1			T38	3		T16	2		T17	2