Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2959892	1			T1	1		T2	1		T3	297
all_pins[1]	2959892	1			T1	1		T2	1		T3	297
all_pins[2]	2959892	1			T1	1		T2	1		T3	297
all_pins[3]	2959892	1			T1	1		T2	1		T3	297
all_pins[4]	2959892	1			T1	1		T2	1		T3	297
all_pins[5]	2959892	1			T1	1		T2	1		T3	297
all_pins[6]	2959892	1			T1	1		T2	1		T3	297
all_pins[7]	2959892	1			T1	1		T2	1		T3	297

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	23641408	1			T1	8		T2	8		T3	2376
values[0x1]	37728	1			T17	16		T18	12		T20	89
transitions[0x0=>0x1]	36237	1			T17	9		T18	10		T20	81
transitions[0x1=>0x0]	36251	1			T17	9		T18	10		T20	81

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2959580	1			T1	1		T2	1		T3	297
all_pins[0]	values[0x1]	312	1			T17	2		T18	1		T20	11
all_pins[0]	transitions[0x0=>0x1]	265	1			T17	2		T18	1		T20	11
all_pins[0]	transitions[0x1=>0x0]	149	1			T17	2		T20	4		T21	5
all_pins[1]	values[0x0]	2959696	1			T1	1		T2	1		T3	297
all_pins[1]	values[0x1]	196	1			T17	2		T20	4		T21	6
all_pins[1]	transitions[0x0=>0x1]	139	1			T17	1		T20	4		T21	6
all_pins[1]	transitions[0x1=>0x0]	151	1			T18	2		T20	9		T22	4
all_pins[2]	values[0x0]	2959684	1			T1	1		T2	1		T3	297
all_pins[2]	values[0x1]	208	1			T17	1		T18	2		T20	9
all_pins[2]	transitions[0x0=>0x1]	177	1			T17	1		T18	2		T20	7
all_pins[2]	transitions[0x1=>0x0]	134	1			T17	1		T18	3		T20	1
all_pins[3]	values[0x0]	2959727	1			T1	1		T2	1		T3	297
all_pins[3]	values[0x1]	165	1			T17	1		T18	3		T20	3
all_pins[3]	transitions[0x0=>0x1]	113	1			T17	1		T18	1		T20	3
all_pins[3]	transitions[0x1=>0x0]	144	1			T17	1		T18	2		T20	4
all_pins[4]	values[0x0]	2959696	1			T1	1		T2	1		T3	297
all_pins[4]	values[0x1]	196	1			T17	1		T18	4		T20	4
all_pins[4]	transitions[0x0=>0x1]	155	1			T17	1		T18	4		T20	2
all_pins[4]	transitions[0x1=>0x0]	2510	1			T17	2		T20	50		T21	3
all_pins[5]	values[0x0]	2957341	1			T1	1		T2	1		T3	297
all_pins[5]	values[0x1]	2551	1			T17	2		T20	52		T21	4
all_pins[5]	transitions[0x0=>0x1]	1400	1			T20	51		T21	4		T23	1
all_pins[5]	transitions[0x1=>0x0]	32770	1			T17	2		T18	2		T20	1
all_pins[6]	values[0x0]	2925971	1			T1	1		T2	1		T3	297
all_pins[6]	values[0x1]	33921	1			T17	4		T18	2		T20	2
all_pins[6]	transitions[0x0=>0x1]	33862	1			T17	1		T18	2		T20	1
all_pins[6]	transitions[0x1=>0x0]	120	1			T20	3		T21	5		T22	1
all_pins[7]	values[0x0]	2959713	1			T1	1		T2	1		T3	297
all_pins[7]	values[0x1]	179	1			T17	3		T20	4		T21	6
all_pins[7]	transitions[0x0=>0x1]	126	1			T17	2		T20	2		T21	5
all_pins[7]	transitions[0x1=>0x0]	273	1			T17	1		T18	1		T20	9