Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18311

1

T3

14

T14

193

T49

20

auto[1]

14221

1

T1

20

T2

12

T14

29

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3592	1			T14	20		T102	22		T169	8
values[1]	4761	1			T14	154		T26	20		T28	50
values[2]	3982	1			T3	14		T33	28		T26	20
values[3]	3819	1			T14	23		T25	10		T16	22
values[4]	3707	1			T1	20		T16	49		T48	41
values[5]	4210	1			T16	20		T178	22		T184	14
values[6]	4202	1			T2	12		T14	25		T33	42
values[7]	4259	1			T49	20		T33	20		T26	23

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4420	1			T14	154		T16	21		T245	65
values[1]	3875	1			T1	20		T3	14		T14	20
values[2]	4532	1			T26	20		T16	20		T169	8
values[3]	3827	1			T2	12		T14	25		T33	42
values[4]	3970	1			T49	20		T33	48		T26	20
values[5]	4178	1			T28	50		T183	16		T16	23
values[6]	4135	1			T14	23		T101	8		T102	22
values[7]	3595	1			T25	10		T29	16		T173	16

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	383	1			T245	65		T21	14		T246	12
auto[0]	values[0]	values[1]	416	1			T14	12		T19	35		T50	10
auto[0]	values[0]	values[2]	234	1			T169	8		T50	10		T195	10
auto[0]	values[0]	values[3]	142	1			T247	12		T54	13		T181	15
auto[0]	values[0]	values[4]	134	1			T179	14		T97	18		T205	13
auto[0]	values[0]	values[5]	201	1			T21	23		T216	12		T59	13
auto[0]	values[0]	values[6]	398	1			T48	11		T248	4		T57	14
auto[0]	values[0]	values[7]	178	1			T52	15		T234	12		T205	16
auto[0]	values[1]	values[0]	611	1			T14	146		T54	17		T216	49
auto[0]	values[1]	values[1]	191	1			T195	7		T214	11		T206	7
auto[0]	values[1]	values[2]	591	1			T26	5		T249	4		T22	9
auto[0]	values[1]	values[3]	266	1			T225	14		T65	23		T217	6
auto[0]	values[1]	values[4]	334	1			T53	12		T181	9		T41	13
auto[0]	values[1]	values[5]	256	1			T28	50		T183	16		T50	16
auto[0]	values[1]	values[6]	343	1			T101	8		T57	13		T67	11
auto[0]	values[1]	values[7]	360	1			T222	12		T250	2		T23	60
auto[0]	values[2]	values[0]	280	1			T216	13		T198	17		T251	14
auto[0]	values[2]	values[1]	399	1			T3	14		T50	11		T52	11
auto[0]	values[2]	values[2]	345	1			T181	6		T252	8		T146	6
auto[0]	values[2]	values[3]	130	1			T227	4		T88	2		T65	10
auto[0]	values[2]	values[4]	450	1			T33	6		T26	14		T16	14
auto[0]	values[2]	values[5]	228	1			T50	10		T52	10		T23	11
auto[0]	values[2]	values[6]	288	1			T16	14		T170	10		T253	10
auto[0]	values[2]	values[7]	159	1			T29	16		T48	16		T67	15
auto[0]	values[3]	values[0]	320	1			T48	12		T23	12		T216	9
auto[0]	values[3]	values[1]	153	1			T52	21		T23	27		T65	11
auto[0]	values[3]	values[2]	287	1			T171	6		T57	7		T146	13
auto[0]	values[3]	values[3]	444	1			T16	7		T35	31		T98	11
auto[0]	values[3]	values[4]	269	1			T146	31		T41	14		T254	18
auto[0]	values[3]	values[5]	267	1			T48	17		T255	4		T54	12
auto[0]	values[3]	values[6]	172	1			T14	15		T22	9		T195	3
auto[0]	values[3]	values[7]	218	1			T25	10		T21	13		T198	10
auto[0]	values[4]	values[0]	210	1			T48	13		T198	15		T256	20
auto[0]	values[4]	values[1]	328	1			T52	9		T181	13		T57	9
auto[0]	values[4]	values[2]	169	1			T57	11		T67	11		T217	9
auto[0]	values[4]	values[3]	142	1			T257	4		T23	12		T57	17
auto[0]	values[4]	values[4]	254	1			T54	11		T181	6		T57	9
auto[0]	values[4]	values[5]	390	1			T258	8		T23	15		T259	11
auto[0]	values[4]	values[6]	276	1			T16	13		T54	55		T195	24
auto[0]	values[4]	values[7]	301	1			T48	12		T181	14		T57	10
auto[0]	values[5]	values[0]	196	1			T226	6		T205	9		T60	27
auto[0]	values[5]	values[1]	173	1			T21	11		T54	21		T260	6
auto[0]	values[5]	values[2]	328	1			T178	22		T50	8		T52	21
auto[0]	values[5]	values[3]	218	1			T16	8		T21	13		T195	9
auto[0]	values[5]	values[4]	397	1			T50	22		T53	9		T21	13
auto[0]	values[5]	values[5]	408	1			T85	2		T198	14		T261	16
auto[0]	values[5]	values[6]	175	1			T54	13		T198	10		T262	8
auto[0]	values[5]	values[7]	224	1			T48	14		T59	10		T242	10
auto[0]	values[6]	values[0]	176	1			T16	9		T53	8		T199	8
auto[0]	values[6]	values[1]	218	1			T180	20		T50	10		T54	87
auto[0]	values[6]	values[2]	203	1			T53	13		T35	8		T98	12
auto[0]	values[6]	values[3]	235	1			T14	20		T33	23		T181	14
auto[0]	values[6]	values[4]	275	1			T50	76		T53	9		T217	12
auto[0]	values[6]	values[5]	333	1			T50	10		T52	8		T212	15
auto[0]	values[6]	values[6]	458	1			T53	16		T21	34		T22	14
auto[0]	values[6]	values[7]	347	1			T50	39		T21	8		T54	17
auto[0]	values[7]	values[0]	260	1			T21	50		T23	7		T198	15
auto[0]	values[7]	values[1]	192	1			T26	13		T263	2		T52	15
auto[0]	values[7]	values[2]	280	1			T16	9		T179	13		T48	8
auto[0]	values[7]	values[3]	393	1			T16	12		T22	9		T197	85
auto[0]	values[7]	values[4]	318	1			T49	20		T33	12		T181	11
auto[0]	values[7]	values[5]	434	1			T16	15		T196	14		T50	22
auto[0]	values[7]	values[6]	270	1			T53	25		T264	2		T265	16
auto[0]	values[7]	values[7]	283	1			T48	27		T54	12		T23	9
auto[1]	values[0]	values[0]	272	1			T21	6		T41	21		T212	26
auto[1]	values[0]	values[1]	269	1			T14	8		T229	18		T19	15
auto[1]	values[0]	values[2]	177	1			T50	16		T195	10		T216	53
auto[1]	values[0]	values[3]	127	1			T54	14		T181	5		T165	8
auto[1]	values[0]	values[4]	51	1			T179	6		T205	7		T41	14
auto[1]	values[0]	values[5]	101	1			T21	7		T216	13		T266	2
auto[1]	values[0]	values[6]	314	1			T102	22		T48	10		T57	12
auto[1]	values[0]	values[7]	195	1			T173	16		T52	5		T205	120
auto[1]	values[1]	values[0]	261	1			T14	8		T54	4		T216	8
auto[1]	values[1]	values[1]	150	1			T195	13		T214	9		T206	13
auto[1]	values[1]	values[2]	254	1			T26	15		T22	18		T35	26
auto[1]	values[1]	values[3]	341	1			T65	6		T217	27		T221	14
auto[1]	values[1]	values[4]	179	1			T53	23		T181	11		T241	14
auto[1]	values[1]	values[5]	236	1			T50	9		T67	12		T41	11
auto[1]	values[1]	values[6]	175	1			T57	9		T67	9		T41	11
auto[1]	values[1]	values[7]	213	1			T23	18		T98	9		T65	18
auto[1]	values[2]	values[0]	363	1			T216	150		T198	15		T212	21
auto[1]	values[2]	values[1]	276	1			T219	16		T50	10		T52	9
auto[1]	values[2]	values[2]	247	1			T181	14		T146	18		T267	15
auto[1]	values[2]	values[3]	150	1			T65	18		T215	8		T167	59
auto[1]	values[2]	values[4]	253	1			T33	22		T26	6		T16	6
auto[1]	values[2]	values[5]	225	1			T50	28		T52	10		T23	9
auto[1]	values[2]	values[6]	125	1			T16	9		T170	10		T57	7
auto[1]	values[2]	values[7]	64	1			T48	4		T67	5		T268	8
auto[1]	values[3]	values[0]	252	1			T48	8		T23	8		T237	14
auto[1]	values[3]	values[1]	140	1			T52	19		T23	4		T65	17
auto[1]	values[3]	values[2]	293	1			T57	20		T146	12		T217	28
auto[1]	values[3]	values[3]	166	1			T16	15		T35	15		T98	9
auto[1]	values[3]	values[4]	166	1			T146	16		T41	11		T254	6
auto[1]	values[3]	values[5]	193	1			T48	6		T54	8		T22	7
auto[1]	values[3]	values[6]	283	1			T14	8		T144	22		T22	11
auto[1]	values[3]	values[7]	196	1			T21	9		T198	11		T165	14
auto[1]	values[4]	values[0]	188	1			T48	7		T198	5		T269	24
auto[1]	values[4]	values[1]	217	1			T1	20		T52	11		T181	7
auto[1]	values[4]	values[2]	191	1			T57	15		T67	9		T217	11
auto[1]	values[4]	values[3]	219	1			T23	33		T57	5		T65	25
auto[1]	values[4]	values[4]	255	1			T54	9		T181	14		T57	15
auto[1]	values[4]	values[5]	150	1			T23	5		T259	9		T270	5
auto[1]	values[4]	values[6]	181	1			T16	36		T54	4		T195	16
auto[1]	values[4]	values[7]	236	1			T48	9		T181	6		T57	11
auto[1]	values[5]	values[0]	186	1			T205	43		T60	18		T206	16
auto[1]	values[5]	values[1]	414	1			T21	9		T54	7		T271	2
auto[1]	values[5]	values[2]	366	1			T184	14		T50	13		T52	19
auto[1]	values[5]	values[3]	203	1			T16	12		T21	37		T195	11
auto[1]	values[5]	values[4]	286	1			T50	11		T53	11		T21	14
auto[1]	values[5]	values[5]	160	1			T198	11		T261	4		T57	7
auto[1]	values[5]	values[6]	281	1			T54	24		T198	14		T203	12
auto[1]	values[5]	values[7]	195	1			T243	20		T48	8		T59	31
auto[1]	values[6]	values[0]	316	1			T16	12		T53	12		T146	14
auto[1]	values[6]	values[1]	110	1			T50	10		T54	12		T272	9
auto[1]	values[6]	values[2]	222	1			T53	7		T35	12		T98	8
auto[1]	values[6]	values[3]	325	1			T2	12		T14	5		T33	19
auto[1]	values[6]	values[4]	155	1			T50	4		T53	11		T83	10
auto[1]	values[6]	values[5]	261	1			T50	10		T52	12		T212	14
auto[1]	values[6]	values[6]	293	1			T53	4		T21	12		T22	6
auto[1]	values[6]	values[7]	275	1			T50	10		T21	40		T54	24
auto[1]	values[7]	values[0]	146	1			T21	3		T23	14		T198	5
auto[1]	values[7]	values[1]	229	1			T26	10		T52	5		T272	9
auto[1]	values[7]	values[2]	345	1			T16	11		T179	7		T48	12
auto[1]	values[7]	values[3]	326	1			T16	8		T51	18		T22	11
auto[1]	values[7]	values[4]	194	1			T33	8		T181	9		T195	6
auto[1]	values[7]	values[5]	335	1			T16	8		T50	18		T216	6
auto[1]	values[7]	values[6]	103	1			T53	7		T239	13		T242	8
auto[1]	values[7]	values[7]	151	1			T48	26		T54	21		T23	27