Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	456	1			T14	1		T26	2		T101	4
auto[ReadAddrCrossIntoMailbox]	317	1			T14	2		T16	1		T48	9
auto[ReadAddrCrossOutOfMailbox]	352	1			T14	1		T33	1		T26	1
auto[ReadAddrCrossAllMailbox]	260	1			T16	1		T170	1		T179	1
auto[ReadAddrOutsideMailbox]	3713	1			T1	10		T2	4		T14	10

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2461

1

T1

5

T2

2

T14

5

auto[1]

2637

1

T1

5

T2

2

T14

9

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	833	1			T14	1		T33	3		T25	4
read_ops[0x0b]	855	1			T2	4		T49	2		T33	2
read_ops[0x3b]	820	1			T14	3		T49	4		T33	1
read_ops[0x6b]	862	1			T1	4		T14	1		T33	3
read_ops[0xbb]	886	1			T1	6		T14	6		T33	8
read_ops[0xeb]	842	1			T14	3		T33	1		T25	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	36	1			T16	1		T50	2		T52	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	39	1			T48	1		T54	1		T195	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	31	1			T50	1		T21	1		T23	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	28	1			T181	1		T216	1		T41	2
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	28	1			T195	1		T225	1		T165	2
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	26	1			T53	1		T225	1		T67	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	22	1			T48	1		T98	1		T57	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	19	1			T48	1		T52	1		T216	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	249	1			T33	3		T25	2		T180	2
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	355	1			T14	1		T25	2		T180	2
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	39	1			T48	1		T52	2		T21	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	39	1			T48	1		T248	1		T216	2
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	23	1			T50	1		T52	1		T21	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	20	1			T48	1		T21	1		T195	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	32	1			T179	1		T52	2		T273	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	29	1			T52	1		T41	1		T212	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	24	1			T16	1		T179	1		T21	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	19	1			T21	1		T216	1		T272	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	297	1			T2	2		T49	1		T33	2
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	333	1			T2	2		T49	1		T26	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	35	1			T26	1		T222	1		T50	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	29	1			T14	1		T222	1		T52	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	32	1			T48	2		T54	1		T88	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	20	1			T50	2		T52	1		T53	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	25	1			T216	1		T98	2		T67	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	28	1			T52	1		T216	2		T205	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	19	1			T170	1		T48	3		T181	2
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	19	1			T50	1		T22	1		T274	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	281	1			T49	2		T183	1		T16	2
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	332	1			T14	2		T49	2		T33	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	33	1			T19	1		T22	1		T23	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	34	1			T52	2		T53	1		T216	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	21	1			T48	1		T21	2		T195	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	29	1			T48	1		T52	2		T23	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T50	1		T22	1		T198	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	38	1			T33	1		T26	1		T50	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	24	1			T21	1		T22	2		T85	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	20	1			T195	1		T85	1		T67	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	327	1			T1	2		T33	1		T26	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	313	1			T1	2		T14	1		T33	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	45	1			T101	2		T48	2		T21	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	38	1			T26	1		T101	2		T50	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	27	1			T23	1		T195	1		T216	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	30	1			T195	1		T216	3		T225	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	30	1			T14	1		T48	1		T50	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	26	1			T16	1		T52	2		T181	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	21	1			T52	1		T23	1		T195	2
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	22	1			T216	1		T67	2		T205	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	322	1			T1	3		T14	1		T33	8
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	325	1			T1	3		T14	4		T25	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	48	1			T170	1		T222	1		T52	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	41	1			T222	1		T48	1		T21	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	26	1			T14	2		T16	1		T48	2
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	30	1			T48	2		T50	1		T53	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	36	1			T48	1		T50	1		T216	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	31	1			T48	2		T21	1		T54	2
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	24	1			T53	1		T227	1		T217	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	27	1			T48	1		T227	1		T216	2
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	281	1			T14	1		T25	1		T26	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	298	1			T33	1		T25	1		T16	1