Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3605	1			T14	23		T101	8		T243	20
values[1]	3630	1			T49	20		T33	22		T26	20
values[2]	4138	1			T3	14		T25	10		T26	20
values[3]	3813	1			T1	20		T28	50		T16	49
values[4]	4598	1			T14	45		T183	16		T170	20
values[5]	4647	1			T14	154		T33	20		T26	23
values[6]	4038	1			T2	12		T33	20		T171	6
values[7]	4063	1			T33	28		T102	22		T16	23

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4017	1			T33	42		T16	69		T171	6
values[1]	3520	1			T33	28		T26	23		T102	22
values[2]	3643	1			T14	48		T33	20		T173	16
values[3]	4567	1			T14	20		T26	20		T29	16
values[4]	3991	1			T25	10		T16	64		T222	12
values[5]	4019	1			T1	20		T2	12		T14	154
values[6]	4325	1			T183	16		T16	20		T170	20
values[7]	4450	1			T3	14		T49	20		T26	20

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31641

1

T1

20

T2

10

T3

14

auto[1]

891

1

T2

2

T14

5

T33

1

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	425	1			T50	20		T21	33		T198	29
auto[0]	values[0]	values[1]	426	1			T48	46		T144	22		T52	18
auto[0]	values[0]	values[2]	404	1			T14	22		T48	28		T50	37
auto[0]	values[0]	values[3]	329	1			T54	26		T22	20		T35	20
auto[0]	values[0]	values[4]	295	1			T52	20		T57	19		T212	20
auto[0]	values[0]	values[5]	459	1			T52	17		T262	8		T165	135
auto[0]	values[0]	values[6]	680	1			T23	43		T198	24		T67	19
auto[0]	values[0]	values[7]	488	1			T101	8		T243	20		T181	18
auto[0]	values[1]	values[0]	260	1			T33	22		T50	49		T53	20
auto[0]	values[1]	values[1]	295	1			T218	4		T275	2		T276	4
auto[0]	values[1]	values[2]	261	1			T253	10		T249	4		T277	20
auto[0]	values[1]	values[3]	434	1			T16	18		T278	18		T205	47
auto[0]	values[1]	values[4]	725	1			T16	40		T48	20		T52	20
auto[0]	values[1]	values[5]	419	1			T23	58		T230	22		T273	39
auto[0]	values[1]	values[6]	431	1			T16	18		T263	2		T21	52
auto[0]	values[1]	values[7]	706	1			T49	20		T26	20		T180	20
auto[0]	values[2]	values[0]	666	1			T16	20		T195	19		T216	54
auto[0]	values[2]	values[1]	481	1			T21	22		T195	20		T216	25
auto[0]	values[2]	values[2]	374	1			T53	35		T217	39		T221	20
auto[0]	values[2]	values[3]	612	1			T26	20		T52	20		T54	20
auto[0]	values[2]	values[4]	783	1			T25	10		T50	80		T52	15
auto[0]	values[2]	values[5]	407	1			T52	20		T23	20		T35	19
auto[0]	values[2]	values[6]	279	1			T279	2		T41	23		T206	19
auto[0]	values[2]	values[7]	418	1			T3	14		T16	22		T181	19
auto[0]	values[3]	values[0]	390	1			T16	49		T57	20		T67	20
auto[0]	values[3]	values[1]	498	1			T216	26		T280	6		T246	12
auto[0]	values[3]	values[2]	286	1			T52	15		T85	2		T230	21
auto[0]	values[3]	values[3]	466	1			T179	20		T50	20		T260	6
auto[0]	values[3]	values[4]	264	1			T281	14		T67	18		T212	35
auto[0]	values[3]	values[5]	626	1			T1	20		T51	14		T195	20
auto[0]	values[3]	values[6]	542	1			T52	20		T21	47		T54	20
auto[0]	values[3]	values[7]	642	1			T28	50		T169	8		T196	14
auto[0]	values[4]	values[0]	630	1			T219	16		T22	25		T214	19
auto[0]	values[4]	values[1]	353	1			T282	2		T165	20		T283	18
auto[0]	values[4]	values[2]	424	1			T14	22		T173	16		T179	20
auto[0]	values[4]	values[3]	640	1			T14	20		T48	21		T98	17
auto[0]	values[4]	values[4]	649	1			T48	24		T22	20		T23	56
auto[0]	values[4]	values[5]	571	1			T181	18		T23	30		T198	20
auto[0]	values[4]	values[6]	671	1			T183	16		T170	20		T245	65
auto[0]	values[4]	values[7]	545	1			T50	25		T53	20		T54	59
auto[0]	values[5]	values[0]	626	1			T53	20		T21	50		T234	12
auto[0]	values[5]	values[1]	367	1			T26	23		T50	26		T259	20
auto[0]	values[5]	values[2]	813	1			T33	20		T229	18		T52	18
auto[0]	values[5]	values[3]	978	1			T29	16		T178	22		T48	20
auto[0]	values[5]	values[4]	249	1			T48	20		T54	41		T181	20
auto[0]	values[5]	values[5]	419	1			T14	153		T226	6		T71	26
auto[0]	values[5]	values[6]	551	1			T221	19		T232	19		T284	20
auto[0]	values[5]	values[7]	523	1			T184	14		T53	20		T285	8
auto[0]	values[6]	values[0]	518	1			T33	20		T171	6		T48	20
auto[0]	values[6]	values[1]	384	1			T50	20		T257	4		T198	20
auto[0]	values[6]	values[2]	474	1			T19	50		T21	20		T65	35
auto[0]	values[6]	values[3]	469	1			T50	20		T215	20		T286	2
auto[0]	values[6]	values[4]	577	1			T222	12		T53	32		T146	47
auto[0]	values[6]	values[5]	480	1			T2	10		T52	20		T252	8
auto[0]	values[6]	values[6]	641	1			T50	53		T181	20		T250	2
auto[0]	values[6]	values[7]	384	1			T248	4		T195	19		T57	22
auto[0]	values[7]	values[0]	404	1			T195	20		T225	14		T57	21
auto[0]	values[7]	values[1]	628	1			T33	27		T102	22		T50	20
auto[0]	values[7]	values[2]	488	1			T23	21		T287	2		T235	35
auto[0]	values[7]	values[3]	502	1			T54	20		T57	43		T266	2
auto[0]	values[7]	values[4]	335	1			T16	23		T48	16		T21	18
auto[0]	values[7]	values[5]	536	1			T53	71		T22	20		T227	4
auto[0]	values[7]	values[6]	405	1			T97	18		T48	21		T53	19
auto[0]	values[7]	values[7]	636	1			T255	4		T181	19		T98	18
auto[1]	values[0]	values[0]	8	1			T146	2		T165	1		T288	1
auto[1]	values[0]	values[1]	8	1			T48	1		T52	2		T221	3
auto[1]	values[0]	values[2]	10	1			T14	1		T48	1		T50	1
auto[1]	values[0]	values[3]	11	1			T54	1		T41	2		T147	4
auto[1]	values[0]	values[4]	6	1			T57	1		T220	2		T289	1
auto[1]	values[0]	values[5]	17	1			T52	3		T165	4		T207	1
auto[1]	values[0]	values[6]	20	1			T23	2		T198	1		T67	1
auto[1]	values[0]	values[7]	19	1			T181	2		T288	1		T200	2
auto[1]	values[1]	values[0]	1	1			T65	1		-	-		-	-
auto[1]	values[1]	values[1]	2	1			T289	1		T290	1		-	-
auto[1]	values[1]	values[2]	3	1			T254	2		T291	1		-	-
auto[1]	values[1]	values[3]	24	1			T16	2		T205	5		T41	2
auto[1]	values[1]	values[4]	22	1			T16	1		T198	1		T292	2
auto[1]	values[1]	values[5]	14	1			T273	3		T217	3		T221	2
auto[1]	values[1]	values[6]	20	1			T16	2		T21	1		T23	1
auto[1]	values[1]	values[7]	13	1			T16	1		T54	1		T217	2
auto[1]	values[2]	values[0]	20	1			T195	1		T216	3		T41	2
auto[1]	values[2]	values[1]	5	1			T41	2		T233	1		T293	2
auto[1]	values[2]	values[2]	6	1			T232	1		T294	2		T291	1
auto[1]	values[2]	values[3]	20	1			T272	1		T221	3		T207	2
auto[1]	values[2]	values[4]	22	1			T52	5		T274	1		T203	1
auto[1]	values[2]	values[5]	15	1			T35	1		T205	2		T295	1
auto[1]	values[2]	values[6]	11	1			T206	1		T167	6		T296	2
auto[1]	values[2]	values[7]	19	1			T181	1		T65	1		T206	3
auto[1]	values[3]	values[0]	6	1			T297	4		T298	2		-	-
auto[1]	values[3]	values[1]	20	1			T216	1		T295	3		T299	1
auto[1]	values[3]	values[2]	14	1			T52	5		T230	1		T300	1
auto[1]	values[3]	values[3]	8	1			T67	2		T215	2		T301	1
auto[1]	values[3]	values[4]	5	1			T67	2		T212	2		T302	1
auto[1]	values[3]	values[5]	17	1			T51	4		T241	2		T288	2
auto[1]	values[3]	values[6]	20	1			T21	1		T54	1		T41	3
auto[1]	values[3]	values[7]	9	1			T50	1		T54	1		T267	2
auto[1]	values[4]	values[0]	22	1			T214	1		T239	2		T242	1
auto[1]	values[4]	values[1]	15	1			T303	4		T284	3		T268	4
auto[1]	values[4]	values[2]	19	1			T14	3		T98	1		T230	1
auto[1]	values[4]	values[3]	17	1			T98	3		T269	1		T304	3
auto[1]	values[4]	values[4]	16	1			T41	1		T239	2		T305	4
auto[1]	values[4]	values[5]	8	1			T181	2		T23	1		T295	1
auto[1]	values[4]	values[6]	11	1			T221	2		T300	1		T306	3
auto[1]	values[4]	values[7]	7	1			T181	1		T292	1		T166	1
auto[1]	values[5]	values[0]	13	1			T254	2		T167	1		T299	3
auto[1]	values[5]	values[1]	7	1			T59	1		T206	1		T242	1
auto[1]	values[5]	values[2]	29	1			T52	2		T216	1		T198	1
auto[1]	values[5]	values[3]	38	1			T54	4		T23	1		T261	2
auto[1]	values[5]	values[4]	10	1			T48	2		T57	1		T307	2
auto[1]	values[5]	values[5]	3	1			T14	1		T206	1		T62	1
auto[1]	values[5]	values[6]	15	1			T221	1		T232	1		T308	2
auto[1]	values[5]	values[7]	6	1			T217	1		T242	1		T147	1
auto[1]	values[6]	values[0]	13	1			T21	1		T216	3		T98	1
auto[1]	values[6]	values[1]	12	1			T198	1		T98	3		T59	1
auto[1]	values[6]	values[2]	24	1			T65	3		T146	2		T41	1
auto[1]	values[6]	values[3]	1	1			T64	1		-	-		-	-
auto[1]	values[6]	values[4]	15	1			T146	4		T165	1		T41	1
auto[1]	values[6]	values[5]	9	1			T2	2		T203	1		T242	2
auto[1]	values[6]	values[6]	19	1			T216	1		T205	2		T146	4
auto[1]	values[6]	values[7]	18	1			T195	1		T309	2		T310	6
auto[1]	values[7]	values[0]	15	1			T65	3		T274	1		T304	2
auto[1]	values[7]	values[1]	19	1			T33	1		T50	1		T21	1
auto[1]	values[7]	values[2]	14	1			T306	1		T299	1		T311	2
auto[1]	values[7]	values[3]	18	1			T57	3		T146	2		T59	2
auto[1]	values[7]	values[4]	18	1			T48	4		T21	2		T35	3
auto[1]	values[7]	values[5]	19	1			T53	1		T35	1		T59	2
auto[1]	values[7]	values[6]	9	1			T53	1		T270	2		T312	1
auto[1]	values[7]	values[7]	17	1			T181	1		T98	2		T217	3