Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	805	1			T17	7		T18	7		T20	14
all_values[1]	805	1			T17	7		T18	7		T20	14
all_values[2]	805	1			T17	7		T18	7		T20	14
all_values[3]	805	1			T17	7		T18	7		T20	14
all_values[4]	805	1			T17	7		T18	7		T20	14
all_values[5]	805	1			T17	7		T18	7		T20	14
all_values[6]	805	1			T17	7		T18	7		T20	14
all_values[7]	805	1			T17	7		T18	7		T20	14

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3485

1

T17

32

T18

28

T20

49

auto[1]

2955

1

T17

24

T18

28

T20

63

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2616

1

T17

24

T18

25

T20

48

auto[1]

3824

1

T17

32

T18

31

T20

64

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3697

1

T17

35

T18

32

T20

64

auto[1]

2743

1

T17

21

T18

24

T20

48

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	149	1			T17	2		T18	3		T20	3
all_values[0]	auto[0]	auto[0]	auto[1]	87	1			T20	2		T21	4		T22	3
all_values[0]	auto[0]	auto[1]	auto[0]	137	1			T17	1		T18	1		T20	3
all_values[0]	auto[0]	auto[1]	auto[1]	92	1			T17	1		T20	1		T21	1
all_values[0]	auto[1]	auto[0]	auto[1]	211	1			T17	2		T18	2		T20	5
all_values[0]	auto[1]	auto[1]	auto[1]	129	1			T17	1		T18	1		T21	1
all_values[1]	auto[0]	auto[0]	auto[0]	171	1			T17	2		T18	5		T20	1
all_values[1]	auto[0]	auto[0]	auto[1]	80	1			T20	1		T23	2		T40	3
all_values[1]	auto[0]	auto[1]	auto[0]	156	1			T17	2		T20	4		T21	2
all_values[1]	auto[0]	auto[1]	auto[1]	71	1			T17	1		T20	3		T21	2
all_values[1]	auto[1]	auto[0]	auto[1]	173	1			T17	1		T18	2		T20	2
all_values[1]	auto[1]	auto[1]	auto[1]	154	1			T17	1		T20	3		T21	4
all_values[2]	auto[0]	auto[0]	auto[0]	194	1			T17	5		T20	2		T21	7
all_values[2]	auto[0]	auto[0]	auto[1]	71	1			T17	1		T18	1		T23	2
all_values[2]	auto[0]	auto[1]	auto[0]	143	1			T18	2		T20	3		T21	4
all_values[2]	auto[0]	auto[1]	auto[1]	71	1			T20	3		T22	1		T23	3
all_values[2]	auto[1]	auto[0]	auto[1]	185	1			T18	1		T20	3		T22	3
all_values[2]	auto[1]	auto[1]	auto[1]	141	1			T17	1		T18	3		T20	3
all_values[3]	auto[0]	auto[0]	auto[0]	185	1			T17	1		T20	1		T21	2
all_values[3]	auto[0]	auto[0]	auto[1]	76	1			T17	2		T21	1		T23	1
all_values[3]	auto[0]	auto[1]	auto[0]	149	1			T18	1		T20	5		T21	1
all_values[3]	auto[0]	auto[1]	auto[1]	56	1			T17	1		T18	2		T21	1
all_values[3]	auto[1]	auto[0]	auto[1]	182	1			T17	3		T18	2		T20	3
all_values[3]	auto[1]	auto[1]	auto[1]	157	1			T18	2		T20	5		T21	3
all_values[4]	auto[0]	auto[0]	auto[0]	147	1			T17	1		T20	2		T21	1
all_values[4]	auto[0]	auto[0]	auto[1]	83	1			T18	1		T21	2		T22	1
all_values[4]	auto[0]	auto[1]	auto[0]	141	1			T17	2		T18	1		T20	4
all_values[4]	auto[0]	auto[1]	auto[1]	80	1			T17	1		T18	2		T20	1
all_values[4]	auto[1]	auto[0]	auto[1]	200	1			T17	3		T20	4		T21	3
all_values[4]	auto[1]	auto[1]	auto[1]	154	1			T18	3		T20	3		T21	3
all_values[5]	auto[0]	auto[0]	auto[0]	246	1			T17	2		T18	1		T20	3
all_values[5]	auto[0]	auto[1]	auto[0]	212	1			T17	2		T18	3		T20	4
all_values[5]	auto[1]	auto[0]	auto[1]	187	1			T17	1		T18	3		T20	5
all_values[5]	auto[1]	auto[1]	auto[1]	160	1			T17	2		T20	2		T21	2
all_values[6]	auto[0]	auto[0]	auto[0]	162	1			T17	1		T18	1		T20	2
all_values[6]	auto[0]	auto[0]	auto[1]	74	1			T20	2		T21	1		T22	1
all_values[6]	auto[0]	auto[1]	auto[0]	129	1			T17	1		T18	2		T20	6
all_values[6]	auto[0]	auto[1]	auto[1]	77	1			T17	1		T18	1		T20	1
all_values[6]	auto[1]	auto[0]	auto[1]	194	1			T17	1		T18	2		T20	2
all_values[6]	auto[1]	auto[1]	auto[1]	169	1			T17	3		T18	1		T20	1
all_values[7]	auto[0]	auto[0]	auto[0]	151	1			T17	2		T18	2		T20	3
all_values[7]	auto[0]	auto[0]	auto[1]	89	1			T17	1		T23	2		T35	1
all_values[7]	auto[0]	auto[1]	auto[0]	144	1			T18	3		T20	2		T21	3
all_values[7]	auto[0]	auto[1]	auto[1]	74	1			T17	2		T20	2		T21	2
all_values[7]	auto[1]	auto[0]	auto[1]	188	1			T17	1		T18	2		T20	3
all_values[7]	auto[1]	auto[1]	auto[1]	159	1			T17	1		T20	4		T21	4

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal