Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1869

1

T11

19

T12

12

T14

2

auto[1]

1937

1

T11

16

T12

8

T31

17

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2115

1

T12

15

T14

1

T30

2

auto[1]

1691

1

T11

35

T12

5

T14

1

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3028

1

T11

35

T12

12

T14

2

auto[1]

778

1

T12

8

T30

1

T33

5

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	806	1			T11	6		T12	3		T14	2
valid[1]	726	1			T11	7		T12	4		T31	9
valid[2]	777	1			T11	11		T12	4		T31	3
valid[3]	705	1			T11	9		T12	5		T30	1
valid[4]	792	1			T11	2		T12	4		T30	1

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	159	1			T14	1		T33	2		T26	2
auto[0]	auto[0]	valid[0]	auto[1]	186	1			T11	2		T12	2		T14	1
auto[0]	auto[0]	valid[1]	auto[0]	119	1			T33	1		T26	2		T16	2
auto[0]	auto[0]	valid[1]	auto[1]	181	1			T11	4		T31	3		T36	1
auto[0]	auto[0]	valid[2]	auto[0]	127	1			T12	1		T15	2		T26	1
auto[0]	auto[0]	valid[2]	auto[1]	166	1			T11	9		T12	1		T31	1
auto[0]	auto[0]	valid[3]	auto[0]	126	1			T12	2		T30	1		T33	1
auto[0]	auto[0]	valid[3]	auto[1]	140	1			T11	4		T12	1		T31	2
auto[0]	auto[0]	valid[4]	auto[0]	124	1			T12	1		T33	2		T15	1
auto[0]	auto[0]	valid[4]	auto[1]	157	1			T31	4		T16	2		T96	5
auto[0]	auto[1]	valid[0]	auto[0]	129	1			T33	4		T15	2		T26	1
auto[0]	auto[1]	valid[0]	auto[1]	180	1			T11	4		T31	2		T32	1
auto[0]	auto[1]	valid[1]	auto[0]	110	1			T12	1		T15	1		T26	1
auto[0]	auto[1]	valid[1]	auto[1]	147	1			T11	3		T31	6		T36	1
auto[0]	auto[1]	valid[2]	auto[0]	164	1			T12	1		T33	1		T15	3
auto[0]	auto[1]	valid[2]	auto[1]	174	1			T11	2		T31	2		T32	1
auto[0]	auto[1]	valid[3]	auto[0]	127	1			T12	1		T16	1		T48	2
auto[0]	auto[1]	valid[3]	auto[1]	173	1			T11	5		T12	1		T31	5
auto[0]	auto[1]	valid[4]	auto[0]	152	1			T33	2		T15	2		T26	3
auto[0]	auto[1]	valid[4]	auto[1]	187	1			T11	2		T31	2		T36	1
auto[1]	auto[0]	valid[0]	auto[0]	77	1			T12	1		T33	1		T15	3
auto[1]	auto[0]	valid[1]	auto[0]	78	1			T12	1		T34	2		T16	1
auto[1]	auto[0]	valid[2]	auto[0]	62	1			T12	1		T15	2		T26	1
auto[1]	auto[0]	valid[3]	auto[0]	74	1			T33	2		T34	1		T332	1
auto[1]	auto[0]	valid[4]	auto[0]	93	1			T12	1		T30	1		T33	1
auto[1]	auto[1]	valid[0]	auto[0]	75	1			T33	1		T34	1		T176	1
auto[1]	auto[1]	valid[1]	auto[0]	91	1			T12	2		T15	1		T26	1
auto[1]	auto[1]	valid[2]	auto[0]	84	1			T26	2		T176	1		T327	1
auto[1]	auto[1]	valid[3]	auto[0]	65	1			T34	1		T16	4		T18	4
auto[1]	auto[1]	valid[4]	auto[0]	79	1			T12	2		T15	1		T26	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal