Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

52970

1

T12

340

T14

40

T30

80

auto[1]

17744

1

T11

344

T12

66

T14

4

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

51518

1

T11

344

T12

273

T14

31

auto[1]

19196

1

T12

133

T14

13

T30

34

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	36457	1			T11	171		T12	207		T14	22
others[1]	5946	1			T11	24		T12	33		T14	3
others[2]	5876	1			T11	23		T12	32		T14	2
others[3]	6749	1			T11	45		T12	41		T14	2
interest[1]	3942	1			T11	27		T12	21		T14	4
interest[4]	23664	1			T11	110		T12	121		T14	13
interest[64]	11744	1			T11	54		T12	72		T14	11

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	17327	1			T12	112		T14	14		T30	23
auto[0]	auto[0]	others[1]	2896	1			T12	12		T14	3		T30	4
auto[0]	auto[0]	others[2]	2788	1			T12	14		T14	1		T30	1
auto[0]	auto[0]	others[3]	3217	1			T12	23		T14	1		T30	3
auto[0]	auto[0]	interest[1]	1916	1			T12	10		T14	1		T30	5
auto[0]	auto[0]	interest[4]	11268	1			T12	68		T14	6		T30	14
auto[0]	auto[0]	interest[64]	5630	1			T12	36		T14	7		T30	10
auto[0]	auto[1]	others[0]	9303	1			T11	171		T12	35		T14	3
auto[0]	auto[1]	others[1]	1443	1			T11	24		T12	6		T30	1
auto[0]	auto[1]	others[2]	1476	1			T11	23		T12	6		T30	2
auto[0]	auto[1]	others[3]	1651	1			T11	45		T12	3		T30	7
auto[0]	auto[1]	interest[1]	953	1			T11	27		T12	7		T14	1
auto[0]	auto[1]	interest[4]	6112	1			T11	110		T12	21		T14	2
auto[0]	auto[1]	interest[64]	2918	1			T11	54		T12	9		T30	1
auto[1]	auto[0]	others[0]	9827	1			T12	60		T14	5		T30	17
auto[1]	auto[0]	others[1]	1607	1			T12	15		T30	5		T33	6
auto[1]	auto[0]	others[2]	1612	1			T12	12		T14	1		T30	1
auto[1]	auto[0]	others[3]	1881	1			T12	15		T14	1		T30	6
auto[1]	auto[0]	interest[1]	1073	1			T12	4		T14	2		T33	6
auto[1]	auto[0]	interest[4]	6284	1			T12	32		T14	5		T30	12
auto[1]	auto[0]	interest[64]	3196	1			T12	27		T14	4		T30	5

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal