Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.07 98.44 94.08 98.62 89.36 97.28 95.43 99.26


Total test records in report: 1150
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html
T122 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.1276499780 Jul 28 05:18:03 PM PDT 24 Jul 28 05:18:07 PM PDT 24 113297672 ps
T1043 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.1248915789 Jul 28 05:18:32 PM PDT 24 Jul 28 05:18:33 PM PDT 24 11424227 ps
T1044 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.1846917259 Jul 28 05:18:04 PM PDT 24 Jul 28 05:18:06 PM PDT 24 130415692 ps
T125 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.3923751991 Jul 28 05:18:04 PM PDT 24 Jul 28 05:18:06 PM PDT 24 138677614 ps
T110 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.283724571 Jul 28 05:18:01 PM PDT 24 Jul 28 05:18:04 PM PDT 24 50921925 ps
T1045 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1989807978 Jul 28 05:18:21 PM PDT 24 Jul 28 05:18:22 PM PDT 24 20816346 ps
T1046 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.3685177626 Jul 28 05:18:07 PM PDT 24 Jul 28 05:18:08 PM PDT 24 29345772 ps
T1047 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.929927505 Jul 28 05:18:29 PM PDT 24 Jul 28 05:18:30 PM PDT 24 51931380 ps
T1048 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1516154746 Jul 28 05:18:12 PM PDT 24 Jul 28 05:18:12 PM PDT 24 21766205 ps
T129 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3249228072 Jul 28 05:18:07 PM PDT 24 Jul 28 05:18:10 PM PDT 24 417479074 ps
T130 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.790376269 Jul 28 05:18:13 PM PDT 24 Jul 28 05:18:15 PM PDT 24 30581599 ps
T1049 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.2237271914 Jul 28 05:17:43 PM PDT 24 Jul 28 05:17:47 PM PDT 24 114688749 ps
T131 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.3400181558 Jul 28 05:17:58 PM PDT 24 Jul 28 05:18:00 PM PDT 24 90980840 ps
T119 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.3425626409 Jul 28 05:18:06 PM PDT 24 Jul 28 05:18:09 PM PDT 24 36455454 ps
T92 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.674466783 Jul 28 05:17:47 PM PDT 24 Jul 28 05:17:48 PM PDT 24 65857417 ps
T1050 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.3926573217 Jul 28 05:17:51 PM PDT 24 Jul 28 05:17:52 PM PDT 24 12935646 ps
T117 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.1202119906 Jul 28 05:17:58 PM PDT 24 Jul 28 05:18:00 PM PDT 24 163474891 ps
T1051 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1634170681 Jul 28 05:17:58 PM PDT 24 Jul 28 05:18:00 PM PDT 24 73173549 ps
T1052 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.854623160 Jul 28 05:18:01 PM PDT 24 Jul 28 05:18:02 PM PDT 24 19358531 ps
T114 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.4190792526 Jul 28 05:17:59 PM PDT 24 Jul 28 05:18:03 PM PDT 24 1398601930 ps
T1053 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.3552692709 Jul 28 05:18:01 PM PDT 24 Jul 28 05:18:04 PM PDT 24 53077942 ps
T1054 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.3486255683 Jul 28 05:17:52 PM PDT 24 Jul 28 05:17:52 PM PDT 24 15981399 ps
T111 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3074153901 Jul 28 05:17:51 PM PDT 24 Jul 28 05:18:06 PM PDT 24 574868176 ps
T163 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.3396962979 Jul 28 05:18:12 PM PDT 24 Jul 28 05:18:13 PM PDT 24 443683742 ps
T115 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.264979900 Jul 28 05:17:52 PM PDT 24 Jul 28 05:17:57 PM PDT 24 676546079 ps
T121 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.873944070 Jul 28 05:17:53 PM PDT 24 Jul 28 05:17:55 PM PDT 24 183219291 ps
T1055 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.963668615 Jul 28 05:18:02 PM PDT 24 Jul 28 05:18:03 PM PDT 24 14900158 ps
T1056 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2648536887 Jul 28 05:18:21 PM PDT 24 Jul 28 05:18:22 PM PDT 24 15860123 ps
T1057 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3209567103 Jul 28 05:17:51 PM PDT 24 Jul 28 05:17:53 PM PDT 24 192439585 ps
T1058 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.2519685140 Jul 28 05:17:50 PM PDT 24 Jul 28 05:17:52 PM PDT 24 39726508 ps
T132 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.184229341 Jul 28 05:17:48 PM PDT 24 Jul 28 05:17:50 PM PDT 24 335522001 ps
T1059 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.1717944917 Jul 28 05:17:56 PM PDT 24 Jul 28 05:17:58 PM PDT 24 1200936092 ps
T1060 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.1179161446 Jul 28 05:18:08 PM PDT 24 Jul 28 05:18:09 PM PDT 24 21430988 ps
T133 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.720701621 Jul 28 05:17:52 PM PDT 24 Jul 28 05:17:55 PM PDT 24 95857348 ps
T1061 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.1315522315 Jul 28 05:18:06 PM PDT 24 Jul 28 05:18:07 PM PDT 24 52162935 ps
T112 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1398875673 Jul 28 05:17:57 PM PDT 24 Jul 28 05:18:11 PM PDT 24 1509701563 ps
T159 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.2383999461 Jul 28 05:17:57 PM PDT 24 Jul 28 05:18:05 PM PDT 24 384685448 ps
T160 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1618200183 Jul 28 05:18:06 PM PDT 24 Jul 28 05:18:08 PM PDT 24 92434225 ps
T120 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.2820122177 Jul 28 05:18:10 PM PDT 24 Jul 28 05:18:13 PM PDT 24 322298878 ps
T1062 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.883778595 Jul 28 05:17:48 PM PDT 24 Jul 28 05:17:50 PM PDT 24 57882956 ps
T1063 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.945798252 Jul 28 05:18:10 PM PDT 24 Jul 28 05:18:11 PM PDT 24 94209378 ps
T194 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.1944706388 Jul 28 05:17:53 PM PDT 24 Jul 28 05:18:05 PM PDT 24 243362073 ps
T1064 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.4245768696 Jul 28 05:18:00 PM PDT 24 Jul 28 05:18:03 PM PDT 24 52516180 ps
T1065 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.2017429684 Jul 28 05:18:23 PM PDT 24 Jul 28 05:18:24 PM PDT 24 67984044 ps
T1066 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.1343949827 Jul 28 05:18:40 PM PDT 24 Jul 28 05:18:41 PM PDT 24 28071970 ps
T187 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.2624401816 Jul 28 05:18:08 PM PDT 24 Jul 28 05:18:23 PM PDT 24 555964095 ps
T134 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.1434148473 Jul 28 05:18:11 PM PDT 24 Jul 28 05:18:14 PM PDT 24 782675083 ps
T1067 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3130504001 Jul 28 05:17:53 PM PDT 24 Jul 28 05:17:54 PM PDT 24 56083666 ps
T136 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.3832922255 Jul 28 05:17:59 PM PDT 24 Jul 28 05:18:07 PM PDT 24 1227978431 ps
T116 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.4247507055 Jul 28 05:18:03 PM PDT 24 Jul 28 05:18:07 PM PDT 24 254191227 ps
T137 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.2776909921 Jul 28 05:18:12 PM PDT 24 Jul 28 05:18:14 PM PDT 24 102497457 ps
T1068 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.3747588791 Jul 28 05:18:27 PM PDT 24 Jul 28 05:18:28 PM PDT 24 35201438 ps
T161 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.163025871 Jul 28 05:17:57 PM PDT 24 Jul 28 05:18:04 PM PDT 24 839500324 ps
T1069 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.115235130 Jul 28 05:17:59 PM PDT 24 Jul 28 05:18:33 PM PDT 24 2276247525 ps
T1070 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.3274612928 Jul 28 05:18:05 PM PDT 24 Jul 28 05:18:06 PM PDT 24 20294684 ps
T1071 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1074878243 Jul 28 05:18:08 PM PDT 24 Jul 28 05:18:09 PM PDT 24 106091313 ps
T1072 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.12114257 Jul 28 05:18:12 PM PDT 24 Jul 28 05:18:14 PM PDT 24 260814753 ps
T1073 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.1503883356 Jul 28 05:18:09 PM PDT 24 Jul 28 05:18:10 PM PDT 24 34089752 ps
T190 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.522693958 Jul 28 05:18:08 PM PDT 24 Jul 28 05:18:26 PM PDT 24 303367725 ps
T1074 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1742701543 Jul 28 05:18:30 PM PDT 24 Jul 28 05:18:34 PM PDT 24 62576878 ps
T177 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.1317710700 Jul 28 05:18:19 PM PDT 24 Jul 28 05:18:22 PM PDT 24 1438233239 ps
T1075 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.3388106223 Jul 28 05:18:23 PM PDT 24 Jul 28 05:18:24 PM PDT 24 54483423 ps
T193 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1442941542 Jul 28 05:18:14 PM PDT 24 Jul 28 05:18:28 PM PDT 24 1009113138 ps
T1076 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.2620626062 Jul 28 05:17:54 PM PDT 24 Jul 28 05:17:56 PM PDT 24 225081558 ps
T1077 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.1968703607 Jul 28 05:17:59 PM PDT 24 Jul 28 05:18:00 PM PDT 24 16409153 ps
T1078 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3200140330 Jul 28 05:18:06 PM PDT 24 Jul 28 05:18:08 PM PDT 24 77853000 ps
T1079 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2295035369 Jul 28 05:18:10 PM PDT 24 Jul 28 05:18:11 PM PDT 24 39869422 ps
T1080 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.4073200742 Jul 28 05:18:17 PM PDT 24 Jul 28 05:18:18 PM PDT 24 17444376 ps
T191 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.641906522 Jul 28 05:18:00 PM PDT 24 Jul 28 05:18:21 PM PDT 24 923560390 ps
T1081 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3060051017 Jul 28 05:18:04 PM PDT 24 Jul 28 05:18:07 PM PDT 24 179489519 ps
T1082 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.2805006185 Jul 28 05:18:09 PM PDT 24 Jul 28 05:18:10 PM PDT 24 13264592 ps
T1083 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.508682396 Jul 28 05:17:52 PM PDT 24 Jul 28 05:18:21 PM PDT 24 2148466763 ps
T1084 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.1870205447 Jul 28 05:18:00 PM PDT 24 Jul 28 05:18:01 PM PDT 24 53695878 ps
T1085 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.2669339187 Jul 28 05:17:54 PM PDT 24 Jul 28 05:17:55 PM PDT 24 70176954 ps
T1086 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.3019984016 Jul 28 05:18:14 PM PDT 24 Jul 28 05:18:21 PM PDT 24 278490314 ps
T1087 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.837329145 Jul 28 05:18:02 PM PDT 24 Jul 28 05:18:06 PM PDT 24 120008436 ps
T192 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.1492542306 Jul 28 05:18:07 PM PDT 24 Jul 28 05:18:15 PM PDT 24 862888518 ps
T1088 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.1074148666 Jul 28 05:17:52 PM PDT 24 Jul 28 05:17:54 PM PDT 24 53491642 ps
T1089 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.1893344171 Jul 28 05:18:07 PM PDT 24 Jul 28 05:18:08 PM PDT 24 14829240 ps
T1090 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.525567178 Jul 28 05:18:15 PM PDT 24 Jul 28 05:18:16 PM PDT 24 16070481 ps
T118 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.3106356948 Jul 28 05:17:56 PM PDT 24 Jul 28 05:18:00 PM PDT 24 132403472 ps
T1091 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1746078947 Jul 28 05:18:00 PM PDT 24 Jul 28 05:18:04 PM PDT 24 58889154 ps
T1092 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.1249668310 Jul 28 05:18:24 PM PDT 24 Jul 28 05:18:27 PM PDT 24 132804640 ps
T1093 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.4248309245 Jul 28 05:18:03 PM PDT 24 Jul 28 05:18:05 PM PDT 24 60296135 ps
T1094 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.1497157869 Jul 28 05:17:53 PM PDT 24 Jul 28 05:17:55 PM PDT 24 66648756 ps
T1095 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.2228993122 Jul 28 05:18:11 PM PDT 24 Jul 28 05:18:12 PM PDT 24 30133050 ps
T1096 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2303657258 Jul 28 05:18:00 PM PDT 24 Jul 28 05:18:01 PM PDT 24 20803400 ps
T1097 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.3358523433 Jul 28 05:18:15 PM PDT 24 Jul 28 05:18:17 PM PDT 24 61314036 ps
T1098 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.3071122806 Jul 28 05:18:08 PM PDT 24 Jul 28 05:18:09 PM PDT 24 91420572 ps
T1099 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.733710943 Jul 28 05:18:02 PM PDT 24 Jul 28 05:18:16 PM PDT 24 420761482 ps
T1100 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.590931626 Jul 28 05:17:58 PM PDT 24 Jul 28 05:18:00 PM PDT 24 29620469 ps
T1101 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2914646051 Jul 28 05:18:09 PM PDT 24 Jul 28 05:18:10 PM PDT 24 15240755 ps
T124 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.3238002818 Jul 28 05:18:03 PM PDT 24 Jul 28 05:18:06 PM PDT 24 84784439 ps
T1102 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.3026723144 Jul 28 05:18:21 PM PDT 24 Jul 28 05:18:29 PM PDT 24 2994586734 ps
T93 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3184378009 Jul 28 05:17:51 PM PDT 24 Jul 28 05:17:52 PM PDT 24 67913078 ps
T1103 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.1186463036 Jul 28 05:18:26 PM PDT 24 Jul 28 05:18:28 PM PDT 24 58410048 ps
T1104 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3612619505 Jul 28 05:18:06 PM PDT 24 Jul 28 05:18:08 PM PDT 24 288999664 ps
T94 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3594432903 Jul 28 05:17:50 PM PDT 24 Jul 28 05:17:51 PM PDT 24 57342941 ps
T1105 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.939997447 Jul 28 05:18:24 PM PDT 24 Jul 28 05:18:25 PM PDT 24 13816118 ps
T1106 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.3296760545 Jul 28 05:18:08 PM PDT 24 Jul 28 05:18:09 PM PDT 24 30683177 ps
T1107 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.4079347152 Jul 28 05:18:29 PM PDT 24 Jul 28 05:18:30 PM PDT 24 44341186 ps
T1108 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.1779095910 Jul 28 05:17:58 PM PDT 24 Jul 28 05:17:59 PM PDT 24 38121752 ps
T1109 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.47582196 Jul 28 05:18:06 PM PDT 24 Jul 28 05:18:41 PM PDT 24 9811065274 ps
T1110 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.650096273 Jul 28 05:17:54 PM PDT 24 Jul 28 05:17:58 PM PDT 24 208856535 ps
T1111 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.2319632360 Jul 28 05:18:04 PM PDT 24 Jul 28 05:18:05 PM PDT 24 44405230 ps
T1112 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3808806124 Jul 28 05:17:59 PM PDT 24 Jul 28 05:18:00 PM PDT 24 44718917 ps
T1113 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.399394435 Jul 28 05:18:03 PM PDT 24 Jul 28 05:18:24 PM PDT 24 1883193540 ps
T1114 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2246330352 Jul 28 05:17:43 PM PDT 24 Jul 28 05:17:47 PM PDT 24 60208334 ps
T123 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.58140228 Jul 28 05:17:54 PM PDT 24 Jul 28 05:17:58 PM PDT 24 466477831 ps
T1115 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.2481660709 Jul 28 05:18:24 PM PDT 24 Jul 28 05:18:26 PM PDT 24 160260976 ps
T1116 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.829287781 Jul 28 05:17:59 PM PDT 24 Jul 28 05:18:13 PM PDT 24 255970388 ps
T1117 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.919369376 Jul 28 05:18:11 PM PDT 24 Jul 28 05:18:12 PM PDT 24 12049908 ps
T1118 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.917113246 Jul 28 05:18:12 PM PDT 24 Jul 28 05:18:12 PM PDT 24 78288003 ps
T1119 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.503220257 Jul 28 05:18:08 PM PDT 24 Jul 28 05:18:11 PM PDT 24 108764651 ps
T95 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.514782765 Jul 28 05:18:02 PM PDT 24 Jul 28 05:18:04 PM PDT 24 23559836 ps
T1120 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3911586758 Jul 28 05:18:01 PM PDT 24 Jul 28 05:18:05 PM PDT 24 248066597 ps
T1121 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.3334693543 Jul 28 05:18:19 PM PDT 24 Jul 28 05:18:20 PM PDT 24 32708222 ps
T1122 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.813459683 Jul 28 05:18:08 PM PDT 24 Jul 28 05:18:09 PM PDT 24 16828135 ps
T1123 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1195641998 Jul 28 05:18:12 PM PDT 24 Jul 28 05:18:14 PM PDT 24 112216352 ps
T1124 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.3045057124 Jul 28 05:17:59 PM PDT 24 Jul 28 05:18:01 PM PDT 24 48744726 ps
T1125 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.2174526444 Jul 28 05:17:58 PM PDT 24 Jul 28 05:17:59 PM PDT 24 46668576 ps
T1126 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.1009762600 Jul 28 05:17:58 PM PDT 24 Jul 28 05:18:05 PM PDT 24 414602834 ps
T1127 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1016789900 Jul 28 05:18:04 PM PDT 24 Jul 28 05:18:06 PM PDT 24 99624391 ps
T1128 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.4201295808 Jul 28 05:17:57 PM PDT 24 Jul 28 05:18:06 PM PDT 24 2773181225 ps
T1129 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.2729511147 Jul 28 05:18:08 PM PDT 24 Jul 28 05:18:10 PM PDT 24 122562933 ps
T1130 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.2101158153 Jul 28 05:18:07 PM PDT 24 Jul 28 05:18:09 PM PDT 24 51127923 ps
T1131 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.3590301002 Jul 28 05:18:09 PM PDT 24 Jul 28 05:18:13 PM PDT 24 495767668 ps
T1132 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.969290789 Jul 28 05:18:23 PM PDT 24 Jul 28 05:18:24 PM PDT 24 324358454 ps
T1133 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.3432712369 Jul 28 05:18:01 PM PDT 24 Jul 28 05:18:05 PM PDT 24 60002299 ps
T1134 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1486773769 Jul 28 05:17:54 PM PDT 24 Jul 28 05:17:56 PM PDT 24 61177046 ps
T1135 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2399219742 Jul 28 05:18:10 PM PDT 24 Jul 28 05:18:24 PM PDT 24 679835476 ps
T1136 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.1045259319 Jul 28 05:18:15 PM PDT 24 Jul 28 05:18:16 PM PDT 24 47440901 ps
T1137 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.1721652714 Jul 28 05:18:15 PM PDT 24 Jul 28 05:18:18 PM PDT 24 65382115 ps
T1138 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.2917540076 Jul 28 05:18:15 PM PDT 24 Jul 28 05:18:15 PM PDT 24 12119916 ps
T1139 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.572302449 Jul 28 05:17:58 PM PDT 24 Jul 28 05:18:11 PM PDT 24 954167144 ps
T1140 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.3139372687 Jul 28 05:18:08 PM PDT 24 Jul 28 05:18:10 PM PDT 24 68137450 ps
T185 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2106396371 Jul 28 05:17:53 PM PDT 24 Jul 28 05:17:58 PM PDT 24 126376233 ps
T1141 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.2435743134 Jul 28 05:18:08 PM PDT 24 Jul 28 05:18:09 PM PDT 24 9802968 ps
T188 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.3092677970 Jul 28 05:17:53 PM PDT 24 Jul 28 05:18:12 PM PDT 24 1208258182 ps
T189 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2185782876 Jul 28 05:17:53 PM PDT 24 Jul 28 05:18:13 PM PDT 24 668184324 ps
T1142 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.2952276643 Jul 28 05:18:18 PM PDT 24 Jul 28 05:18:18 PM PDT 24 152029414 ps
T1143 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.2205501964 Jul 28 05:18:20 PM PDT 24 Jul 28 05:18:21 PM PDT 24 24903981 ps
T186 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2960304182 Jul 28 05:17:59 PM PDT 24 Jul 28 05:18:04 PM PDT 24 76404155 ps
T1144 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1204416721 Jul 28 05:17:54 PM PDT 24 Jul 28 05:17:54 PM PDT 24 38341792 ps
T1145 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.3817851958 Jul 28 05:17:52 PM PDT 24 Jul 28 05:18:17 PM PDT 24 3489625580 ps
T1146 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.4215514913 Jul 28 05:18:04 PM PDT 24 Jul 28 05:18:07 PM PDT 24 208253195 ps
T1147 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.212588460 Jul 28 05:18:06 PM PDT 24 Jul 28 05:18:08 PM PDT 24 56013686 ps
T1148 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.2385853439 Jul 28 05:18:06 PM PDT 24 Jul 28 05:18:07 PM PDT 24 48656616 ps
T1149 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3286679635 Jul 28 05:17:59 PM PDT 24 Jul 28 05:18:32 PM PDT 24 3777038593 ps
T1150 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3054504238 Jul 28 05:18:08 PM PDT 24 Jul 28 05:18:11 PM PDT 24 128189170 ps

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.813694982
Short name T1
Test name
Test status
Simulation time 1525542790 ps
CPU time 7.18 seconds
Started Jul 28 07:18:56 PM PDT 24
Finished Jul 28 07:19:03 PM PDT 24
Peak memory 233608 kb
Host smart-91fe0da6-92c9-4054-9d4d-8e9bf20da4de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813694982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap.
813694982
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.3560806565
Short name T12
Test name
Test status
Simulation time 11895976457 ps
CPU time 68.31 seconds
Started Jul 28 07:20:49 PM PDT 24
Finished Jul 28 07:21:58 PM PDT 24
Peak memory 254612 kb
Host smart-c61af7a0-ed56-48ed-84fc-b66409e82973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560806565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.3560806565
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.2202527004
Short name T16
Test name
Test status
Simulation time 87589540137 ps
CPU time 785.76 seconds
Started Jul 28 07:19:25 PM PDT 24
Finished Jul 28 07:32:31 PM PDT 24
Peak memory 282924 kb
Host smart-7bd617a0-514f-45fc-896f-544cca910c83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202527004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.2202527004
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.1150197899
Short name T21
Test name
Test status
Simulation time 103906551488 ps
CPU time 351.11 seconds
Started Jul 28 07:19:52 PM PDT 24
Finished Jul 28 07:25:44 PM PDT 24
Peak memory 266084 kb
Host smart-12186c51-5e0e-4be3-80ca-bdcbf5d67532
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150197899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.1150197899
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.3923751991
Short name T125
Test name
Test status
Simulation time 138677614 ps
CPU time 2.58 seconds
Started Jul 28 05:18:04 PM PDT 24
Finished Jul 28 05:18:06 PM PDT 24
Peak memory 217168 kb
Host smart-f3a71a4d-9bb5-4b9a-844d-ed556c6ab197
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923751991 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.3923751991
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.3143632204
Short name T48
Test name
Test status
Simulation time 153595786058 ps
CPU time 707.38 seconds
Started Jul 28 07:21:19 PM PDT 24
Finished Jul 28 07:33:07 PM PDT 24
Peak memory 282464 kb
Host smart-0d776e74-0f46-4ff3-8681-f45b4830ab9b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143632204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.3143632204
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.1484045921
Short name T75
Test name
Test status
Simulation time 22127509 ps
CPU time 0.74 seconds
Started Jul 28 07:18:08 PM PDT 24
Finished Jul 28 07:18:09 PM PDT 24
Peak memory 216900 kb
Host smart-5ae91bb7-5f97-4c89-9121-20d3fa2189bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484045921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.1484045921
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.136274759
Short name T57
Test name
Test status
Simulation time 367135653564 ps
CPU time 850.86 seconds
Started Jul 28 07:22:08 PM PDT 24
Finished Jul 28 07:36:19 PM PDT 24
Peak memory 266532 kb
Host smart-5c2584b6-df09-49ed-afb4-10cdfadeee50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136274759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stres
s_all.136274759
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.1068634426
Short name T65
Test name
Test status
Simulation time 9152323963 ps
CPU time 98.43 seconds
Started Jul 28 07:21:27 PM PDT 24
Finished Jul 28 07:23:05 PM PDT 24
Peak memory 267216 kb
Host smart-55acc16c-ef72-45a9-b685-bd9e6dff4ded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068634426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.1068634426
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.259999730
Short name T76
Test name
Test status
Simulation time 62079742 ps
CPU time 1.13 seconds
Started Jul 28 07:18:23 PM PDT 24
Finished Jul 28 07:18:25 PM PDT 24
Peak memory 235956 kb
Host smart-3219a968-8cd9-4d5b-96f2-1ceb85f751a9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259999730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.259999730
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.2907937466
Short name T41
Test name
Test status
Simulation time 423480122513 ps
CPU time 779.69 seconds
Started Jul 28 07:18:55 PM PDT 24
Finished Jul 28 07:31:55 PM PDT 24
Peak memory 274452 kb
Host smart-21cac36b-57de-4777-b090-150c5e2ca2df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907937466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.2907937466
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.4166393070
Short name T4
Test name
Test status
Simulation time 7669189860 ps
CPU time 20.48 seconds
Started Jul 28 07:20:29 PM PDT 24
Finished Jul 28 07:20:49 PM PDT 24
Peak memory 219772 kb
Host smart-4b4c71e6-2b33-4e93-b3de-bbe2ae4924f6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4166393070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.4166393070
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.2475717774
Short name T216
Test name
Test status
Simulation time 4770394348 ps
CPU time 98.29 seconds
Started Jul 28 07:20:31 PM PDT 24
Finished Jul 28 07:22:09 PM PDT 24
Peak memory 265776 kb
Host smart-127491f1-45dc-4a18-88b6-b4e9cfbc513f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475717774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.2475717774
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.3676538159
Short name T52
Test name
Test status
Simulation time 39239172982 ps
CPU time 83.02 seconds
Started Jul 28 07:21:01 PM PDT 24
Finished Jul 28 07:22:24 PM PDT 24
Peak memory 265136 kb
Host smart-141020f1-4885-4abe-8fa4-8916999c5443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676538159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmd
s.3676538159
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.641906522
Short name T191
Test name
Test status
Simulation time 923560390 ps
CPU time 20.52 seconds
Started Jul 28 05:18:00 PM PDT 24
Finished Jul 28 05:18:21 PM PDT 24
Peak memory 222032 kb
Host smart-29acfaf2-910f-40f8-b270-2f3b2f24924e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641906522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_
tl_intg_err.641906522
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.3400181558
Short name T131
Test name
Test status
Simulation time 90980840 ps
CPU time 2.18 seconds
Started Jul 28 05:17:58 PM PDT 24
Finished Jul 28 05:18:00 PM PDT 24
Peak memory 215980 kb
Host smart-5b7d0a11-d54c-45d5-ab7b-6be21a76dd41
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400181558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.3
400181558
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.3426371615
Short name T206
Test name
Test status
Simulation time 26219684715 ps
CPU time 243.4 seconds
Started Jul 28 07:18:06 PM PDT 24
Finished Jul 28 07:22:09 PM PDT 24
Peak memory 266080 kb
Host smart-9c21485c-0fd7-42e7-b31d-ed602d48dadb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426371615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds
.3426371615
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.283724571
Short name T110
Test name
Test status
Simulation time 50921925 ps
CPU time 3.37 seconds
Started Jul 28 05:18:01 PM PDT 24
Finished Jul 28 05:18:04 PM PDT 24
Peak memory 216104 kb
Host smart-5ea557da-ea5e-49bd-b7d8-494c74bf7131
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283724571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.283724571
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.2270153584
Short name T198
Test name
Test status
Simulation time 28369081641 ps
CPU time 124.26 seconds
Started Jul 28 07:18:23 PM PDT 24
Finished Jul 28 07:20:27 PM PDT 24
Peak memory 258380 kb
Host smart-ecd35a30-ee7e-4da0-ab9d-1805273a64c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270153584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.2270153584
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.4048798901
Short name T215
Test name
Test status
Simulation time 112007297827 ps
CPU time 234.38 seconds
Started Jul 28 07:20:06 PM PDT 24
Finished Jul 28 07:24:01 PM PDT 24
Peak memory 258452 kb
Host smart-5262677a-7cb2-476c-8a39-261412bccf8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048798901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.4048798901
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.1201913473
Short name T42
Test name
Test status
Simulation time 100486892 ps
CPU time 1.04 seconds
Started Jul 28 07:18:45 PM PDT 24
Finished Jul 28 07:18:46 PM PDT 24
Peak memory 218652 kb
Host smart-c7841f3c-423a-45cb-8398-75701a53c7d4
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201913473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.spi_device_mem_parity.1201913473
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.1198889244
Short name T53
Test name
Test status
Simulation time 180005471015 ps
CPU time 299.43 seconds
Started Jul 28 07:18:15 PM PDT 24
Finished Jul 28 07:23:15 PM PDT 24
Peak memory 250112 kb
Host smart-215bbd20-c7fc-418f-bb5b-4c9afd2b9a80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198889244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.1198889244
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.3974606979
Short name T14
Test name
Test status
Simulation time 1491947634 ps
CPU time 35.89 seconds
Started Jul 28 07:22:12 PM PDT 24
Finished Jul 28 07:22:48 PM PDT 24
Peak memory 256560 kb
Host smart-a5f3f548-fc8a-450c-9f4f-4988d74ae9f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974606979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.3974606979
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.4213085056
Short name T146
Test name
Test status
Simulation time 338515817535 ps
CPU time 778.16 seconds
Started Jul 28 07:19:31 PM PDT 24
Finished Jul 28 07:32:29 PM PDT 24
Peak memory 273924 kb
Host smart-26a79540-d085-44c9-8a85-875f986133c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213085056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.4213085056
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.2810722776
Short name T299
Test name
Test status
Simulation time 7173278480 ps
CPU time 141.73 seconds
Started Jul 28 07:20:36 PM PDT 24
Finished Jul 28 07:22:58 PM PDT 24
Peak memory 269320 kb
Host smart-dc8dd671-66ad-4835-8a1f-e491011f68be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810722776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.2810722776
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.3965437642
Short name T228
Test name
Test status
Simulation time 14023741856 ps
CPU time 178.19 seconds
Started Jul 28 07:22:08 PM PDT 24
Finished Jul 28 07:25:07 PM PDT 24
Peak memory 253944 kb
Host smart-1e9b5e75-c1bb-4f6d-9736-4bb4ea65b9ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965437642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.3965437642
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.3068036675
Short name T366
Test name
Test status
Simulation time 67408353 ps
CPU time 0.69 seconds
Started Jul 28 07:18:18 PM PDT 24
Finished Jul 28 07:18:19 PM PDT 24
Peak memory 206100 kb
Host smart-38b48f52-2376-4f4f-bbf7-bb1df77a3607
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068036675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.3
068036675
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.1130590119
Short name T318
Test name
Test status
Simulation time 248083080 ps
CPU time 13.46 seconds
Started Jul 28 07:20:38 PM PDT 24
Finished Jul 28 07:20:51 PM PDT 24
Peak memory 241900 kb
Host smart-218c6ae1-6f73-46c9-84b5-f4aea1140160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130590119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.1130590119
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.2668035300
Short name T805
Test name
Test status
Simulation time 46248106362 ps
CPU time 165.25 seconds
Started Jul 28 07:21:48 PM PDT 24
Finished Jul 28 07:24:34 PM PDT 24
Peak memory 267604 kb
Host smart-43caa4cd-9170-481a-adc8-296e78d11a3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668035300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.2668035300
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.4029700375
Short name T203
Test name
Test status
Simulation time 213732138041 ps
CPU time 391.62 seconds
Started Jul 28 07:18:42 PM PDT 24
Finished Jul 28 07:25:13 PM PDT 24
Peak memory 257684 kb
Host smart-93504ab3-9a80-4531-b5cc-dd1040ce778d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029700375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.4029700375
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2106396371
Short name T185
Test name
Test status
Simulation time 126376233 ps
CPU time 4.09 seconds
Started Jul 28 05:17:53 PM PDT 24
Finished Jul 28 05:17:58 PM PDT 24
Peak memory 216368 kb
Host smart-614c871d-f1dd-4641-b7a1-006ed0cde4ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106396371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.2
106396371
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.1593783165
Short name T35
Test name
Test status
Simulation time 2816410761 ps
CPU time 62.05 seconds
Started Jul 28 07:21:30 PM PDT 24
Finished Jul 28 07:22:32 PM PDT 24
Peak memory 251156 kb
Host smart-52d8578c-5eec-42e5-82af-8f8496fe8bd2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593783165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.1593783165
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.514398635
Short name T67
Test name
Test status
Simulation time 20760614693 ps
CPU time 143.3 seconds
Started Jul 28 07:18:44 PM PDT 24
Finished Jul 28 07:21:08 PM PDT 24
Peak memory 266432 kb
Host smart-3b5b607b-b16d-4d10-98d3-20d98ea6e0c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514398635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds.
514398635
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1442941542
Short name T193
Test name
Test status
Simulation time 1009113138 ps
CPU time 13.12 seconds
Started Jul 28 05:18:14 PM PDT 24
Finished Jul 28 05:18:28 PM PDT 24
Peak memory 216612 kb
Host smart-5033d0fb-9919-4740-9091-962ec4f60efd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442941542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.1442941542
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.1166773913
Short name T139
Test name
Test status
Simulation time 8407080169 ps
CPU time 5.35 seconds
Started Jul 28 07:18:06 PM PDT 24
Finished Jul 28 07:18:11 PM PDT 24
Peak memory 217256 kb
Host smart-8349ced9-0254-4fc9-9224-aeb90c8647a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166773913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.1166773913
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.1235741237
Short name T208
Test name
Test status
Simulation time 7041988592 ps
CPU time 72.81 seconds
Started Jul 28 07:19:15 PM PDT 24
Finished Jul 28 07:20:28 PM PDT 24
Peak memory 262892 kb
Host smart-68432eb7-027e-4dfb-a514-acc40e86fe5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235741237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.1235741237
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.930280218
Short name T291
Test name
Test status
Simulation time 245987909768 ps
CPU time 635.5 seconds
Started Jul 28 07:20:32 PM PDT 24
Finished Jul 28 07:31:08 PM PDT 24
Peak memory 266532 kb
Host smart-008682bf-0c2b-42d0-b456-8f9d6f1979e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930280218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idle
.930280218
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.2680000078
Short name T289
Test name
Test status
Simulation time 43618752800 ps
CPU time 212.44 seconds
Started Jul 28 07:18:09 PM PDT 24
Finished Jul 28 07:21:41 PM PDT 24
Peak memory 254192 kb
Host smart-bc51f10b-12a3-451a-bf83-38a915213a1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680000078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.2680000078
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.620988048
Short name T149
Test name
Test status
Simulation time 32974350274 ps
CPU time 279.7 seconds
Started Jul 28 07:20:06 PM PDT 24
Finished Jul 28 07:24:45 PM PDT 24
Peak memory 291104 kb
Host smart-69c4737f-5b2c-4693-bf98-e83b99730cb7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620988048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stres
s_all.620988048
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.323479458
Short name T23
Test name
Test status
Simulation time 44791895472 ps
CPU time 219.4 seconds
Started Jul 28 07:20:10 PM PDT 24
Finished Jul 28 07:23:49 PM PDT 24
Peak memory 250160 kb
Host smart-b84e5686-c41c-4ee4-932a-b15a9cf091b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323479458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stres
s_all.323479458
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.2825835686
Short name T324
Test name
Test status
Simulation time 3274011757 ps
CPU time 15.17 seconds
Started Jul 28 07:20:21 PM PDT 24
Finished Jul 28 07:20:36 PM PDT 24
Peak memory 225496 kb
Host smart-4ca6816f-b69d-4cec-9849-7e6a0d7daca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825835686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.2825835686
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.3106356948
Short name T118
Test name
Test status
Simulation time 132403472 ps
CPU time 3.94 seconds
Started Jul 28 05:17:56 PM PDT 24
Finished Jul 28 05:18:00 PM PDT 24
Peak memory 216284 kb
Host smart-baa6150a-03ca-4200-ba50-ab47d6dec86b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106356948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
3106356948
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.1040163865
Short name T45
Test name
Test status
Simulation time 799014185 ps
CPU time 4.49 seconds
Started Jul 28 07:19:11 PM PDT 24
Finished Jul 28 07:19:16 PM PDT 24
Peak memory 225448 kb
Host smart-87e9bbad-a359-4422-b1c8-5205a2592687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040163865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.1040163865
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3074153901
Short name T111
Test name
Test status
Simulation time 574868176 ps
CPU time 14.31 seconds
Started Jul 28 05:17:51 PM PDT 24
Finished Jul 28 05:18:06 PM PDT 24
Peak memory 215960 kb
Host smart-8ba03cbd-24f2-4987-8969-e2b3359b6d89
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074153901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.3074153901
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.1458495193
Short name T39
Test name
Test status
Simulation time 3029626083 ps
CPU time 32.89 seconds
Started Jul 28 07:18:08 PM PDT 24
Finished Jul 28 07:18:41 PM PDT 24
Peak memory 241748 kb
Host smart-a50ae8d5-0a39-4964-b583-d85ab68263ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458495193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.1458495193
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.2834137969
Short name T684
Test name
Test status
Simulation time 5490369358 ps
CPU time 10.63 seconds
Started Jul 28 07:18:04 PM PDT 24
Finished Jul 28 07:18:15 PM PDT 24
Peak memory 225536 kb
Host smart-a752b58f-d0f2-4f15-bb7f-ffd66820055e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834137969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.2834137969
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.1890127221
Short name T645
Test name
Test status
Simulation time 2453393980 ps
CPU time 28.77 seconds
Started Jul 28 07:18:08 PM PDT 24
Finished Jul 28 07:18:37 PM PDT 24
Peak memory 217292 kb
Host smart-c0580850-9201-4c00-8a11-3263acac6801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890127221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.1890127221
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.2518840509
Short name T304
Test name
Test status
Simulation time 49198139987 ps
CPU time 499.66 seconds
Started Jul 28 07:19:35 PM PDT 24
Finished Jul 28 07:27:54 PM PDT 24
Peak memory 265452 kb
Host smart-79f1c166-7e43-4f99-8b0a-e04f373cd9f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518840509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.2518840509
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.2065437444
Short name T157
Test name
Test status
Simulation time 2437884915 ps
CPU time 17.14 seconds
Started Jul 28 07:19:27 PM PDT 24
Finished Jul 28 07:19:44 PM PDT 24
Peak memory 241860 kb
Host smart-36dc561a-74af-4a2e-bf90-21a581616cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065437444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.2065437444
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.2491015194
Short name T297
Test name
Test status
Simulation time 179578234959 ps
CPU time 318.96 seconds
Started Jul 28 07:20:03 PM PDT 24
Finished Jul 28 07:25:22 PM PDT 24
Peak memory 266256 kb
Host smart-b22ad622-e238-478c-9710-5274df12df33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491015194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.2491015194
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.3668309214
Short name T217
Test name
Test status
Simulation time 247695894662 ps
CPU time 479.94 seconds
Started Jul 28 07:20:22 PM PDT 24
Finished Jul 28 07:28:22 PM PDT 24
Peak memory 264500 kb
Host smart-6700775d-5a42-4de5-a37d-d99c2f49c8e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668309214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.3668309214
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.1079085908
Short name T64
Test name
Test status
Simulation time 38859725669 ps
CPU time 416.44 seconds
Started Jul 28 07:21:15 PM PDT 24
Finished Jul 28 07:28:12 PM PDT 24
Peak memory 268240 kb
Host smart-a93e0de6-c1ea-4a22-b2c6-a523fbc7770d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079085908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.1079085908
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3594432903
Short name T94
Test name
Test status
Simulation time 57342941 ps
CPU time 1.41 seconds
Started Jul 28 05:17:50 PM PDT 24
Finished Jul 28 05:17:51 PM PDT 24
Peak memory 207796 kb
Host smart-2617e39b-97de-4525-ac53-795810aa2448
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594432903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.3594432903
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.3110860878
Short name T128
Test name
Test status
Simulation time 2521927599 ps
CPU time 15.12 seconds
Started Jul 28 05:18:14 PM PDT 24
Finished Jul 28 05:18:29 PM PDT 24
Peak memory 207880 kb
Host smart-09c90485-e399-4c7f-bd68-85f5dfe6845e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110860878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.3110860878
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.572302449
Short name T1139
Test name
Test status
Simulation time 954167144 ps
CPU time 13.35 seconds
Started Jul 28 05:17:58 PM PDT 24
Finished Jul 28 05:18:11 PM PDT 24
Peak memory 207536 kb
Host smart-bca6bc90-235b-4329-94a8-3980550074a7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572302449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_bit_bash.572302449
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.3045057124
Short name T1124
Test name
Test status
Simulation time 48744726 ps
CPU time 1.62 seconds
Started Jul 28 05:17:59 PM PDT 24
Finished Jul 28 05:18:01 PM PDT 24
Peak memory 217108 kb
Host smart-3679582a-6979-4077-9530-337f9231b12a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045057124 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.3045057124
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.720701621
Short name T133
Test name
Test status
Simulation time 95857348 ps
CPU time 2.6 seconds
Started Jul 28 05:17:52 PM PDT 24
Finished Jul 28 05:17:55 PM PDT 24
Peak memory 215972 kb
Host smart-4b2afb6b-06de-4f8b-b250-302e9b7b9b11
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720701621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.720701621
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.919369376
Short name T1117
Test name
Test status
Simulation time 12049908 ps
CPU time 0.72 seconds
Started Jul 28 05:18:11 PM PDT 24
Finished Jul 28 05:18:12 PM PDT 24
Peak memory 204452 kb
Host smart-c82e6962-9790-48d8-bfb3-bf12638c47e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919369376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.919369376
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.1074148666
Short name T1088
Test name
Test status
Simulation time 53491642 ps
CPU time 1.4 seconds
Started Jul 28 05:17:52 PM PDT 24
Finished Jul 28 05:17:54 PM PDT 24
Peak memory 216088 kb
Host smart-bd244f6a-a444-456b-b0a7-1ffd7e2fcb16
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074148666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.1074148666
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.2435743134
Short name T1141
Test name
Test status
Simulation time 9802968 ps
CPU time 0.67 seconds
Started Jul 28 05:18:08 PM PDT 24
Finished Jul 28 05:18:09 PM PDT 24
Peak memory 204752 kb
Host smart-60aeb870-dea3-438e-bf21-1527e4cacf9f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435743134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.2435743134
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.2237271914
Short name T1049
Test name
Test status
Simulation time 114688749 ps
CPU time 3.44 seconds
Started Jul 28 05:17:43 PM PDT 24
Finished Jul 28 05:17:47 PM PDT 24
Peak memory 215940 kb
Host smart-4888784b-c9a7-445f-bf6a-3da511081e7e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237271914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.2237271914
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.2504121961
Short name T105
Test name
Test status
Simulation time 483025574 ps
CPU time 2.36 seconds
Started Jul 28 05:17:53 PM PDT 24
Finished Jul 28 05:17:56 PM PDT 24
Peak memory 216260 kb
Host smart-9eb9209d-9272-422f-a855-4c6027f1bbb2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504121961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.2
504121961
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.3832922255
Short name T136
Test name
Test status
Simulation time 1227978431 ps
CPU time 8.66 seconds
Started Jul 28 05:17:59 PM PDT 24
Finished Jul 28 05:18:07 PM PDT 24
Peak memory 215968 kb
Host smart-cfed39b8-ddc0-4e0d-bc8b-33dd2a72f8e0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832922255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.3832922255
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.1361812115
Short name T135
Test name
Test status
Simulation time 4808956996 ps
CPU time 22.98 seconds
Started Jul 28 05:18:00 PM PDT 24
Finished Jul 28 05:18:23 PM PDT 24
Peak memory 207988 kb
Host smart-d48078d6-ddff-4281-ae24-4f21f9091a39
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361812115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.1361812115
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.674466783
Short name T92
Test name
Test status
Simulation time 65857417 ps
CPU time 1.14 seconds
Started Jul 28 05:17:47 PM PDT 24
Finished Jul 28 05:17:48 PM PDT 24
Peak memory 207796 kb
Host smart-e940692b-b178-444a-94d0-6dcfa440a985
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674466783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_hw_reset.674466783
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1195641998
Short name T1123
Test name
Test status
Simulation time 112216352 ps
CPU time 1.63 seconds
Started Jul 28 05:18:12 PM PDT 24
Finished Jul 28 05:18:14 PM PDT 24
Peak memory 216144 kb
Host smart-60b627c5-c632-4982-a863-baaef9aaae91
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195641998 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.1195641998
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.1497157869
Short name T1094
Test name
Test status
Simulation time 66648756 ps
CPU time 2.21 seconds
Started Jul 28 05:17:53 PM PDT 24
Finished Jul 28 05:17:55 PM PDT 24
Peak memory 216020 kb
Host smart-d8409ad7-5cbc-4fea-93c2-5a66281bf300
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497157869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.1
497157869
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3130504001
Short name T1067
Test name
Test status
Simulation time 56083666 ps
CPU time 0.72 seconds
Started Jul 28 05:17:53 PM PDT 24
Finished Jul 28 05:17:54 PM PDT 24
Peak memory 204676 kb
Host smart-0d196701-6b1b-4b02-b569-f815ce638e92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130504001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.3
130504001
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.1977126890
Short name T126
Test name
Test status
Simulation time 23221900 ps
CPU time 1.52 seconds
Started Jul 28 05:18:08 PM PDT 24
Finished Jul 28 05:18:10 PM PDT 24
Peak memory 216044 kb
Host smart-c657f470-9d90-48b7-b603-ce18827c0984
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977126890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.1977126890
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.1779095910
Short name T1108
Test name
Test status
Simulation time 38121752 ps
CPU time 0.71 seconds
Started Jul 28 05:17:58 PM PDT 24
Finished Jul 28 05:17:59 PM PDT 24
Peak memory 204396 kb
Host smart-670a8286-dbb2-4ee0-9f3c-cf77f059b7f1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779095910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.1779095910
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.883778595
Short name T1062
Test name
Test status
Simulation time 57882956 ps
CPU time 1.74 seconds
Started Jul 28 05:17:48 PM PDT 24
Finished Jul 28 05:17:50 PM PDT 24
Peak memory 216028 kb
Host smart-08503638-2354-4d12-92f9-5f3d74a9ba79
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883778595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sp
i_device_same_csr_outstanding.883778595
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.264979900
Short name T115
Test name
Test status
Simulation time 676546079 ps
CPU time 4.73 seconds
Started Jul 28 05:17:52 PM PDT 24
Finished Jul 28 05:17:57 PM PDT 24
Peak memory 216176 kb
Host smart-9a96f681-b1c8-480b-be2e-fa367334330d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264979900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.264979900
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.399394435
Short name T1113
Test name
Test status
Simulation time 1883193540 ps
CPU time 21.13 seconds
Started Jul 28 05:18:03 PM PDT 24
Finished Jul 28 05:18:24 PM PDT 24
Peak memory 220604 kb
Host smart-6bb605ed-d490-41cf-8e37-e1dd1f484f5f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399394435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_
tl_intg_err.399394435
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3209567103
Short name T1057
Test name
Test status
Simulation time 192439585 ps
CPU time 1.73 seconds
Started Jul 28 05:17:51 PM PDT 24
Finished Jul 28 05:17:53 PM PDT 24
Peak memory 217008 kb
Host smart-5fc0319d-1d06-420d-81f6-665004884668
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209567103 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.3209567103
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.1249668310
Short name T1092
Test name
Test status
Simulation time 132804640 ps
CPU time 2.33 seconds
Started Jul 28 05:18:24 PM PDT 24
Finished Jul 28 05:18:27 PM PDT 24
Peak memory 216064 kb
Host smart-a3eb4b29-6215-49f0-a167-0b2ec936e8e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249668310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
1249668310
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.3926573217
Short name T1050
Test name
Test status
Simulation time 12935646 ps
CPU time 0.67 seconds
Started Jul 28 05:17:51 PM PDT 24
Finished Jul 28 05:17:52 PM PDT 24
Peak memory 204796 kb
Host smart-2297ce2b-1376-41c5-9b77-b0e6e760e4be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926573217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
3926573217
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1746078947
Short name T1091
Test name
Test status
Simulation time 58889154 ps
CPU time 3.61 seconds
Started Jul 28 05:18:00 PM PDT 24
Finished Jul 28 05:18:04 PM PDT 24
Peak memory 215976 kb
Host smart-5272401f-492e-4b61-9912-724a2f6d0b8e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746078947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.1746078947
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.4215514913
Short name T1146
Test name
Test status
Simulation time 208253195 ps
CPU time 2.91 seconds
Started Jul 28 05:18:04 PM PDT 24
Finished Jul 28 05:18:07 PM PDT 24
Peak memory 216260 kb
Host smart-52bdbaaa-9c77-4413-8be1-9c7a9d6f750c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215514913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
4215514913
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.522693958
Short name T190
Test name
Test status
Simulation time 303367725 ps
CPU time 17.35 seconds
Started Jul 28 05:18:08 PM PDT 24
Finished Jul 28 05:18:26 PM PDT 24
Peak memory 216040 kb
Host smart-a335aa39-5183-4f75-aeca-e0192f2f6d19
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522693958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device
_tl_intg_err.522693958
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.4245768696
Short name T1064
Test name
Test status
Simulation time 52516180 ps
CPU time 3.6 seconds
Started Jul 28 05:18:00 PM PDT 24
Finished Jul 28 05:18:03 PM PDT 24
Peak memory 218536 kb
Host smart-e5d6c1a7-bf4c-481a-bceb-ec687a9a67ba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245768696 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.4245768696
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.1503883356
Short name T1073
Test name
Test status
Simulation time 34089752 ps
CPU time 1.16 seconds
Started Jul 28 05:18:09 PM PDT 24
Finished Jul 28 05:18:10 PM PDT 24
Peak memory 215976 kb
Host smart-91c054df-4208-4665-94e4-825f9b2a4a8a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503883356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
1503883356
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.1459991724
Short name T1038
Test name
Test status
Simulation time 44025611 ps
CPU time 0.71 seconds
Started Jul 28 05:17:54 PM PDT 24
Finished Jul 28 05:17:55 PM PDT 24
Peak memory 204492 kb
Host smart-9cd6dc6a-502a-412b-8694-e82ffdfbaf2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459991724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
1459991724
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3054504238
Short name T1150
Test name
Test status
Simulation time 128189170 ps
CPU time 2.78 seconds
Started Jul 28 05:18:08 PM PDT 24
Finished Jul 28 05:18:11 PM PDT 24
Peak memory 215932 kb
Host smart-d3c2adb5-c838-498c-89bd-be2738e9dc88
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054504238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.3054504238
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.163025871
Short name T161
Test name
Test status
Simulation time 839500324 ps
CPU time 6.9 seconds
Started Jul 28 05:17:57 PM PDT 24
Finished Jul 28 05:18:04 PM PDT 24
Peak memory 215992 kb
Host smart-dbedc6d3-bf4d-44a4-bd17-236283919321
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163025871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device
_tl_intg_err.163025871
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.2620626062
Short name T1076
Test name
Test status
Simulation time 225081558 ps
CPU time 1.81 seconds
Started Jul 28 05:17:54 PM PDT 24
Finished Jul 28 05:17:56 PM PDT 24
Peak memory 216028 kb
Host smart-e5abd41e-5e86-4f36-8e98-d2598f202685
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620626062 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.2620626062
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.1434148473
Short name T134
Test name
Test status
Simulation time 782675083 ps
CPU time 2.85 seconds
Started Jul 28 05:18:11 PM PDT 24
Finished Jul 28 05:18:14 PM PDT 24
Peak memory 215996 kb
Host smart-765138df-646b-4890-afb4-79d8a0e25d26
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434148473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
1434148473
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.1315522315
Short name T1061
Test name
Test status
Simulation time 52162935 ps
CPU time 0.68 seconds
Started Jul 28 05:18:06 PM PDT 24
Finished Jul 28 05:18:07 PM PDT 24
Peak memory 204476 kb
Host smart-45c55f7c-5cff-4a54-a1b5-bd1f1cdb992b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315522315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
1315522315
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.650096273
Short name T1110
Test name
Test status
Simulation time 208856535 ps
CPU time 3.59 seconds
Started Jul 28 05:17:54 PM PDT 24
Finished Jul 28 05:17:58 PM PDT 24
Peak memory 216076 kb
Host smart-6b37dc00-7c0a-4448-8ae8-3bca388e3946
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650096273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.s
pi_device_same_csr_outstanding.650096273
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.2820122177
Short name T120
Test name
Test status
Simulation time 322298878 ps
CPU time 2.24 seconds
Started Jul 28 05:18:10 PM PDT 24
Finished Jul 28 05:18:13 PM PDT 24
Peak memory 216264 kb
Host smart-932d54a7-81d7-4ef8-89ca-e3aa4255e3a1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820122177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
2820122177
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.1009762600
Short name T1126
Test name
Test status
Simulation time 414602834 ps
CPU time 7.14 seconds
Started Jul 28 05:17:58 PM PDT 24
Finished Jul 28 05:18:05 PM PDT 24
Peak memory 216116 kb
Host smart-7568af99-9f68-4b28-a9f3-0ad082d40588
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009762600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.1009762600
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.1317710700
Short name T177
Test name
Test status
Simulation time 1438233239 ps
CPU time 2.67 seconds
Started Jul 28 05:18:19 PM PDT 24
Finished Jul 28 05:18:22 PM PDT 24
Peak memory 216320 kb
Host smart-680530de-97ce-466b-ba2a-574abf6fea8f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317710700 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.1317710700
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.2776909921
Short name T137
Test name
Test status
Simulation time 102497457 ps
CPU time 1.45 seconds
Started Jul 28 05:18:12 PM PDT 24
Finished Jul 28 05:18:14 PM PDT 24
Peak memory 216068 kb
Host smart-e708b72d-8953-43cb-b2cc-375e3fec8fd6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776909921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
2776909921
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.1968703607
Short name T1077
Test name
Test status
Simulation time 16409153 ps
CPU time 0.78 seconds
Started Jul 28 05:17:59 PM PDT 24
Finished Jul 28 05:18:00 PM PDT 24
Peak memory 204508 kb
Host smart-dcddcffc-94f0-4d8e-af8c-3a905501d875
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968703607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
1968703607
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.837329145
Short name T1087
Test name
Test status
Simulation time 120008436 ps
CPU time 3.69 seconds
Started Jul 28 05:18:02 PM PDT 24
Finished Jul 28 05:18:06 PM PDT 24
Peak memory 216016 kb
Host smart-aa995457-9b07-4cf1-9b83-15952c93c91a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837329145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.s
pi_device_same_csr_outstanding.837329145
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.1202119906
Short name T117
Test name
Test status
Simulation time 163474891 ps
CPU time 1.77 seconds
Started Jul 28 05:17:58 PM PDT 24
Finished Jul 28 05:18:00 PM PDT 24
Peak memory 216248 kb
Host smart-a6aace0b-5554-4ca0-93f6-a6df6e914cb7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202119906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
1202119906
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.1492542306
Short name T192
Test name
Test status
Simulation time 862888518 ps
CPU time 7.82 seconds
Started Jul 28 05:18:07 PM PDT 24
Finished Jul 28 05:18:15 PM PDT 24
Peak memory 216324 kb
Host smart-c03a27ea-17d4-409a-bd66-f125b0a86512
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492542306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.1492542306
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.1276499780
Short name T122
Test name
Test status
Simulation time 113297672 ps
CPU time 4.26 seconds
Started Jul 28 05:18:03 PM PDT 24
Finished Jul 28 05:18:07 PM PDT 24
Peak memory 218800 kb
Host smart-bd0986e8-6cba-4870-a380-e9fe7d962ef0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276499780 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.1276499780
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.2729511147
Short name T1129
Test name
Test status
Simulation time 122562933 ps
CPU time 2.25 seconds
Started Jul 28 05:18:08 PM PDT 24
Finished Jul 28 05:18:10 PM PDT 24
Peak memory 216028 kb
Host smart-4788e942-5ced-4a8e-a8a5-7f33c79ccac2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729511147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
2729511147
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.939997447
Short name T1105
Test name
Test status
Simulation time 13816118 ps
CPU time 0.79 seconds
Started Jul 28 05:18:24 PM PDT 24
Finished Jul 28 05:18:25 PM PDT 24
Peak memory 204808 kb
Host smart-d1ddfbc8-75ae-4e1f-96c2-681c05b3b330
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939997447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.939997447
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.829287781
Short name T1116
Test name
Test status
Simulation time 255970388 ps
CPU time 4.19 seconds
Started Jul 28 05:17:59 PM PDT 24
Finished Jul 28 05:18:13 PM PDT 24
Peak memory 216016 kb
Host smart-8f492ef5-a6fb-4443-ab03-9c0f763e7882
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829287781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.s
pi_device_same_csr_outstanding.829287781
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.517623541
Short name T106
Test name
Test status
Simulation time 60521818 ps
CPU time 3.86 seconds
Started Jul 28 05:18:13 PM PDT 24
Finished Jul 28 05:18:17 PM PDT 24
Peak memory 217276 kb
Host smart-082d32ee-8548-4835-bcf2-63e2e54e5abe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517623541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.517623541
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.3019984016
Short name T1086
Test name
Test status
Simulation time 278490314 ps
CPU time 7.59 seconds
Started Jul 28 05:18:14 PM PDT 24
Finished Jul 28 05:18:21 PM PDT 24
Peak memory 216100 kb
Host smart-7864df4d-77e3-4c2b-9192-243fae14b0e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019984016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.3019984016
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3612619505
Short name T1104
Test name
Test status
Simulation time 288999664 ps
CPU time 1.81 seconds
Started Jul 28 05:18:06 PM PDT 24
Finished Jul 28 05:18:08 PM PDT 24
Peak memory 217024 kb
Host smart-6f23803d-3ac2-4f10-9dc9-b6644209fa3a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612619505 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.3612619505
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.790376269
Short name T130
Test name
Test status
Simulation time 30581599 ps
CPU time 1.85 seconds
Started Jul 28 05:18:13 PM PDT 24
Finished Jul 28 05:18:15 PM PDT 24
Peak memory 215988 kb
Host smart-0d0b2eb3-307e-49e6-9a16-a94b5384952e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790376269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.790376269
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.2805006185
Short name T1082
Test name
Test status
Simulation time 13264592 ps
CPU time 0.7 seconds
Started Jul 28 05:18:09 PM PDT 24
Finished Jul 28 05:18:10 PM PDT 24
Peak memory 204744 kb
Host smart-5de5fa3e-0316-49bc-8e08-d80a72c6f8ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805006185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
2805006185
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.212588460
Short name T1147
Test name
Test status
Simulation time 56013686 ps
CPU time 1.77 seconds
Started Jul 28 05:18:06 PM PDT 24
Finished Jul 28 05:18:08 PM PDT 24
Peak memory 207844 kb
Host smart-d1ab337a-b9aa-4226-9021-fbe5fd0b5e71
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212588460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.s
pi_device_same_csr_outstanding.212588460
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.83697725
Short name T107
Test name
Test status
Simulation time 296343630 ps
CPU time 18.22 seconds
Started Jul 28 05:18:11 PM PDT 24
Finished Jul 28 05:18:29 PM PDT 24
Peak memory 216432 kb
Host smart-b1b1de9b-9838-4e65-9d57-a3a20c4127b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83697725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_
tl_intg_err.83697725
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1486773769
Short name T1134
Test name
Test status
Simulation time 61177046 ps
CPU time 1.83 seconds
Started Jul 28 05:17:54 PM PDT 24
Finished Jul 28 05:17:56 PM PDT 24
Peak memory 216080 kb
Host smart-60f44d0b-dbc1-486e-9f42-3be000f7d6ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486773769 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.1486773769
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.184229341
Short name T132
Test name
Test status
Simulation time 335522001 ps
CPU time 2.18 seconds
Started Jul 28 05:17:48 PM PDT 24
Finished Jul 28 05:17:50 PM PDT 24
Peak memory 207844 kb
Host smart-4f51f6ed-3a94-4d87-8062-ed33a8c713a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184229341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.184229341
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3808806124
Short name T1112
Test name
Test status
Simulation time 44718917 ps
CPU time 0.69 seconds
Started Jul 28 05:17:59 PM PDT 24
Finished Jul 28 05:18:00 PM PDT 24
Peak memory 204488 kb
Host smart-4dcfae09-6f36-49b8-ac6f-692811994b1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808806124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
3808806124
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.503220257
Short name T1119
Test name
Test status
Simulation time 108764651 ps
CPU time 3.31 seconds
Started Jul 28 05:18:08 PM PDT 24
Finished Jul 28 05:18:11 PM PDT 24
Peak memory 216116 kb
Host smart-3847b332-2659-467c-becc-f781c3b0ee2d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503220257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.s
pi_device_same_csr_outstanding.503220257
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.2481660709
Short name T1115
Test name
Test status
Simulation time 160260976 ps
CPU time 2.58 seconds
Started Jul 28 05:18:24 PM PDT 24
Finished Jul 28 05:18:26 PM PDT 24
Peak memory 216288 kb
Host smart-72f5f38b-27c0-4ce1-9e18-877da7b0abc0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481660709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
2481660709
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2399219742
Short name T1135
Test name
Test status
Simulation time 679835476 ps
CPU time 14.31 seconds
Started Jul 28 05:18:10 PM PDT 24
Finished Jul 28 05:18:24 PM PDT 24
Peak memory 224192 kb
Host smart-3815cea6-a2c2-41c1-8794-9d6e6e8f3d41
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399219742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.2399219742
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1016789900
Short name T1127
Test name
Test status
Simulation time 99624391 ps
CPU time 1.64 seconds
Started Jul 28 05:18:04 PM PDT 24
Finished Jul 28 05:18:06 PM PDT 24
Peak memory 217084 kb
Host smart-f89dd344-15b0-48b8-ad4c-dc70ac240b83
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016789900 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.1016789900
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.1721652714
Short name T1137
Test name
Test status
Simulation time 65382115 ps
CPU time 1.99 seconds
Started Jul 28 05:18:15 PM PDT 24
Finished Jul 28 05:18:18 PM PDT 24
Peak memory 216020 kb
Host smart-36bf05d6-6630-4523-a9f2-935813e8097b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721652714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
1721652714
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.3055528757
Short name T1037
Test name
Test status
Simulation time 86923044 ps
CPU time 0.78 seconds
Started Jul 28 05:18:08 PM PDT 24
Finished Jul 28 05:18:08 PM PDT 24
Peak memory 204488 kb
Host smart-01daac47-695d-44d3-8084-e871bd5c41a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055528757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
3055528757
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.590931626
Short name T1100
Test name
Test status
Simulation time 29620469 ps
CPU time 1.77 seconds
Started Jul 28 05:17:58 PM PDT 24
Finished Jul 28 05:18:00 PM PDT 24
Peak memory 207816 kb
Host smart-e5f71c65-9d77-467d-bf47-dc762d2db36e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590931626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.s
pi_device_same_csr_outstanding.590931626
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3911586758
Short name T1120
Test name
Test status
Simulation time 248066597 ps
CPU time 4.14 seconds
Started Jul 28 05:18:01 PM PDT 24
Finished Jul 28 05:18:05 PM PDT 24
Peak memory 216380 kb
Host smart-384235bb-6502-4eaa-b752-e7205284b516
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911586758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
3911586758
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.3092677970
Short name T188
Test name
Test status
Simulation time 1208258182 ps
CPU time 18.83 seconds
Started Jul 28 05:17:53 PM PDT 24
Finished Jul 28 05:18:12 PM PDT 24
Peak memory 216056 kb
Host smart-8e8e41b2-6e41-49ab-93ee-d4ce39c6b3d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092677970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.3092677970
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2816222960
Short name T103
Test name
Test status
Simulation time 90227582 ps
CPU time 2.37 seconds
Started Jul 28 05:17:59 PM PDT 24
Finished Jul 28 05:18:02 PM PDT 24
Peak memory 217072 kb
Host smart-5438ab84-f116-4f71-8394-1bd51901e4a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816222960 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.2816222960
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3249228072
Short name T129
Test name
Test status
Simulation time 417479074 ps
CPU time 2.64 seconds
Started Jul 28 05:18:07 PM PDT 24
Finished Jul 28 05:18:10 PM PDT 24
Peak memory 216052 kb
Host smart-7861e77d-64f7-4e4e-9c54-a1d0403680b0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249228072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
3249228072
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1516154746
Short name T1048
Test name
Test status
Simulation time 21766205 ps
CPU time 0.71 seconds
Started Jul 28 05:18:12 PM PDT 24
Finished Jul 28 05:18:12 PM PDT 24
Peak memory 204804 kb
Host smart-36ae6159-9a65-4e3f-b086-c314937c3e79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516154746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
1516154746
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.3396962979
Short name T163
Test name
Test status
Simulation time 443683742 ps
CPU time 1.72 seconds
Started Jul 28 05:18:12 PM PDT 24
Finished Jul 28 05:18:13 PM PDT 24
Peak memory 216000 kb
Host smart-7aec46f7-9431-4c79-9245-fd7e5a9de666
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396962979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.3396962979
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.3425626409
Short name T119
Test name
Test status
Simulation time 36455454 ps
CPU time 2.29 seconds
Started Jul 28 05:18:06 PM PDT 24
Finished Jul 28 05:18:09 PM PDT 24
Peak memory 216328 kb
Host smart-e0efb1e9-3c5b-42bd-8d4c-6d79884fec3c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425626409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
3425626409
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1398875673
Short name T112
Test name
Test status
Simulation time 1509701563 ps
CPU time 13.24 seconds
Started Jul 28 05:17:57 PM PDT 24
Finished Jul 28 05:18:11 PM PDT 24
Peak memory 216460 kb
Host smart-ec674879-cac0-4bf3-bbb8-a21756b1ef80
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398875673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.1398875673
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.1186463036
Short name T1103
Test name
Test status
Simulation time 58410048 ps
CPU time 1.67 seconds
Started Jul 28 05:18:26 PM PDT 24
Finished Jul 28 05:18:28 PM PDT 24
Peak memory 216128 kb
Host smart-e3125bd9-755f-4c5b-af7c-f3ff51adfc50
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186463036 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.1186463036
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1618200183
Short name T160
Test name
Test status
Simulation time 92434225 ps
CPU time 1.38 seconds
Started Jul 28 05:18:06 PM PDT 24
Finished Jul 28 05:18:08 PM PDT 24
Peak memory 215936 kb
Host smart-1821b496-bc6d-4a16-b30f-90a0f2573045
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618200183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
1618200183
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2914646051
Short name T1101
Test name
Test status
Simulation time 15240755 ps
CPU time 0.74 seconds
Started Jul 28 05:18:09 PM PDT 24
Finished Jul 28 05:18:10 PM PDT 24
Peak memory 204384 kb
Host smart-9583076b-1efb-4487-9417-91663af21a30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914646051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
2914646051
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1742701543
Short name T1074
Test name
Test status
Simulation time 62576878 ps
CPU time 3.98 seconds
Started Jul 28 05:18:30 PM PDT 24
Finished Jul 28 05:18:34 PM PDT 24
Peak memory 216072 kb
Host smart-f13723ca-8690-4b7d-912f-351382212e34
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742701543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.1742701543
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.4190792526
Short name T114
Test name
Test status
Simulation time 1398601930 ps
CPU time 4.28 seconds
Started Jul 28 05:17:59 PM PDT 24
Finished Jul 28 05:18:03 PM PDT 24
Peak memory 216304 kb
Host smart-9c648236-e834-4b02-9dc3-4d159e2cee72
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190792526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
4190792526
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.1944706388
Short name T194
Test name
Test status
Simulation time 243362073 ps
CPU time 12.03 seconds
Started Jul 28 05:17:53 PM PDT 24
Finished Jul 28 05:18:05 PM PDT 24
Peak memory 216024 kb
Host smart-f84e622b-abbe-4066-8a17-b7115550347f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944706388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.1944706388
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.1784965917
Short name T1030
Test name
Test status
Simulation time 113381237 ps
CPU time 7.41 seconds
Started Jul 28 05:18:00 PM PDT 24
Finished Jul 28 05:18:07 PM PDT 24
Peak memory 207908 kb
Host smart-9d1a4337-93c5-4299-921f-11de0e1ae12d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784965917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.1784965917
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3286679635
Short name T1149
Test name
Test status
Simulation time 3777038593 ps
CPU time 33.03 seconds
Started Jul 28 05:17:59 PM PDT 24
Finished Jul 28 05:18:32 PM PDT 24
Peak memory 207932 kb
Host smart-67a47281-b4b4-4ecf-9d83-a6976c8527ed
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286679635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.3286679635
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3184378009
Short name T93
Test name
Test status
Simulation time 67913078 ps
CPU time 0.9 seconds
Started Jul 28 05:17:51 PM PDT 24
Finished Jul 28 05:17:52 PM PDT 24
Peak memory 207620 kb
Host smart-f9ba7f49-925e-48de-a50e-3d8a23aff9cc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184378009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.3184378009
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1634170681
Short name T1051
Test name
Test status
Simulation time 73173549 ps
CPU time 2.43 seconds
Started Jul 28 05:17:58 PM PDT 24
Finished Jul 28 05:18:00 PM PDT 24
Peak memory 217544 kb
Host smart-8feced98-3392-4aeb-8020-2e61d5eca666
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634170681 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.1634170681
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.2519685140
Short name T1058
Test name
Test status
Simulation time 39726508 ps
CPU time 2.28 seconds
Started Jul 28 05:17:50 PM PDT 24
Finished Jul 28 05:17:52 PM PDT 24
Peak memory 216080 kb
Host smart-eeba2589-25d6-42cc-91c6-272b904ba29b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519685140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.2
519685140
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.3486255683
Short name T1054
Test name
Test status
Simulation time 15981399 ps
CPU time 0.69 seconds
Started Jul 28 05:17:52 PM PDT 24
Finished Jul 28 05:17:52 PM PDT 24
Peak memory 204448 kb
Host smart-b65e3e9e-4424-4a4e-a766-3504e66004b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486255683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.3
486255683
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2295035369
Short name T1079
Test name
Test status
Simulation time 39869422 ps
CPU time 1.25 seconds
Started Jul 28 05:18:10 PM PDT 24
Finished Jul 28 05:18:11 PM PDT 24
Peak memory 216040 kb
Host smart-2fd92373-9740-4ce8-b3c5-6224fb03f954
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295035369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.2295035369
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3492226974
Short name T1035
Test name
Test status
Simulation time 14043195 ps
CPU time 0.7 seconds
Started Jul 28 05:18:14 PM PDT 24
Finished Jul 28 05:18:15 PM PDT 24
Peak memory 204736 kb
Host smart-fc56d22f-6386-473a-850d-bf6a57bb5120
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492226974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.3492226974
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.2227658933
Short name T1034
Test name
Test status
Simulation time 113021159 ps
CPU time 1.71 seconds
Started Jul 28 05:17:54 PM PDT 24
Finished Jul 28 05:17:56 PM PDT 24
Peak memory 215940 kb
Host smart-472e9c6a-19fc-4237-8896-ed07de25acd1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227658933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.2227658933
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.4172726508
Short name T108
Test name
Test status
Simulation time 249484352 ps
CPU time 1.37 seconds
Started Jul 28 05:17:48 PM PDT 24
Finished Jul 28 05:17:49 PM PDT 24
Peak memory 216284 kb
Host smart-2c9e7cc5-ce76-4001-8439-f12c10c364ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172726508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.4
172726508
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.3817851958
Short name T1145
Test name
Test status
Simulation time 3489625580 ps
CPU time 19.93 seconds
Started Jul 28 05:17:52 PM PDT 24
Finished Jul 28 05:18:17 PM PDT 24
Peak memory 216176 kb
Host smart-1f7723ce-b0fb-461a-bddc-dfa10c0d6d46
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817851958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.3817851958
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.2319632360
Short name T1111
Test name
Test status
Simulation time 44405230 ps
CPU time 0.78 seconds
Started Jul 28 05:18:04 PM PDT 24
Finished Jul 28 05:18:05 PM PDT 24
Peak memory 204468 kb
Host smart-fd8f501e-8e2a-44eb-95d1-461d9721bd95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319632360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
2319632360
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.2952276643
Short name T1142
Test name
Test status
Simulation time 152029414 ps
CPU time 0.74 seconds
Started Jul 28 05:18:18 PM PDT 24
Finished Jul 28 05:18:18 PM PDT 24
Peak memory 204852 kb
Host smart-b6b936d9-f4a3-444d-807d-9a62630c9cf9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952276643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
2952276643
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.2017429684
Short name T1065
Test name
Test status
Simulation time 67984044 ps
CPU time 0.72 seconds
Started Jul 28 05:18:23 PM PDT 24
Finished Jul 28 05:18:24 PM PDT 24
Peak memory 204768 kb
Host smart-dfb7c74a-9440-4bd0-b316-d711a1d017c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017429684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
2017429684
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.4079347152
Short name T1107
Test name
Test status
Simulation time 44341186 ps
CPU time 0.74 seconds
Started Jul 28 05:18:29 PM PDT 24
Finished Jul 28 05:18:30 PM PDT 24
Peak memory 204476 kb
Host smart-7923cc14-1cd2-48d7-841a-9b7d4996307a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079347152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
4079347152
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1989807978
Short name T1045
Test name
Test status
Simulation time 20816346 ps
CPU time 0.75 seconds
Started Jul 28 05:18:21 PM PDT 24
Finished Jul 28 05:18:22 PM PDT 24
Peak memory 204420 kb
Host smart-4a606b14-487b-4c56-999a-d5ab4d288216
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989807978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
1989807978
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.1343949827
Short name T1066
Test name
Test status
Simulation time 28071970 ps
CPU time 0.75 seconds
Started Jul 28 05:18:40 PM PDT 24
Finished Jul 28 05:18:41 PM PDT 24
Peak memory 204500 kb
Host smart-a5b629ba-e2da-44f9-a41e-327f73bc5efa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343949827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
1343949827
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.854623160
Short name T1052
Test name
Test status
Simulation time 19358531 ps
CPU time 0.68 seconds
Started Jul 28 05:18:01 PM PDT 24
Finished Jul 28 05:18:02 PM PDT 24
Peak memory 204496 kb
Host smart-5091aa65-5746-4051-9c41-7213328b7256
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854623160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.854623160
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.3747588791
Short name T1068
Test name
Test status
Simulation time 35201438 ps
CPU time 0.71 seconds
Started Jul 28 05:18:27 PM PDT 24
Finished Jul 28 05:18:28 PM PDT 24
Peak memory 204520 kb
Host smart-c1c4f2d7-1786-4dcb-9f59-520d960ff1e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747588791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
3747588791
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.16634941
Short name T1040
Test name
Test status
Simulation time 14607307 ps
CPU time 0.8 seconds
Started Jul 28 05:18:07 PM PDT 24
Finished Jul 28 05:18:07 PM PDT 24
Peak memory 204832 kb
Host smart-07ace379-2fb5-43a8-9164-a232e607c5f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16634941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.16634941
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.917113246
Short name T1118
Test name
Test status
Simulation time 78288003 ps
CPU time 0.67 seconds
Started Jul 28 05:18:12 PM PDT 24
Finished Jul 28 05:18:12 PM PDT 24
Peak memory 204484 kb
Host smart-6208b312-7d4c-47af-b540-6f607e4eb14e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917113246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.917113246
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.733710943
Short name T1099
Test name
Test status
Simulation time 420761482 ps
CPU time 13.93 seconds
Started Jul 28 05:18:02 PM PDT 24
Finished Jul 28 05:18:16 PM PDT 24
Peak memory 215972 kb
Host smart-1bf83daa-87a2-4008-b9db-f7899261811b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733710943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_aliasing.733710943
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.115235130
Short name T1069
Test name
Test status
Simulation time 2276247525 ps
CPU time 34.1 seconds
Started Jul 28 05:17:59 PM PDT 24
Finished Jul 28 05:18:33 PM PDT 24
Peak memory 207916 kb
Host smart-66490a80-4eec-4852-a846-9790d3c5e4d4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115235130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_bit_bash.115235130
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.514782765
Short name T95
Test name
Test status
Simulation time 23559836 ps
CPU time 1.41 seconds
Started Jul 28 05:18:02 PM PDT 24
Finished Jul 28 05:18:04 PM PDT 24
Peak memory 208036 kb
Host smart-6321c5e0-c571-4aeb-a572-48e9452669ab
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514782765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_hw_reset.514782765
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.3590301002
Short name T1131
Test name
Test status
Simulation time 495767668 ps
CPU time 3.62 seconds
Started Jul 28 05:18:09 PM PDT 24
Finished Jul 28 05:18:13 PM PDT 24
Peak memory 218736 kb
Host smart-90862c00-9821-4ce1-83d7-5b007cd627e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590301002 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.3590301002
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.3358523433
Short name T1097
Test name
Test status
Simulation time 61314036 ps
CPU time 2.17 seconds
Started Jul 28 05:18:15 PM PDT 24
Finished Jul 28 05:18:17 PM PDT 24
Peak memory 215944 kb
Host smart-1d924144-6802-4e3d-809b-4543368d9eab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358523433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.3
358523433
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.945798252
Short name T1063
Test name
Test status
Simulation time 94209378 ps
CPU time 0.74 seconds
Started Jul 28 05:18:10 PM PDT 24
Finished Jul 28 05:18:11 PM PDT 24
Peak memory 204512 kb
Host smart-577b58bc-5193-4ae2-9c55-29671e1301a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945798252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.945798252
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2124893511
Short name T127
Test name
Test status
Simulation time 28862349 ps
CPU time 2.09 seconds
Started Jul 28 05:18:17 PM PDT 24
Finished Jul 28 05:18:19 PM PDT 24
Peak memory 216104 kb
Host smart-ed816f8d-a5e4-4c88-a429-28f9de1fbbb3
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124893511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.2124893511
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.3334693543
Short name T1121
Test name
Test status
Simulation time 32708222 ps
CPU time 0.63 seconds
Started Jul 28 05:18:19 PM PDT 24
Finished Jul 28 05:18:20 PM PDT 24
Peak memory 204404 kb
Host smart-3e53aad2-57a2-4ce7-8e2b-2702817358e5
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334693543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.3334693543
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1074878243
Short name T1071
Test name
Test status
Simulation time 106091313 ps
CPU time 1.67 seconds
Started Jul 28 05:18:08 PM PDT 24
Finished Jul 28 05:18:09 PM PDT 24
Peak memory 216008 kb
Host smart-18660dd1-c400-4e46-8c2f-6afb00e04f48
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074878243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.1074878243
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.58140228
Short name T123
Test name
Test status
Simulation time 466477831 ps
CPU time 3.53 seconds
Started Jul 28 05:17:54 PM PDT 24
Finished Jul 28 05:17:58 PM PDT 24
Peak memory 216264 kb
Host smart-ba3bb4ea-3d60-448c-a9b1-cc5a3052a463
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58140228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.58140228
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.3026723144
Short name T1102
Test name
Test status
Simulation time 2994586734 ps
CPU time 7.53 seconds
Started Jul 28 05:18:21 PM PDT 24
Finished Jul 28 05:18:29 PM PDT 24
Peak memory 216204 kb
Host smart-3e4fa28f-6727-4530-aa06-089be58fbf57
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026723144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.3026723144
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.929927505
Short name T1047
Test name
Test status
Simulation time 51931380 ps
CPU time 0.71 seconds
Started Jul 28 05:18:29 PM PDT 24
Finished Jul 28 05:18:30 PM PDT 24
Peak memory 204736 kb
Host smart-2933c9a4-5726-4ad7-a070-fe40281e9ffa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929927505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.929927505
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.525567178
Short name T1090
Test name
Test status
Simulation time 16070481 ps
CPU time 0.75 seconds
Started Jul 28 05:18:15 PM PDT 24
Finished Jul 28 05:18:16 PM PDT 24
Peak memory 204760 kb
Host smart-067e4385-35a4-4666-b4e3-f3ac72ca2292
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525567178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.525567178
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.813459683
Short name T1122
Test name
Test status
Simulation time 16828135 ps
CPU time 0.7 seconds
Started Jul 28 05:18:08 PM PDT 24
Finished Jul 28 05:18:09 PM PDT 24
Peak memory 204796 kb
Host smart-95938f5a-d353-4e33-8b15-12a83c1f8539
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813459683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.813459683
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.4267518681
Short name T1042
Test name
Test status
Simulation time 53900832 ps
CPU time 0.76 seconds
Started Jul 28 05:18:10 PM PDT 24
Finished Jul 28 05:18:11 PM PDT 24
Peak memory 204792 kb
Host smart-782125cb-d849-4141-8c58-5c924156ca12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267518681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
4267518681
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.1045259319
Short name T1136
Test name
Test status
Simulation time 47440901 ps
CPU time 0.69 seconds
Started Jul 28 05:18:15 PM PDT 24
Finished Jul 28 05:18:16 PM PDT 24
Peak memory 204488 kb
Host smart-61416c03-ecbe-4295-9505-37a7f8960400
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045259319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
1045259319
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.3388106223
Short name T1075
Test name
Test status
Simulation time 54483423 ps
CPU time 0.71 seconds
Started Jul 28 05:18:23 PM PDT 24
Finished Jul 28 05:18:24 PM PDT 24
Peak memory 204488 kb
Host smart-4d2eebf2-922b-4ceb-9d4e-e77fd066ee3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388106223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
3388106223
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.1248915789
Short name T1043
Test name
Test status
Simulation time 11424227 ps
CPU time 0.68 seconds
Started Jul 28 05:18:32 PM PDT 24
Finished Jul 28 05:18:33 PM PDT 24
Peak memory 204752 kb
Host smart-84715a82-1065-4307-b115-019825683621
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248915789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
1248915789
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.2205501964
Short name T1143
Test name
Test status
Simulation time 24903981 ps
CPU time 0.7 seconds
Started Jul 28 05:18:20 PM PDT 24
Finished Jul 28 05:18:21 PM PDT 24
Peak memory 204524 kb
Host smart-dff62216-e37f-4b24-beb9-1190423cb7de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205501964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
2205501964
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.1313249583
Short name T1041
Test name
Test status
Simulation time 26844355 ps
CPU time 0.71 seconds
Started Jul 28 05:18:13 PM PDT 24
Finished Jul 28 05:18:13 PM PDT 24
Peak memory 204568 kb
Host smart-ea5484e7-24ac-4b22-9c97-dda69f32d86c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313249583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
1313249583
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.3296760545
Short name T1106
Test name
Test status
Simulation time 30683177 ps
CPU time 0.74 seconds
Started Jul 28 05:18:08 PM PDT 24
Finished Jul 28 05:18:09 PM PDT 24
Peak memory 204448 kb
Host smart-c1bfe5ad-461d-425f-a8a6-55e7e6401cdd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296760545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
3296760545
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.4201295808
Short name T1128
Test name
Test status
Simulation time 2773181225 ps
CPU time 8.42 seconds
Started Jul 28 05:17:57 PM PDT 24
Finished Jul 28 05:18:06 PM PDT 24
Peak memory 207896 kb
Host smart-6f638246-5987-47b3-9bcd-33f33da7807e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201295808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.4201295808
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.47582196
Short name T1109
Test name
Test status
Simulation time 9811065274 ps
CPU time 34.41 seconds
Started Jul 28 05:18:06 PM PDT 24
Finished Jul 28 05:18:41 PM PDT 24
Peak memory 207968 kb
Host smart-4794a9b3-fe69-4698-95e9-17b47931add1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47582196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_
bit_bash.47582196
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.2174526444
Short name T1125
Test name
Test status
Simulation time 46668576 ps
CPU time 1.16 seconds
Started Jul 28 05:17:58 PM PDT 24
Finished Jul 28 05:17:59 PM PDT 24
Peak memory 207776 kb
Host smart-a44d30f2-ddf9-43ea-9c53-3258e98aa05d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174526444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.2174526444
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3200140330
Short name T1078
Test name
Test status
Simulation time 77853000 ps
CPU time 1.74 seconds
Started Jul 28 05:18:06 PM PDT 24
Finished Jul 28 05:18:08 PM PDT 24
Peak memory 217124 kb
Host smart-1acd67cd-be1b-4c8e-aa8b-763411ef14e9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200140330 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.3200140330
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.969290789
Short name T1132
Test name
Test status
Simulation time 324358454 ps
CPU time 1.29 seconds
Started Jul 28 05:18:23 PM PDT 24
Finished Jul 28 05:18:24 PM PDT 24
Peak memory 216256 kb
Host smart-8c0a3916-9093-4568-a7cd-3351c5f34d52
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969290789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.969290789
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3199061407
Short name T1039
Test name
Test status
Simulation time 12646211 ps
CPU time 0.71 seconds
Started Jul 28 05:18:08 PM PDT 24
Finished Jul 28 05:18:09 PM PDT 24
Peak memory 204520 kb
Host smart-85a512ff-cb38-4c4c-aece-f5ebe30e4261
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199061407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.3
199061407
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.12114257
Short name T1072
Test name
Test status
Simulation time 260814753 ps
CPU time 2.17 seconds
Started Jul 28 05:18:12 PM PDT 24
Finished Jul 28 05:18:14 PM PDT 24
Peak memory 216128 kb
Host smart-33a73204-cb10-4bef-a5de-a71a93e6eac2
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12114257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi
_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_d
evice_mem_partial_access.12114257
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.2187291109
Short name T1036
Test name
Test status
Simulation time 10806077 ps
CPU time 0.68 seconds
Started Jul 28 05:18:05 PM PDT 24
Finished Jul 28 05:18:06 PM PDT 24
Peak memory 204364 kb
Host smart-2e71abf8-4e2c-4412-8df2-8ec866b2581e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187291109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.2187291109
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1319854794
Short name T1031
Test name
Test status
Simulation time 98265780 ps
CPU time 1.66 seconds
Started Jul 28 05:17:52 PM PDT 24
Finished Jul 28 05:17:54 PM PDT 24
Peak memory 216092 kb
Host smart-5ef8b0bd-1b3a-4c18-99b1-8ce7a96042c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319854794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.1319854794
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2960304182
Short name T186
Test name
Test status
Simulation time 76404155 ps
CPU time 4.51 seconds
Started Jul 28 05:17:59 PM PDT 24
Finished Jul 28 05:18:04 PM PDT 24
Peak memory 216356 kb
Host smart-0986359d-6a1d-4ded-9885-0da048de8818
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960304182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.2
960304182
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.508682396
Short name T1083
Test name
Test status
Simulation time 2148466763 ps
CPU time 23.59 seconds
Started Jul 28 05:17:52 PM PDT 24
Finished Jul 28 05:18:21 PM PDT 24
Peak memory 216612 kb
Host smart-ef583b01-746a-492d-a47e-a416c1a307d4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508682396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_
tl_intg_err.508682396
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.3274612928
Short name T1070
Test name
Test status
Simulation time 20294684 ps
CPU time 0.78 seconds
Started Jul 28 05:18:05 PM PDT 24
Finished Jul 28 05:18:06 PM PDT 24
Peak memory 204452 kb
Host smart-bd05f583-b356-44d1-8c98-3cdfb84a6628
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274612928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
3274612928
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.2385853439
Short name T1148
Test name
Test status
Simulation time 48656616 ps
CPU time 0.78 seconds
Started Jul 28 05:18:06 PM PDT 24
Finished Jul 28 05:18:07 PM PDT 24
Peak memory 204496 kb
Host smart-cbdcf245-6a07-44f5-b44a-1710badbffb3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385853439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
2385853439
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.1893344171
Short name T1089
Test name
Test status
Simulation time 14829240 ps
CPU time 0.73 seconds
Started Jul 28 05:18:07 PM PDT 24
Finished Jul 28 05:18:08 PM PDT 24
Peak memory 204440 kb
Host smart-8e1e86e7-35e5-4dd6-a3f4-e6ced8b56ad7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893344171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
1893344171
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.3071122806
Short name T1098
Test name
Test status
Simulation time 91420572 ps
CPU time 0.68 seconds
Started Jul 28 05:18:08 PM PDT 24
Finished Jul 28 05:18:09 PM PDT 24
Peak memory 204512 kb
Host smart-fa8d430e-0d3d-49a5-b280-ecb00be644dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071122806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
3071122806
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.963668615
Short name T1055
Test name
Test status
Simulation time 14900158 ps
CPU time 0.72 seconds
Started Jul 28 05:18:02 PM PDT 24
Finished Jul 28 05:18:03 PM PDT 24
Peak memory 204480 kb
Host smart-552eab9b-3a21-4726-ad5f-ba1000f15e10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963668615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.963668615
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.2228993122
Short name T1095
Test name
Test status
Simulation time 30133050 ps
CPU time 0.7 seconds
Started Jul 28 05:18:11 PM PDT 24
Finished Jul 28 05:18:12 PM PDT 24
Peak memory 204456 kb
Host smart-dbf665f6-1e19-45a9-835a-536bed102fed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228993122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
2228993122
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.3792791822
Short name T1033
Test name
Test status
Simulation time 15338202 ps
CPU time 0.75 seconds
Started Jul 28 05:18:26 PM PDT 24
Finished Jul 28 05:18:27 PM PDT 24
Peak memory 204480 kb
Host smart-74f7fe54-69b3-45da-84c4-126e62b8f3dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792791822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
3792791822
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.1179161446
Short name T1060
Test name
Test status
Simulation time 21430988 ps
CPU time 0.72 seconds
Started Jul 28 05:18:08 PM PDT 24
Finished Jul 28 05:18:09 PM PDT 24
Peak memory 204496 kb
Host smart-43a05c15-da3f-47c3-a37c-3320443625ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179161446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
1179161446
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2648536887
Short name T1056
Test name
Test status
Simulation time 15860123 ps
CPU time 0.73 seconds
Started Jul 28 05:18:21 PM PDT 24
Finished Jul 28 05:18:22 PM PDT 24
Peak memory 204476 kb
Host smart-805de690-175a-43de-9bfa-3017f1323f52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648536887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
2648536887
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.4073200742
Short name T1080
Test name
Test status
Simulation time 17444376 ps
CPU time 0.72 seconds
Started Jul 28 05:18:17 PM PDT 24
Finished Jul 28 05:18:18 PM PDT 24
Peak memory 204804 kb
Host smart-6b274d9d-35b1-4e73-a3ec-d47d8a1ca325
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073200742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
4073200742
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.2101158153
Short name T1130
Test name
Test status
Simulation time 51127923 ps
CPU time 1.75 seconds
Started Jul 28 05:18:07 PM PDT 24
Finished Jul 28 05:18:09 PM PDT 24
Peak memory 216044 kb
Host smart-7362656c-f041-4edb-af85-193c4bcbe12b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101158153 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.2101158153
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.2669339187
Short name T1085
Test name
Test status
Simulation time 70176954 ps
CPU time 1.31 seconds
Started Jul 28 05:17:54 PM PDT 24
Finished Jul 28 05:17:55 PM PDT 24
Peak memory 207736 kb
Host smart-64e12abb-7c1e-4dad-9130-92c1fc37fe41
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669339187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.2
669339187
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.3685177626
Short name T1046
Test name
Test status
Simulation time 29345772 ps
CPU time 0.7 seconds
Started Jul 28 05:18:07 PM PDT 24
Finished Jul 28 05:18:08 PM PDT 24
Peak memory 204512 kb
Host smart-cce29a02-766c-4a98-b1cc-9e9911fe2f6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685177626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.3
685177626
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.4248309245
Short name T1093
Test name
Test status
Simulation time 60296135 ps
CPU time 1.81 seconds
Started Jul 28 05:18:03 PM PDT 24
Finished Jul 28 05:18:05 PM PDT 24
Peak memory 207800 kb
Host smart-73051461-ef23-46b8-9c75-80921b877db0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248309245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.4248309245
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.3238002818
Short name T124
Test name
Test status
Simulation time 84784439 ps
CPU time 2.82 seconds
Started Jul 28 05:18:03 PM PDT 24
Finished Jul 28 05:18:06 PM PDT 24
Peak memory 216424 kb
Host smart-2e15d2b9-70df-4f74-b89b-8faf06452833
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238002818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.3
238002818
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.261604259
Short name T109
Test name
Test status
Simulation time 118409409 ps
CPU time 1.78 seconds
Started Jul 28 05:17:54 PM PDT 24
Finished Jul 28 05:17:56 PM PDT 24
Peak memory 216084 kb
Host smart-8b018d2d-20a1-47e2-86dd-b53999992359
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261604259 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.261604259
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.3977850796
Short name T162
Test name
Test status
Simulation time 69081476 ps
CPU time 1.27 seconds
Started Jul 28 05:18:14 PM PDT 24
Finished Jul 28 05:18:16 PM PDT 24
Peak memory 216112 kb
Host smart-4cc8f3fb-8bc3-435a-b614-f129a2e8ee27
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977850796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.3
977850796
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2303657258
Short name T1096
Test name
Test status
Simulation time 20803400 ps
CPU time 0.67 seconds
Started Jul 28 05:18:00 PM PDT 24
Finished Jul 28 05:18:01 PM PDT 24
Peak memory 204456 kb
Host smart-2925ce09-fcf4-4c9a-b44c-4ecfd1efb123
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303657258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.2
303657258
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3060051017
Short name T1081
Test name
Test status
Simulation time 179489519 ps
CPU time 2.87 seconds
Started Jul 28 05:18:04 PM PDT 24
Finished Jul 28 05:18:07 PM PDT 24
Peak memory 216068 kb
Host smart-b5e15eed-1e1c-4187-bd0b-3fb4f7de5c7a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060051017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.3060051017
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.4247507055
Short name T116
Test name
Test status
Simulation time 254191227 ps
CPU time 3.55 seconds
Started Jul 28 05:18:03 PM PDT 24
Finished Jul 28 05:18:07 PM PDT 24
Peak memory 217768 kb
Host smart-e5cf9c74-7825-4fdd-8b29-c17769e680b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247507055 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.4247507055
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.3139372687
Short name T1140
Test name
Test status
Simulation time 68137450 ps
CPU time 1.86 seconds
Started Jul 28 05:18:08 PM PDT 24
Finished Jul 28 05:18:10 PM PDT 24
Peak memory 207936 kb
Host smart-8810a95c-6ccc-4180-b9b4-39bc8723d0b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139372687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.3
139372687
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.2917540076
Short name T1138
Test name
Test status
Simulation time 12119916 ps
CPU time 0.73 seconds
Started Jul 28 05:18:15 PM PDT 24
Finished Jul 28 05:18:15 PM PDT 24
Peak memory 204468 kb
Host smart-9c4cbb12-0235-43a8-b479-520c2943c9ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917540076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.2
917540076
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1109666963
Short name T1032
Test name
Test status
Simulation time 217676006 ps
CPU time 2.86 seconds
Started Jul 28 05:17:58 PM PDT 24
Finished Jul 28 05:18:01 PM PDT 24
Peak memory 215988 kb
Host smart-1b7c88b0-a6bb-4ac4-bacb-b0a0dd6d2acc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109666963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.1109666963
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.3432712369
Short name T1133
Test name
Test status
Simulation time 60002299 ps
CPU time 3.81 seconds
Started Jul 28 05:18:01 PM PDT 24
Finished Jul 28 05:18:05 PM PDT 24
Peak memory 216256 kb
Host smart-3023c211-fad5-4414-8f29-9eb672056680
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432712369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.3
432712369
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.2624401816
Short name T187
Test name
Test status
Simulation time 555964095 ps
CPU time 14.89 seconds
Started Jul 28 05:18:08 PM PDT 24
Finished Jul 28 05:18:23 PM PDT 24
Peak memory 215932 kb
Host smart-31587c03-4363-4a72-9a55-0c4f8b423895
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624401816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.2624401816
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2451118901
Short name T104
Test name
Test status
Simulation time 187947384 ps
CPU time 3.24 seconds
Started Jul 28 05:18:06 PM PDT 24
Finished Jul 28 05:18:09 PM PDT 24
Peak memory 218792 kb
Host smart-0f306daa-e1e7-4458-ad18-8356e02dfc8d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451118901 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.2451118901
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.1717944917
Short name T1059
Test name
Test status
Simulation time 1200936092 ps
CPU time 1.97 seconds
Started Jul 28 05:17:56 PM PDT 24
Finished Jul 28 05:17:58 PM PDT 24
Peak memory 216044 kb
Host smart-9f651527-4eef-4120-9c1b-42f6ab6fbb79
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717944917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.1
717944917
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1204416721
Short name T1144
Test name
Test status
Simulation time 38341792 ps
CPU time 0.72 seconds
Started Jul 28 05:17:54 PM PDT 24
Finished Jul 28 05:17:54 PM PDT 24
Peak memory 204400 kb
Host smart-b24f4edd-8934-4e1e-926d-ea5809a90a63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204416721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.1
204416721
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.3552692709
Short name T1053
Test name
Test status
Simulation time 53077942 ps
CPU time 2.99 seconds
Started Jul 28 05:18:01 PM PDT 24
Finished Jul 28 05:18:04 PM PDT 24
Peak memory 215996 kb
Host smart-07b5f918-a371-4e85-b1f8-e62019445206
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552692709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.3552692709
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2246330352
Short name T1114
Test name
Test status
Simulation time 60208334 ps
CPU time 3.69 seconds
Started Jul 28 05:17:43 PM PDT 24
Finished Jul 28 05:17:47 PM PDT 24
Peak memory 216184 kb
Host smart-1da7c24b-4e90-4aa1-9944-129e2a680780
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246330352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.2
246330352
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.2383999461
Short name T159
Test name
Test status
Simulation time 384685448 ps
CPU time 7.35 seconds
Started Jul 28 05:17:57 PM PDT 24
Finished Jul 28 05:18:05 PM PDT 24
Peak memory 217340 kb
Host smart-7360a528-5537-45cb-bea9-a38333cf43d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383999461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.2383999461
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.1870205447
Short name T1084
Test name
Test status
Simulation time 53695878 ps
CPU time 0.72 seconds
Started Jul 28 05:18:00 PM PDT 24
Finished Jul 28 05:18:01 PM PDT 24
Peak memory 204488 kb
Host smart-5d448f81-780c-463d-bf1a-e26d392c0803
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870205447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.1
870205447
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.1846917259
Short name T1044
Test name
Test status
Simulation time 130415692 ps
CPU time 1.78 seconds
Started Jul 28 05:18:04 PM PDT 24
Finished Jul 28 05:18:06 PM PDT 24
Peak memory 216472 kb
Host smart-1ae12ef0-f081-4921-8e0f-83fef3e5c5c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846917259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.1846917259
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.873944070
Short name T121
Test name
Test status
Simulation time 183219291 ps
CPU time 1.76 seconds
Started Jul 28 05:17:53 PM PDT 24
Finished Jul 28 05:17:55 PM PDT 24
Peak memory 217304 kb
Host smart-32995602-053c-451e-a446-0fb53ba2bc67
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873944070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.873944070
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2185782876
Short name T189
Test name
Test status
Simulation time 668184324 ps
CPU time 19.59 seconds
Started Jul 28 05:17:53 PM PDT 24
Finished Jul 28 05:18:13 PM PDT 24
Peak memory 216328 kb
Host smart-5c0ef2ab-59eb-4899-83e3-b1f11f08397c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185782876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.2185782876
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.233270878
Short name T964
Test name
Test status
Simulation time 13620928 ps
CPU time 0.75 seconds
Started Jul 28 07:18:10 PM PDT 24
Finished Jul 28 07:18:10 PM PDT 24
Peak memory 205984 kb
Host smart-a4be1840-a271-4c9a-b715-f83295465167
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233270878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.233270878
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.122435723
Short name T425
Test name
Test status
Simulation time 37933723 ps
CPU time 2.4 seconds
Started Jul 28 07:18:08 PM PDT 24
Finished Jul 28 07:18:10 PM PDT 24
Peak memory 233652 kb
Host smart-57141be2-da06-4929-bbeb-4a7ffa305f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122435723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.122435723
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.1579304682
Short name T732
Test name
Test status
Simulation time 13038084 ps
CPU time 0.77 seconds
Started Jul 28 07:18:03 PM PDT 24
Finished Jul 28 07:18:04 PM PDT 24
Peak memory 206528 kb
Host smart-88b883cf-9d26-4d0a-a3f4-29b93dd24647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579304682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.1579304682
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.2281517122
Short name T272
Test name
Test status
Simulation time 10841300652 ps
CPU time 78.87 seconds
Started Jul 28 07:18:04 PM PDT 24
Finished Jul 28 07:19:23 PM PDT 24
Peak memory 233636 kb
Host smart-18d15965-8bda-4fcb-8f3e-f267426b6cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281517122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.2281517122
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.759682101
Short name T58
Test name
Test status
Simulation time 19167151193 ps
CPU time 117.84 seconds
Started Jul 28 07:18:07 PM PDT 24
Finished Jul 28 07:20:05 PM PDT 24
Peak memory 256392 kb
Host smart-6ad32fba-d482-431e-a9e9-efdd953c4044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759682101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.759682101
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.742375930
Short name T988
Test name
Test status
Simulation time 674498280 ps
CPU time 9.28 seconds
Started Jul 28 07:18:08 PM PDT 24
Finished Jul 28 07:18:18 PM PDT 24
Peak memory 250064 kb
Host smart-6b2bcc82-ace1-4167-896d-97480b7a3a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742375930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.742375930
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_intercept.4113065949
Short name T440
Test name
Test status
Simulation time 1551618856 ps
CPU time 17.19 seconds
Started Jul 28 07:18:07 PM PDT 24
Finished Jul 28 07:18:24 PM PDT 24
Peak memory 233656 kb
Host smart-c977762c-f986-4191-b644-89578dbd116f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113065949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.4113065949
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.3793333969
Short name T526
Test name
Test status
Simulation time 65892378184 ps
CPU time 189.02 seconds
Started Jul 28 07:18:08 PM PDT 24
Finished Jul 28 07:21:17 PM PDT 24
Peak memory 238168 kb
Host smart-f2598a6d-cd6a-490b-860e-824371a638de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793333969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.3793333969
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.3589140088
Short name T846
Test name
Test status
Simulation time 14705293 ps
CPU time 1.03 seconds
Started Jul 28 07:18:01 PM PDT 24
Finished Jul 28 07:18:02 PM PDT 24
Peak memory 217356 kb
Host smart-f89ce61a-df46-408c-997d-260e3339f7fa
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589140088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.spi_device_mem_parity.3589140088
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.3737419383
Short name T972
Test name
Test status
Simulation time 9899877027 ps
CPU time 26.5 seconds
Started Jul 28 07:18:05 PM PDT 24
Finished Jul 28 07:18:31 PM PDT 24
Peak memory 233692 kb
Host smart-b6e77d30-12bb-4f24-b4dc-0fac4fd1c020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737419383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.3737419383
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.93166170
Short name T528
Test name
Test status
Simulation time 2899974467 ps
CPU time 5.39 seconds
Started Jul 28 07:18:04 PM PDT 24
Finished Jul 28 07:18:10 PM PDT 24
Peak memory 221672 kb
Host smart-ba8a7420-6db0-4a53-aba2-ec40a87deceb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=93166170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_direct
.93166170
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.259269588
Short name T78
Test name
Test status
Simulation time 325012438 ps
CPU time 1.22 seconds
Started Jul 28 07:18:12 PM PDT 24
Finished Jul 28 07:18:13 PM PDT 24
Peak memory 236400 kb
Host smart-d23fa0e2-3a52-48f8-998f-0993ca63d8aa
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259269588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.259269588
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.3613536934
Short name T719
Test name
Test status
Simulation time 41820463 ps
CPU time 0.96 seconds
Started Jul 28 07:18:09 PM PDT 24
Finished Jul 28 07:18:10 PM PDT 24
Peak memory 208120 kb
Host smart-b4d51796-7e39-4720-bd8d-04e57294d602
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613536934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.3613536934
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.2058656685
Short name T470
Test name
Test status
Simulation time 470540923 ps
CPU time 2.04 seconds
Started Jul 28 07:18:05 PM PDT 24
Finished Jul 28 07:18:07 PM PDT 24
Peak memory 217224 kb
Host smart-d2d01b3e-baa2-44c2-b52c-e311252dcb13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058656685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.2058656685
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.78086372
Short name T449
Test name
Test status
Simulation time 141697958 ps
CPU time 0.91 seconds
Started Jul 28 07:18:06 PM PDT 24
Finished Jul 28 07:18:07 PM PDT 24
Peak memory 206768 kb
Host smart-ef5259e7-d31e-4db5-85cd-6ba997d1b549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78086372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.78086372
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.734951216
Short name T903
Test name
Test status
Simulation time 2873342964 ps
CPU time 4.98 seconds
Started Jul 28 07:18:05 PM PDT 24
Finished Jul 28 07:18:10 PM PDT 24
Peak memory 225504 kb
Host smart-cfa635f6-e683-4cb4-ab24-aebc62e4987d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734951216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.734951216
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.1637464303
Short name T775
Test name
Test status
Simulation time 1049600270 ps
CPU time 8.28 seconds
Started Jul 28 07:18:13 PM PDT 24
Finished Jul 28 07:18:22 PM PDT 24
Peak memory 225452 kb
Host smart-564ba9db-4377-4f3c-b87a-78e73c060526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637464303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.1637464303
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.2760774188
Short name T337
Test name
Test status
Simulation time 20367315 ps
CPU time 0.82 seconds
Started Jul 28 07:18:09 PM PDT 24
Finished Jul 28 07:18:10 PM PDT 24
Peak memory 207256 kb
Host smart-dd19182c-f6b6-4a3d-bdb2-7230779110d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760774188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.2760774188
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.2255877997
Short name T628
Test name
Test status
Simulation time 2327142031 ps
CPU time 18.64 seconds
Started Jul 28 07:18:13 PM PDT 24
Finished Jul 28 07:18:32 PM PDT 24
Peak memory 218420 kb
Host smart-58104a6c-a78e-40ce-a214-5cb655d123f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255877997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.2255877997
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.1735001202
Short name T818
Test name
Test status
Simulation time 42782118373 ps
CPU time 101.51 seconds
Started Jul 28 07:18:15 PM PDT 24
Finished Jul 28 07:19:57 PM PDT 24
Peak memory 233784 kb
Host smart-aca15c07-3de3-4111-8cd8-78063375bf6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735001202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.1735001202
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.1473540745
Short name T658
Test name
Test status
Simulation time 1037537899 ps
CPU time 5.16 seconds
Started Jul 28 07:18:18 PM PDT 24
Finished Jul 28 07:18:23 PM PDT 24
Peak memory 225396 kb
Host smart-948264d2-2e64-4636-a250-f32a76fa3712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473540745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.1473540745
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.3753103580
Short name T894
Test name
Test status
Simulation time 58793469 ps
CPU time 0.76 seconds
Started Jul 28 07:18:14 PM PDT 24
Finished Jul 28 07:18:14 PM PDT 24
Peak memory 208472 kb
Host smart-99816e7a-7dac-4817-b664-a8c032863520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753103580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds
.3753103580
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/1.spi_device_intercept.2120201175
Short name T915
Test name
Test status
Simulation time 4800827562 ps
CPU time 12.81 seconds
Started Jul 28 07:18:14 PM PDT 24
Finished Jul 28 07:18:27 PM PDT 24
Peak memory 233724 kb
Host smart-2b5f3a42-3b0f-47a5-b7a1-ab24f6526566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120201175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.2120201175
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.1548520906
Short name T501
Test name
Test status
Simulation time 4150226944 ps
CPU time 34.12 seconds
Started Jul 28 07:18:14 PM PDT 24
Finished Jul 28 07:18:48 PM PDT 24
Peak memory 233776 kb
Host smart-8794a54c-757a-49ee-9c52-fcde2de2183d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548520906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.1548520906
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.1084355951
Short name T483
Test name
Test status
Simulation time 161207246 ps
CPU time 1.03 seconds
Started Jul 28 07:18:13 PM PDT 24
Finished Jul 28 07:18:14 PM PDT 24
Peak memory 218716 kb
Host smart-47c199a1-9d02-4609-a7f0-b796d0aafb7b
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084355951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.spi_device_mem_parity.1084355951
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.3041221259
Short name T102
Test name
Test status
Simulation time 11449113972 ps
CPU time 31.3 seconds
Started Jul 28 07:18:14 PM PDT 24
Finished Jul 28 07:18:46 PM PDT 24
Peak memory 225420 kb
Host smart-24d48a43-10fa-471f-94bc-7092e965b5a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041221259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.3041221259
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.65325682
Short name T574
Test name
Test status
Simulation time 3917863381 ps
CPU time 15.31 seconds
Started Jul 28 07:18:12 PM PDT 24
Finished Jul 28 07:18:28 PM PDT 24
Peak memory 241552 kb
Host smart-1cb1cc5b-a20c-4b96-9ab4-7b4f18de59a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65325682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.65325682
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.1034060229
Short name T847
Test name
Test status
Simulation time 2683015399 ps
CPU time 15.52 seconds
Started Jul 28 07:18:14 PM PDT 24
Finished Jul 28 07:18:30 PM PDT 24
Peak memory 221448 kb
Host smart-00a3b9bb-51c0-485d-ba03-4309207f538b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1034060229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.1034060229
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.169297983
Short name T80
Test name
Test status
Simulation time 97691916 ps
CPU time 1.19 seconds
Started Jul 28 07:18:13 PM PDT 24
Finished Jul 28 07:18:15 PM PDT 24
Peak memory 235980 kb
Host smart-39a5807d-1747-423f-bc4d-b887f91ca01e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169297983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.169297983
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.2904560948
Short name T720
Test name
Test status
Simulation time 20147532 ps
CPU time 0.73 seconds
Started Jul 28 07:18:09 PM PDT 24
Finished Jul 28 07:18:10 PM PDT 24
Peak memory 206356 kb
Host smart-253a0de2-95c0-4eb7-8b82-c7655c460ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904560948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.2904560948
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.3623454795
Short name T409
Test name
Test status
Simulation time 11224453 ps
CPU time 0.75 seconds
Started Jul 28 07:18:12 PM PDT 24
Finished Jul 28 07:18:13 PM PDT 24
Peak memory 206372 kb
Host smart-7686777b-2fb5-4129-aedc-7d06641f118a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623454795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.3623454795
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.499678816
Short name T506
Test name
Test status
Simulation time 38686292 ps
CPU time 0.93 seconds
Started Jul 28 07:18:14 PM PDT 24
Finished Jul 28 07:18:15 PM PDT 24
Peak memory 207520 kb
Host smart-64a8ce37-dc52-4d25-81f1-36baaf11e550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499678816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.499678816
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.324656508
Short name T1017
Test name
Test status
Simulation time 480472128 ps
CPU time 0.85 seconds
Started Jul 28 07:18:08 PM PDT 24
Finished Jul 28 07:18:09 PM PDT 24
Peak memory 206764 kb
Host smart-adc144b4-3c03-4ae3-89c6-1db64eed3e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324656508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.324656508
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.716467886
Short name T1003
Test name
Test status
Simulation time 345706061 ps
CPU time 5.74 seconds
Started Jul 28 07:18:13 PM PDT 24
Finished Jul 28 07:18:19 PM PDT 24
Peak memory 225356 kb
Host smart-2a305b77-b324-4de7-bdda-9789757f41d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716467886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.716467886
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.338081279
Short name T665
Test name
Test status
Simulation time 12164827 ps
CPU time 0.66 seconds
Started Jul 28 07:19:06 PM PDT 24
Finished Jul 28 07:19:07 PM PDT 24
Peak memory 206380 kb
Host smart-da96f134-b7c6-4bb0-9bd0-bf89afe488f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338081279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.338081279
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.1727416439
Short name T987
Test name
Test status
Simulation time 171092472 ps
CPU time 3.38 seconds
Started Jul 28 07:19:04 PM PDT 24
Finished Jul 28 07:19:07 PM PDT 24
Peak memory 225424 kb
Host smart-8a5d64ff-dd8f-4252-95dd-0a5df7b7c87d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727416439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.1727416439
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.70433373
Short name T1005
Test name
Test status
Simulation time 18890462 ps
CPU time 0.77 seconds
Started Jul 28 07:18:58 PM PDT 24
Finished Jul 28 07:18:59 PM PDT 24
Peak memory 207240 kb
Host smart-a28e5566-ce20-482d-be2a-78a07489f4a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70433373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.70433373
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.3097172251
Short name T467
Test name
Test status
Simulation time 1670507494 ps
CPU time 32.33 seconds
Started Jul 28 07:19:08 PM PDT 24
Finished Jul 28 07:19:41 PM PDT 24
Peak memory 257584 kb
Host smart-389f3ff1-d4f3-42c5-b465-c38de787b540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097172251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.3097172251
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.1954665203
Short name T267
Test name
Test status
Simulation time 37707474343 ps
CPU time 108.91 seconds
Started Jul 28 07:19:06 PM PDT 24
Finished Jul 28 07:20:55 PM PDT 24
Peak memory 225428 kb
Host smart-d58f88ed-ed6e-4a09-96ae-e58e7e5460f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954665203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.1954665203
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.1194355978
Short name T214
Test name
Test status
Simulation time 5698244209 ps
CPU time 116.45 seconds
Started Jul 28 07:19:06 PM PDT 24
Finished Jul 28 07:21:03 PM PDT 24
Peak memory 256280 kb
Host smart-0ffff8a7-1dd4-4ec9-941e-aa10095ec8e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194355978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.1194355978
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.1877036351
Short name T414
Test name
Test status
Simulation time 415716362 ps
CPU time 10.25 seconds
Started Jul 28 07:19:04 PM PDT 24
Finished Jul 28 07:19:14 PM PDT 24
Peak memory 238800 kb
Host smart-9d7cd5b9-a46f-4960-9c2d-0cb430ba4cd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877036351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.1877036351
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.3647683490
Short name T100
Test name
Test status
Simulation time 6932637574 ps
CPU time 66.3 seconds
Started Jul 28 07:19:07 PM PDT 24
Finished Jul 28 07:20:13 PM PDT 24
Peak memory 251224 kb
Host smart-b505024a-eae3-4120-a582-634852369eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647683490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmd
s.3647683490
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/10.spi_device_intercept.1651746603
Short name T285
Test name
Test status
Simulation time 1882932211 ps
CPU time 15.42 seconds
Started Jul 28 07:19:02 PM PDT 24
Finished Jul 28 07:19:17 PM PDT 24
Peak memory 225436 kb
Host smart-58e88972-32f8-4752-bc32-d893f1e0c9e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651746603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.1651746603
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.103059319
Short name T837
Test name
Test status
Simulation time 14953466860 ps
CPU time 26.32 seconds
Started Jul 28 07:19:03 PM PDT 24
Finished Jul 28 07:19:29 PM PDT 24
Peak memory 234724 kb
Host smart-f3a5f004-fdb3-42c1-b0bb-b451625f4f23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103059319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.103059319
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.3707082821
Short name T44
Test name
Test status
Simulation time 32116232 ps
CPU time 1.08 seconds
Started Jul 28 07:19:05 PM PDT 24
Finished Jul 28 07:19:06 PM PDT 24
Peak memory 217340 kb
Host smart-a7439d18-0b74-484b-9df4-5a576b605257
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707082821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.spi_device_mem_parity.3707082821
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.2043776053
Short name T868
Test name
Test status
Simulation time 5592985166 ps
CPU time 19.01 seconds
Started Jul 28 07:19:05 PM PDT 24
Finished Jul 28 07:19:24 PM PDT 24
Peak memory 236496 kb
Host smart-291d22db-dd54-4be6-8098-87f78df3cfb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043776053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.2043776053
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.1290313151
Short name T655
Test name
Test status
Simulation time 979504348 ps
CPU time 4.35 seconds
Started Jul 28 07:19:04 PM PDT 24
Finished Jul 28 07:19:08 PM PDT 24
Peak memory 233628 kb
Host smart-a3ae8a91-193d-45eb-a442-6207f9171a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290313151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.1290313151
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.1130910833
Short name T873
Test name
Test status
Simulation time 452590743 ps
CPU time 3.55 seconds
Started Jul 28 07:19:08 PM PDT 24
Finished Jul 28 07:19:12 PM PDT 24
Peak memory 220120 kb
Host smart-93f3be9f-7ee4-48e9-9e80-95b711988fd8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1130910833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.1130910833
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.2103889408
Short name T975
Test name
Test status
Simulation time 71599925498 ps
CPU time 329.24 seconds
Started Jul 28 07:19:08 PM PDT 24
Finished Jul 28 07:24:37 PM PDT 24
Peak memory 250192 kb
Host smart-391a32e9-93c6-4c07-9135-e560ae8ae49f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103889408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.2103889408
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.1717332503
Short name T140
Test name
Test status
Simulation time 3743576984 ps
CPU time 6.35 seconds
Started Jul 28 07:19:03 PM PDT 24
Finished Jul 28 07:19:10 PM PDT 24
Peak memory 217216 kb
Host smart-cf06feb2-1726-4841-96ec-0c446cf49171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717332503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.1717332503
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.155236680
Short name T976
Test name
Test status
Simulation time 2358975424 ps
CPU time 5.72 seconds
Started Jul 28 07:19:03 PM PDT 24
Finished Jul 28 07:19:09 PM PDT 24
Peak memory 217192 kb
Host smart-01e0fbcd-3f0b-4398-ad3f-f2f4f845bca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155236680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.155236680
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.1753342307
Short name T432
Test name
Test status
Simulation time 479550862 ps
CPU time 2.37 seconds
Started Jul 28 07:19:04 PM PDT 24
Finished Jul 28 07:19:06 PM PDT 24
Peak memory 217168 kb
Host smart-c417f524-7f9e-499b-a06a-47fedd6e12d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753342307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.1753342307
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.1382640458
Short name T368
Test name
Test status
Simulation time 116827582 ps
CPU time 0.86 seconds
Started Jul 28 07:19:06 PM PDT 24
Finished Jul 28 07:19:07 PM PDT 24
Peak memory 206848 kb
Host smart-888a36c4-198a-4c0d-8b7b-c86b4c424bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382640458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.1382640458
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.3599992913
Short name T478
Test name
Test status
Simulation time 2225552778 ps
CPU time 10.68 seconds
Started Jul 28 07:19:04 PM PDT 24
Finished Jul 28 07:19:14 PM PDT 24
Peak memory 225484 kb
Host smart-343be881-c18f-4b63-8a36-332a0fe35e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599992913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.3599992913
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.712739208
Short name T551
Test name
Test status
Simulation time 66265434 ps
CPU time 0.71 seconds
Started Jul 28 07:19:08 PM PDT 24
Finished Jul 28 07:19:09 PM PDT 24
Peak memory 206052 kb
Host smart-cf661c36-c046-478a-bbc5-f665d331b981
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712739208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.712739208
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.3928127048
Short name T249
Test name
Test status
Simulation time 2796819793 ps
CPU time 4.81 seconds
Started Jul 28 07:19:14 PM PDT 24
Finished Jul 28 07:19:18 PM PDT 24
Peak memory 233712 kb
Host smart-33d5bb9f-d070-4647-aa9e-1a275f50cb92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928127048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.3928127048
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.1989274454
Short name T896
Test name
Test status
Simulation time 67622495 ps
CPU time 0.78 seconds
Started Jul 28 07:19:08 PM PDT 24
Finished Jul 28 07:19:09 PM PDT 24
Peak memory 207576 kb
Host smart-e473f808-e24d-4313-821f-8b8961ef3754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989274454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.1989274454
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.2333339419
Short name T909
Test name
Test status
Simulation time 87197386838 ps
CPU time 155.44 seconds
Started Jul 28 07:19:13 PM PDT 24
Finished Jul 28 07:21:48 PM PDT 24
Peak memory 257060 kb
Host smart-0ea29ca6-d8b8-4bed-8b10-3f0dbfaac7a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333339419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.2333339419
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.1679023160
Short name T152
Test name
Test status
Simulation time 178406491221 ps
CPU time 259.45 seconds
Started Jul 28 07:19:08 PM PDT 24
Finished Jul 28 07:23:27 PM PDT 24
Peak memory 250012 kb
Host smart-a2034ddc-1179-4ade-8024-11a67da8d149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679023160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.1679023160
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.687780913
Short name T1010
Test name
Test status
Simulation time 17255894876 ps
CPU time 32.43 seconds
Started Jul 28 07:19:11 PM PDT 24
Finished Jul 28 07:19:44 PM PDT 24
Peak memory 239416 kb
Host smart-5ff4bad1-9e50-4c68-8413-f58894b665b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687780913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idle
.687780913
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.866068737
Short name T484
Test name
Test status
Simulation time 38440478 ps
CPU time 2.79 seconds
Started Jul 28 07:19:10 PM PDT 24
Finished Jul 28 07:19:13 PM PDT 24
Peak memory 233644 kb
Host smart-5758bff4-5161-4ade-8a78-158361f154fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866068737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.866068737
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.1373570591
Short name T179
Test name
Test status
Simulation time 24583239359 ps
CPU time 103.66 seconds
Started Jul 28 07:19:08 PM PDT 24
Finished Jul 28 07:20:51 PM PDT 24
Peak memory 238640 kb
Host smart-57f9faf4-2d4e-41ae-8381-1ad1d9681e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373570591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmd
s.1373570591
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_intercept.521047277
Short name T427
Test name
Test status
Simulation time 1335114490 ps
CPU time 13.02 seconds
Started Jul 28 07:19:07 PM PDT 24
Finished Jul 28 07:19:21 PM PDT 24
Peak memory 233608 kb
Host smart-17ba5868-f59c-4206-b55a-d37730329a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521047277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.521047277
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.604561240
Short name T251
Test name
Test status
Simulation time 317381396 ps
CPU time 7.93 seconds
Started Jul 28 07:19:13 PM PDT 24
Finished Jul 28 07:19:21 PM PDT 24
Peak memory 225496 kb
Host smart-b318c5a1-ffaf-4c5a-873a-07a606fe1768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604561240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.604561240
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.145819977
Short name T840
Test name
Test status
Simulation time 25797341 ps
CPU time 1.11 seconds
Started Jul 28 07:19:07 PM PDT 24
Finished Jul 28 07:19:08 PM PDT 24
Peak memory 217412 kb
Host smart-16c43b96-8a79-43e0-bcd9-417b57647d2a
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145819977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.spi_device_mem_parity.145819977
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.493366485
Short name T173
Test name
Test status
Simulation time 10222715410 ps
CPU time 16.2 seconds
Started Jul 28 07:19:07 PM PDT 24
Finished Jul 28 07:19:24 PM PDT 24
Peak memory 249688 kb
Host smart-aa248328-0012-4804-a96e-f996ee3ec7a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493366485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swap
.493366485
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.359360898
Short name T867
Test name
Test status
Simulation time 8212875333 ps
CPU time 26.23 seconds
Started Jul 28 07:19:09 PM PDT 24
Finished Jul 28 07:19:35 PM PDT 24
Peak memory 241640 kb
Host smart-59fd5c5a-69da-4105-bbcd-0643383b0d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359360898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.359360898
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.2204753325
Short name T599
Test name
Test status
Simulation time 181053897 ps
CPU time 3.71 seconds
Started Jul 28 07:19:08 PM PDT 24
Finished Jul 28 07:19:12 PM PDT 24
Peak memory 221040 kb
Host smart-7a598718-79f9-4a68-b014-8bd707d93202
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2204753325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.2204753325
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.2373973628
Short name T654
Test name
Test status
Simulation time 154343747297 ps
CPU time 325.26 seconds
Started Jul 28 07:19:11 PM PDT 24
Finished Jul 28 07:24:37 PM PDT 24
Peak memory 267400 kb
Host smart-4f100fc4-4cf7-4282-8dd9-fd4bed91a615
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373973628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.2373973628
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.3895037147
Short name T497
Test name
Test status
Simulation time 818940935 ps
CPU time 10.08 seconds
Started Jul 28 07:19:10 PM PDT 24
Finished Jul 28 07:19:20 PM PDT 24
Peak memory 217312 kb
Host smart-b5aca40b-8d70-44d6-aa2d-cf995763d420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895037147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.3895037147
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.1090093929
Short name T356
Test name
Test status
Simulation time 10175693922 ps
CPU time 4.4 seconds
Started Jul 28 07:19:07 PM PDT 24
Finished Jul 28 07:19:12 PM PDT 24
Peak memory 217216 kb
Host smart-2975f4ed-758b-4b2d-ad1d-09ed53fe0f5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090093929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.1090093929
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.2603251067
Short name T889
Test name
Test status
Simulation time 12534534 ps
CPU time 0.72 seconds
Started Jul 28 07:19:08 PM PDT 24
Finished Jul 28 07:19:09 PM PDT 24
Peak memory 206264 kb
Host smart-bf6acea2-ea99-4afb-8017-a7b2724571bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603251067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.2603251067
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.2405272416
Short name T89
Test name
Test status
Simulation time 43560093 ps
CPU time 0.74 seconds
Started Jul 28 07:19:10 PM PDT 24
Finished Jul 28 07:19:11 PM PDT 24
Peak memory 206344 kb
Host smart-72e3cfde-fa88-4152-a796-df7e16009bc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405272416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.2405272416
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.851321959
Short name T180
Test name
Test status
Simulation time 4603501504 ps
CPU time 19.43 seconds
Started Jul 28 07:19:08 PM PDT 24
Finished Jul 28 07:19:28 PM PDT 24
Peak memory 233636 kb
Host smart-44d3fb9e-a597-4fc7-abdc-4df6b85cccf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851321959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.851321959
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.2543794199
Short name T558
Test name
Test status
Simulation time 40441471 ps
CPU time 0.75 seconds
Started Jul 28 07:19:15 PM PDT 24
Finished Jul 28 07:19:16 PM PDT 24
Peak memory 206016 kb
Host smart-25dae867-a4ae-496a-8a24-a79571cc0626
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543794199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
2543794199
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.3099404101
Short name T196
Test name
Test status
Simulation time 1618608810 ps
CPU time 5.11 seconds
Started Jul 28 07:19:12 PM PDT 24
Finished Jul 28 07:19:17 PM PDT 24
Peak memory 233624 kb
Host smart-703cb2ed-b768-4f51-9f91-0a11454c6de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099404101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.3099404101
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.3969987207
Short name T956
Test name
Test status
Simulation time 55256080 ps
CPU time 0.81 seconds
Started Jul 28 07:19:11 PM PDT 24
Finished Jul 28 07:19:12 PM PDT 24
Peak memory 206388 kb
Host smart-ee7d5a40-4c8b-4bd3-b767-b202b7ae6282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969987207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.3969987207
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.2469828287
Short name T729
Test name
Test status
Simulation time 118973578466 ps
CPU time 312.64 seconds
Started Jul 28 07:19:13 PM PDT 24
Finished Jul 28 07:24:25 PM PDT 24
Peak memory 263524 kb
Host smart-e9dd95b3-983e-489c-8676-192870293663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469828287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.2469828287
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.1809851990
Short name T66
Test name
Test status
Simulation time 71349725774 ps
CPU time 94.38 seconds
Started Jul 28 07:19:09 PM PDT 24
Finished Jul 28 07:20:44 PM PDT 24
Peak memory 250132 kb
Host smart-2e82c799-c246-4e07-945a-81674b7e1729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809851990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.1809851990
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.704377517
Short name T1029
Test name
Test status
Simulation time 187269998 ps
CPU time 0.92 seconds
Started Jul 28 07:19:13 PM PDT 24
Finished Jul 28 07:19:14 PM PDT 24
Peak memory 216864 kb
Host smart-319f3c24-259d-4590-95a8-ece8558f195b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704377517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmds
.704377517
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_intercept.3870004322
Short name T735
Test name
Test status
Simulation time 1511521834 ps
CPU time 7.03 seconds
Started Jul 28 07:19:12 PM PDT 24
Finished Jul 28 07:19:19 PM PDT 24
Peak memory 233644 kb
Host smart-e86fa6f1-8b84-4ac0-9052-be452e07a3c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870004322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.3870004322
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.1663025958
Short name T113
Test name
Test status
Simulation time 31652410 ps
CPU time 2.38 seconds
Started Jul 28 07:19:11 PM PDT 24
Finished Jul 28 07:19:14 PM PDT 24
Peak memory 233220 kb
Host smart-16cd4dbe-b4a2-4026-b296-f52f8b0ed054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663025958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.1663025958
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.3289922255
Short name T834
Test name
Test status
Simulation time 283384179 ps
CPU time 1.06 seconds
Started Jul 28 07:19:12 PM PDT 24
Finished Jul 28 07:19:13 PM PDT 24
Peak memory 217360 kb
Host smart-58a38d3b-aeb6-4cb3-bb3f-723b2840c609
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289922255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.spi_device_mem_parity.3289922255
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.2252526133
Short name T812
Test name
Test status
Simulation time 444302870 ps
CPU time 2.75 seconds
Started Jul 28 07:19:12 PM PDT 24
Finished Jul 28 07:19:15 PM PDT 24
Peak memory 233660 kb
Host smart-7b7af8ff-591e-4cf3-b270-4019246fa011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252526133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.2252526133
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.669962406
Short name T283
Test name
Test status
Simulation time 2343889608 ps
CPU time 8.96 seconds
Started Jul 28 07:19:11 PM PDT 24
Finished Jul 28 07:19:21 PM PDT 24
Peak memory 225448 kb
Host smart-076c7503-699b-40e2-acb3-9664d2baa0f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669962406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.669962406
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.557696157
Short name T573
Test name
Test status
Simulation time 483265444 ps
CPU time 6.31 seconds
Started Jul 28 07:19:15 PM PDT 24
Finished Jul 28 07:19:22 PM PDT 24
Peak memory 222796 kb
Host smart-8e064ac4-03ae-4e66-915e-2ce32731b499
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=557696157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dire
ct.557696157
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.560218102
Short name T769
Test name
Test status
Simulation time 3546281936 ps
CPU time 56.09 seconds
Started Jul 28 07:19:16 PM PDT 24
Finished Jul 28 07:20:12 PM PDT 24
Peak memory 250108 kb
Host smart-6d8a3deb-77ac-43bd-85df-287748d17bda
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560218102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stres
s_all.560218102
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.3027941970
Short name T448
Test name
Test status
Simulation time 4251473722 ps
CPU time 9.32 seconds
Started Jul 28 07:19:12 PM PDT 24
Finished Jul 28 07:19:21 PM PDT 24
Peak memory 217260 kb
Host smart-16b264f8-85af-43c4-af98-eeb3770576f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027941970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.3027941970
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.1730728315
Short name T567
Test name
Test status
Simulation time 1621549120 ps
CPU time 5.97 seconds
Started Jul 28 07:19:13 PM PDT 24
Finished Jul 28 07:19:19 PM PDT 24
Peak memory 217140 kb
Host smart-448dbb6c-03ed-480d-9c87-30abcd53bd94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730728315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.1730728315
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.2700530321
Short name T145
Test name
Test status
Simulation time 661571120 ps
CPU time 8.63 seconds
Started Jul 28 07:19:14 PM PDT 24
Finished Jul 28 07:19:23 PM PDT 24
Peak memory 217124 kb
Host smart-0affc56f-3a5a-4869-a783-1be6e4c6a797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700530321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.2700530321
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.2955570657
Short name T398
Test name
Test status
Simulation time 69825535 ps
CPU time 0.94 seconds
Started Jul 28 07:19:11 PM PDT 24
Finished Jul 28 07:19:12 PM PDT 24
Peak memory 207716 kb
Host smart-101c01ca-99b6-43c1-9ac7-28daa8e9a453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955570657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.2955570657
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.2850871992
Short name T469
Test name
Test status
Simulation time 229888370 ps
CPU time 4.32 seconds
Started Jul 28 07:19:11 PM PDT 24
Finished Jul 28 07:19:16 PM PDT 24
Peak memory 225424 kb
Host smart-84c993b1-833a-4471-9bc8-a5ccddd7f03a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850871992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.2850871992
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.3136109435
Short name T671
Test name
Test status
Simulation time 11892379 ps
CPU time 0.71 seconds
Started Jul 28 07:19:20 PM PDT 24
Finished Jul 28 07:19:20 PM PDT 24
Peak memory 206100 kb
Host smart-17dbcbd6-3c18-4669-8d2e-0d0f768a2475
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136109435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
3136109435
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.3789998802
Short name T730
Test name
Test status
Simulation time 3743683949 ps
CPU time 8.77 seconds
Started Jul 28 07:19:20 PM PDT 24
Finished Jul 28 07:19:29 PM PDT 24
Peak memory 225532 kb
Host smart-3ddf09ff-1bbe-469f-b202-1034013f344e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789998802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.3789998802
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.661683514
Short name T795
Test name
Test status
Simulation time 67236397 ps
CPU time 0.79 seconds
Started Jul 28 07:19:13 PM PDT 24
Finished Jul 28 07:19:14 PM PDT 24
Peak memory 207560 kb
Host smart-06038134-da29-44fa-b77b-182bb8b2b86b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661683514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.661683514
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.1922374048
Short name T431
Test name
Test status
Simulation time 29020423398 ps
CPU time 109.36 seconds
Started Jul 28 07:19:17 PM PDT 24
Finished Jul 28 07:21:06 PM PDT 24
Peak memory 255120 kb
Host smart-01339904-ecf4-4b32-af17-8fe39bc5bd43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922374048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.1922374048
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.1894797570
Short name T416
Test name
Test status
Simulation time 14306389178 ps
CPU time 83.41 seconds
Started Jul 28 07:19:18 PM PDT 24
Finished Jul 28 07:20:42 PM PDT 24
Peak memory 250900 kb
Host smart-dbab1718-bb27-438a-bd8a-58bba7675af0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894797570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.1894797570
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.268480150
Short name T472
Test name
Test status
Simulation time 8545410900 ps
CPU time 98.28 seconds
Started Jul 28 07:19:17 PM PDT 24
Finished Jul 28 07:20:56 PM PDT 24
Peak memory 250140 kb
Host smart-93bf4a87-f6c5-433d-91b6-6789fa9c8a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268480150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idle
.268480150
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.4205941407
Short name T321
Test name
Test status
Simulation time 3874615228 ps
CPU time 17.38 seconds
Started Jul 28 07:19:17 PM PDT 24
Finished Jul 28 07:19:34 PM PDT 24
Peak memory 225500 kb
Host smart-4b20df45-c40d-4b14-a6f7-d39ff8081df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205941407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.4205941407
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.701811310
Short name T426
Test name
Test status
Simulation time 3227243262 ps
CPU time 35.93 seconds
Started Jul 28 07:19:17 PM PDT 24
Finished Jul 28 07:19:53 PM PDT 24
Peak memory 254844 kb
Host smart-330aff49-4015-4d33-911b-c581d83a8cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701811310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmds
.701811310
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/13.spi_device_intercept.2696929376
Short name T209
Test name
Test status
Simulation time 340280762 ps
CPU time 7.79 seconds
Started Jul 28 07:19:18 PM PDT 24
Finished Jul 28 07:19:26 PM PDT 24
Peak memory 233656 kb
Host smart-992dc16d-1b7d-40c7-9319-bae31c7a7d48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696929376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.2696929376
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.3325373984
Short name T853
Test name
Test status
Simulation time 591311531 ps
CPU time 5.99 seconds
Started Jul 28 07:19:16 PM PDT 24
Finished Jul 28 07:19:22 PM PDT 24
Peak memory 225424 kb
Host smart-f9572469-9042-4904-85d2-787036c94b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325373984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.3325373984
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.2762137021
Short name T1018
Test name
Test status
Simulation time 32323013 ps
CPU time 1.11 seconds
Started Jul 28 07:19:19 PM PDT 24
Finished Jul 28 07:19:20 PM PDT 24
Peak memory 217480 kb
Host smart-c13aba28-5ff0-4a73-9f97-1b3715a298df
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762137021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.spi_device_mem_parity.2762137021
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.738994626
Short name T307
Test name
Test status
Simulation time 55325061075 ps
CPU time 16.14 seconds
Started Jul 28 07:19:19 PM PDT 24
Finished Jul 28 07:19:35 PM PDT 24
Peak memory 241840 kb
Host smart-87e42729-f424-433c-be6a-76906a1167fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738994626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swap
.738994626
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.1949618101
Short name T963
Test name
Test status
Simulation time 1791078885 ps
CPU time 10.75 seconds
Started Jul 28 07:19:16 PM PDT 24
Finished Jul 28 07:19:27 PM PDT 24
Peak memory 233628 kb
Host smart-389eae1b-5bf1-4aa9-8f81-3f1ce8792f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949618101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.1949618101
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.235128711
Short name T365
Test name
Test status
Simulation time 2853423833 ps
CPU time 4.78 seconds
Started Jul 28 07:19:16 PM PDT 24
Finished Jul 28 07:19:21 PM PDT 24
Peak memory 221724 kb
Host smart-fac1a233-c1a0-4d9b-8f6b-6550c7094b0b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=235128711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dire
ct.235128711
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.4043028964
Short name T20
Test name
Test status
Simulation time 10738691261 ps
CPU time 32.79 seconds
Started Jul 28 07:19:17 PM PDT 24
Finished Jul 28 07:19:50 PM PDT 24
Peak memory 256860 kb
Host smart-20664150-358f-46b7-ae64-6a0265e990bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043028964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.4043028964
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.4040565958
Short name T434
Test name
Test status
Simulation time 23503282472 ps
CPU time 22.87 seconds
Started Jul 28 07:19:16 PM PDT 24
Finished Jul 28 07:19:39 PM PDT 24
Peak memory 218500 kb
Host smart-0421aee2-f891-495e-b013-bde181fccd03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040565958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.4040565958
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.2674872937
Short name T474
Test name
Test status
Simulation time 3635204730 ps
CPU time 6.32 seconds
Started Jul 28 07:19:16 PM PDT 24
Finished Jul 28 07:19:23 PM PDT 24
Peak memory 217280 kb
Host smart-173e5d0a-2b9f-4c47-8d36-efa3e14f711a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674872937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.2674872937
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.2265003814
Short name T360
Test name
Test status
Simulation time 206004319 ps
CPU time 2.84 seconds
Started Jul 28 07:19:16 PM PDT 24
Finished Jul 28 07:19:19 PM PDT 24
Peak memory 217112 kb
Host smart-34f2e8e2-988d-4d32-886b-aede80929bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265003814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.2265003814
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.3457741682
Short name T381
Test name
Test status
Simulation time 28487262 ps
CPU time 0.85 seconds
Started Jul 28 07:19:16 PM PDT 24
Finished Jul 28 07:19:17 PM PDT 24
Peak memory 206772 kb
Host smart-f4cf0526-9d01-41c8-8ec7-8730dc3ca38d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457741682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.3457741682
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.3689066344
Short name T771
Test name
Test status
Simulation time 572144735 ps
CPU time 7.29 seconds
Started Jul 28 07:19:16 PM PDT 24
Finished Jul 28 07:19:23 PM PDT 24
Peak memory 225408 kb
Host smart-4a974c7c-0efc-4a0d-bf86-4382df4c0457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689066344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.3689066344
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.3712061560
Short name T945
Test name
Test status
Simulation time 47244978 ps
CPU time 0.74 seconds
Started Jul 28 07:19:25 PM PDT 24
Finished Jul 28 07:19:26 PM PDT 24
Peak memory 205512 kb
Host smart-ab5e5f6f-eeed-4c3e-8bb6-8f0218479bfb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712061560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
3712061560
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.462130412
Short name T389
Test name
Test status
Simulation time 157386413 ps
CPU time 3.96 seconds
Started Jul 28 07:19:22 PM PDT 24
Finished Jul 28 07:19:26 PM PDT 24
Peak memory 233628 kb
Host smart-70edcf3b-d51d-460b-945e-05b01054b53b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462130412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.462130412
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.1538315631
Short name T534
Test name
Test status
Simulation time 34425308 ps
CPU time 0.78 seconds
Started Jul 28 07:19:23 PM PDT 24
Finished Jul 28 07:19:24 PM PDT 24
Peak memory 207252 kb
Host smart-14546a57-f9f8-46fa-b171-b1e4550fa0e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538315631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.1538315631
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.265791208
Short name T294
Test name
Test status
Simulation time 14063992673 ps
CPU time 148.05 seconds
Started Jul 28 07:19:20 PM PDT 24
Finished Jul 28 07:21:48 PM PDT 24
Peak memory 266392 kb
Host smart-d7421900-62dc-45e4-859f-b372d3d3ec47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265791208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.265791208
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.3151341244
Short name T244
Test name
Test status
Simulation time 8188882686 ps
CPU time 66.04 seconds
Started Jul 28 07:19:24 PM PDT 24
Finished Jul 28 07:20:31 PM PDT 24
Peak memory 240132 kb
Host smart-d3af20c7-0275-4f0d-8bf2-34230b914b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151341244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.3151341244
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.3299057088
Short name T447
Test name
Test status
Simulation time 52379195921 ps
CPU time 98.43 seconds
Started Jul 28 07:19:25 PM PDT 24
Finished Jul 28 07:21:03 PM PDT 24
Peak memory 234776 kb
Host smart-a534f7c7-6f2f-400c-9b1f-44099115811b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299057088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.3299057088
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.1509585682
Short name T864
Test name
Test status
Simulation time 671738093 ps
CPU time 7.31 seconds
Started Jul 28 07:19:20 PM PDT 24
Finished Jul 28 07:19:28 PM PDT 24
Peak memory 241808 kb
Host smart-c7f2746c-20ec-4da0-8d47-8446552b4650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509585682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.1509585682
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.3911385728
Short name T221
Test name
Test status
Simulation time 161788290049 ps
CPU time 547.43 seconds
Started Jul 28 07:19:24 PM PDT 24
Finished Jul 28 07:28:32 PM PDT 24
Peak memory 282920 kb
Host smart-3d38cd83-3f69-4f8f-ba06-4334b0ca9f7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911385728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmd
s.3911385728
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_intercept.3159768198
Short name T998
Test name
Test status
Simulation time 476974718 ps
CPU time 5.13 seconds
Started Jul 28 07:19:29 PM PDT 24
Finished Jul 28 07:19:34 PM PDT 24
Peak memory 225408 kb
Host smart-0173e87e-fc11-464d-b9ed-abf5813c930c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159768198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.3159768198
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.1889350195
Short name T260
Test name
Test status
Simulation time 18693052172 ps
CPU time 40.12 seconds
Started Jul 28 07:19:20 PM PDT 24
Finished Jul 28 07:20:00 PM PDT 24
Peak memory 241568 kb
Host smart-7834f5ea-d830-474b-a8d0-6be6437d8185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889350195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.1889350195
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.825849914
Short name T388
Test name
Test status
Simulation time 25872365 ps
CPU time 1.07 seconds
Started Jul 28 07:19:20 PM PDT 24
Finished Jul 28 07:19:21 PM PDT 24
Peak memory 217412 kb
Host smart-1c7479e2-f6fa-443e-9379-62bb18a9f39d
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825849914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.spi_device_mem_parity.825849914
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.269579684
Short name T271
Test name
Test status
Simulation time 203629349 ps
CPU time 2.71 seconds
Started Jul 28 07:19:22 PM PDT 24
Finished Jul 28 07:19:25 PM PDT 24
Peak memory 225396 kb
Host smart-31025f1c-457e-4517-820c-3b8fef7ef9ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269579684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swap
.269579684
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.3405431148
Short name T540
Test name
Test status
Simulation time 467024028 ps
CPU time 3.62 seconds
Started Jul 28 07:19:27 PM PDT 24
Finished Jul 28 07:19:31 PM PDT 24
Peak memory 225336 kb
Host smart-9116ed83-4a8c-4115-a82b-8f51744b7422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405431148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.3405431148
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.934631450
Short name T46
Test name
Test status
Simulation time 1259495753 ps
CPU time 13.46 seconds
Started Jul 28 07:19:21 PM PDT 24
Finished Jul 28 07:19:35 PM PDT 24
Peak memory 223156 kb
Host smart-419c822d-0077-488f-bcbe-8a653cc883bc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=934631450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dire
ct.934631450
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.1824073292
Short name T897
Test name
Test status
Simulation time 4561434245 ps
CPU time 16.2 seconds
Started Jul 28 07:19:23 PM PDT 24
Finished Jul 28 07:19:39 PM PDT 24
Peak memory 217384 kb
Host smart-ae9d2142-278e-496a-843a-fc729e603ea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824073292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.1824073292
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.1906519796
Short name T911
Test name
Test status
Simulation time 16960106260 ps
CPU time 15.29 seconds
Started Jul 28 07:19:21 PM PDT 24
Finished Jul 28 07:19:36 PM PDT 24
Peak memory 217288 kb
Host smart-c74369e6-68b5-4a61-a44c-0bdf38254d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906519796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.1906519796
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.3380389874
Short name T931
Test name
Test status
Simulation time 788482969 ps
CPU time 3.16 seconds
Started Jul 28 07:19:22 PM PDT 24
Finished Jul 28 07:19:25 PM PDT 24
Peak memory 217196 kb
Host smart-823eeee5-48db-462c-a4be-96a586564126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380389874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.3380389874
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.2782005149
Short name T673
Test name
Test status
Simulation time 78830514 ps
CPU time 0.97 seconds
Started Jul 28 07:19:23 PM PDT 24
Finished Jul 28 07:19:24 PM PDT 24
Peak memory 206772 kb
Host smart-be887a5a-c949-48f3-93c6-7eff44948aae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782005149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.2782005149
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.1774294817
Short name T598
Test name
Test status
Simulation time 633734710 ps
CPU time 5.97 seconds
Started Jul 28 07:19:19 PM PDT 24
Finished Jul 28 07:19:25 PM PDT 24
Peak memory 233660 kb
Host smart-1152f249-5313-44e0-b8d9-2ddfac8fb0ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774294817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.1774294817
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.664559828
Short name T633
Test name
Test status
Simulation time 42559150 ps
CPU time 0.74 seconds
Started Jul 28 07:19:26 PM PDT 24
Finished Jul 28 07:19:27 PM PDT 24
Peak memory 205528 kb
Host smart-7db74198-fe87-4d09-804a-8483a97323f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664559828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.664559828
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.1207640683
Short name T29
Test name
Test status
Simulation time 54777998 ps
CPU time 3.02 seconds
Started Jul 28 07:19:27 PM PDT 24
Finished Jul 28 07:19:30 PM PDT 24
Peak memory 233648 kb
Host smart-14ae26a3-e4fd-4b9d-a3d5-bee8097dd83b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207640683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.1207640683
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.3284184290
Short name T496
Test name
Test status
Simulation time 20881807 ps
CPU time 0.73 seconds
Started Jul 28 07:19:26 PM PDT 24
Finished Jul 28 07:19:27 PM PDT 24
Peak memory 206216 kb
Host smart-b8666001-a706-483a-a554-224f02e3ee49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284184290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.3284184290
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.1589935724
Short name T212
Test name
Test status
Simulation time 3877509901 ps
CPU time 72.78 seconds
Started Jul 28 07:19:26 PM PDT 24
Finished Jul 28 07:20:39 PM PDT 24
Peak memory 274196 kb
Host smart-db9635d9-d349-4a53-8971-e934813102ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589935724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.1589935724
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.1112438691
Short name T415
Test name
Test status
Simulation time 45516524188 ps
CPU time 219.45 seconds
Started Jul 28 07:19:26 PM PDT 24
Finished Jul 28 07:23:06 PM PDT 24
Peak memory 251260 kb
Host smart-dc9075e9-16a7-457c-bd3f-5e7f5bd18339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112438691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.1112438691
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.1802797452
Short name T968
Test name
Test status
Simulation time 7374763277 ps
CPU time 27.05 seconds
Started Jul 28 07:19:29 PM PDT 24
Finished Jul 28 07:19:56 PM PDT 24
Peak memory 234736 kb
Host smart-194e9b4c-a742-4843-8a79-2f9c11ce99d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802797452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmd
s.1802797452
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/15.spi_device_intercept.2763444900
Short name T262
Test name
Test status
Simulation time 373161919 ps
CPU time 4.44 seconds
Started Jul 28 07:19:28 PM PDT 24
Finished Jul 28 07:19:33 PM PDT 24
Peak memory 233608 kb
Host smart-68caa506-11c6-4731-b632-d9d363003e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763444900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.2763444900
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.1326914641
Short name T843
Test name
Test status
Simulation time 2385057547 ps
CPU time 11.52 seconds
Started Jul 28 07:19:27 PM PDT 24
Finished Jul 28 07:19:39 PM PDT 24
Peak memory 233680 kb
Host smart-204d3c01-2da8-46e7-9ba2-9860377f8a84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326914641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.1326914641
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.1571156538
Short name T967
Test name
Test status
Simulation time 26769499 ps
CPU time 1.04 seconds
Started Jul 28 07:19:26 PM PDT 24
Finished Jul 28 07:19:28 PM PDT 24
Peak memory 217424 kb
Host smart-66aa6d61-593e-4146-801c-82d7efcff958
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571156538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.1571156538
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.968056170
Short name T532
Test name
Test status
Simulation time 352152790 ps
CPU time 2.57 seconds
Started Jul 28 07:19:26 PM PDT 24
Finished Jul 28 07:19:29 PM PDT 24
Peak memory 233624 kb
Host smart-d525fbe5-7bcd-44b1-a02a-182b08511773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968056170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swap
.968056170
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.621084300
Short name T276
Test name
Test status
Simulation time 142892070 ps
CPU time 2.61 seconds
Started Jul 28 07:19:25 PM PDT 24
Finished Jul 28 07:19:27 PM PDT 24
Peak memory 225472 kb
Host smart-ef463da3-12a0-4825-8f14-23320b11fb91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621084300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.621084300
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.403169734
Short name T669
Test name
Test status
Simulation time 1051878155 ps
CPU time 4.54 seconds
Started Jul 28 07:19:25 PM PDT 24
Finished Jul 28 07:19:29 PM PDT 24
Peak memory 223856 kb
Host smart-786bf495-e207-448c-8720-6f0e49792551
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=403169734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dire
ct.403169734
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.2468584770
Short name T728
Test name
Test status
Simulation time 66191869 ps
CPU time 1.03 seconds
Started Jul 28 07:19:31 PM PDT 24
Finished Jul 28 07:19:33 PM PDT 24
Peak memory 207352 kb
Host smart-b293dd8b-96a5-4d35-a18b-287acde0c41a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468584770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.2468584770
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.836970744
Short name T362
Test name
Test status
Simulation time 3429197700 ps
CPU time 2.77 seconds
Started Jul 28 07:19:25 PM PDT 24
Finished Jul 28 07:19:28 PM PDT 24
Peak memory 217260 kb
Host smart-1b51fedd-f9ab-4f58-a761-71a140e0042e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836970744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.836970744
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.629860932
Short name T635
Test name
Test status
Simulation time 524334578 ps
CPU time 3.33 seconds
Started Jul 28 07:19:26 PM PDT 24
Finished Jul 28 07:19:29 PM PDT 24
Peak memory 217072 kb
Host smart-5a852649-76a1-4112-a4f1-b046d3105fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629860932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.629860932
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.4050955320
Short name T334
Test name
Test status
Simulation time 381841617 ps
CPU time 6.76 seconds
Started Jul 28 07:19:29 PM PDT 24
Finished Jul 28 07:19:36 PM PDT 24
Peak memory 217192 kb
Host smart-574b71c5-f945-46f5-abb7-93e780198519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050955320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.4050955320
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.2941011976
Short name T640
Test name
Test status
Simulation time 191026063 ps
CPU time 0.82 seconds
Started Jul 28 07:19:28 PM PDT 24
Finished Jul 28 07:19:29 PM PDT 24
Peak memory 206724 kb
Host smart-66915750-1154-4ce9-86fe-9951d0869018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941011976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.2941011976
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.1184911303
Short name T49
Test name
Test status
Simulation time 16919970963 ps
CPU time 11.12 seconds
Started Jul 28 07:19:26 PM PDT 24
Finished Jul 28 07:19:37 PM PDT 24
Peak memory 233728 kb
Host smart-5ad94055-4f12-492f-b61b-269f1e685d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184911303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.1184911303
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.431669375
Short name T8
Test name
Test status
Simulation time 14048603 ps
CPU time 0.69 seconds
Started Jul 28 07:19:36 PM PDT 24
Finished Jul 28 07:19:37 PM PDT 24
Peak memory 205488 kb
Host smart-a11771c4-213d-457b-b7e5-edd0db4352dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431669375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.431669375
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.3858802579
Short name T752
Test name
Test status
Simulation time 604270420 ps
CPU time 5.03 seconds
Started Jul 28 07:19:32 PM PDT 24
Finished Jul 28 07:19:37 PM PDT 24
Peak memory 225444 kb
Host smart-fc1c512b-45ce-4ca5-8e53-b26b22b14d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858802579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.3858802579
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.873910461
Short name T588
Test name
Test status
Simulation time 14617329 ps
CPU time 0.76 seconds
Started Jul 28 07:19:30 PM PDT 24
Finished Jul 28 07:19:30 PM PDT 24
Peak memory 206216 kb
Host smart-4f99ce5c-b926-40a9-8e32-c550be23ecae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873910461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.873910461
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.1654147959
Short name T700
Test name
Test status
Simulation time 5486676577 ps
CPU time 40.73 seconds
Started Jul 28 07:19:34 PM PDT 24
Finished Jul 28 07:20:15 PM PDT 24
Peak memory 239396 kb
Host smart-d95cb67a-c65b-4f8c-9ddf-426c264c23d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654147959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.1654147959
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.1355495168
Short name T464
Test name
Test status
Simulation time 4089552638 ps
CPU time 43.19 seconds
Started Jul 28 07:19:33 PM PDT 24
Finished Jul 28 07:20:16 PM PDT 24
Peak memory 240600 kb
Host smart-3efeaebe-b45e-4008-851f-c0c220e76d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355495168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.1355495168
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.1958964971
Short name T340
Test name
Test status
Simulation time 69573020 ps
CPU time 3.04 seconds
Started Jul 28 07:19:29 PM PDT 24
Finished Jul 28 07:19:32 PM PDT 24
Peak memory 233668 kb
Host smart-21d19892-28ea-4128-b921-4aea56f10717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958964971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.1958964971
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.166163496
Short name T261
Test name
Test status
Simulation time 2781584874 ps
CPU time 8.78 seconds
Started Jul 28 07:19:34 PM PDT 24
Finished Jul 28 07:19:43 PM PDT 24
Peak memory 225496 kb
Host smart-a31b6093-45e3-44a2-8621-3f88968fc56c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166163496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmds
.166163496
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/16.spi_device_intercept.2755972704
Short name T250
Test name
Test status
Simulation time 189742824 ps
CPU time 2.78 seconds
Started Jul 28 07:19:30 PM PDT 24
Finished Jul 28 07:19:33 PM PDT 24
Peak memory 225444 kb
Host smart-1d2f269f-34f8-4ca5-bf66-47d77ff21006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755972704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.2755972704
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.1731935833
Short name T169
Test name
Test status
Simulation time 891586159 ps
CPU time 6.35 seconds
Started Jul 28 07:19:28 PM PDT 24
Finished Jul 28 07:19:34 PM PDT 24
Peak memory 233636 kb
Host smart-9cbae0bf-1ce4-4f1b-ab50-52c731df39de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731935833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.1731935833
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.748414326
Short name T604
Test name
Test status
Simulation time 34241782 ps
CPU time 1.08 seconds
Started Jul 28 07:19:30 PM PDT 24
Finished Jul 28 07:19:31 PM PDT 24
Peak memory 217340 kb
Host smart-e89e35b1-b2fe-4c78-9baa-027b2e5a284f
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748414326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.spi_device_mem_parity.748414326
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.2046231968
Short name T83
Test name
Test status
Simulation time 1525301956 ps
CPU time 4.29 seconds
Started Jul 28 07:19:31 PM PDT 24
Finished Jul 28 07:19:35 PM PDT 24
Peak memory 225340 kb
Host smart-ed8e24d7-e25a-4d74-b499-ce425ccbd8c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046231968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.2046231968
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.211472835
Short name T454
Test name
Test status
Simulation time 1075009454 ps
CPU time 4.48 seconds
Started Jul 28 07:19:30 PM PDT 24
Finished Jul 28 07:19:35 PM PDT 24
Peak memory 225496 kb
Host smart-bdbcb857-ece0-432e-a216-6753abb37462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211472835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.211472835
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.15941360
Short name T747
Test name
Test status
Simulation time 107887406 ps
CPU time 3.62 seconds
Started Jul 28 07:19:28 PM PDT 24
Finished Jul 28 07:19:31 PM PDT 24
Peak memory 223228 kb
Host smart-84053d01-8148-47b0-8f41-1c74db709f70
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=15941360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_direc
t.15941360
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.4112007541
Short name T585
Test name
Test status
Simulation time 16075414588 ps
CPU time 142.52 seconds
Started Jul 28 07:19:35 PM PDT 24
Finished Jul 28 07:21:57 PM PDT 24
Peak memory 254280 kb
Host smart-e76cf2ae-7cbb-43f4-9650-8912b8e7c6ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112007541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.4112007541
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.3728703014
Short name T502
Test name
Test status
Simulation time 205526886 ps
CPU time 2.05 seconds
Started Jul 28 07:19:29 PM PDT 24
Finished Jul 28 07:19:31 PM PDT 24
Peak memory 218440 kb
Host smart-96dfe2f9-9770-4882-9a23-c45f6da55739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728703014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.3728703014
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.977549838
Short name T453
Test name
Test status
Simulation time 4420578557 ps
CPU time 5.16 seconds
Started Jul 28 07:19:29 PM PDT 24
Finished Jul 28 07:19:34 PM PDT 24
Peak memory 217248 kb
Host smart-a9de832b-d60b-4e8f-a093-ad742b5b4c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977549838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.977549838
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.3181167006
Short name T682
Test name
Test status
Simulation time 349503189 ps
CPU time 1.7 seconds
Started Jul 28 07:19:31 PM PDT 24
Finished Jul 28 07:19:32 PM PDT 24
Peak memory 217240 kb
Host smart-269a23ff-2ffe-403e-b806-8a5922677389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181167006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.3181167006
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.3423465498
Short name T810
Test name
Test status
Simulation time 84716961 ps
CPU time 0.76 seconds
Started Jul 28 07:19:32 PM PDT 24
Finished Jul 28 07:19:33 PM PDT 24
Peak memory 206772 kb
Host smart-92f3aadd-d721-4a29-a158-b62939af34a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423465498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.3423465498
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.3942445164
Short name T703
Test name
Test status
Simulation time 13539086196 ps
CPU time 22.42 seconds
Started Jul 28 07:19:30 PM PDT 24
Finished Jul 28 07:19:52 PM PDT 24
Peak memory 231624 kb
Host smart-a943bbda-93f5-4cb3-8873-210e771a8909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942445164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.3942445164
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.1564115147
Short name T529
Test name
Test status
Simulation time 37244373 ps
CPU time 0.73 seconds
Started Jul 28 07:19:41 PM PDT 24
Finished Jul 28 07:19:42 PM PDT 24
Peak memory 206380 kb
Host smart-19ec435a-4048-442f-b707-b6eb5566c6c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564115147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
1564115147
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.2270580862
Short name T406
Test name
Test status
Simulation time 1903953484 ps
CPU time 18.06 seconds
Started Jul 28 07:19:40 PM PDT 24
Finished Jul 28 07:19:58 PM PDT 24
Peak memory 233676 kb
Host smart-fe1bb946-a48c-4594-bc33-7a26330d9984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270580862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.2270580862
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.371132222
Short name T674
Test name
Test status
Simulation time 15378929 ps
CPU time 0.77 seconds
Started Jul 28 07:19:34 PM PDT 24
Finished Jul 28 07:19:35 PM PDT 24
Peak memory 206224 kb
Host smart-065a9d14-b715-4ba7-b330-0e653060b362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371132222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.371132222
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.2176373155
Short name T960
Test name
Test status
Simulation time 30999319288 ps
CPU time 51.98 seconds
Started Jul 28 07:19:38 PM PDT 24
Finished Jul 28 07:20:30 PM PDT 24
Peak memory 255776 kb
Host smart-aff922a6-dabb-408a-9b5a-8899825acc09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176373155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.2176373155
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.1898130191
Short name T766
Test name
Test status
Simulation time 57132995322 ps
CPU time 566.24 seconds
Started Jul 28 07:19:40 PM PDT 24
Finished Jul 28 07:29:07 PM PDT 24
Peak memory 254324 kb
Host smart-3f689a5c-f48e-44db-a21b-be5b6d900091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898130191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.1898130191
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.862979136
Short name T150
Test name
Test status
Simulation time 20248917513 ps
CPU time 213.32 seconds
Started Jul 28 07:19:41 PM PDT 24
Finished Jul 28 07:23:14 PM PDT 24
Peak memory 254644 kb
Host smart-657fb014-05e8-4592-b7de-733fbfa7991c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862979136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idle
.862979136
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.3141710128
Short name T830
Test name
Test status
Simulation time 170990804 ps
CPU time 6.72 seconds
Started Jul 28 07:19:35 PM PDT 24
Finished Jul 28 07:19:42 PM PDT 24
Peak memory 233808 kb
Host smart-fa754913-f731-4a41-a24a-06b3340d7681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141710128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.3141710128
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.1167890395
Short name T195
Test name
Test status
Simulation time 6964724341 ps
CPU time 52.1 seconds
Started Jul 28 07:19:39 PM PDT 24
Finished Jul 28 07:20:31 PM PDT 24
Peak memory 251068 kb
Host smart-b1e8dff6-332e-45df-b2bf-e50a98496423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167890395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmd
s.1167890395
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/17.spi_device_intercept.1129111254
Short name T226
Test name
Test status
Simulation time 79414100 ps
CPU time 3.35 seconds
Started Jul 28 07:19:34 PM PDT 24
Finished Jul 28 07:19:37 PM PDT 24
Peak memory 233580 kb
Host smart-df382bef-890b-4bad-b838-0a3bebeedfc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129111254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.1129111254
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.2812452305
Short name T500
Test name
Test status
Simulation time 1037444360 ps
CPU time 10.1 seconds
Started Jul 28 07:19:38 PM PDT 24
Finished Jul 28 07:19:48 PM PDT 24
Peak memory 233548 kb
Host smart-b3721a60-f221-4abd-9195-2efebd84cd0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812452305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.2812452305
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.226632760
Short name T600
Test name
Test status
Simulation time 122175248 ps
CPU time 1.12 seconds
Started Jul 28 07:19:34 PM PDT 24
Finished Jul 28 07:19:35 PM PDT 24
Peak memory 217376 kb
Host smart-78c6b012-83c3-4cb8-8429-e377911ac559
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226632760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.spi_device_mem_parity.226632760
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.3004545973
Short name T855
Test name
Test status
Simulation time 35537502271 ps
CPU time 11.49 seconds
Started Jul 28 07:19:34 PM PDT 24
Finished Jul 28 07:19:45 PM PDT 24
Peak memory 233700 kb
Host smart-ebc275f2-33f4-4784-808e-cbf3ac9251b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004545973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.3004545973
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.15180378
Short name T450
Test name
Test status
Simulation time 1062966476 ps
CPU time 4.14 seconds
Started Jul 28 07:19:35 PM PDT 24
Finished Jul 28 07:19:39 PM PDT 24
Peak memory 233660 kb
Host smart-a807198c-a0d8-4a2b-aaea-473d64e0e51b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15180378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.15180378
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.3095010971
Short name T407
Test name
Test status
Simulation time 2230508765 ps
CPU time 8.76 seconds
Started Jul 28 07:19:40 PM PDT 24
Finished Jul 28 07:19:49 PM PDT 24
Peak memory 220212 kb
Host smart-e87a8392-6d0a-44c1-9778-861c947025b5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3095010971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.3095010971
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.1921311683
Short name T884
Test name
Test status
Simulation time 48146581 ps
CPU time 1.06 seconds
Started Jul 28 07:19:40 PM PDT 24
Finished Jul 28 07:19:41 PM PDT 24
Peak memory 207520 kb
Host smart-96bb20fe-750d-4c94-bab5-e0d0c33122f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921311683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.1921311683
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.344938146
Short name T328
Test name
Test status
Simulation time 129013502 ps
CPU time 2.21 seconds
Started Jul 28 07:19:33 PM PDT 24
Finished Jul 28 07:19:36 PM PDT 24
Peak memory 219192 kb
Host smart-9f16a40f-f366-4da4-b935-ef71fb4ac383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344938146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.344938146
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.1727131726
Short name T505
Test name
Test status
Simulation time 2078430724 ps
CPU time 6.35 seconds
Started Jul 28 07:19:34 PM PDT 24
Finished Jul 28 07:19:41 PM PDT 24
Peak memory 217216 kb
Host smart-8f2cc063-9be2-4012-9886-b05fb82b6b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727131726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.1727131726
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.3025399023
Short name T516
Test name
Test status
Simulation time 46564658 ps
CPU time 1.2 seconds
Started Jul 28 07:19:32 PM PDT 24
Finished Jul 28 07:19:33 PM PDT 24
Peak memory 217184 kb
Host smart-e076a9f4-88ac-4b73-a6d9-44b5efa603d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025399023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.3025399023
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.984271919
Short name T937
Test name
Test status
Simulation time 35007300 ps
CPU time 0.7 seconds
Started Jul 28 07:19:34 PM PDT 24
Finished Jul 28 07:19:34 PM PDT 24
Peak memory 206348 kb
Host smart-b75c2872-9903-4040-bbf4-851288d3337f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984271919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.984271919
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.2757968845
Short name T831
Test name
Test status
Simulation time 5211490427 ps
CPU time 18.14 seconds
Started Jul 28 07:19:35 PM PDT 24
Finished Jul 28 07:19:53 PM PDT 24
Peak memory 233700 kb
Host smart-1cfe603e-68c8-4831-be01-34256c7fc71a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757968845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.2757968845
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.2409042986
Short name T774
Test name
Test status
Simulation time 23629776 ps
CPU time 0.72 seconds
Started Jul 28 07:19:46 PM PDT 24
Finished Jul 28 07:19:46 PM PDT 24
Peak memory 206068 kb
Host smart-b5fcc700-9baa-4070-b1b5-04ba8acc0008
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409042986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
2409042986
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.3134305785
Short name T724
Test name
Test status
Simulation time 1530959575 ps
CPU time 5.12 seconds
Started Jul 28 07:19:43 PM PDT 24
Finished Jul 28 07:19:49 PM PDT 24
Peak memory 225296 kb
Host smart-887a90fc-c87d-41fa-ab53-184612609545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134305785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.3134305785
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.1921345115
Short name T27
Test name
Test status
Simulation time 36542827 ps
CPU time 0.78 seconds
Started Jul 28 07:19:41 PM PDT 24
Finished Jul 28 07:19:41 PM PDT 24
Peak memory 207600 kb
Host smart-75bc4690-32bc-4c54-95c6-4b80e0ea8c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921345115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.1921345115
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.2367102952
Short name T817
Test name
Test status
Simulation time 79340645388 ps
CPU time 63.14 seconds
Started Jul 28 07:19:47 PM PDT 24
Finished Jul 28 07:20:50 PM PDT 24
Peak memory 250096 kb
Host smart-b660cf65-b452-4a73-8601-23cafa95ca77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367102952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.2367102952
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.124836016
Short name T602
Test name
Test status
Simulation time 1389709531 ps
CPU time 12.2 seconds
Started Jul 28 07:19:44 PM PDT 24
Finished Jul 28 07:19:56 PM PDT 24
Peak memory 241912 kb
Host smart-576e38c9-8e84-4919-ad65-edce3e1902e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124836016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.124836016
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.1367403013
Short name T642
Test name
Test status
Simulation time 313745422 ps
CPU time 3.68 seconds
Started Jul 28 07:19:44 PM PDT 24
Finished Jul 28 07:19:48 PM PDT 24
Peak memory 218472 kb
Host smart-50e5e7ff-d239-4535-83fc-9ebf8eeb9078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367403013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.1367403013
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.2139651633
Short name T512
Test name
Test status
Simulation time 267833703 ps
CPU time 5.39 seconds
Started Jul 28 07:19:50 PM PDT 24
Finished Jul 28 07:19:55 PM PDT 24
Peak memory 240188 kb
Host smart-8411b1ef-c8d0-4a38-bec5-7ba58031429a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139651633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.2139651633
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.1591316235
Short name T295
Test name
Test status
Simulation time 8347275015 ps
CPU time 78.59 seconds
Started Jul 28 07:19:42 PM PDT 24
Finished Jul 28 07:21:01 PM PDT 24
Peak memory 251268 kb
Host smart-d04e9160-fa1a-4180-a736-866338dd3bf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591316235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmd
s.1591316235
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/18.spi_device_intercept.1217518734
Short name T25
Test name
Test status
Simulation time 841304977 ps
CPU time 5.27 seconds
Started Jul 28 07:19:42 PM PDT 24
Finished Jul 28 07:19:47 PM PDT 24
Peak memory 233632 kb
Host smart-11c81f64-364b-4b6d-907b-c917d269cf8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217518734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.1217518734
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.1354834962
Short name T435
Test name
Test status
Simulation time 176415180 ps
CPU time 4.21 seconds
Started Jul 28 07:19:43 PM PDT 24
Finished Jul 28 07:19:47 PM PDT 24
Peak memory 233580 kb
Host smart-8afc7841-33c8-4b19-bb59-49657c42484b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354834962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.1354834962
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.3485321328
Short name T809
Test name
Test status
Simulation time 18074271 ps
CPU time 1.04 seconds
Started Jul 28 07:19:40 PM PDT 24
Finished Jul 28 07:19:41 PM PDT 24
Peak memory 217476 kb
Host smart-ded2a7dc-e744-4ff8-8934-fa1694e4c2e2
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485321328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.spi_device_mem_parity.3485321328
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.2428134768
Short name T82
Test name
Test status
Simulation time 3098002649 ps
CPU time 8.94 seconds
Started Jul 28 07:19:41 PM PDT 24
Finished Jul 28 07:19:50 PM PDT 24
Peak memory 241408 kb
Host smart-268b9ec2-fb5e-458b-b78f-f0e1ed6e6b3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428134768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.2428134768
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.912657820
Short name T819
Test name
Test status
Simulation time 1112684342 ps
CPU time 5.97 seconds
Started Jul 28 07:19:43 PM PDT 24
Finished Jul 28 07:19:50 PM PDT 24
Peak memory 233500 kb
Host smart-cf0d59e7-07c5-43ef-90d5-cd5171c5f063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912657820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.912657820
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.236205061
Short name T756
Test name
Test status
Simulation time 2730594847 ps
CPU time 19.85 seconds
Started Jul 28 07:19:42 PM PDT 24
Finished Jul 28 07:20:02 PM PDT 24
Peak memory 221052 kb
Host smart-4122df8a-0daf-4f42-8c93-5d218fd80e72
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=236205061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dire
ct.236205061
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.1315212733
Short name T727
Test name
Test status
Simulation time 3305105046 ps
CPU time 45.73 seconds
Started Jul 28 07:19:43 PM PDT 24
Finished Jul 28 07:20:29 PM PDT 24
Peak memory 237560 kb
Host smart-34d496a8-86f0-4df6-9afb-460804daee6a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315212733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.1315212733
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.1802394333
Short name T459
Test name
Test status
Simulation time 528552111 ps
CPU time 2.01 seconds
Started Jul 28 07:19:43 PM PDT 24
Finished Jul 28 07:19:46 PM PDT 24
Peak memory 217252 kb
Host smart-b0ca46a2-7b91-4e65-880d-ac793d038f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802394333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.1802394333
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.742822065
Short name T86
Test name
Test status
Simulation time 7527996379 ps
CPU time 19.57 seconds
Started Jul 28 07:19:44 PM PDT 24
Finished Jul 28 07:20:03 PM PDT 24
Peak memory 217240 kb
Host smart-134f0f7a-a0e1-4d6a-af07-666097e273b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742822065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.742822065
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.3535184144
Short name T463
Test name
Test status
Simulation time 43309814 ps
CPU time 1.69 seconds
Started Jul 28 07:19:39 PM PDT 24
Finished Jul 28 07:19:41 PM PDT 24
Peak memory 217180 kb
Host smart-a6a4f990-be29-42a0-afbd-5ba2158163c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535184144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.3535184144
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.524621237
Short name T978
Test name
Test status
Simulation time 132215853 ps
CPU time 0.77 seconds
Started Jul 28 07:19:42 PM PDT 24
Finished Jul 28 07:19:43 PM PDT 24
Peak memory 206740 kb
Host smart-3c6f4f3a-8c61-43f1-af9f-bfca0feeacfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524621237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.524621237
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.1233710484
Short name T231
Test name
Test status
Simulation time 22096238318 ps
CPU time 16.08 seconds
Started Jul 28 07:19:43 PM PDT 24
Finished Jul 28 07:19:59 PM PDT 24
Peak memory 235872 kb
Host smart-9e15be6f-90ab-425a-b7d9-92ae934d65b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233710484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.1233710484
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.3803667708
Short name T875
Test name
Test status
Simulation time 38442645 ps
CPU time 0.68 seconds
Started Jul 28 07:19:52 PM PDT 24
Finished Jul 28 07:19:53 PM PDT 24
Peak memory 206072 kb
Host smart-c0c71542-7a9a-4ff1-bd4b-5e622dd9359a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803667708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
3803667708
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.981764466
Short name T275
Test name
Test status
Simulation time 320355578 ps
CPU time 3.44 seconds
Started Jul 28 07:19:49 PM PDT 24
Finished Jul 28 07:19:52 PM PDT 24
Peak memory 225388 kb
Host smart-32ee660b-af51-44a3-910b-a6466bfd7b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981764466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.981764466
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.2660363346
Short name T641
Test name
Test status
Simulation time 137825014 ps
CPU time 0.81 seconds
Started Jul 28 07:19:42 PM PDT 24
Finished Jul 28 07:19:43 PM PDT 24
Peak memory 206276 kb
Host smart-51027991-ccf8-4de0-8ec1-be1e67558236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660363346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.2660363346
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.667811448
Short name T269
Test name
Test status
Simulation time 153945385225 ps
CPU time 256.86 seconds
Started Jul 28 07:19:50 PM PDT 24
Finished Jul 28 07:24:07 PM PDT 24
Peak memory 249544 kb
Host smart-1e001a2d-a5e6-4fdb-84b3-76db23863b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667811448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.667811448
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.2582837747
Short name T990
Test name
Test status
Simulation time 17490269844 ps
CPU time 26.23 seconds
Started Jul 28 07:19:47 PM PDT 24
Finished Jul 28 07:20:13 PM PDT 24
Peak memory 220628 kb
Host smart-1062d18e-2c9c-468d-80e6-93d953966798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582837747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.2582837747
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.3557180658
Short name T148
Test name
Test status
Simulation time 4362182214 ps
CPU time 41.46 seconds
Started Jul 28 07:19:47 PM PDT 24
Finished Jul 28 07:20:29 PM PDT 24
Peak memory 253880 kb
Host smart-0a275cd8-77d8-461e-a836-1ee669346783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557180658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.3557180658
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.2049011138
Short name T1008
Test name
Test status
Simulation time 49880948 ps
CPU time 3.14 seconds
Started Jul 28 07:19:46 PM PDT 24
Finished Jul 28 07:19:49 PM PDT 24
Peak memory 233652 kb
Host smart-93f38a60-b401-4b31-8e1f-a191bc195ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049011138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.2049011138
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.800282282
Short name T1022
Test name
Test status
Simulation time 10253346570 ps
CPU time 139.18 seconds
Started Jul 28 07:19:44 PM PDT 24
Finished Jul 28 07:22:04 PM PDT 24
Peak memory 268556 kb
Host smart-deb11bfc-8dbb-4447-887a-e23dd3c39097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800282282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmds
.800282282
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_intercept.446234873
Short name T521
Test name
Test status
Simulation time 124096883 ps
CPU time 3.37 seconds
Started Jul 28 07:19:48 PM PDT 24
Finished Jul 28 07:19:52 PM PDT 24
Peak memory 233628 kb
Host smart-266c9c55-674f-440b-9cad-a2fc99a355ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446234873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.446234873
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.3553176020
Short name T996
Test name
Test status
Simulation time 13188924613 ps
CPU time 67.46 seconds
Started Jul 28 07:19:47 PM PDT 24
Finished Jul 28 07:20:55 PM PDT 24
Peak memory 225508 kb
Host smart-680a34e6-c051-47f4-b311-de1f0f61a7a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553176020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.3553176020
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.2731164444
Short name T746
Test name
Test status
Simulation time 24857731 ps
CPU time 1.08 seconds
Started Jul 28 07:19:46 PM PDT 24
Finished Jul 28 07:19:47 PM PDT 24
Peak memory 217400 kb
Host smart-8cf8e32f-b2e5-4262-ba1a-27901560ac14
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731164444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.spi_device_mem_parity.2731164444
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.643864409
Short name T999
Test name
Test status
Simulation time 8243570799 ps
CPU time 8.96 seconds
Started Jul 28 07:19:50 PM PDT 24
Finished Jul 28 07:19:59 PM PDT 24
Peak memory 225476 kb
Host smart-7515e2f1-eba0-4d0f-b59d-7703040f8b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643864409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swap
.643864409
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.4230957650
Short name T904
Test name
Test status
Simulation time 1639101783 ps
CPU time 2.82 seconds
Started Jul 28 07:19:47 PM PDT 24
Finished Jul 28 07:19:50 PM PDT 24
Peak memory 225412 kb
Host smart-2b681048-9348-4c24-8a80-518dbc561c3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230957650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.4230957650
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.13293938
Short name T666
Test name
Test status
Simulation time 4136443751 ps
CPU time 12.16 seconds
Started Jul 28 07:19:46 PM PDT 24
Finished Jul 28 07:19:59 PM PDT 24
Peak memory 224076 kb
Host smart-2ebdf219-0674-4472-a8dd-bf0eec13e29d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=13293938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_direc
t.13293938
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.2160178740
Short name T498
Test name
Test status
Simulation time 5460914039 ps
CPU time 27.78 seconds
Started Jul 28 07:19:47 PM PDT 24
Finished Jul 28 07:20:15 PM PDT 24
Peak memory 217244 kb
Host smart-7c486dcc-5d55-42ad-8d1b-167351e0468a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160178740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.2160178740
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.1856827356
Short name T767
Test name
Test status
Simulation time 2008715888 ps
CPU time 1.81 seconds
Started Jul 28 07:19:47 PM PDT 24
Finished Jul 28 07:19:49 PM PDT 24
Peak memory 208656 kb
Host smart-2d38546e-3e30-4804-95f7-def7c93bc87f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856827356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.1856827356
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.2236058260
Short name T738
Test name
Test status
Simulation time 113912782 ps
CPU time 4.12 seconds
Started Jul 28 07:19:46 PM PDT 24
Finished Jul 28 07:19:51 PM PDT 24
Peak memory 217156 kb
Host smart-3f8b4fbe-ca0c-43d7-9dfe-97caeda01926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236058260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.2236058260
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.682923241
Short name T437
Test name
Test status
Simulation time 33248295 ps
CPU time 0.77 seconds
Started Jul 28 07:19:44 PM PDT 24
Finished Jul 28 07:19:45 PM PDT 24
Peak memory 206916 kb
Host smart-c9a3a10d-7197-4381-9216-9798c1134bc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682923241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.682923241
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.3577534143
Short name T672
Test name
Test status
Simulation time 1114933159 ps
CPU time 5.59 seconds
Started Jul 28 07:19:46 PM PDT 24
Finished Jul 28 07:19:52 PM PDT 24
Peak memory 233580 kb
Host smart-1cd0a294-b2bd-4f36-963b-8deddc719ca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577534143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.3577534143
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.2384991153
Short name T794
Test name
Test status
Simulation time 32656356 ps
CPU time 0.73 seconds
Started Jul 28 07:18:22 PM PDT 24
Finished Jul 28 07:18:23 PM PDT 24
Peak memory 205488 kb
Host smart-54c80114-cc8e-44e6-b7c3-9d008cba36cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384991153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.2
384991153
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.1048254487
Short name T919
Test name
Test status
Simulation time 484111493 ps
CPU time 2.53 seconds
Started Jul 28 07:18:18 PM PDT 24
Finished Jul 28 07:18:21 PM PDT 24
Peak memory 225420 kb
Host smart-a94f9baa-6ff5-49d7-bfa1-4148b1456987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048254487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.1048254487
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.1487917132
Short name T865
Test name
Test status
Simulation time 16740189 ps
CPU time 0.82 seconds
Started Jul 28 07:18:19 PM PDT 24
Finished Jul 28 07:18:20 PM PDT 24
Peak memory 206268 kb
Host smart-6f8a1641-33b1-4a8d-a5b5-6d58f5b25bd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487917132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.1487917132
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.3505552364
Short name T709
Test name
Test status
Simulation time 84763307488 ps
CPU time 214.5 seconds
Started Jul 28 07:18:23 PM PDT 24
Finished Jul 28 07:21:57 PM PDT 24
Peak memory 257552 kb
Host smart-a2d87efd-ce8e-4b9f-b7ca-4719beb26f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505552364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.3505552364
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.36907025
Short name T331
Test name
Test status
Simulation time 1215771171 ps
CPU time 10.06 seconds
Started Jul 28 07:18:24 PM PDT 24
Finished Jul 28 07:18:34 PM PDT 24
Peak memory 218688 kb
Host smart-dc0ba265-b5ae-4a2c-8fb0-757682b3443b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36907025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle.36907025
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.2091150450
Short name T928
Test name
Test status
Simulation time 216232714 ps
CPU time 4.53 seconds
Started Jul 28 07:18:24 PM PDT 24
Finished Jul 28 07:18:28 PM PDT 24
Peak memory 225448 kb
Host smart-f4a546d2-069b-4561-bb6e-d2d4db255954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091150450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.2091150450
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.111886319
Short name T936
Test name
Test status
Simulation time 315648651432 ps
CPU time 129.53 seconds
Started Jul 28 07:18:21 PM PDT 24
Finished Jul 28 07:20:31 PM PDT 24
Peak memory 254716 kb
Host smart-053c281b-33bc-4367-aad5-7de17f880877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111886319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds.
111886319
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_intercept.2412203252
Short name T856
Test name
Test status
Simulation time 3258364617 ps
CPU time 22.17 seconds
Started Jul 28 07:18:21 PM PDT 24
Finished Jul 28 07:18:44 PM PDT 24
Peak memory 225468 kb
Host smart-8cff691a-243b-4d71-9637-6ac06b822bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412203252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.2412203252
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.1398808032
Short name T685
Test name
Test status
Simulation time 9276010480 ps
CPU time 30.84 seconds
Started Jul 28 07:18:18 PM PDT 24
Finished Jul 28 07:18:49 PM PDT 24
Peak memory 241896 kb
Host smart-8b44586c-f1dd-433f-97eb-6caf05650c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398808032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.1398808032
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.1131173318
Short name T444
Test name
Test status
Simulation time 58339368 ps
CPU time 1.02 seconds
Started Jul 28 07:18:18 PM PDT 24
Finished Jul 28 07:18:19 PM PDT 24
Peak memory 218664 kb
Host smart-a4a1e2dd-29e2-4746-9539-76c969edcf39
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131173318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.spi_device_mem_parity.1131173318
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.1889765678
Short name T613
Test name
Test status
Simulation time 10320773022 ps
CPU time 16.6 seconds
Started Jul 28 07:18:21 PM PDT 24
Finished Jul 28 07:18:38 PM PDT 24
Peak memory 241168 kb
Host smart-0aa1f1a9-a6b9-44e6-9f4f-2587d730269c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889765678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.1889765678
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.1227304576
Short name T910
Test name
Test status
Simulation time 7151218454 ps
CPU time 11.67 seconds
Started Jul 28 07:18:18 PM PDT 24
Finished Jul 28 07:18:30 PM PDT 24
Peak memory 225468 kb
Host smart-39c99c3b-265a-43a9-8886-163c48013cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227304576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.1227304576
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.1187187729
Short name T713
Test name
Test status
Simulation time 432933245 ps
CPU time 3.64 seconds
Started Jul 28 07:18:23 PM PDT 24
Finished Jul 28 07:18:27 PM PDT 24
Peak memory 219728 kb
Host smart-61d097c1-c00d-498f-83ab-5b5babdf0882
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1187187729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.1187187729
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.1059846995
Short name T15
Test name
Test status
Simulation time 10342718208 ps
CPU time 138.19 seconds
Started Jul 28 07:18:23 PM PDT 24
Finished Jul 28 07:20:41 PM PDT 24
Peak memory 258352 kb
Host smart-6c408072-637a-4106-ac6d-f1a7cabb2088
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059846995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.1059846995
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.3158300461
Short name T176
Test name
Test status
Simulation time 2570954028 ps
CPU time 15.22 seconds
Started Jul 28 07:18:21 PM PDT 24
Finished Jul 28 07:18:37 PM PDT 24
Peak memory 217236 kb
Host smart-3d9d9660-a1f3-4e5b-96d8-0d4478477240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158300461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.3158300461
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.1436718911
Short name T983
Test name
Test status
Simulation time 41556660772 ps
CPU time 14.55 seconds
Started Jul 28 07:18:19 PM PDT 24
Finished Jul 28 07:18:34 PM PDT 24
Peak memory 217168 kb
Host smart-0e313f16-e1fe-4549-bf05-84825d2cb91e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436718911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.1436718911
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.1109760205
Short name T385
Test name
Test status
Simulation time 290685199 ps
CPU time 1.56 seconds
Started Jul 28 07:18:18 PM PDT 24
Finished Jul 28 07:18:19 PM PDT 24
Peak memory 217140 kb
Host smart-c06a93c7-3e4c-4058-a4ae-e0c56f69f3dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109760205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.1109760205
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.114640831
Short name T32
Test name
Test status
Simulation time 79630937 ps
CPU time 0.8 seconds
Started Jul 28 07:18:21 PM PDT 24
Finished Jul 28 07:18:22 PM PDT 24
Peak memory 206760 kb
Host smart-378ab3d8-648c-487c-ad98-0ad676777309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114640831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.114640831
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.2687071421
Short name T197
Test name
Test status
Simulation time 1112762400 ps
CPU time 9.24 seconds
Started Jul 28 07:18:17 PM PDT 24
Finished Jul 28 07:18:26 PM PDT 24
Peak memory 240016 kb
Host smart-f4fce3b8-b618-4b3e-84a1-cb19b9de9d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687071421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.2687071421
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.1694071856
Short name T924
Test name
Test status
Simulation time 13247249 ps
CPU time 0.72 seconds
Started Jul 28 07:19:58 PM PDT 24
Finished Jul 28 07:19:59 PM PDT 24
Peak memory 206404 kb
Host smart-a22db208-c9b2-41b1-88ce-50413a14ccaf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694071856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
1694071856
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.61622709
Short name T803
Test name
Test status
Simulation time 2017840249 ps
CPU time 7.53 seconds
Started Jul 28 07:19:53 PM PDT 24
Finished Jul 28 07:20:00 PM PDT 24
Peak memory 233596 kb
Host smart-4b4f163a-008f-417c-a264-443d2e69616e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61622709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.61622709
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.4221540416
Short name T480
Test name
Test status
Simulation time 48605866 ps
CPU time 0.76 seconds
Started Jul 28 07:19:51 PM PDT 24
Finished Jul 28 07:19:52 PM PDT 24
Peak memory 207308 kb
Host smart-4e499817-20e7-4b43-90f6-d2211164ee14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221540416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.4221540416
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.3348503741
Short name T220
Test name
Test status
Simulation time 17940414270 ps
CPU time 69.99 seconds
Started Jul 28 07:19:56 PM PDT 24
Finished Jul 28 07:21:07 PM PDT 24
Peak memory 255568 kb
Host smart-fc3abef7-3a26-4262-86a4-17e8c3acc40b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348503741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.3348503741
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.82555277
Short name T288
Test name
Test status
Simulation time 4605462017 ps
CPU time 90.8 seconds
Started Jul 28 07:20:00 PM PDT 24
Finished Jul 28 07:21:30 PM PDT 24
Peak memory 257900 kb
Host smart-86b28937-5623-41c1-8008-5ef4332a13ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82555277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.82555277
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.1708760943
Short name T361
Test name
Test status
Simulation time 14292975219 ps
CPU time 73.37 seconds
Started Jul 28 07:19:58 PM PDT 24
Finished Jul 28 07:21:11 PM PDT 24
Peak memory 253720 kb
Host smart-2bf07945-1c60-47a2-a891-a2b7a366892d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708760943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.1708760943
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.2743087977
Short name T344
Test name
Test status
Simulation time 212699039 ps
CPU time 4.87 seconds
Started Jul 28 07:19:51 PM PDT 24
Finished Jul 28 07:19:56 PM PDT 24
Peak memory 225484 kb
Host smart-2cd12bfe-9496-42cc-8ad7-c9dad9a60b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743087977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.2743087977
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.3137496234
Short name T99
Test name
Test status
Simulation time 1781756642 ps
CPU time 17.98 seconds
Started Jul 28 07:19:53 PM PDT 24
Finished Jul 28 07:20:11 PM PDT 24
Peak memory 241888 kb
Host smart-caaa5615-7a90-4294-bcda-98a9f2fc9629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137496234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmd
s.3137496234
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/20.spi_device_intercept.1118245010
Short name T248
Test name
Test status
Simulation time 60534204 ps
CPU time 2.99 seconds
Started Jul 28 07:19:52 PM PDT 24
Finished Jul 28 07:19:55 PM PDT 24
Peak memory 225428 kb
Host smart-efb85dd8-1ad0-4a47-9fa3-5eab94649a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118245010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.1118245010
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.1795947764
Short name T1007
Test name
Test status
Simulation time 1907061454 ps
CPU time 14.32 seconds
Started Jul 28 07:19:51 PM PDT 24
Finished Jul 28 07:20:05 PM PDT 24
Peak memory 249928 kb
Host smart-b63e628a-b61b-4104-8115-16156989f84d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795947764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.1795947764
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.51462443
Short name T565
Test name
Test status
Simulation time 468650835 ps
CPU time 5.19 seconds
Started Jul 28 07:19:47 PM PDT 24
Finished Jul 28 07:19:53 PM PDT 24
Peak memory 233588 kb
Host smart-780b6e45-cba9-4144-bd67-5da494ad548a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51462443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swap.51462443
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.1313517020
Short name T257
Test name
Test status
Simulation time 21118635135 ps
CPU time 8.55 seconds
Started Jul 28 07:19:51 PM PDT 24
Finished Jul 28 07:20:00 PM PDT 24
Peak memory 225472 kb
Host smart-0f1b3b84-050e-40ab-9c26-abc56e654797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313517020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.1313517020
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.1840843835
Short name T603
Test name
Test status
Simulation time 863071121 ps
CPU time 4.69 seconds
Started Jul 28 07:19:54 PM PDT 24
Finished Jul 28 07:19:58 PM PDT 24
Peak memory 223784 kb
Host smart-6b095ea0-c3da-4ffc-8703-bfe6f5c12b2e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1840843835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.1840843835
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.376154299
Short name T508
Test name
Test status
Simulation time 298809604 ps
CPU time 1.02 seconds
Started Jul 28 07:19:57 PM PDT 24
Finished Jul 28 07:19:58 PM PDT 24
Peak memory 207772 kb
Host smart-db0dd6f8-9178-474b-9cea-0e3ee28b3348
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376154299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stres
s_all.376154299
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.3826087932
Short name T982
Test name
Test status
Simulation time 3760034015 ps
CPU time 21.11 seconds
Started Jul 28 07:19:52 PM PDT 24
Finished Jul 28 07:20:13 PM PDT 24
Peak memory 217344 kb
Host smart-a6e71221-12cd-438b-8f03-535fccd62b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826087932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.3826087932
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.942167596
Short name T570
Test name
Test status
Simulation time 11360721809 ps
CPU time 15.26 seconds
Started Jul 28 07:19:50 PM PDT 24
Finished Jul 28 07:20:05 PM PDT 24
Peak memory 217204 kb
Host smart-7e72b853-3d19-437d-bc61-dc1c1a6d4342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942167596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.942167596
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.644870131
Short name T422
Test name
Test status
Simulation time 59904258 ps
CPU time 1.62 seconds
Started Jul 28 07:19:52 PM PDT 24
Finished Jul 28 07:19:53 PM PDT 24
Peak memory 217168 kb
Host smart-b354e948-f857-464f-804a-cba599e93601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644870131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.644870131
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.2566133191
Short name T172
Test name
Test status
Simulation time 81343742 ps
CPU time 0.88 seconds
Started Jul 28 07:19:52 PM PDT 24
Finished Jul 28 07:19:53 PM PDT 24
Peak memory 206796 kb
Host smart-d23db5e7-1577-41cf-b895-ca4f7e5a27bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566133191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.2566133191
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.1023273133
Short name T893
Test name
Test status
Simulation time 1464814239 ps
CPU time 2.95 seconds
Started Jul 28 07:19:52 PM PDT 24
Finished Jul 28 07:19:55 PM PDT 24
Peak memory 225452 kb
Host smart-1f553a5a-0ea7-4155-b2ba-262cc3c3428b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023273133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.1023273133
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.3290694401
Short name T820
Test name
Test status
Simulation time 44931133 ps
CPU time 0.76 seconds
Started Jul 28 07:20:02 PM PDT 24
Finished Jul 28 07:20:03 PM PDT 24
Peak memory 206056 kb
Host smart-bc8fc2be-42c5-4877-bc75-fffd6dea8cd8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290694401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
3290694401
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.379808946
Short name T97
Test name
Test status
Simulation time 294045841 ps
CPU time 4.78 seconds
Started Jul 28 07:19:56 PM PDT 24
Finished Jul 28 07:20:01 PM PDT 24
Peak memory 225440 kb
Host smart-595f2c1b-f94d-45d0-87b3-2001b734569d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379808946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.379808946
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.3871805977
Short name T338
Test name
Test status
Simulation time 46636069 ps
CPU time 0.78 seconds
Started Jul 28 07:19:55 PM PDT 24
Finished Jul 28 07:19:56 PM PDT 24
Peak memory 207288 kb
Host smart-cbe28436-ee1f-4e1b-ae2e-1a253b168bd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871805977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.3871805977
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.1632088672
Short name T591
Test name
Test status
Simulation time 13356639209 ps
CPU time 106.98 seconds
Started Jul 28 07:19:57 PM PDT 24
Finished Jul 28 07:21:44 PM PDT 24
Peak memory 253568 kb
Host smart-4b160323-ae36-4273-afb2-407acdd0af77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632088672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.1632088672
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.917577462
Short name T268
Test name
Test status
Simulation time 173360180531 ps
CPU time 434.31 seconds
Started Jul 28 07:20:01 PM PDT 24
Finished Jul 28 07:27:15 PM PDT 24
Peak memory 264876 kb
Host smart-2f6d31da-1862-495d-9a3f-4c356f935b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917577462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.917577462
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.2941963576
Short name T764
Test name
Test status
Simulation time 10713553895 ps
CPU time 86.31 seconds
Started Jul 28 07:20:01 PM PDT 24
Finished Jul 28 07:21:27 PM PDT 24
Peak memory 258404 kb
Host smart-5c9a7bdd-2a6e-4819-ba34-44c130bb0f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941963576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.2941963576
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.2113022629
Short name T339
Test name
Test status
Simulation time 189301220 ps
CPU time 2.95 seconds
Started Jul 28 07:19:57 PM PDT 24
Finished Jul 28 07:20:00 PM PDT 24
Peak memory 233632 kb
Host smart-311f4860-4777-4f9e-868d-bf4a12ec8fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113022629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.2113022629
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.416141327
Short name T72
Test name
Test status
Simulation time 40709175577 ps
CPU time 140.8 seconds
Started Jul 28 07:20:01 PM PDT 24
Finished Jul 28 07:22:22 PM PDT 24
Peak memory 257104 kb
Host smart-2c6635f2-de97-4b09-86a3-f56a535fad53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416141327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmds
.416141327
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_intercept.161642632
Short name T218
Test name
Test status
Simulation time 5330686596 ps
CPU time 13.93 seconds
Started Jul 28 07:19:57 PM PDT 24
Finished Jul 28 07:20:11 PM PDT 24
Peak memory 233676 kb
Host smart-38397c04-da0e-46aa-9ed3-45277c5f8f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161642632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.161642632
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.2599172353
Short name T471
Test name
Test status
Simulation time 2038435664 ps
CPU time 13.72 seconds
Started Jul 28 07:19:55 PM PDT 24
Finished Jul 28 07:20:09 PM PDT 24
Peak memory 233716 kb
Host smart-a0e26f5e-dcc9-4ff9-a3f0-5bd6f1d52f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599172353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.2599172353
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.363098282
Short name T576
Test name
Test status
Simulation time 5410060515 ps
CPU time 9.53 seconds
Started Jul 28 07:20:02 PM PDT 24
Finished Jul 28 07:20:12 PM PDT 24
Peak memory 233596 kb
Host smart-984d6ee0-b45c-4c20-b081-a0255ea7351d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363098282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swap
.363098282
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.3158239451
Short name T849
Test name
Test status
Simulation time 142807989 ps
CPU time 2.19 seconds
Started Jul 28 07:19:57 PM PDT 24
Finished Jul 28 07:19:59 PM PDT 24
Peak memory 223952 kb
Host smart-66395567-fc18-4550-a187-1b1529b3bb12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158239451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.3158239451
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.2234287737
Short name T861
Test name
Test status
Simulation time 725441390 ps
CPU time 6.95 seconds
Started Jul 28 07:19:57 PM PDT 24
Finished Jul 28 07:20:04 PM PDT 24
Peak memory 222784 kb
Host smart-520b8a74-9fc3-4030-af76-92b0eb502482
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2234287737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.2234287737
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.3588978259
Short name T386
Test name
Test status
Simulation time 14566228174 ps
CPU time 30.09 seconds
Started Jul 28 07:20:01 PM PDT 24
Finished Jul 28 07:20:31 PM PDT 24
Peak memory 238052 kb
Host smart-e6813d84-46af-4a92-b5e8-b556af5287d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588978259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.3588978259
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.1393882737
Short name T326
Test name
Test status
Simulation time 6597856462 ps
CPU time 35.92 seconds
Started Jul 28 07:19:58 PM PDT 24
Finished Jul 28 07:20:34 PM PDT 24
Peak memory 217256 kb
Host smart-e5cac8a4-a1e8-4487-8f6a-056ecc1eeb36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393882737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.1393882737
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.1055023287
Short name T564
Test name
Test status
Simulation time 620867595 ps
CPU time 2.44 seconds
Started Jul 28 07:20:02 PM PDT 24
Finished Jul 28 07:20:04 PM PDT 24
Peak memory 217172 kb
Host smart-05400877-07be-4f2b-b758-34575d181bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055023287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.1055023287
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.2693461714
Short name T699
Test name
Test status
Simulation time 161817432 ps
CPU time 6.97 seconds
Started Jul 28 07:19:57 PM PDT 24
Finished Jul 28 07:20:04 PM PDT 24
Peak memory 217144 kb
Host smart-7cf7c3b3-52b4-4d0e-9397-515269465940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693461714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.2693461714
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.2977244527
Short name T544
Test name
Test status
Simulation time 50276007 ps
CPU time 0.79 seconds
Started Jul 28 07:19:55 PM PDT 24
Finished Jul 28 07:19:56 PM PDT 24
Peak memory 206712 kb
Host smart-82925ae6-3d79-48ae-bb86-cfa1b71477bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977244527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.2977244527
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.2683590187
Short name T286
Test name
Test status
Simulation time 735542003 ps
CPU time 2.42 seconds
Started Jul 28 07:19:56 PM PDT 24
Finished Jul 28 07:19:58 PM PDT 24
Peak memory 233604 kb
Host smart-604a166d-612d-4d6a-8837-1a790872f6b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683590187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.2683590187
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.147314464
Short name T784
Test name
Test status
Simulation time 137913293 ps
CPU time 0.75 seconds
Started Jul 28 07:20:03 PM PDT 24
Finished Jul 28 07:20:04 PM PDT 24
Peak memory 205528 kb
Host smart-6db186e2-831a-4469-8226-4909060b8d81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147314464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.147314464
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.2770248978
Short name T887
Test name
Test status
Simulation time 508013601 ps
CPU time 3.37 seconds
Started Jul 28 07:19:59 PM PDT 24
Finished Jul 28 07:20:03 PM PDT 24
Peak memory 233580 kb
Host smart-301b88a3-9d53-4425-a6f1-167616eb440a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770248978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.2770248978
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.535475930
Short name T959
Test name
Test status
Simulation time 201063068 ps
CPU time 0.81 seconds
Started Jul 28 07:19:59 PM PDT 24
Finished Jul 28 07:20:00 PM PDT 24
Peak memory 207304 kb
Host smart-39928b03-463f-4f5c-87ed-f70a328954c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535475930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.535475930
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.4043413851
Short name T494
Test name
Test status
Simulation time 4355993300 ps
CPU time 20.66 seconds
Started Jul 28 07:20:01 PM PDT 24
Finished Jul 28 07:20:22 PM PDT 24
Peak memory 241996 kb
Host smart-ad1f0ea3-58cc-4416-b7bc-89b4556f82f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043413851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.4043413851
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.1371645549
Short name T932
Test name
Test status
Simulation time 26959640969 ps
CPU time 134.24 seconds
Started Jul 28 07:20:04 PM PDT 24
Finished Jul 28 07:22:18 PM PDT 24
Peak memory 257464 kb
Host smart-869c98e5-4bba-4d83-ac86-2c4fd2266675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371645549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.1371645549
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.1516842604
Short name T320
Test name
Test status
Simulation time 643536863 ps
CPU time 12.59 seconds
Started Jul 28 07:20:03 PM PDT 24
Finished Jul 28 07:20:16 PM PDT 24
Peak memory 241792 kb
Host smart-4effda4c-002b-46c7-a609-ecb444ea0a11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516842604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.1516842604
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.4155250841
Short name T1012
Test name
Test status
Simulation time 9333079750 ps
CPU time 132.44 seconds
Started Jul 28 07:19:59 PM PDT 24
Finished Jul 28 07:22:11 PM PDT 24
Peak memory 262732 kb
Host smart-16836736-d37f-46c9-bbd5-57845b8980d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155250841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmd
s.4155250841
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_intercept.4069080049
Short name T688
Test name
Test status
Simulation time 1285242460 ps
CPU time 12.35 seconds
Started Jul 28 07:19:59 PM PDT 24
Finished Jul 28 07:20:11 PM PDT 24
Peak memory 233548 kb
Host smart-55213db4-397a-461f-ab0f-a751d7246570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069080049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.4069080049
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.3842519329
Short name T790
Test name
Test status
Simulation time 16028661563 ps
CPU time 82.99 seconds
Started Jul 28 07:20:03 PM PDT 24
Finished Jul 28 07:21:26 PM PDT 24
Peak memory 241668 kb
Host smart-36217da0-56b6-4696-a305-f3a7c6725e38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842519329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.3842519329
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.1258577215
Short name T51
Test name
Test status
Simulation time 7489142054 ps
CPU time 10.39 seconds
Started Jul 28 07:20:00 PM PDT 24
Finished Jul 28 07:20:11 PM PDT 24
Peak memory 233684 kb
Host smart-a901b69f-c0a5-4e76-b28f-d955c3dafd9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258577215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.1258577215
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.1981174910
Short name T859
Test name
Test status
Simulation time 6338854837 ps
CPU time 24.64 seconds
Started Jul 28 07:20:03 PM PDT 24
Finished Jul 28 07:20:28 PM PDT 24
Peak memory 241296 kb
Host smart-e6ccb868-376c-48d2-a9f3-c947788cd587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981174910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.1981174910
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.1022609561
Short name T862
Test name
Test status
Simulation time 1989216991 ps
CPU time 22.8 seconds
Started Jul 28 07:20:00 PM PDT 24
Finished Jul 28 07:20:23 PM PDT 24
Peak memory 222896 kb
Host smart-fbea3f85-8c97-4164-bc57-07ad0edfb7c0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1022609561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.1022609561
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.3866611724
Short name T948
Test name
Test status
Simulation time 3653639322 ps
CPU time 29.07 seconds
Started Jul 28 07:20:04 PM PDT 24
Finished Jul 28 07:20:33 PM PDT 24
Peak memory 217192 kb
Host smart-7ef75d1c-8059-4cd4-9f3f-3d5c80b4d487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866611724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.3866611724
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.4161379235
Short name T343
Test name
Test status
Simulation time 16037040923 ps
CPU time 23.11 seconds
Started Jul 28 07:20:00 PM PDT 24
Finished Jul 28 07:20:23 PM PDT 24
Peak memory 217272 kb
Host smart-659e460e-bbe5-430f-b557-5525119aa821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161379235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.4161379235
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.1132031862
Short name T535
Test name
Test status
Simulation time 28299688 ps
CPU time 0.69 seconds
Started Jul 28 07:20:03 PM PDT 24
Finished Jul 28 07:20:04 PM PDT 24
Peak memory 206276 kb
Host smart-a55b7463-bf8d-4b92-872c-824ec8cd99c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132031862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.1132031862
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.923962461
Short name T536
Test name
Test status
Simulation time 116918471 ps
CPU time 0.83 seconds
Started Jul 28 07:20:03 PM PDT 24
Finished Jul 28 07:20:04 PM PDT 24
Peak memory 206740 kb
Host smart-9f38ca1f-7a7b-4ea6-a2fe-1f8d97dc517a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923962461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.923962461
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.3410647452
Short name T559
Test name
Test status
Simulation time 12000611168 ps
CPU time 13.58 seconds
Started Jul 28 07:20:00 PM PDT 24
Finished Jul 28 07:20:13 PM PDT 24
Peak memory 233764 kb
Host smart-b85a2648-87ac-49cc-b13a-27b7caa78ccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410647452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.3410647452
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.1653595752
Short name T354
Test name
Test status
Simulation time 30470899 ps
CPU time 0.74 seconds
Started Jul 28 07:20:11 PM PDT 24
Finished Jul 28 07:20:12 PM PDT 24
Peak memory 206044 kb
Host smart-0dc8a0e9-296b-41d6-a11f-8658e5b32389
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653595752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
1653595752
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.1889858699
Short name T47
Test name
Test status
Simulation time 780048770 ps
CPU time 4.27 seconds
Started Jul 28 07:20:03 PM PDT 24
Finished Jul 28 07:20:08 PM PDT 24
Peak memory 225500 kb
Host smart-17e1c7ee-b3cf-4f7c-83b1-1182e9f62231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889858699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.1889858699
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.212098655
Short name T587
Test name
Test status
Simulation time 16152409 ps
CPU time 0.79 seconds
Started Jul 28 07:20:05 PM PDT 24
Finished Jul 28 07:20:06 PM PDT 24
Peak memory 206552 kb
Host smart-408f6980-c321-400f-b86a-fdb8a8d2db59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212098655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.212098655
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.576919168
Short name T952
Test name
Test status
Simulation time 21144880 ps
CPU time 0.74 seconds
Started Jul 28 07:20:05 PM PDT 24
Finished Jul 28 07:20:06 PM PDT 24
Peak memory 216644 kb
Host smart-815be684-9fbb-47ef-9032-c017839c08b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576919168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.576919168
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.1683205020
Short name T833
Test name
Test status
Simulation time 43382922265 ps
CPU time 67.62 seconds
Started Jul 28 07:20:00 PM PDT 24
Finished Jul 28 07:21:08 PM PDT 24
Peak memory 250468 kb
Host smart-bf002042-ba89-4d79-8674-c65f7b5c2915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683205020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.1683205020
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.3732932391
Short name T974
Test name
Test status
Simulation time 91873072125 ps
CPU time 466.91 seconds
Started Jul 28 07:20:05 PM PDT 24
Finished Jul 28 07:27:52 PM PDT 24
Peak memory 264752 kb
Host smart-fff7a72e-a007-4a22-abcf-b666bfef6949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732932391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.3732932391
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.3507814773
Short name T648
Test name
Test status
Simulation time 182541999 ps
CPU time 3.97 seconds
Started Jul 28 07:20:05 PM PDT 24
Finished Jul 28 07:20:09 PM PDT 24
Peak memory 225492 kb
Host smart-ac07450d-0e2a-4d99-b667-4ff4ab153eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507814773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.3507814773
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.3287222028
Short name T839
Test name
Test status
Simulation time 17686391291 ps
CPU time 167.53 seconds
Started Jul 28 07:20:02 PM PDT 24
Finished Jul 28 07:22:50 PM PDT 24
Peak memory 253840 kb
Host smart-1bbc9f09-e1b7-47e1-858b-45437895c7ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287222028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmd
s.3287222028
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/23.spi_device_intercept.2306063164
Short name T845
Test name
Test status
Simulation time 1170175691 ps
CPU time 14.17 seconds
Started Jul 28 07:20:12 PM PDT 24
Finished Jul 28 07:20:26 PM PDT 24
Peak memory 225436 kb
Host smart-bbd7f72d-e8f3-4b22-944f-78bbd56ba49a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306063164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.2306063164
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.1217529710
Short name T279
Test name
Test status
Simulation time 1260836728 ps
CPU time 6.87 seconds
Started Jul 28 07:20:04 PM PDT 24
Finished Jul 28 07:20:11 PM PDT 24
Peak memory 233608 kb
Host smart-07f198f5-580a-437e-a53e-9e8489304f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217529710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.1217529710
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.3907564886
Short name T243
Test name
Test status
Simulation time 1441444946 ps
CPU time 9.25 seconds
Started Jul 28 07:20:05 PM PDT 24
Finished Jul 28 07:20:14 PM PDT 24
Peak memory 225440 kb
Host smart-4bd8e205-a3ca-48d1-9f19-00bed7f442df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907564886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.3907564886
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.1396740766
Short name T629
Test name
Test status
Simulation time 1152151764 ps
CPU time 3.57 seconds
Started Jul 28 07:20:07 PM PDT 24
Finished Jul 28 07:20:11 PM PDT 24
Peak memory 225460 kb
Host smart-cc3b323e-2afa-49b4-ab84-3b5729d6a963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396740766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.1396740766
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.947838461
Short name T687
Test name
Test status
Simulation time 5296205411 ps
CPU time 15.23 seconds
Started Jul 28 07:20:07 PM PDT 24
Finished Jul 28 07:20:22 PM PDT 24
Peak memory 221048 kb
Host smart-3134cf75-9b94-4c85-aded-ee92aaf89fd6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=947838461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dire
ct.947838461
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.4070931802
Short name T301
Test name
Test status
Simulation time 117967016338 ps
CPU time 622.59 seconds
Started Jul 28 07:20:13 PM PDT 24
Finished Jul 28 07:30:36 PM PDT 24
Peak memory 289724 kb
Host smart-260a506c-7e08-41a1-94f6-23956eb1c20b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070931802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.4070931802
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.3556717497
Short name T740
Test name
Test status
Simulation time 9771441539 ps
CPU time 18.01 seconds
Started Jul 28 07:20:04 PM PDT 24
Finished Jul 28 07:20:22 PM PDT 24
Peak memory 217232 kb
Host smart-23937736-04dd-445a-8e5e-037932d5b1d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556717497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.3556717497
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.3970929607
Short name T31
Test name
Test status
Simulation time 3250285276 ps
CPU time 10.43 seconds
Started Jul 28 07:20:08 PM PDT 24
Finished Jul 28 07:20:19 PM PDT 24
Peak memory 217248 kb
Host smart-72bd6a9f-f1f4-460f-a98b-1042695aeae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970929607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.3970929607
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.1698340522
Short name T143
Test name
Test status
Simulation time 13888315 ps
CPU time 0.83 seconds
Started Jul 28 07:20:03 PM PDT 24
Finished Jul 28 07:20:04 PM PDT 24
Peak memory 207796 kb
Host smart-3fecd112-d1d5-4a44-84cd-b6b3ab79ac80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698340522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.1698340522
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.2246431772
Short name T943
Test name
Test status
Simulation time 73251851 ps
CPU time 0.8 seconds
Started Jul 28 07:20:03 PM PDT 24
Finished Jul 28 07:20:04 PM PDT 24
Peak memory 206684 kb
Host smart-d2950794-eac1-45b4-8306-8456826daebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246431772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.2246431772
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.612427879
Short name T723
Test name
Test status
Simulation time 5152396723 ps
CPU time 7.25 seconds
Started Jul 28 07:20:05 PM PDT 24
Finished Jul 28 07:20:12 PM PDT 24
Peak memory 225492 kb
Host smart-bdd48672-46e5-46d7-a5c5-7a15fda66872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612427879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.612427879
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.3738184979
Short name T694
Test name
Test status
Simulation time 49083445 ps
CPU time 0.74 seconds
Started Jul 28 07:20:15 PM PDT 24
Finished Jul 28 07:20:16 PM PDT 24
Peak memory 206372 kb
Host smart-7c603716-1dc2-4865-8928-9c5aac1d2c3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738184979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
3738184979
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.407103220
Short name T898
Test name
Test status
Simulation time 172474334 ps
CPU time 2.59 seconds
Started Jul 28 07:20:09 PM PDT 24
Finished Jul 28 07:20:12 PM PDT 24
Peak memory 225384 kb
Host smart-a8ff15ac-8b24-48e0-b005-5f50c1ae2f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407103220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.407103220
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.1549890591
Short name T951
Test name
Test status
Simulation time 27050249 ps
CPU time 0.78 seconds
Started Jul 28 07:20:14 PM PDT 24
Finished Jul 28 07:20:16 PM PDT 24
Peak memory 207244 kb
Host smart-a937518a-6968-493a-a9e2-9cc59be0ac3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549890591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.1549890591
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.1330662870
Short name T69
Test name
Test status
Simulation time 4667503248 ps
CPU time 24.53 seconds
Started Jul 28 07:20:10 PM PDT 24
Finished Jul 28 07:20:36 PM PDT 24
Peak memory 218492 kb
Host smart-adf20866-de4a-4e2e-9015-b5b2afe79bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330662870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.1330662870
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.4163059563
Short name T969
Test name
Test status
Simulation time 13432505673 ps
CPU time 149.25 seconds
Started Jul 28 07:20:12 PM PDT 24
Finished Jul 28 07:22:41 PM PDT 24
Peak memory 256360 kb
Host smart-b9f390ed-5448-44c0-a4af-68ff789e1fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163059563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.4163059563
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.1290749852
Short name T7
Test name
Test status
Simulation time 788702153 ps
CPU time 3.55 seconds
Started Jul 28 07:20:12 PM PDT 24
Finished Jul 28 07:20:15 PM PDT 24
Peak memory 233616 kb
Host smart-fbf9e008-8854-46f9-a597-4bc97372029a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290749852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.1290749852
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.3742501568
Short name T293
Test name
Test status
Simulation time 5475320763 ps
CPU time 40.45 seconds
Started Jul 28 07:20:09 PM PDT 24
Finished Jul 28 07:20:50 PM PDT 24
Peak memory 255364 kb
Host smart-6baac474-1ae7-4d8f-9aa6-b005f759a7f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742501568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmd
s.3742501568
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/24.spi_device_intercept.190814537
Short name T1021
Test name
Test status
Simulation time 1582722954 ps
CPU time 4.37 seconds
Started Jul 28 07:20:10 PM PDT 24
Finished Jul 28 07:20:14 PM PDT 24
Peak memory 225356 kb
Host smart-52df037e-7b45-402e-8318-f61bb522830d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190814537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.190814537
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.3958474037
Short name T656
Test name
Test status
Simulation time 4351693802 ps
CPU time 21.07 seconds
Started Jul 28 07:20:14 PM PDT 24
Finished Jul 28 07:20:36 PM PDT 24
Peak memory 233644 kb
Host smart-377925cc-6187-497c-8db4-15648d4e799b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958474037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.3958474037
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.2120806388
Short name T902
Test name
Test status
Simulation time 912185562 ps
CPU time 3.81 seconds
Started Jul 28 07:20:15 PM PDT 24
Finished Jul 28 07:20:19 PM PDT 24
Peak memory 225460 kb
Host smart-62f54267-ba47-4a10-97ff-adde25bb3378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120806388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.2120806388
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.1126780899
Short name T994
Test name
Test status
Simulation time 420005476 ps
CPU time 4.93 seconds
Started Jul 28 07:20:10 PM PDT 24
Finished Jul 28 07:20:15 PM PDT 24
Peak memory 225460 kb
Host smart-2b6c5c0d-41f0-45af-a168-21fd4329d8d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126780899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.1126780899
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.2402542680
Short name T711
Test name
Test status
Simulation time 1501339116 ps
CPU time 11.46 seconds
Started Jul 28 07:20:20 PM PDT 24
Finished Jul 28 07:20:31 PM PDT 24
Peak memory 221712 kb
Host smart-863c5762-086b-4516-969e-1df1636f719c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2402542680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.2402542680
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.1437371855
Short name T801
Test name
Test status
Simulation time 9605157895 ps
CPU time 25.98 seconds
Started Jul 28 07:20:20 PM PDT 24
Finished Jul 28 07:20:46 PM PDT 24
Peak memory 217172 kb
Host smart-93844846-00c9-42e0-b3cf-3e1a67691c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437371855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.1437371855
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.1368334702
Short name T73
Test name
Test status
Simulation time 926161164 ps
CPU time 1.83 seconds
Started Jul 28 07:20:10 PM PDT 24
Finished Jul 28 07:20:12 PM PDT 24
Peak memory 208720 kb
Host smart-6635b6a8-6b77-4ed6-be28-55bc47e05e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368334702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.1368334702
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.2756301342
Short name T358
Test name
Test status
Simulation time 88677114 ps
CPU time 1.37 seconds
Started Jul 28 07:20:05 PM PDT 24
Finished Jul 28 07:20:07 PM PDT 24
Peak memory 217400 kb
Host smart-ccf66162-08b6-4c85-92fd-8afdaf11059c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756301342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.2756301342
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.3358842402
Short name T404
Test name
Test status
Simulation time 162625563 ps
CPU time 0.76 seconds
Started Jul 28 07:20:20 PM PDT 24
Finished Jul 28 07:20:21 PM PDT 24
Peak memory 206732 kb
Host smart-11aff78f-242c-4f41-b5a4-e85eb3a5f247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358842402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.3358842402
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.457181261
Short name T749
Test name
Test status
Simulation time 2031679670 ps
CPU time 9.24 seconds
Started Jul 28 07:20:11 PM PDT 24
Finished Jul 28 07:20:20 PM PDT 24
Peak memory 241560 kb
Host smart-2ea438f9-bf89-41d4-a2fb-aa27e7445884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457181261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.457181261
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.3974386816
Short name T710
Test name
Test status
Simulation time 32927391 ps
CPU time 0.7 seconds
Started Jul 28 07:20:16 PM PDT 24
Finished Jul 28 07:20:17 PM PDT 24
Peak memory 206444 kb
Host smart-3c4b156c-1510-4a41-b640-96815c95d1a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974386816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
3974386816
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.99268220
Short name T647
Test name
Test status
Simulation time 822918020 ps
CPU time 2.59 seconds
Started Jul 28 07:20:15 PM PDT 24
Finished Jul 28 07:20:18 PM PDT 24
Peak memory 225416 kb
Host smart-50b1d90f-c4b5-4806-8346-661162c9acc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99268220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.99268220
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.3549373165
Short name T511
Test name
Test status
Simulation time 18419258 ps
CPU time 0.75 seconds
Started Jul 28 07:20:13 PM PDT 24
Finished Jul 28 07:20:14 PM PDT 24
Peak memory 206208 kb
Host smart-40eb001f-9397-4cfc-8830-2bf90d1b0754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549373165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.3549373165
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.4121237943
Short name T721
Test name
Test status
Simulation time 12078430 ps
CPU time 0.8 seconds
Started Jul 28 07:20:16 PM PDT 24
Finished Jul 28 07:20:17 PM PDT 24
Peak memory 216624 kb
Host smart-9a8344e8-014f-4d7e-9bbb-9794aa73eba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121237943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.4121237943
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.3372817657
Short name T308
Test name
Test status
Simulation time 89317241381 ps
CPU time 218.68 seconds
Started Jul 28 07:20:21 PM PDT 24
Finished Jul 28 07:24:00 PM PDT 24
Peak memory 258812 kb
Host smart-68148839-b893-4c8d-8efe-4205953cda1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372817657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.3372817657
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.2728552422
Short name T572
Test name
Test status
Simulation time 20936372199 ps
CPU time 85.33 seconds
Started Jul 28 07:20:16 PM PDT 24
Finished Jul 28 07:21:42 PM PDT 24
Peak memory 235696 kb
Host smart-9f9f546c-fffd-41fa-80d3-f58300957403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728552422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.2728552422
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.2856503175
Short name T858
Test name
Test status
Simulation time 2196897840 ps
CPU time 15.38 seconds
Started Jul 28 07:20:15 PM PDT 24
Finished Jul 28 07:20:30 PM PDT 24
Peak memory 225472 kb
Host smart-2748a731-d3c9-4a6d-ada2-f360a4cf324f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856503175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.2856503175
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.1282158351
Short name T857
Test name
Test status
Simulation time 68171983879 ps
CPU time 155.42 seconds
Started Jul 28 07:20:15 PM PDT 24
Finished Jul 28 07:22:50 PM PDT 24
Peak memory 250144 kb
Host smart-9b9bc25c-55e1-465d-93c2-38210afaff75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282158351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmd
s.1282158351
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_intercept.3745757311
Short name T224
Test name
Test status
Simulation time 5490700429 ps
CPU time 10.58 seconds
Started Jul 28 07:20:14 PM PDT 24
Finished Jul 28 07:20:25 PM PDT 24
Peak memory 225548 kb
Host smart-a443f42c-aa28-419f-ba50-d9c3e9e85328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745757311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.3745757311
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.2063201615
Short name T1011
Test name
Test status
Simulation time 77803973 ps
CPU time 3.87 seconds
Started Jul 28 07:20:15 PM PDT 24
Finished Jul 28 07:20:19 PM PDT 24
Peak memory 225440 kb
Host smart-ddcdd1fc-03da-4a72-ac2e-dddfefe508c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063201615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.2063201615
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.1260781876
Short name T144
Test name
Test status
Simulation time 27668860490 ps
CPU time 20.28 seconds
Started Jul 28 07:20:14 PM PDT 24
Finished Jul 28 07:20:35 PM PDT 24
Peak memory 233728 kb
Host smart-f1e4ac85-3e24-42a1-9501-29faec19ce93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260781876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.1260781876
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.620675451
Short name T632
Test name
Test status
Simulation time 97749974 ps
CPU time 2.29 seconds
Started Jul 28 07:20:15 PM PDT 24
Finished Jul 28 07:20:18 PM PDT 24
Peak memory 233312 kb
Host smart-b9bf54c7-9e99-4397-971a-2671f2c69b88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620675451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.620675451
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.2362796917
Short name T892
Test name
Test status
Simulation time 202888107 ps
CPU time 5.16 seconds
Started Jul 28 07:20:14 PM PDT 24
Finished Jul 28 07:20:19 PM PDT 24
Peak memory 223256 kb
Host smart-638c1d3c-fd0b-489d-96bb-90770ad3b454
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2362796917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.2362796917
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.4249574777
Short name T40
Test name
Test status
Simulation time 7099597731 ps
CPU time 60.74 seconds
Started Jul 28 07:20:17 PM PDT 24
Finished Jul 28 07:21:18 PM PDT 24
Peak memory 250008 kb
Host smart-d283332d-b7e8-427e-ac56-4fa85d8ae6b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249574777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.4249574777
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.2069443494
Short name T30
Test name
Test status
Simulation time 1372640121 ps
CPU time 8.1 seconds
Started Jul 28 07:20:14 PM PDT 24
Finished Jul 28 07:20:22 PM PDT 24
Peak memory 217176 kb
Host smart-6d40170e-e47e-4e63-b6d7-076605d5c712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069443494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.2069443494
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.2117339371
Short name T821
Test name
Test status
Simulation time 37401720 ps
CPU time 0.71 seconds
Started Jul 28 07:20:15 PM PDT 24
Finished Jul 28 07:20:16 PM PDT 24
Peak memory 206348 kb
Host smart-3cbe408f-3607-4f20-807a-cfcebb8cd36c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117339371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.2117339371
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.2801795171
Short name T722
Test name
Test status
Simulation time 126333999 ps
CPU time 1.2 seconds
Started Jul 28 07:20:16 PM PDT 24
Finished Jul 28 07:20:17 PM PDT 24
Peak memory 217168 kb
Host smart-6b302e41-0978-4d4c-ae21-c53275562f6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801795171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.2801795171
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.124286056
Short name T363
Test name
Test status
Simulation time 79169498 ps
CPU time 0.85 seconds
Started Jul 28 07:20:14 PM PDT 24
Finished Jul 28 07:20:15 PM PDT 24
Peak memory 206788 kb
Host smart-c07fb781-8623-4a65-b41a-6e1bb98bde3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124286056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.124286056
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.1497040588
Short name T696
Test name
Test status
Simulation time 1111096016 ps
CPU time 4.35 seconds
Started Jul 28 07:20:13 PM PDT 24
Finished Jul 28 07:20:18 PM PDT 24
Peak memory 241732 kb
Host smart-c7a34d50-ec0d-4099-98fd-72b66066e9a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497040588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.1497040588
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.757552048
Short name T556
Test name
Test status
Simulation time 11567286 ps
CPU time 0.72 seconds
Started Jul 28 07:20:23 PM PDT 24
Finished Jul 28 07:20:24 PM PDT 24
Peak memory 205516 kb
Host smart-1c7f1c1a-d50e-4266-810a-e22b5dabc758
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757552048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.757552048
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.341649713
Short name T882
Test name
Test status
Simulation time 837952259 ps
CPU time 9.57 seconds
Started Jul 28 07:20:25 PM PDT 24
Finished Jul 28 07:20:35 PM PDT 24
Peak memory 225468 kb
Host smart-7468c05b-8359-4222-9ce2-6afde3a80063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341649713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.341649713
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.647851844
Short name T872
Test name
Test status
Simulation time 50881066 ps
CPU time 0.75 seconds
Started Jul 28 07:20:19 PM PDT 24
Finished Jul 28 07:20:20 PM PDT 24
Peak memory 206224 kb
Host smart-7f634494-6a2b-4668-ac7d-0bc0e43ac776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647851844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.647851844
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.2081641467
Short name T851
Test name
Test status
Simulation time 2393077079 ps
CPU time 61.51 seconds
Started Jul 28 07:20:22 PM PDT 24
Finished Jul 28 07:21:24 PM PDT 24
Peak memory 249484 kb
Host smart-1efa2fcc-72b5-4831-9164-2b07454723a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081641467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.2081641467
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.3760338039
Short name T412
Test name
Test status
Simulation time 881780084 ps
CPU time 3.21 seconds
Started Jul 28 07:20:23 PM PDT 24
Finished Jul 28 07:20:26 PM PDT 24
Peak memory 218532 kb
Host smart-041b7a9e-2190-4db0-a438-b96c6bcbfe0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760338039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.3760338039
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.2208563196
Short name T486
Test name
Test status
Simulation time 18623848757 ps
CPU time 135.19 seconds
Started Jul 28 07:20:23 PM PDT 24
Finished Jul 28 07:22:38 PM PDT 24
Peak memory 250124 kb
Host smart-e048c52c-daff-4aed-b8dc-f80718d7fe71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208563196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmd
s.2208563196
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_intercept.1987290599
Short name T765
Test name
Test status
Simulation time 1004568363 ps
CPU time 11.75 seconds
Started Jul 28 07:20:17 PM PDT 24
Finished Jul 28 07:20:29 PM PDT 24
Peak memory 233840 kb
Host smart-81a2cd71-ea26-4d44-91fa-96ca2e969f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987290599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.1987290599
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.1749756755
Short name T88
Test name
Test status
Simulation time 621159616 ps
CPU time 8.15 seconds
Started Jul 28 07:20:17 PM PDT 24
Finished Jul 28 07:20:26 PM PDT 24
Peak memory 241776 kb
Host smart-0d0a5e11-e1df-4559-a430-b81a8af8910c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749756755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.1749756755
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.1002172918
Short name T352
Test name
Test status
Simulation time 49779608 ps
CPU time 2.25 seconds
Started Jul 28 07:20:18 PM PDT 24
Finished Jul 28 07:20:20 PM PDT 24
Peak memory 224960 kb
Host smart-11140eb1-2e2a-48ba-a882-e1c70ee250ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002172918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.1002172918
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.1067236944
Short name T677
Test name
Test status
Simulation time 11145951358 ps
CPU time 17.83 seconds
Started Jul 28 07:20:20 PM PDT 24
Finished Jul 28 07:20:38 PM PDT 24
Peak memory 240984 kb
Host smart-7b1071ee-7c0e-473e-b5cf-4b9873d6253a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067236944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.1067236944
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.3128876775
Short name T87
Test name
Test status
Simulation time 6412054244 ps
CPU time 14 seconds
Started Jul 28 07:20:24 PM PDT 24
Finished Jul 28 07:20:38 PM PDT 24
Peak memory 223492 kb
Host smart-3c66a5db-1b36-44fd-8b5a-77c7a4058d33
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3128876775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.3128876775
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.1665265823
Short name T19
Test name
Test status
Simulation time 172991012723 ps
CPU time 572.81 seconds
Started Jul 28 07:20:24 PM PDT 24
Finished Jul 28 07:29:57 PM PDT 24
Peak memory 266556 kb
Host smart-7ac7c4cb-e5f3-49ef-a37d-8585c04157b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665265823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.1665265823
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.3593366832
Short name T482
Test name
Test status
Simulation time 2573307186 ps
CPU time 10.81 seconds
Started Jul 28 07:20:19 PM PDT 24
Finished Jul 28 07:20:30 PM PDT 24
Peak memory 217304 kb
Host smart-f1d38659-78ae-4cdd-8d79-8c700bae9240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593366832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.3593366832
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.4121696709
Short name T646
Test name
Test status
Simulation time 31301497876 ps
CPU time 16.31 seconds
Started Jul 28 07:20:20 PM PDT 24
Finished Jul 28 07:20:36 PM PDT 24
Peak memory 217232 kb
Host smart-f2f92461-d1a3-445a-b825-282b04883128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121696709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.4121696709
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.1309538640
Short name T670
Test name
Test status
Simulation time 84320399 ps
CPU time 1.48 seconds
Started Jul 28 07:20:18 PM PDT 24
Finished Jul 28 07:20:20 PM PDT 24
Peak memory 217148 kb
Host smart-9d52d4cf-6348-4588-a7bd-d5a68419dc67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309538640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.1309538640
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.4186822615
Short name T1004
Test name
Test status
Simulation time 387942132 ps
CPU time 0.88 seconds
Started Jul 28 07:20:19 PM PDT 24
Finished Jul 28 07:20:20 PM PDT 24
Peak memory 206804 kb
Host smart-eecdfd74-8bb8-440f-bf56-093bca10e838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186822615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.4186822615
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.149416424
Short name T702
Test name
Test status
Simulation time 79902528 ps
CPU time 2.44 seconds
Started Jul 28 07:20:20 PM PDT 24
Finished Jul 28 07:20:23 PM PDT 24
Peak memory 233580 kb
Host smart-59aa60e2-f3f8-4fe5-b3de-07e02e6d10ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149416424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.149416424
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.3052572327
Short name T806
Test name
Test status
Simulation time 19578865 ps
CPU time 0.7 seconds
Started Jul 28 07:20:33 PM PDT 24
Finished Jul 28 07:20:34 PM PDT 24
Peak memory 206112 kb
Host smart-eed1396c-d999-4f84-a9eb-0b38eeef7609
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052572327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
3052572327
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.2059405223
Short name T705
Test name
Test status
Simulation time 2730566317 ps
CPU time 6.69 seconds
Started Jul 28 07:20:33 PM PDT 24
Finished Jul 28 07:20:40 PM PDT 24
Peak memory 233732 kb
Host smart-7a04af72-c6d3-46fe-a871-e7f67e12cbdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059405223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.2059405223
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.1526186889
Short name T411
Test name
Test status
Simulation time 220804790 ps
CPU time 0.77 seconds
Started Jul 28 07:20:22 PM PDT 24
Finished Jul 28 07:20:23 PM PDT 24
Peak memory 206216 kb
Host smart-4335e1c1-5caa-444f-a606-93da9fc9a060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526186889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.1526186889
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.495223706
Short name T712
Test name
Test status
Simulation time 54185633576 ps
CPU time 202.52 seconds
Started Jul 28 07:20:29 PM PDT 24
Finished Jul 28 07:23:52 PM PDT 24
Peak memory 254660 kb
Host smart-bbcee402-4c6c-44b8-ac20-c6a3a8898d9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495223706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.495223706
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.1271765601
Short name T259
Test name
Test status
Simulation time 11286893807 ps
CPU time 18.75 seconds
Started Jul 28 07:20:28 PM PDT 24
Finished Jul 28 07:20:47 PM PDT 24
Peak memory 250148 kb
Host smart-580ba56a-4506-4764-be9c-ac18ac8939cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271765601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.1271765601
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.1906363523
Short name T912
Test name
Test status
Simulation time 2871371605 ps
CPU time 9.12 seconds
Started Jul 28 07:20:25 PM PDT 24
Finished Jul 28 07:20:35 PM PDT 24
Peak memory 218792 kb
Host smart-a28694f4-9483-4e6a-8872-e7b6e21a3d4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906363523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.1906363523
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.4180478762
Short name T316
Test name
Test status
Simulation time 5311120480 ps
CPU time 14.92 seconds
Started Jul 28 07:20:26 PM PDT 24
Finished Jul 28 07:20:41 PM PDT 24
Peak memory 225492 kb
Host smart-08cc74c0-60fd-4f50-8f12-ea78974dba49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180478762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.4180478762
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.258049029
Short name T98
Test name
Test status
Simulation time 16270906516 ps
CPU time 57.45 seconds
Started Jul 28 07:20:33 PM PDT 24
Finished Jul 28 07:21:31 PM PDT 24
Peak memory 250188 kb
Host smart-173a3f92-8f2e-4dca-9aca-1d1b40c56236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258049029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmds
.258049029
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_intercept.138326784
Short name T660
Test name
Test status
Simulation time 3132169115 ps
CPU time 11.08 seconds
Started Jul 28 07:20:29 PM PDT 24
Finished Jul 28 07:20:40 PM PDT 24
Peak memory 233676 kb
Host smart-101d00b0-5a75-4b61-878c-e4ca10c060a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138326784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.138326784
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.1177679074
Short name T265
Test name
Test status
Simulation time 613457448 ps
CPU time 9.28 seconds
Started Jul 28 07:20:27 PM PDT 24
Finished Jul 28 07:20:37 PM PDT 24
Peak memory 233684 kb
Host smart-f621225f-b121-459c-9dd3-4b03eab0b289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177679074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.1177679074
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.3423465992
Short name T2
Test name
Test status
Simulation time 24196038382 ps
CPU time 16.56 seconds
Started Jul 28 07:20:24 PM PDT 24
Finished Jul 28 07:20:41 PM PDT 24
Peak memory 233616 kb
Host smart-a0ffa22f-52cd-4551-ab24-ab27d899f10e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423465992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.3423465992
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.3903312647
Short name T465
Test name
Test status
Simulation time 1577346371 ps
CPU time 7.93 seconds
Started Jul 28 07:20:24 PM PDT 24
Finished Jul 28 07:20:32 PM PDT 24
Peak memory 240800 kb
Host smart-0b648a0c-1f61-46e2-8252-cb207887aa35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903312647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.3903312647
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.452519978
Short name T168
Test name
Test status
Simulation time 254349331621 ps
CPU time 592.94 seconds
Started Jul 28 07:20:27 PM PDT 24
Finished Jul 28 07:30:20 PM PDT 24
Peak memory 272764 kb
Host smart-18af3e55-091e-4b1c-a70e-136b005838e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452519978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stres
s_all.452519978
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.3088846865
Short name T650
Test name
Test status
Simulation time 839673042 ps
CPU time 5.75 seconds
Started Jul 28 07:20:24 PM PDT 24
Finished Jul 28 07:20:30 PM PDT 24
Peak memory 217292 kb
Host smart-deb6cb4f-8008-46aa-ac37-b672505c28e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088846865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.3088846865
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.2914261134
Short name T547
Test name
Test status
Simulation time 5244701495 ps
CPU time 13.63 seconds
Started Jul 28 07:20:24 PM PDT 24
Finished Jul 28 07:20:38 PM PDT 24
Peak memory 217216 kb
Host smart-e8e1ab30-a176-4e32-83e0-09694e6803b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914261134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.2914261134
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.3507741983
Short name T789
Test name
Test status
Simulation time 110441216 ps
CPU time 1.11 seconds
Started Jul 28 07:20:24 PM PDT 24
Finished Jul 28 07:20:25 PM PDT 24
Peak memory 207936 kb
Host smart-fc87a218-8bd5-4989-a471-d47a6c5348a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507741983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.3507741983
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.829928547
Short name T906
Test name
Test status
Simulation time 56581577 ps
CPU time 0.87 seconds
Started Jul 28 07:20:22 PM PDT 24
Finished Jul 28 07:20:23 PM PDT 24
Peak memory 207836 kb
Host smart-13aa77d5-7710-4a27-8869-d963008a67a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829928547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.829928547
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.3478907493
Short name T697
Test name
Test status
Simulation time 17420867016 ps
CPU time 27.3 seconds
Started Jul 28 07:20:27 PM PDT 24
Finished Jul 28 07:20:54 PM PDT 24
Peak memory 233732 kb
Host smart-8574b5d4-3f14-4e0e-ae5d-0077c33a0836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478907493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.3478907493
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.940636390
Short name T736
Test name
Test status
Simulation time 17257156 ps
CPU time 0.74 seconds
Started Jul 28 07:20:33 PM PDT 24
Finished Jul 28 07:20:34 PM PDT 24
Peak memory 206404 kb
Host smart-5e42e565-b848-4850-958d-2c7e12304506
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940636390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.940636390
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.1187159175
Short name T5
Test name
Test status
Simulation time 7354793180 ps
CPU time 17.25 seconds
Started Jul 28 07:20:28 PM PDT 24
Finished Jul 28 07:20:45 PM PDT 24
Peak memory 225452 kb
Host smart-a8f88887-226a-4b2d-8504-84f94dff7ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187159175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.1187159175
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.4146762253
Short name T942
Test name
Test status
Simulation time 31193465 ps
CPU time 0.77 seconds
Started Jul 28 07:20:27 PM PDT 24
Finished Jul 28 07:20:28 PM PDT 24
Peak memory 207220 kb
Host smart-a6866b45-c25e-4502-9558-266d0a5c8460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146762253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.4146762253
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.1085890613
Short name T935
Test name
Test status
Simulation time 772982380 ps
CPU time 18.32 seconds
Started Jul 28 07:20:32 PM PDT 24
Finished Jul 28 07:20:50 PM PDT 24
Peak memory 237604 kb
Host smart-2fdfc3d0-e4a1-42a0-98c4-53bef7a55145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085890613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.1085890613
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.923208897
Short name T609
Test name
Test status
Simulation time 19749915024 ps
CPU time 48.32 seconds
Started Jul 28 07:20:32 PM PDT 24
Finished Jul 28 07:21:21 PM PDT 24
Peak memory 241936 kb
Host smart-0d27ece2-f464-426a-96fc-02d2175968c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923208897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.923208897
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.3881054560
Short name T850
Test name
Test status
Simulation time 2564453870 ps
CPU time 14.74 seconds
Started Jul 28 07:20:31 PM PDT 24
Finished Jul 28 07:20:46 PM PDT 24
Peak memory 241896 kb
Host smart-14a5f6f3-8e47-4683-b239-f592e3681efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881054560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.3881054560
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.3733739965
Short name T626
Test name
Test status
Simulation time 10106012657 ps
CPU time 51.09 seconds
Started Jul 28 07:20:32 PM PDT 24
Finished Jul 28 07:21:23 PM PDT 24
Peak memory 250100 kb
Host smart-1eaa2bf4-600c-4ca7-9530-9eb8d0e83eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733739965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmd
s.3733739965
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_intercept.4044705315
Short name T264
Test name
Test status
Simulation time 141087572 ps
CPU time 2.59 seconds
Started Jul 28 07:20:32 PM PDT 24
Finished Jul 28 07:20:35 PM PDT 24
Peak memory 225364 kb
Host smart-d574e5d2-7b63-4b59-93c1-245f50e733a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044705315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.4044705315
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.3444215104
Short name T686
Test name
Test status
Simulation time 796323763 ps
CPU time 10.94 seconds
Started Jul 28 07:20:36 PM PDT 24
Finished Jul 28 07:20:47 PM PDT 24
Peak memory 233612 kb
Host smart-bede666b-6d6f-402f-9670-d1e6a318d38c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444215104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.3444215104
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.170246021
Short name T962
Test name
Test status
Simulation time 2438958281 ps
CPU time 6.63 seconds
Started Jul 28 07:20:31 PM PDT 24
Finished Jul 28 07:20:38 PM PDT 24
Peak memory 225476 kb
Host smart-6dd722dc-b057-4516-ad0b-02d5f1b1902a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170246021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swap
.170246021
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.450767474
Short name T575
Test name
Test status
Simulation time 1681275546 ps
CPU time 11.59 seconds
Started Jul 28 07:20:33 PM PDT 24
Finished Jul 28 07:20:45 PM PDT 24
Peak memory 233712 kb
Host smart-77f08f9f-ed47-4cfd-b35b-ddf5cf86bceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450767474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.450767474
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.148896814
Short name T616
Test name
Test status
Simulation time 238231983 ps
CPU time 5.32 seconds
Started Jul 28 07:20:33 PM PDT 24
Finished Jul 28 07:20:38 PM PDT 24
Peak memory 221020 kb
Host smart-bf1831fa-aaef-4a09-a63e-4a1875ef6872
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=148896814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dire
ct.148896814
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.402236080
Short name T579
Test name
Test status
Simulation time 2503550634 ps
CPU time 28.27 seconds
Started Jul 28 07:20:30 PM PDT 24
Finished Jul 28 07:20:58 PM PDT 24
Peak memory 217304 kb
Host smart-f51ff5cb-9a10-41bd-8383-8674e7bfe97f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402236080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.402236080
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.471535919
Short name T707
Test name
Test status
Simulation time 38485626957 ps
CPU time 8.54 seconds
Started Jul 28 07:20:28 PM PDT 24
Finished Jul 28 07:20:37 PM PDT 24
Peak memory 217208 kb
Host smart-2cde38b5-fdfa-42cd-b89d-0d876a49fa98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471535919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.471535919
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.3920735947
Short name T333
Test name
Test status
Simulation time 43967260 ps
CPU time 1.58 seconds
Started Jul 28 07:20:33 PM PDT 24
Finished Jul 28 07:20:35 PM PDT 24
Peak memory 217120 kb
Host smart-6b03b242-fe6a-433d-b52f-3bc0f4cdb3dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920735947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.3920735947
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.77526633
Short name T644
Test name
Test status
Simulation time 42700256 ps
CPU time 0.78 seconds
Started Jul 28 07:20:32 PM PDT 24
Finished Jul 28 07:20:33 PM PDT 24
Peak memory 206748 kb
Host smart-aca53649-e1a5-467b-b5d7-f4820e4e87b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77526633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.77526633
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.2064510336
Short name T1028
Test name
Test status
Simulation time 53989221 ps
CPU time 2.46 seconds
Started Jul 28 07:20:33 PM PDT 24
Finished Jul 28 07:20:36 PM PDT 24
Peak memory 225496 kb
Host smart-6c8eebfb-24da-4a5d-9f3a-d26970651f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064510336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.2064510336
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.437122999
Short name T991
Test name
Test status
Simulation time 144393634 ps
CPU time 0.7 seconds
Started Jul 28 07:20:35 PM PDT 24
Finished Jul 28 07:20:36 PM PDT 24
Peak memory 206080 kb
Host smart-c7799de5-6f77-4027-952f-5b34cf4bb4c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437122999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.437122999
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.1420877417
Short name T347
Test name
Test status
Simulation time 1348310321 ps
CPU time 13.75 seconds
Started Jul 28 07:20:33 PM PDT 24
Finished Jul 28 07:20:47 PM PDT 24
Peak memory 225452 kb
Host smart-a9af1e86-eee8-4cfa-82bf-e496cf6b2d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420877417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.1420877417
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.759381697
Short name T418
Test name
Test status
Simulation time 20490553 ps
CPU time 0.8 seconds
Started Jul 28 07:20:29 PM PDT 24
Finished Jul 28 07:20:30 PM PDT 24
Peak memory 207304 kb
Host smart-43ff3541-4ca1-4c45-8b97-951ca4484c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759381697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.759381697
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.1040049111
Short name T523
Test name
Test status
Simulation time 3615578235 ps
CPU time 26.56 seconds
Started Jul 28 07:20:33 PM PDT 24
Finished Jul 28 07:21:00 PM PDT 24
Peak memory 235488 kb
Host smart-9647dc50-c573-41aa-8939-a0c394a10b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040049111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.1040049111
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.3444235489
Short name T230
Test name
Test status
Simulation time 18673387934 ps
CPU time 180.42 seconds
Started Jul 28 07:20:35 PM PDT 24
Finished Jul 28 07:23:36 PM PDT 24
Peak memory 241952 kb
Host smart-14d7eaf7-3513-4344-b267-5fe5c3dc2ac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444235489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.3444235489
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.3833015278
Short name T290
Test name
Test status
Simulation time 4187793129 ps
CPU time 46.37 seconds
Started Jul 28 07:20:36 PM PDT 24
Finished Jul 28 07:21:22 PM PDT 24
Peak memory 251528 kb
Host smart-dacc5026-65cc-4501-94b0-c0158ffc5ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833015278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmd
s.3833015278
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_intercept.2098194489
Short name T737
Test name
Test status
Simulation time 454727744 ps
CPU time 4.44 seconds
Started Jul 28 07:20:35 PM PDT 24
Finished Jul 28 07:20:40 PM PDT 24
Peak memory 225392 kb
Host smart-8ff60e25-0eeb-4a74-80e4-cd5c400a9dda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098194489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.2098194489
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.1670193485
Short name T227
Test name
Test status
Simulation time 1643997662 ps
CPU time 18.74 seconds
Started Jul 28 07:20:38 PM PDT 24
Finished Jul 28 07:20:57 PM PDT 24
Peak memory 225460 kb
Host smart-7ab743bb-f9f8-467c-a803-567b6d3c4b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670193485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.1670193485
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.713084209
Short name T229
Test name
Test status
Simulation time 12851504367 ps
CPU time 15.36 seconds
Started Jul 28 07:20:35 PM PDT 24
Finished Jul 28 07:20:50 PM PDT 24
Peak memory 233592 kb
Host smart-de109c66-a152-44af-af77-d3802b4fc74d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713084209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swap
.713084209
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.3806637248
Short name T70
Test name
Test status
Simulation time 533238482 ps
CPU time 4.11 seconds
Started Jul 28 07:20:36 PM PDT 24
Finished Jul 28 07:20:40 PM PDT 24
Peak memory 233632 kb
Host smart-d3369469-77ae-4747-a01a-c9645c8496fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806637248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.3806637248
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.1916234557
Short name T158
Test name
Test status
Simulation time 2472429864 ps
CPU time 13.94 seconds
Started Jul 28 07:20:37 PM PDT 24
Finished Jul 28 07:20:51 PM PDT 24
Peak memory 220196 kb
Host smart-621717e3-1241-4d18-8ddb-a9189b67d2de
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1916234557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.1916234557
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.3672432756
Short name T166
Test name
Test status
Simulation time 60652371242 ps
CPU time 225.9 seconds
Started Jul 28 07:20:37 PM PDT 24
Finished Jul 28 07:24:23 PM PDT 24
Peak memory 257544 kb
Host smart-dfccf86f-9dae-4f07-855d-5c62c91ee2bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672432756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.3672432756
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.3935539553
Short name T533
Test name
Test status
Simulation time 14370167532 ps
CPU time 42.37 seconds
Started Jul 28 07:20:35 PM PDT 24
Finished Jul 28 07:21:17 PM PDT 24
Peak memory 217440 kb
Host smart-4025604e-4dfa-4ef9-a105-51cf253c300f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935539553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.3935539553
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.3647867359
Short name T390
Test name
Test status
Simulation time 11693714699 ps
CPU time 15.46 seconds
Started Jul 28 07:20:31 PM PDT 24
Finished Jul 28 07:20:46 PM PDT 24
Peak memory 217192 kb
Host smart-da6c2686-bf8b-4cf8-b62e-7429485f726a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647867359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.3647867359
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.2928598359
Short name T758
Test name
Test status
Simulation time 54695073 ps
CPU time 1.37 seconds
Started Jul 28 07:20:38 PM PDT 24
Finished Jul 28 07:20:40 PM PDT 24
Peak memory 208964 kb
Host smart-c2d03163-8e9e-444b-9c7c-0e46ea49acd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928598359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.2928598359
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.3828032854
Short name T659
Test name
Test status
Simulation time 100799655 ps
CPU time 1.08 seconds
Started Jul 28 07:20:38 PM PDT 24
Finished Jul 28 07:20:39 PM PDT 24
Peak memory 207828 kb
Host smart-4ea93c1c-b810-42e8-90fb-fca5aa7f5aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828032854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.3828032854
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.676217327
Short name T510
Test name
Test status
Simulation time 332656613 ps
CPU time 4.27 seconds
Started Jul 28 07:20:35 PM PDT 24
Finished Jul 28 07:20:39 PM PDT 24
Peak memory 234644 kb
Host smart-a21a2a3a-ff35-45f9-8da8-d68f3bff59cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676217327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.676217327
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.1789291238
Short name T399
Test name
Test status
Simulation time 52233043 ps
CPU time 0.73 seconds
Started Jul 28 07:18:31 PM PDT 24
Finished Jul 28 07:18:32 PM PDT 24
Peak memory 206392 kb
Host smart-3566c4d8-a03b-4afb-a6b5-b0037d98c8fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789291238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.1
789291238
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.2806006227
Short name T548
Test name
Test status
Simulation time 158716168 ps
CPU time 5.3 seconds
Started Jul 28 07:18:25 PM PDT 24
Finished Jul 28 07:18:30 PM PDT 24
Peak memory 233632 kb
Host smart-9fbb82f0-2cbb-406a-bb76-027a53dd6fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806006227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.2806006227
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.520941525
Short name T348
Test name
Test status
Simulation time 51072833 ps
CPU time 0.81 seconds
Started Jul 28 07:18:22 PM PDT 24
Finished Jul 28 07:18:23 PM PDT 24
Peak memory 207576 kb
Host smart-534745ae-3dc3-4341-b559-7c5aba19bc5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520941525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.520941525
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.1268722133
Short name T205
Test name
Test status
Simulation time 7923306201 ps
CPU time 52.38 seconds
Started Jul 28 07:18:28 PM PDT 24
Finished Jul 28 07:19:20 PM PDT 24
Peak memory 256124 kb
Host smart-4e25db01-0be4-4fe9-95f3-915fa439d550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268722133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.1268722133
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.2472032918
Short name T239
Test name
Test status
Simulation time 1024237657919 ps
CPU time 717.53 seconds
Started Jul 28 07:18:27 PM PDT 24
Finished Jul 28 07:30:25 PM PDT 24
Peak memory 274340 kb
Host smart-1eff67d7-027a-403e-9a98-1a8d5ea43f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472032918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.2472032918
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.3908291383
Short name T292
Test name
Test status
Simulation time 30220787220 ps
CPU time 308.51 seconds
Started Jul 28 07:18:32 PM PDT 24
Finished Jul 28 07:23:40 PM PDT 24
Peak memory 254400 kb
Host smart-5bc6cbf8-2147-4ec5-8898-fb4b06bb3202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908291383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.3908291383
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.3109380252
Short name T829
Test name
Test status
Simulation time 472462932 ps
CPU time 5.39 seconds
Started Jul 28 07:18:26 PM PDT 24
Finished Jul 28 07:18:32 PM PDT 24
Peak memory 234304 kb
Host smart-75ddb100-fdcf-4240-aeca-32d217de16be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109380252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.3109380252
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.2801701593
Short name T708
Test name
Test status
Simulation time 1606075224 ps
CPU time 20.71 seconds
Started Jul 28 07:18:26 PM PDT 24
Finished Jul 28 07:18:47 PM PDT 24
Peak memory 237452 kb
Host smart-2dbf2954-3884-4512-90a2-8057569ff254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801701593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds
.2801701593
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_intercept.436175448
Short name T439
Test name
Test status
Simulation time 434118998 ps
CPU time 4.79 seconds
Started Jul 28 07:18:26 PM PDT 24
Finished Jul 28 07:18:31 PM PDT 24
Peak memory 230524 kb
Host smart-f4e1a02d-6932-4cd0-8d34-8bf9ab4ab09d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436175448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.436175448
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.1032023806
Short name T634
Test name
Test status
Simulation time 1623729548 ps
CPU time 22.31 seconds
Started Jul 28 07:18:27 PM PDT 24
Finished Jul 28 07:18:50 PM PDT 24
Peak memory 240708 kb
Host smart-d9e9f56c-eedf-48b7-9e8c-402556496d97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032023806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.1032023806
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.2324676265
Short name T785
Test name
Test status
Simulation time 29771899 ps
CPU time 1.14 seconds
Started Jul 28 07:18:24 PM PDT 24
Finished Jul 28 07:18:25 PM PDT 24
Peak memory 217384 kb
Host smart-0cb5ab8c-5521-4e97-95ed-b8aab7dd0c6e
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324676265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.spi_device_mem_parity.2324676265
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.876894742
Short name T184
Test name
Test status
Simulation time 2330999086 ps
CPU time 7.98 seconds
Started Jul 28 07:18:26 PM PDT 24
Finished Jul 28 07:18:34 PM PDT 24
Peak memory 225520 kb
Host smart-c3937741-228c-4cb9-9b37-d48929862051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876894742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap.
876894742
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.1668367317
Short name T201
Test name
Test status
Simulation time 13131460079 ps
CPU time 9.21 seconds
Started Jul 28 07:18:22 PM PDT 24
Finished Jul 28 07:18:32 PM PDT 24
Peak memory 225436 kb
Host smart-d71b7b08-db3f-4964-9d83-dcf4ec04a2f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668367317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.1668367317
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.736557016
Short name T901
Test name
Test status
Simulation time 974823932 ps
CPU time 5.99 seconds
Started Jul 28 07:18:26 PM PDT 24
Finished Jul 28 07:18:33 PM PDT 24
Peak memory 223840 kb
Host smart-1eb1408d-4bde-4dfc-bd2b-3b445ffc169f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=736557016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_direc
t.736557016
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.1410206206
Short name T79
Test name
Test status
Simulation time 112084819 ps
CPU time 1.14 seconds
Started Jul 28 07:18:33 PM PDT 24
Finished Jul 28 07:18:34 PM PDT 24
Peak memory 236336 kb
Host smart-6b54d416-6209-4a09-b8aa-612d8aadba7e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410206206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.1410206206
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.1864438273
Short name T18
Test name
Test status
Simulation time 13369789147 ps
CPU time 102.65 seconds
Started Jul 28 07:18:32 PM PDT 24
Finished Jul 28 07:20:15 PM PDT 24
Peak memory 241392 kb
Host smart-528acf8d-013a-40ee-8b53-d05fee952763
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864438273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.1864438273
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.3002114565
Short name T327
Test name
Test status
Simulation time 988900366 ps
CPU time 10.28 seconds
Started Jul 28 07:18:24 PM PDT 24
Finished Jul 28 07:18:34 PM PDT 24
Peak memory 219464 kb
Host smart-efed057d-5019-4c9f-886e-222abec9af03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002114565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.3002114565
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.2641039161
Short name T1025
Test name
Test status
Simulation time 29649685499 ps
CPU time 19.06 seconds
Started Jul 28 07:18:23 PM PDT 24
Finished Jul 28 07:18:42 PM PDT 24
Peak memory 217284 kb
Host smart-ab342c84-4ed3-48c4-a1fe-ff441e5de351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641039161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.2641039161
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.1249652969
Short name T1009
Test name
Test status
Simulation time 380296179 ps
CPU time 1.56 seconds
Started Jul 28 07:18:23 PM PDT 24
Finished Jul 28 07:18:25 PM PDT 24
Peak memory 217152 kb
Host smart-5475d30f-e0d1-4b82-9aa5-d360a4abb386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249652969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.1249652969
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.564178787
Short name T442
Test name
Test status
Simulation time 33141847 ps
CPU time 0.89 seconds
Started Jul 28 07:18:23 PM PDT 24
Finished Jul 28 07:18:24 PM PDT 24
Peak memory 207796 kb
Host smart-73d4163d-5175-4046-bce3-ec5b216be67b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564178787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.564178787
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.1716936653
Short name T199
Test name
Test status
Simulation time 6805658269 ps
CPU time 5.52 seconds
Started Jul 28 07:18:26 PM PDT 24
Finished Jul 28 07:18:32 PM PDT 24
Peak memory 225540 kb
Host smart-7b8759ee-a2ae-40a4-80d5-e15b9a133b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716936653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.1716936653
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.72258651
Short name T520
Test name
Test status
Simulation time 49115904 ps
CPU time 0.73 seconds
Started Jul 28 07:20:45 PM PDT 24
Finished Jul 28 07:20:46 PM PDT 24
Peak memory 205452 kb
Host smart-6da8c6b4-9f91-4d27-a6a4-35d0c29ff122
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72258651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.72258651
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.3049202028
Short name T287
Test name
Test status
Simulation time 157375941 ps
CPU time 2.74 seconds
Started Jul 28 07:20:40 PM PDT 24
Finished Jul 28 07:20:43 PM PDT 24
Peak memory 233600 kb
Host smart-eb169393-c865-4ee9-ba23-180fbae0929e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049202028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.3049202028
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.4085591944
Short name T947
Test name
Test status
Simulation time 33336390 ps
CPU time 0.75 seconds
Started Jul 28 07:20:43 PM PDT 24
Finished Jul 28 07:20:43 PM PDT 24
Peak memory 206544 kb
Host smart-957356a1-7e80-4467-b868-3610aa2fc055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085591944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.4085591944
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.3732426991
Short name T50
Test name
Test status
Simulation time 84506818559 ps
CPU time 570.6 seconds
Started Jul 28 07:20:43 PM PDT 24
Finished Jul 28 07:30:13 PM PDT 24
Peak memory 251572 kb
Host smart-b98cd7e1-6ac1-4be4-b6d9-bd76adb14173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732426991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.3732426991
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.232362342
Short name T652
Test name
Test status
Simulation time 106796812618 ps
CPU time 247.61 seconds
Started Jul 28 07:20:43 PM PDT 24
Finished Jul 28 07:24:51 PM PDT 24
Peak memory 250176 kb
Host smart-523c2547-f574-4660-a682-1f083fbd021c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232362342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.232362342
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.1128269533
Short name T593
Test name
Test status
Simulation time 8536100775 ps
CPU time 70.78 seconds
Started Jul 28 07:20:43 PM PDT 24
Finished Jul 28 07:21:54 PM PDT 24
Peak memory 257500 kb
Host smart-65c6a81d-53a8-43a3-ab87-de40cf375f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128269533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.1128269533
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.999934515
Short name T545
Test name
Test status
Simulation time 496846300 ps
CPU time 5.85 seconds
Started Jul 28 07:20:42 PM PDT 24
Finished Jul 28 07:20:48 PM PDT 24
Peak memory 233648 kb
Host smart-16991710-d887-4f9a-98f0-ebd9e00cceeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999934515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.999934515
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.694284230
Short name T393
Test name
Test status
Simulation time 2559587678 ps
CPU time 15.39 seconds
Started Jul 28 07:20:46 PM PDT 24
Finished Jul 28 07:21:01 PM PDT 24
Peak memory 238616 kb
Host smart-71cd6444-8053-488f-aa57-9030594ab002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694284230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmds
.694284230
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/30.spi_device_intercept.1772133728
Short name T584
Test name
Test status
Simulation time 267694090 ps
CPU time 3.5 seconds
Started Jul 28 07:20:43 PM PDT 24
Finished Jul 28 07:20:47 PM PDT 24
Peak memory 233680 kb
Host smart-2bf99ad8-4b90-40b0-95f7-49408f381266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772133728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.1772133728
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.3970556066
Short name T345
Test name
Test status
Simulation time 662129687 ps
CPU time 6.81 seconds
Started Jul 28 07:20:39 PM PDT 24
Finished Jul 28 07:20:46 PM PDT 24
Peak memory 241592 kb
Host smart-91563c6b-20d1-4b9e-8466-63fb943515c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970556066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.3970556066
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.601730709
Short name T1020
Test name
Test status
Simulation time 2748487395 ps
CPU time 11.59 seconds
Started Jul 28 07:20:39 PM PDT 24
Finished Jul 28 07:20:51 PM PDT 24
Peak memory 233704 kb
Host smart-ab3c33d0-6d89-44e1-971f-98540531f2c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601730709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swap
.601730709
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.3816373917
Short name T621
Test name
Test status
Simulation time 1226733683 ps
CPU time 4.43 seconds
Started Jul 28 07:20:38 PM PDT 24
Finished Jul 28 07:20:43 PM PDT 24
Peak memory 233692 kb
Host smart-f5301a90-1871-490c-940d-099d51cb673d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816373917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.3816373917
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.816015270
Short name T155
Test name
Test status
Simulation time 1689756788 ps
CPU time 17.34 seconds
Started Jul 28 07:20:46 PM PDT 24
Finished Jul 28 07:21:03 PM PDT 24
Peak memory 221344 kb
Host smart-3593ea1c-ecbd-402f-9b3c-c9c325ac059a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=816015270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dire
ct.816015270
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.2669934139
Short name T825
Test name
Test status
Simulation time 3651561195 ps
CPU time 45.68 seconds
Started Jul 28 07:20:46 PM PDT 24
Finished Jul 28 07:21:32 PM PDT 24
Peak memory 250056 kb
Host smart-95643b4e-979b-4649-b9c9-9f8b86d1a2b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669934139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.2669934139
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.2603196714
Short name T499
Test name
Test status
Simulation time 13497395 ps
CPU time 0.79 seconds
Started Jul 28 07:20:46 PM PDT 24
Finished Jul 28 07:20:47 PM PDT 24
Peak memory 206348 kb
Host smart-c3d0bc36-7e03-4948-84af-6b20971ae791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603196714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.2603196714
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.3183710408
Short name T643
Test name
Test status
Simulation time 464811036 ps
CPU time 1.25 seconds
Started Jul 28 07:20:40 PM PDT 24
Finished Jul 28 07:20:41 PM PDT 24
Peak memory 208560 kb
Host smart-5e4111a2-68ac-4749-bafb-79635bbea29c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183710408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.3183710408
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.122581111
Short name T913
Test name
Test status
Simulation time 243958802 ps
CPU time 2.94 seconds
Started Jul 28 07:20:41 PM PDT 24
Finished Jul 28 07:20:44 PM PDT 24
Peak memory 217160 kb
Host smart-600bbf73-ec4a-4d24-9df2-a71cff455b6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122581111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.122581111
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.2105848529
Short name T1006
Test name
Test status
Simulation time 72750191 ps
CPU time 0.97 seconds
Started Jul 28 07:20:40 PM PDT 24
Finished Jul 28 07:20:42 PM PDT 24
Peak memory 206792 kb
Host smart-17771601-be1e-441d-a80a-327d25690cd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105848529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.2105848529
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.1592524971
Short name T424
Test name
Test status
Simulation time 1107635222 ps
CPU time 5.68 seconds
Started Jul 28 07:20:41 PM PDT 24
Finished Jul 28 07:20:47 PM PDT 24
Peak memory 225496 kb
Host smart-d3ee4e53-ea9d-43e5-85dc-7aad446092c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592524971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.1592524971
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.4223651211
Short name T675
Test name
Test status
Simulation time 18228393 ps
CPU time 0.72 seconds
Started Jul 28 07:20:48 PM PDT 24
Finished Jul 28 07:20:48 PM PDT 24
Peak memory 206048 kb
Host smart-374a8681-f2e5-4745-8720-593bc2c0dc35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223651211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
4223651211
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.1309747276
Short name T814
Test name
Test status
Simulation time 5773384412 ps
CPU time 10.2 seconds
Started Jul 28 07:20:46 PM PDT 24
Finished Jul 28 07:20:56 PM PDT 24
Peak memory 233736 kb
Host smart-c0099814-cabe-4537-bc1e-dd8e0f91a9c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309747276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.1309747276
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.764206875
Short name T341
Test name
Test status
Simulation time 28507030 ps
CPU time 0.84 seconds
Started Jul 28 07:20:44 PM PDT 24
Finished Jul 28 07:20:45 PM PDT 24
Peak memory 207280 kb
Host smart-efcc4576-3b0e-46df-93ea-7e7646b40de9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764206875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.764206875
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.2005311381
Short name T302
Test name
Test status
Simulation time 48436658834 ps
CPU time 357.8 seconds
Started Jul 28 07:20:50 PM PDT 24
Finished Jul 28 07:26:47 PM PDT 24
Peak memory 265752 kb
Host smart-711f6f21-cb81-44ec-9bbd-9a1e540e10e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005311381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.2005311381
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.2007690379
Short name T300
Test name
Test status
Simulation time 3877967224 ps
CPU time 98.35 seconds
Started Jul 28 07:20:48 PM PDT 24
Finished Jul 28 07:22:27 PM PDT 24
Peak memory 263096 kb
Host smart-d7de6e2d-1e24-45cf-ade0-0868812e3b6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007690379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.2007690379
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.4104316809
Short name T313
Test name
Test status
Simulation time 5211645948 ps
CPU time 33.6 seconds
Started Jul 28 07:20:49 PM PDT 24
Finished Jul 28 07:21:23 PM PDT 24
Peak memory 233708 kb
Host smart-c9d58626-aaed-4e5e-bfee-b6d01e4603dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104316809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.4104316809
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.3636161541
Short name T743
Test name
Test status
Simulation time 1201748524 ps
CPU time 10.74 seconds
Started Jul 28 07:20:50 PM PDT 24
Finished Jul 28 07:21:01 PM PDT 24
Peak memory 225420 kb
Host smart-afbb76ed-bb5d-486a-a3b9-4a39787d2426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636161541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmd
s.3636161541
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/31.spi_device_intercept.3453173232
Short name T828
Test name
Test status
Simulation time 35291665 ps
CPU time 2.33 seconds
Started Jul 28 07:20:51 PM PDT 24
Finished Jul 28 07:20:54 PM PDT 24
Peak memory 227624 kb
Host smart-8dc5dda4-d57a-4224-b39e-e6647435346a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453173232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.3453173232
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.1107399968
Short name T524
Test name
Test status
Simulation time 2306819206 ps
CPU time 14.59 seconds
Started Jul 28 07:20:48 PM PDT 24
Finished Jul 28 07:21:03 PM PDT 24
Peak memory 236676 kb
Host smart-3f012fda-dcf8-4843-9fea-aa473235ec1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107399968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.1107399968
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.1256440188
Short name T826
Test name
Test status
Simulation time 556453865 ps
CPU time 5.53 seconds
Started Jul 28 07:20:50 PM PDT 24
Finished Jul 28 07:20:56 PM PDT 24
Peak memory 225440 kb
Host smart-420d43c4-8f1e-4554-bf40-a5d0295de4da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256440188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.1256440188
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.2799086443
Short name T256
Test name
Test status
Simulation time 1450450114 ps
CPU time 11.27 seconds
Started Jul 28 07:20:45 PM PDT 24
Finished Jul 28 07:20:57 PM PDT 24
Peak memory 233824 kb
Host smart-4aa6dd3d-c3f3-4f57-86af-a0a883219ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799086443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.2799086443
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.3050886674
Short name T848
Test name
Test status
Simulation time 528765678 ps
CPU time 3.75 seconds
Started Jul 28 07:20:49 PM PDT 24
Finished Jul 28 07:20:53 PM PDT 24
Peak memory 223848 kb
Host smart-b9ae28f5-4277-4417-9374-a50441478485
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3050886674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.3050886674
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.3008578102
Short name T984
Test name
Test status
Simulation time 4677997948 ps
CPU time 87.62 seconds
Started Jul 28 07:20:50 PM PDT 24
Finished Jul 28 07:22:18 PM PDT 24
Peak memory 250164 kb
Host smart-5d02643e-10f0-4cb1-a330-cd8eb9e02750
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008578102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.3008578102
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.1686409343
Short name T369
Test name
Test status
Simulation time 5186541066 ps
CPU time 21.71 seconds
Started Jul 28 07:20:44 PM PDT 24
Finished Jul 28 07:21:06 PM PDT 24
Peak memory 220940 kb
Host smart-382bb424-dfa5-477f-9de2-0beec73bb8ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686409343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.1686409343
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.1777668660
Short name T11
Test name
Test status
Simulation time 5991065111 ps
CPU time 16.45 seconds
Started Jul 28 07:20:43 PM PDT 24
Finished Jul 28 07:21:00 PM PDT 24
Peak memory 217248 kb
Host smart-102346c2-9398-4c3e-9e6e-a6a0bd2a3b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777668660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.1777668660
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.2274820739
Short name T748
Test name
Test status
Simulation time 75484191 ps
CPU time 1.37 seconds
Started Jul 28 07:20:45 PM PDT 24
Finished Jul 28 07:20:47 PM PDT 24
Peak memory 217360 kb
Host smart-b4f44300-9f16-4e9f-8744-bc36fec34173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274820739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.2274820739
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.2913211181
Short name T405
Test name
Test status
Simulation time 47985698 ps
CPU time 0.74 seconds
Started Jul 28 07:20:44 PM PDT 24
Finished Jul 28 07:20:45 PM PDT 24
Peak memory 206780 kb
Host smart-41f5171c-9122-4e85-b5b2-aeb7cf2f0300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913211181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.2913211181
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.539853605
Short name T493
Test name
Test status
Simulation time 5302489804 ps
CPU time 6.47 seconds
Started Jul 28 07:20:50 PM PDT 24
Finished Jul 28 07:20:57 PM PDT 24
Peak memory 233668 kb
Host smart-6ab36817-b50b-439d-a9f3-2b14f32de74e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539853605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.539853605
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.271346878
Short name T142
Test name
Test status
Simulation time 53374169 ps
CPU time 0.75 seconds
Started Jul 28 07:20:53 PM PDT 24
Finished Jul 28 07:20:54 PM PDT 24
Peak memory 205480 kb
Host smart-6b35896e-5da7-4123-a98d-0f9999833a68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271346878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.271346878
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.584827912
Short name T693
Test name
Test status
Simulation time 648037582 ps
CPU time 4.74 seconds
Started Jul 28 07:20:49 PM PDT 24
Finished Jul 28 07:20:54 PM PDT 24
Peak memory 225432 kb
Host smart-0aa3f51b-8c7e-41cf-8bb4-a72687c0be41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584827912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.584827912
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.600444047
Short name T402
Test name
Test status
Simulation time 57429361 ps
CPU time 0.8 seconds
Started Jul 28 07:20:49 PM PDT 24
Finished Jul 28 07:20:50 PM PDT 24
Peak memory 207252 kb
Host smart-e431fea2-edf1-43b6-aee5-542169e959e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600444047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.600444047
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.3855676960
Short name T706
Test name
Test status
Simulation time 11936265904 ps
CPU time 13.58 seconds
Started Jul 28 07:20:52 PM PDT 24
Finished Jul 28 07:21:06 PM PDT 24
Peak memory 236076 kb
Host smart-ea59e470-ef32-4876-b81f-4cf3684e10bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855676960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.3855676960
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.3707888771
Short name T26
Test name
Test status
Simulation time 39718597013 ps
CPU time 98.17 seconds
Started Jul 28 07:20:53 PM PDT 24
Finished Jul 28 07:22:31 PM PDT 24
Peak memory 238588 kb
Host smart-731247c0-cc19-4993-95f9-097df7897322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707888771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.3707888771
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.995364393
Short name T62
Test name
Test status
Simulation time 34269989806 ps
CPU time 138.67 seconds
Started Jul 28 07:20:53 PM PDT 24
Finished Jul 28 07:23:12 PM PDT 24
Peak memory 256972 kb
Host smart-27e8c67e-ee59-4aa6-a3e7-2f66ebdbfd35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995364393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idle
.995364393
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.3943697210
Short name T944
Test name
Test status
Simulation time 155887608 ps
CPU time 5 seconds
Started Jul 28 07:20:51 PM PDT 24
Finished Jul 28 07:20:56 PM PDT 24
Peak memory 225404 kb
Host smart-5bde5b4d-bf9d-414f-abd6-2019e237a07a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943697210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.3943697210
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.1405553005
Short name T421
Test name
Test status
Simulation time 7045576247 ps
CPU time 17.58 seconds
Started Jul 28 07:20:52 PM PDT 24
Finished Jul 28 07:21:09 PM PDT 24
Peak memory 240552 kb
Host smart-a67e447d-21d7-48c1-9bfc-05b7eb74984d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405553005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmd
s.1405553005
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_intercept.598423213
Short name T667
Test name
Test status
Simulation time 97232678 ps
CPU time 3.58 seconds
Started Jul 28 07:20:48 PM PDT 24
Finished Jul 28 07:20:52 PM PDT 24
Peak memory 233644 kb
Host smart-cda8dc22-0dfd-447e-8701-0775334b56f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598423213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.598423213
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.3828912233
Short name T792
Test name
Test status
Simulation time 21058147335 ps
CPU time 72.58 seconds
Started Jul 28 07:20:51 PM PDT 24
Finished Jul 28 07:22:04 PM PDT 24
Peak memory 225480 kb
Host smart-6c581f71-0c8e-41bd-a4d0-8be0286f8f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828912233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.3828912233
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.520034449
Short name T1013
Test name
Test status
Simulation time 2050529706 ps
CPU time 4.88 seconds
Started Jul 28 07:20:49 PM PDT 24
Finished Jul 28 07:20:54 PM PDT 24
Peak memory 233624 kb
Host smart-bb3ba567-9fb0-4dba-b6d1-31041c33fac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520034449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swap
.520034449
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.1090037109
Short name T178
Test name
Test status
Simulation time 18696334935 ps
CPU time 23.17 seconds
Started Jul 28 07:20:49 PM PDT 24
Finished Jul 28 07:21:12 PM PDT 24
Peak memory 233608 kb
Host smart-84d797da-0860-44fa-a2ba-125428a7275c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090037109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.1090037109
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.1340228346
Short name T446
Test name
Test status
Simulation time 1349281500 ps
CPU time 18.98 seconds
Started Jul 28 07:20:55 PM PDT 24
Finished Jul 28 07:21:14 PM PDT 24
Peak memory 221484 kb
Host smart-45307115-e077-4e7a-941c-5c028aff3d45
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1340228346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.1340228346
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.2962861279
Short name T17
Test name
Test status
Simulation time 36583166239 ps
CPU time 319.59 seconds
Started Jul 28 07:20:52 PM PDT 24
Finished Jul 28 07:26:12 PM PDT 24
Peak memory 270852 kb
Host smart-7b27c0da-ff39-4889-8859-bcdd56a5b30e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962861279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.2962861279
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.3397305857
Short name T922
Test name
Test status
Simulation time 3791045267 ps
CPU time 2.38 seconds
Started Jul 28 07:20:46 PM PDT 24
Finished Jul 28 07:20:49 PM PDT 24
Peak memory 217364 kb
Host smart-2816ada1-a6a8-418c-8377-63b7daf1aa7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397305857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.3397305857
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.3818755484
Short name T701
Test name
Test status
Simulation time 3418910778 ps
CPU time 3.07 seconds
Started Jul 28 07:20:49 PM PDT 24
Finished Jul 28 07:20:52 PM PDT 24
Peak memory 217256 kb
Host smart-4f3680eb-3fa0-4bca-afd9-7daacb62df95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818755484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.3818755484
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.1579055450
Short name T977
Test name
Test status
Simulation time 11058360 ps
CPU time 0.73 seconds
Started Jul 28 07:20:53 PM PDT 24
Finished Jul 28 07:20:54 PM PDT 24
Peak memory 206312 kb
Host smart-476798b6-8941-43ee-98e9-dd7dffecb72b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579055450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.1579055450
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.2181520771
Short name T907
Test name
Test status
Simulation time 25153494 ps
CPU time 0.74 seconds
Started Jul 28 07:20:49 PM PDT 24
Finished Jul 28 07:20:50 PM PDT 24
Peak memory 206776 kb
Host smart-23e38512-e502-40d4-97f8-50bafb6b0884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181520771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.2181520771
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.2042039490
Short name T760
Test name
Test status
Simulation time 2203045973 ps
CPU time 5.52 seconds
Started Jul 28 07:20:49 PM PDT 24
Finished Jul 28 07:20:54 PM PDT 24
Peak memory 225500 kb
Host smart-75db1d48-2cc8-4721-9def-7882a9eb1f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042039490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.2042039490
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.787159265
Short name T346
Test name
Test status
Simulation time 16079616 ps
CPU time 0.73 seconds
Started Jul 28 07:20:57 PM PDT 24
Finished Jul 28 07:20:58 PM PDT 24
Peak memory 206064 kb
Host smart-8214bd37-cf37-43a7-bd66-addf2c4442a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787159265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.787159265
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.1681358857
Short name T246
Test name
Test status
Simulation time 1177729274 ps
CPU time 10.86 seconds
Started Jul 28 07:20:54 PM PDT 24
Finished Jul 28 07:21:05 PM PDT 24
Peak memory 225444 kb
Host smart-652816ad-0713-4780-9aff-084a0ef2c227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681358857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.1681358857
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.496910124
Short name T731
Test name
Test status
Simulation time 17436155 ps
CPU time 0.83 seconds
Started Jul 28 07:20:55 PM PDT 24
Finished Jul 28 07:20:55 PM PDT 24
Peak memory 207540 kb
Host smart-c3e0f17f-3973-4daf-9432-14c32035ada5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496910124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.496910124
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.1563775350
Short name T90
Test name
Test status
Simulation time 8457948323 ps
CPU time 58.52 seconds
Started Jul 28 07:20:57 PM PDT 24
Finished Jul 28 07:21:55 PM PDT 24
Peak memory 250080 kb
Host smart-6c1dafce-099f-4ab4-b827-7df3a3b91d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563775350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.1563775350
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.1634850361
Short name T620
Test name
Test status
Simulation time 64824210630 ps
CPU time 148.98 seconds
Started Jul 28 07:20:59 PM PDT 24
Finished Jul 28 07:23:28 PM PDT 24
Peak memory 251540 kb
Host smart-7bd41509-2b11-4f2b-9c11-9650d1039f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634850361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.1634850361
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.450540156
Short name T61
Test name
Test status
Simulation time 19488979706 ps
CPU time 196.75 seconds
Started Jul 28 07:20:57 PM PDT 24
Finished Jul 28 07:24:14 PM PDT 24
Peak memory 251252 kb
Host smart-1c6c5788-5d25-4200-af22-6d54a0b848e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450540156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idle
.450540156
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.2835400008
Short name T653
Test name
Test status
Simulation time 212990474 ps
CPU time 4.34 seconds
Started Jul 28 07:20:59 PM PDT 24
Finished Jul 28 07:21:04 PM PDT 24
Peak memory 225484 kb
Host smart-ddbc7280-ceae-4a09-a9b8-127cd96fd1dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835400008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.2835400008
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.3978123942
Short name T933
Test name
Test status
Simulation time 29236745181 ps
CPU time 216.65 seconds
Started Jul 28 07:20:57 PM PDT 24
Finished Jul 28 07:24:34 PM PDT 24
Peak memory 255936 kb
Host smart-44dbdee9-fd0a-470f-8234-ec78a9a25c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978123942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmd
s.3978123942
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_intercept.2735853881
Short name T202
Test name
Test status
Simulation time 522741209 ps
CPU time 5.01 seconds
Started Jul 28 07:20:54 PM PDT 24
Finished Jul 28 07:20:59 PM PDT 24
Peak memory 225492 kb
Host smart-0f9f06b2-250f-4f8a-b444-b02de493f29a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735853881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.2735853881
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.2060021783
Short name T980
Test name
Test status
Simulation time 5943258584 ps
CPU time 22.42 seconds
Started Jul 28 07:20:52 PM PDT 24
Finished Jul 28 07:21:14 PM PDT 24
Peak memory 233728 kb
Host smart-babac73a-1bd6-49e3-8284-0b2f576844a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060021783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.2060021783
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.1094551208
Short name T668
Test name
Test status
Simulation time 4652342869 ps
CPU time 20.15 seconds
Started Jul 28 07:20:54 PM PDT 24
Finished Jul 28 07:21:14 PM PDT 24
Peak memory 233780 kb
Host smart-ec95ec85-024e-4e50-b3ae-4a326137ae7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094551208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.1094551208
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.1906241236
Short name T278
Test name
Test status
Simulation time 554560106 ps
CPU time 5.12 seconds
Started Jul 28 07:20:54 PM PDT 24
Finished Jul 28 07:20:59 PM PDT 24
Peak memory 233688 kb
Host smart-753abfd4-3049-477f-9bf8-e3ef4db332ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906241236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.1906241236
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.39681614
Short name T476
Test name
Test status
Simulation time 113120562 ps
CPU time 4.45 seconds
Started Jul 28 07:20:57 PM PDT 24
Finished Jul 28 07:21:02 PM PDT 24
Peak memory 223204 kb
Host smart-43fdd0e9-859e-438e-a416-d7b0f90a6fd1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=39681614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_direc
t.39681614
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.2648665179
Short name T779
Test name
Test status
Simulation time 150920507272 ps
CPU time 303.91 seconds
Started Jul 28 07:20:58 PM PDT 24
Finished Jul 28 07:26:02 PM PDT 24
Peak memory 273800 kb
Host smart-7cb6b4e9-ebfc-48f3-9dc7-a0fb6dea3a54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648665179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.2648665179
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.1644241347
Short name T816
Test name
Test status
Simulation time 54837671 ps
CPU time 0.72 seconds
Started Jul 28 07:20:55 PM PDT 24
Finished Jul 28 07:20:56 PM PDT 24
Peak memory 206356 kb
Host smart-a6534796-d97c-45d2-a731-7ba5e9372a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644241347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.1644241347
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.3397404308
Short name T965
Test name
Test status
Simulation time 1683639781 ps
CPU time 3.55 seconds
Started Jul 28 07:20:53 PM PDT 24
Finished Jul 28 07:20:57 PM PDT 24
Peak memory 217180 kb
Host smart-ca24f517-5795-434c-9e63-d0d5fbd4f77c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397404308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.3397404308
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.2032607784
Short name T773
Test name
Test status
Simulation time 22354955 ps
CPU time 1.24 seconds
Started Jul 28 07:20:54 PM PDT 24
Finished Jul 28 07:20:56 PM PDT 24
Peak memory 209024 kb
Host smart-93714846-32e8-4541-a800-0f4b9226a628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032607784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.2032607784
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.1937642206
Short name T622
Test name
Test status
Simulation time 162465869 ps
CPU time 0.84 seconds
Started Jul 28 07:20:53 PM PDT 24
Finished Jul 28 07:20:54 PM PDT 24
Peak memory 206816 kb
Host smart-13440ef2-66d3-451c-b831-c9190e2cbe3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937642206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.1937642206
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.2421486790
Short name T879
Test name
Test status
Simulation time 15389560514 ps
CPU time 22.18 seconds
Started Jul 28 07:20:53 PM PDT 24
Finished Jul 28 07:21:15 PM PDT 24
Peak memory 233672 kb
Host smart-a011a193-8f89-46d9-953b-9271280841f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421486790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.2421486790
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.630116342
Short name T796
Test name
Test status
Simulation time 35585843 ps
CPU time 0.75 seconds
Started Jul 28 07:21:07 PM PDT 24
Finished Jul 28 07:21:08 PM PDT 24
Peak memory 206132 kb
Host smart-26f1f763-6c30-4934-90cc-a258a6fa3e23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630116342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.630116342
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.74257898
Short name T888
Test name
Test status
Simulation time 56344176 ps
CPU time 2.48 seconds
Started Jul 28 07:21:02 PM PDT 24
Finished Jul 28 07:21:05 PM PDT 24
Peak memory 233668 kb
Host smart-115fcde2-fee3-4960-ae87-fa59c37be07a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74257898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.74257898
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.3572152055
Short name T349
Test name
Test status
Simulation time 14916297 ps
CPU time 0.76 seconds
Started Jul 28 07:20:54 PM PDT 24
Finished Jul 28 07:20:55 PM PDT 24
Peak memory 206280 kb
Host smart-0bc3d756-484d-40b3-813d-d99ee4e4232c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572152055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.3572152055
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.1311252150
Short name T305
Test name
Test status
Simulation time 10041346816 ps
CPU time 55.7 seconds
Started Jul 28 07:21:03 PM PDT 24
Finished Jul 28 07:21:59 PM PDT 24
Peak memory 256340 kb
Host smart-578e52f7-5a8f-4df0-af5f-420528a30a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311252150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.1311252150
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.2804829407
Short name T303
Test name
Test status
Simulation time 2877104949 ps
CPU time 33.99 seconds
Started Jul 28 07:21:08 PM PDT 24
Finished Jul 28 07:21:42 PM PDT 24
Peak memory 237528 kb
Host smart-6bc985da-e3ad-4a85-9ed3-33bcd36eccd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804829407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.2804829407
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.1647467120
Short name T309
Test name
Test status
Simulation time 721542703 ps
CPU time 10.46 seconds
Started Jul 28 07:21:03 PM PDT 24
Finished Jul 28 07:21:14 PM PDT 24
Peak memory 238276 kb
Host smart-ad687e12-0035-4814-bc48-733feec06a2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647467120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.1647467120
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.210646845
Short name T552
Test name
Test status
Simulation time 107710683 ps
CPU time 3.92 seconds
Started Jul 28 07:21:02 PM PDT 24
Finished Jul 28 07:21:06 PM PDT 24
Peak memory 233956 kb
Host smart-c010bb07-e4c7-40db-9a55-69e155044c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210646845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.210646845
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_intercept.713248822
Short name T836
Test name
Test status
Simulation time 224362057 ps
CPU time 2.35 seconds
Started Jul 28 07:21:00 PM PDT 24
Finished Jul 28 07:21:03 PM PDT 24
Peak memory 225444 kb
Host smart-271789bf-a5c0-4627-8f1f-3ea52face5e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713248822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.713248822
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.258607294
Short name T630
Test name
Test status
Simulation time 1877415915 ps
CPU time 17.83 seconds
Started Jul 28 07:21:02 PM PDT 24
Finished Jul 28 07:21:20 PM PDT 24
Peak memory 225384 kb
Host smart-943c1c0c-b0ba-450c-a056-632ad1752444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258607294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.258607294
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.2290841003
Short name T890
Test name
Test status
Simulation time 15750188888 ps
CPU time 12.91 seconds
Started Jul 28 07:21:02 PM PDT 24
Finished Jul 28 07:21:14 PM PDT 24
Peak memory 239264 kb
Host smart-13b8960b-9ade-400c-9f99-c3210f20dc3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290841003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.2290841003
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.1451195702
Short name T844
Test name
Test status
Simulation time 77755614 ps
CPU time 2.13 seconds
Started Jul 28 07:21:01 PM PDT 24
Finished Jul 28 07:21:03 PM PDT 24
Peak memory 224960 kb
Host smart-210537e8-179b-443b-a92e-5f994ef5ad65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451195702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.1451195702
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.2377480766
Short name T504
Test name
Test status
Simulation time 1305288232 ps
CPU time 4.35 seconds
Started Jul 28 07:21:01 PM PDT 24
Finished Jul 28 07:21:05 PM PDT 24
Peak memory 219848 kb
Host smart-f0b4b4b1-41a4-4ed8-9804-6e785fd9aa1a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2377480766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.2377480766
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.117194553
Short name T1024
Test name
Test status
Simulation time 299952782185 ps
CPU time 475.97 seconds
Started Jul 28 07:21:08 PM PDT 24
Finished Jul 28 07:29:04 PM PDT 24
Peak memory 258316 kb
Host smart-3dc1294e-4c91-42ec-955b-baaca04aebb7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117194553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stres
s_all.117194553
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.427910746
Short name T1000
Test name
Test status
Simulation time 7652413707 ps
CPU time 44.48 seconds
Started Jul 28 07:20:58 PM PDT 24
Finished Jul 28 07:21:43 PM PDT 24
Peak memory 217300 kb
Host smart-2b48ec6a-7e2a-4eae-ae9e-2673a6dc9736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427910746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.427910746
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.2213271343
Short name T842
Test name
Test status
Simulation time 6417180975 ps
CPU time 5.59 seconds
Started Jul 28 07:20:57 PM PDT 24
Finished Jul 28 07:21:02 PM PDT 24
Peak memory 217180 kb
Host smart-d9b7b204-89a7-4440-8eba-b4a8943d8bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213271343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.2213271343
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.900974642
Short name T81
Test name
Test status
Simulation time 38213372 ps
CPU time 1.33 seconds
Started Jul 28 07:21:00 PM PDT 24
Finished Jul 28 07:21:02 PM PDT 24
Peak memory 217244 kb
Host smart-ae9dba7c-1af1-43fb-aca7-de1a0898ac3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900974642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.900974642
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.722882885
Short name T364
Test name
Test status
Simulation time 213949102 ps
CPU time 0.94 seconds
Started Jul 28 07:21:01 PM PDT 24
Finished Jul 28 07:21:02 PM PDT 24
Peak memory 207756 kb
Host smart-743f4bb3-d767-4224-a58a-481fd8499a24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722882885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.722882885
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.2108483497
Short name T606
Test name
Test status
Simulation time 57320821112 ps
CPU time 44.67 seconds
Started Jul 28 07:21:02 PM PDT 24
Finished Jul 28 07:21:46 PM PDT 24
Peak memory 249960 kb
Host smart-e4d29f5b-e803-4665-b231-40f6da32898b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108483497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.2108483497
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.977203775
Short name T392
Test name
Test status
Simulation time 14846673 ps
CPU time 0.75 seconds
Started Jul 28 07:21:12 PM PDT 24
Finished Jul 28 07:21:13 PM PDT 24
Peak memory 206068 kb
Host smart-98cae08e-4686-4109-9a86-60a4605d3f1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977203775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.977203775
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.3378536988
Short name T438
Test name
Test status
Simulation time 532937617 ps
CPU time 6.26 seconds
Started Jul 28 07:21:06 PM PDT 24
Finished Jul 28 07:21:13 PM PDT 24
Peak memory 233564 kb
Host smart-52149c0f-9bc1-4462-8506-69f8433583d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378536988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.3378536988
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.2405351735
Short name T374
Test name
Test status
Simulation time 61870466 ps
CPU time 0.77 seconds
Started Jul 28 07:21:08 PM PDT 24
Finished Jul 28 07:21:09 PM PDT 24
Peak memory 207244 kb
Host smart-76179e4f-13ba-4651-9073-f180c8703515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405351735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.2405351735
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.46095641
Short name T860
Test name
Test status
Simulation time 83748389518 ps
CPU time 576.52 seconds
Started Jul 28 07:21:09 PM PDT 24
Finished Jul 28 07:30:46 PM PDT 24
Peak memory 267604 kb
Host smart-448f8f86-b585-4660-bdb0-db61f0c2c40f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46095641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.46095641
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.3321980143
Short name T725
Test name
Test status
Simulation time 44626997030 ps
CPU time 191.56 seconds
Started Jul 28 07:21:11 PM PDT 24
Finished Jul 28 07:24:22 PM PDT 24
Peak memory 254912 kb
Host smart-2b53085a-79ff-44ec-a1e8-75cc31a65888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321980143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.3321980143
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.2044427887
Short name T91
Test name
Test status
Simulation time 4653748861 ps
CPU time 89.58 seconds
Started Jul 28 07:21:13 PM PDT 24
Finished Jul 28 07:22:42 PM PDT 24
Peak memory 258292 kb
Host smart-f061e0b7-0532-47a0-a4f1-c23f45518aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044427887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.2044427887
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.2172131456
Short name T24
Test name
Test status
Simulation time 744069691 ps
CPU time 10.54 seconds
Started Jul 28 07:21:07 PM PDT 24
Finished Jul 28 07:21:18 PM PDT 24
Peak memory 250140 kb
Host smart-28dca85c-2d94-4cf2-a6f4-873fde51a3d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172131456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.2172131456
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.683728986
Short name T759
Test name
Test status
Simulation time 139947598497 ps
CPU time 212.41 seconds
Started Jul 28 07:21:10 PM PDT 24
Finished Jul 28 07:24:43 PM PDT 24
Peak memory 257208 kb
Host smart-a436c972-01ec-4215-a09e-bbdef3dbd2e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683728986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmds
.683728986
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/35.spi_device_intercept.458594945
Short name T966
Test name
Test status
Simulation time 38628977 ps
CPU time 2.63 seconds
Started Jul 28 07:21:06 PM PDT 24
Finished Jul 28 07:21:09 PM PDT 24
Peak memory 233600 kb
Host smart-788691ea-90a6-4008-a0c7-4d855ab293a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458594945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.458594945
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.518908285
Short name T742
Test name
Test status
Simulation time 291281241 ps
CPU time 2.52 seconds
Started Jul 28 07:21:06 PM PDT 24
Finished Jul 28 07:21:09 PM PDT 24
Peak memory 225488 kb
Host smart-2e8e71b3-d20d-47b0-905d-48df8629a024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518908285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.518908285
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.1353724817
Short name T744
Test name
Test status
Simulation time 1254168078 ps
CPU time 9.56 seconds
Started Jul 28 07:21:06 PM PDT 24
Finished Jul 28 07:21:15 PM PDT 24
Peak memory 234724 kb
Host smart-5e4f65e9-acf8-42d8-aa1c-570a7aeef8e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353724817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.1353724817
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.4010069637
Short name T252
Test name
Test status
Simulation time 145742442 ps
CPU time 3.65 seconds
Started Jul 28 07:21:05 PM PDT 24
Finished Jul 28 07:21:09 PM PDT 24
Peak memory 225456 kb
Host smart-de8a4f7e-871c-49ba-a412-b217bdaa25e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010069637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.4010069637
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.3286356673
Short name T908
Test name
Test status
Simulation time 2788016094 ps
CPU time 17.03 seconds
Started Jul 28 07:21:10 PM PDT 24
Finished Jul 28 07:21:27 PM PDT 24
Peak memory 222980 kb
Host smart-18274bdd-3c33-4d6d-ab16-1ccbcaff5f4d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3286356673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.3286356673
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.2123832006
Short name T692
Test name
Test status
Simulation time 147166551 ps
CPU time 0.92 seconds
Started Jul 28 07:21:11 PM PDT 24
Finished Jul 28 07:21:12 PM PDT 24
Peak memory 207420 kb
Host smart-7828d0ba-2c3d-4b93-b7a1-d1b0f8499825
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123832006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.2123832006
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.1284427075
Short name T445
Test name
Test status
Simulation time 5968055721 ps
CPU time 22.44 seconds
Started Jul 28 07:21:08 PM PDT 24
Finished Jul 28 07:21:31 PM PDT 24
Peak memory 217248 kb
Host smart-afb315a8-f4dd-4913-9bfa-0bf2d72f61df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284427075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.1284427075
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.3898454630
Short name T955
Test name
Test status
Simulation time 925218983 ps
CPU time 6.92 seconds
Started Jul 28 07:21:06 PM PDT 24
Finished Jul 28 07:21:13 PM PDT 24
Peak memory 217172 kb
Host smart-fe6a6cd0-1769-423b-9022-cf9ad38ee4d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898454630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.3898454630
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.294330445
Short name T617
Test name
Test status
Simulation time 127025121 ps
CPU time 1.06 seconds
Started Jul 28 07:21:06 PM PDT 24
Finished Jul 28 07:21:07 PM PDT 24
Peak memory 208736 kb
Host smart-6eb9f75e-9ff8-4ed0-9e12-e067565da65b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294330445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.294330445
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.2145482484
Short name T577
Test name
Test status
Simulation time 66480549 ps
CPU time 0.85 seconds
Started Jul 28 07:21:06 PM PDT 24
Finished Jul 28 07:21:07 PM PDT 24
Peak memory 206800 kb
Host smart-4525903e-1bb6-446d-aecf-7684f194130b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145482484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.2145482484
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.2562236383
Short name T71
Test name
Test status
Simulation time 891200688 ps
CPU time 6.77 seconds
Started Jul 28 07:21:06 PM PDT 24
Finished Jul 28 07:21:13 PM PDT 24
Peak memory 233652 kb
Host smart-5c6059a0-2b60-42bb-8459-19b33f3102fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562236383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.2562236383
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.3773813760
Short name T1014
Test name
Test status
Simulation time 13250670 ps
CPU time 0.73 seconds
Started Jul 28 07:21:15 PM PDT 24
Finished Jul 28 07:21:16 PM PDT 24
Peak memory 205496 kb
Host smart-931d829b-3d1a-453f-be5e-58f6a66b371a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773813760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
3773813760
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.2345731187
Short name T436
Test name
Test status
Simulation time 108305584 ps
CPU time 2.88 seconds
Started Jul 28 07:21:19 PM PDT 24
Finished Jul 28 07:21:22 PM PDT 24
Peak memory 225436 kb
Host smart-c120b40c-8d8d-4038-b830-68ae2abb834f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345731187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.2345731187
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.3322611188
Short name T507
Test name
Test status
Simulation time 21592509 ps
CPU time 0.81 seconds
Started Jul 28 07:21:11 PM PDT 24
Finished Jul 28 07:21:12 PM PDT 24
Peak memory 207256 kb
Host smart-9317cc8d-b038-4945-afc8-67c25f2cb865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322611188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.3322611188
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.560141896
Short name T233
Test name
Test status
Simulation time 47814308589 ps
CPU time 176.66 seconds
Started Jul 28 07:21:17 PM PDT 24
Finished Jul 28 07:24:13 PM PDT 24
Peak memory 258304 kb
Host smart-5cf32ec1-bf0d-4368-878a-baa4c154db3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560141896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.560141896
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.2714152515
Short name T781
Test name
Test status
Simulation time 3268627052 ps
CPU time 45.48 seconds
Started Jul 28 07:21:15 PM PDT 24
Finished Jul 28 07:22:01 PM PDT 24
Peak memory 250132 kb
Host smart-ab674bd6-3b70-4c9a-b59e-41d1ceb25177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714152515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.2714152515
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.1592947079
Short name T636
Test name
Test status
Simulation time 62230750 ps
CPU time 2.98 seconds
Started Jul 28 07:21:12 PM PDT 24
Finished Jul 28 07:21:15 PM PDT 24
Peak memory 233600 kb
Host smart-61570f09-743e-4832-9ef6-4173d149e919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592947079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.1592947079
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.2946294487
Short name T487
Test name
Test status
Simulation time 6751275105 ps
CPU time 63.52 seconds
Started Jul 28 07:21:11 PM PDT 24
Finished Jul 28 07:22:14 PM PDT 24
Peak memory 251340 kb
Host smart-3716a28c-878c-40d6-8293-a6d8c85a19e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946294487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmd
s.2946294487
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_intercept.2057734934
Short name T870
Test name
Test status
Simulation time 720601118 ps
CPU time 5.23 seconds
Started Jul 28 07:21:10 PM PDT 24
Finished Jul 28 07:21:16 PM PDT 24
Peak memory 233672 kb
Host smart-c7f10c4f-8543-44a3-92b8-cc411a09d66d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057734934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.2057734934
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.1771682447
Short name T263
Test name
Test status
Simulation time 9379866381 ps
CPU time 117.68 seconds
Started Jul 28 07:21:11 PM PDT 24
Finished Jul 28 07:23:09 PM PDT 24
Peak memory 235448 kb
Host smart-61264042-4ce2-4b79-adee-a595de01a7de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771682447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.1771682447
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.1097676054
Short name T992
Test name
Test status
Simulation time 6987988333 ps
CPU time 6.81 seconds
Started Jul 28 07:21:11 PM PDT 24
Finished Jul 28 07:21:18 PM PDT 24
Peak memory 225456 kb
Host smart-31d1a35e-091e-4345-8a0f-92fb1af53332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097676054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.1097676054
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.1209352436
Short name T649
Test name
Test status
Simulation time 3026383518 ps
CPU time 7.24 seconds
Started Jul 28 07:21:10 PM PDT 24
Finished Jul 28 07:21:17 PM PDT 24
Peak memory 233724 kb
Host smart-beceddd6-2f58-4767-b6a2-4ac7f5c2db5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209352436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.1209352436
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.2113293692
Short name T777
Test name
Test status
Simulation time 9495778891 ps
CPU time 18.67 seconds
Started Jul 28 07:21:10 PM PDT 24
Finished Jul 28 07:21:28 PM PDT 24
Peak memory 224080 kb
Host smart-99e12333-b7b6-4473-a402-11b545ace3d3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2113293692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.2113293692
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.2544903068
Short name T995
Test name
Test status
Simulation time 9112329767 ps
CPU time 59.73 seconds
Started Jul 28 07:21:15 PM PDT 24
Finished Jul 28 07:22:15 PM PDT 24
Peak memory 255604 kb
Host smart-d953d2e6-f78d-4006-aeda-95331dcbc60e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544903068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.2544903068
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.2042477529
Short name T637
Test name
Test status
Simulation time 353998908 ps
CPU time 3.51 seconds
Started Jul 28 07:21:12 PM PDT 24
Finished Jul 28 07:21:15 PM PDT 24
Peak memory 217412 kb
Host smart-ecec5967-812d-47bc-82be-575adc520883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042477529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.2042477529
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.101617854
Short name T538
Test name
Test status
Simulation time 4056460061 ps
CPU time 12.36 seconds
Started Jul 28 07:21:09 PM PDT 24
Finished Jul 28 07:21:22 PM PDT 24
Peak memory 217244 kb
Host smart-4a00d569-d2b0-4c3b-8ddf-623bd22bc806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101617854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.101617854
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.1833414522
Short name T479
Test name
Test status
Simulation time 15853304 ps
CPU time 1.04 seconds
Started Jul 28 07:21:13 PM PDT 24
Finished Jul 28 07:21:14 PM PDT 24
Peak memory 207900 kb
Host smart-49fc452d-c0a5-4a6d-8e95-ab22a6cdce22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833414522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.1833414522
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.2051578391
Short name T549
Test name
Test status
Simulation time 218501632 ps
CPU time 0.87 seconds
Started Jul 28 07:21:09 PM PDT 24
Finished Jul 28 07:21:10 PM PDT 24
Peak memory 206808 kb
Host smart-eb5ead97-2e59-4f89-9751-7873ea7f3fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051578391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.2051578391
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.360686229
Short name T213
Test name
Test status
Simulation time 149894973 ps
CPU time 3.34 seconds
Started Jul 28 07:21:10 PM PDT 24
Finished Jul 28 07:21:13 PM PDT 24
Peak memory 233588 kb
Host smart-360f27de-56af-4cd8-9f04-909caaa248d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360686229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.360686229
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.2791943486
Short name T876
Test name
Test status
Simulation time 18991050 ps
CPU time 0.7 seconds
Started Jul 28 07:21:19 PM PDT 24
Finished Jul 28 07:21:20 PM PDT 24
Peak memory 206064 kb
Host smart-6208fc65-37c5-43ec-b937-966f9b5d77d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791943486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
2791943486
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.3957518255
Short name T247
Test name
Test status
Simulation time 319585205 ps
CPU time 5.7 seconds
Started Jul 28 07:21:21 PM PDT 24
Finished Jul 28 07:21:27 PM PDT 24
Peak memory 233648 kb
Host smart-07ccbe66-7e86-4362-bd20-4bbf5d404703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957518255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.3957518255
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.3638920618
Short name T84
Test name
Test status
Simulation time 42093283 ps
CPU time 0.76 seconds
Started Jul 28 07:21:17 PM PDT 24
Finished Jul 28 07:21:18 PM PDT 24
Peak memory 207284 kb
Host smart-ef54aabc-22a0-4ff1-ba93-d8970660d5f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638920618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.3638920618
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.3447839725
Short name T929
Test name
Test status
Simulation time 9066609952 ps
CPU time 34.89 seconds
Started Jul 28 07:21:22 PM PDT 24
Finished Jul 28 07:21:57 PM PDT 24
Peak memory 239060 kb
Host smart-c2cc3d6c-9eb4-49ba-92fe-dc118d23a747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447839725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.3447839725
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.1507588361
Short name T542
Test name
Test status
Simulation time 49072417051 ps
CPU time 61.32 seconds
Started Jul 28 07:21:19 PM PDT 24
Finished Jul 28 07:22:20 PM PDT 24
Peak memory 250184 kb
Host smart-94a3e433-d82b-4cc8-98c9-b0e2e7fd4df8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507588361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.1507588361
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.3779524792
Short name T941
Test name
Test status
Simulation time 18933878050 ps
CPU time 156.08 seconds
Started Jul 28 07:21:21 PM PDT 24
Finished Jul 28 07:23:58 PM PDT 24
Peak memory 250152 kb
Host smart-ea22ea44-80bd-45ca-a185-5390d825cd55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779524792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.3779524792
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.3059411127
Short name T783
Test name
Test status
Simulation time 56815210 ps
CPU time 2.71 seconds
Started Jul 28 07:21:20 PM PDT 24
Finished Jul 28 07:21:23 PM PDT 24
Peak memory 233652 kb
Host smart-3504e2ea-d80e-430e-918a-e6ec439e958e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059411127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.3059411127
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.3690278859
Short name T38
Test name
Test status
Simulation time 8160085640 ps
CPU time 62.4 seconds
Started Jul 28 07:21:18 PM PDT 24
Finished Jul 28 07:22:20 PM PDT 24
Peak memory 241888 kb
Host smart-d6a1a9cf-97ad-4be8-964a-e1d5e887cb94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690278859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmd
s.3690278859
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/37.spi_device_intercept.49030365
Short name T739
Test name
Test status
Simulation time 611610103 ps
CPU time 8.88 seconds
Started Jul 28 07:21:15 PM PDT 24
Finished Jul 28 07:21:24 PM PDT 24
Peak memory 225492 kb
Host smart-2e1b47f5-2bef-401e-8c2a-db4866c9698f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49030365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.49030365
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.3232187926
Short name T939
Test name
Test status
Simulation time 8168818122 ps
CPU time 58.67 seconds
Started Jul 28 07:21:14 PM PDT 24
Finished Jul 28 07:22:13 PM PDT 24
Peak memory 233696 kb
Host smart-9cd84038-0a6f-4c0f-9b9c-7b0da792173a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232187926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.3232187926
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.1581266202
Short name T396
Test name
Test status
Simulation time 5022154889 ps
CPU time 8.72 seconds
Started Jul 28 07:21:14 PM PDT 24
Finished Jul 28 07:21:23 PM PDT 24
Peak memory 233676 kb
Host smart-cdd2cc92-926b-475a-a7c3-81874032defe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581266202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.1581266202
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.1652976408
Short name T513
Test name
Test status
Simulation time 34117652915 ps
CPU time 16.37 seconds
Started Jul 28 07:21:14 PM PDT 24
Finished Jul 28 07:21:30 PM PDT 24
Peak memory 233728 kb
Host smart-d2bcce2f-ced4-4562-936c-6e7855b7d564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652976408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.1652976408
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.1838170753
Short name T639
Test name
Test status
Simulation time 156208326 ps
CPU time 4.72 seconds
Started Jul 28 07:21:21 PM PDT 24
Finished Jul 28 07:21:25 PM PDT 24
Peak memory 223404 kb
Host smart-5512a1cd-51c1-433e-945c-65685718625d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1838170753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.1838170753
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.3413051102
Short name T325
Test name
Test status
Simulation time 9127796209 ps
CPU time 29.01 seconds
Started Jul 28 07:21:13 PM PDT 24
Finished Jul 28 07:21:43 PM PDT 24
Peak memory 217288 kb
Host smart-1f7469b6-264c-467f-ac70-8b1b7847316f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413051102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.3413051102
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.4010953192
Short name T1016
Test name
Test status
Simulation time 1504238999 ps
CPU time 3.54 seconds
Started Jul 28 07:21:20 PM PDT 24
Finished Jul 28 07:21:23 PM PDT 24
Peak memory 217140 kb
Host smart-3ce77e95-cea2-4865-98c0-48b814738acd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010953192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.4010953192
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.1975340221
Short name T993
Test name
Test status
Simulation time 196061234 ps
CPU time 1.99 seconds
Started Jul 28 07:21:14 PM PDT 24
Finished Jul 28 07:21:16 PM PDT 24
Peak memory 208928 kb
Host smart-19a3099a-9273-484c-bdf6-9f0b0c09724b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975340221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.1975340221
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.2396879120
Short name T452
Test name
Test status
Simulation time 15669608 ps
CPU time 0.78 seconds
Started Jul 28 07:21:16 PM PDT 24
Finished Jul 28 07:21:17 PM PDT 24
Peak memory 206764 kb
Host smart-3f59d086-2aad-4d4c-b8ae-44ea1ed3eda0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396879120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.2396879120
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.1114061896
Short name T481
Test name
Test status
Simulation time 84781081 ps
CPU time 2.34 seconds
Started Jul 28 07:21:23 PM PDT 24
Finished Jul 28 07:21:25 PM PDT 24
Peak memory 225036 kb
Host smart-b88e829f-da4b-4c2a-80de-0deca0dec761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114061896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.1114061896
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.3095375128
Short name T878
Test name
Test status
Simulation time 16145145 ps
CPU time 0.81 seconds
Started Jul 28 07:21:23 PM PDT 24
Finished Jul 28 07:21:24 PM PDT 24
Peak memory 206040 kb
Host smart-5eb3ea05-100f-413b-9c10-e3d9199a539d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095375128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
3095375128
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.4096958532
Short name T680
Test name
Test status
Simulation time 92439365 ps
CPU time 3.11 seconds
Started Jul 28 07:21:23 PM PDT 24
Finished Jul 28 07:21:26 PM PDT 24
Peak memory 225364 kb
Host smart-50bae7ae-f31f-41cb-b6df-d4210ab8cb05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096958532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.4096958532
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.1689320320
Short name T485
Test name
Test status
Simulation time 20511243 ps
CPU time 0.73 seconds
Started Jul 28 07:21:19 PM PDT 24
Finished Jul 28 07:21:20 PM PDT 24
Peak memory 207556 kb
Host smart-76f994d2-1ca8-430c-a6f7-c9b622230b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689320320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.1689320320
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.3860040740
Short name T863
Test name
Test status
Simulation time 67501465540 ps
CPU time 465.7 seconds
Started Jul 28 07:21:23 PM PDT 24
Finished Jul 28 07:29:09 PM PDT 24
Peak memory 257084 kb
Host smart-aee52c0d-3616-4584-a0b0-8eba634cc3d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860040740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.3860040740
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.1150472143
Short name T254
Test name
Test status
Simulation time 210832802611 ps
CPU time 538.16 seconds
Started Jul 28 07:21:24 PM PDT 24
Finished Jul 28 07:30:22 PM PDT 24
Peak memory 258292 kb
Host smart-5b692568-0b1a-4c64-861c-c34b7c5265eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150472143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.1150472143
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.1050907020
Short name T306
Test name
Test status
Simulation time 20816676040 ps
CPU time 147.15 seconds
Started Jul 28 07:21:21 PM PDT 24
Finished Jul 28 07:23:48 PM PDT 24
Peak memory 272236 kb
Host smart-c5dab1bc-3204-4911-a0e8-e3609d93e39d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050907020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.1050907020
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.4186120962
Short name T317
Test name
Test status
Simulation time 956194185 ps
CPU time 20.7 seconds
Started Jul 28 07:21:17 PM PDT 24
Finished Jul 28 07:21:38 PM PDT 24
Peak memory 236348 kb
Host smart-052771fa-4648-41c2-ac88-c911e5b8ddf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186120962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.4186120962
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.1317772846
Short name T981
Test name
Test status
Simulation time 4142608973 ps
CPU time 49.47 seconds
Started Jul 28 07:21:26 PM PDT 24
Finished Jul 28 07:22:15 PM PDT 24
Peak memory 257840 kb
Host smart-dbb01429-2ea3-40fe-afb8-644939a0a6ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317772846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmd
s.1317772846
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/38.spi_device_intercept.3449478568
Short name T690
Test name
Test status
Simulation time 1325491114 ps
CPU time 14.83 seconds
Started Jul 28 07:21:20 PM PDT 24
Finished Jul 28 07:21:35 PM PDT 24
Peak memory 233652 kb
Host smart-fa6117c2-f46e-4a6a-8ffd-0860e7c7df59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449478568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.3449478568
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.1160577772
Short name T530
Test name
Test status
Simulation time 7442048634 ps
CPU time 67.66 seconds
Started Jul 28 07:21:24 PM PDT 24
Finished Jul 28 07:22:32 PM PDT 24
Peak memory 241540 kb
Host smart-babf8345-2467-4b8e-8ff5-e668780d3476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160577772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.1160577772
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.1544422403
Short name T266
Test name
Test status
Simulation time 1860022478 ps
CPU time 7.25 seconds
Started Jul 28 07:21:21 PM PDT 24
Finished Jul 28 07:21:29 PM PDT 24
Peak memory 233628 kb
Host smart-c3f0f095-e972-414b-be52-ae98ec5b5886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544422403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.1544422403
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.2905258171
Short name T253
Test name
Test status
Simulation time 4724416368 ps
CPU time 9.53 seconds
Started Jul 28 07:21:20 PM PDT 24
Finished Jul 28 07:21:29 PM PDT 24
Peak memory 233788 kb
Host smart-20b270d7-49f7-415e-ba5c-574a08b83b10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905258171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.2905258171
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.4251836284
Short name T823
Test name
Test status
Simulation time 2429111543 ps
CPU time 14.2 seconds
Started Jul 28 07:21:25 PM PDT 24
Finished Jul 28 07:21:39 PM PDT 24
Peak memory 223012 kb
Host smart-1606da68-8dc8-4270-92f7-1bc33c7f3543
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4251836284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.4251836284
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.1772098217
Short name T778
Test name
Test status
Simulation time 107218081148 ps
CPU time 281.61 seconds
Started Jul 28 07:21:23 PM PDT 24
Finished Jul 28 07:26:05 PM PDT 24
Peak memory 266252 kb
Host smart-e1b87800-10d4-453e-83aa-40d94e5cb797
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772098217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.1772098217
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.980234440
Short name T678
Test name
Test status
Simulation time 3014593414 ps
CPU time 27.64 seconds
Started Jul 28 07:21:19 PM PDT 24
Finished Jul 28 07:21:46 PM PDT 24
Peak memory 220452 kb
Host smart-8e2ff6a1-28b9-4b42-bff7-74f87a84c780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980234440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.980234440
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.4136631921
Short name T378
Test name
Test status
Simulation time 5419502969 ps
CPU time 16.92 seconds
Started Jul 28 07:21:24 PM PDT 24
Finished Jul 28 07:21:41 PM PDT 24
Peak memory 217260 kb
Host smart-391967b5-aab2-4370-977d-fc65ed101c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136631921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.4136631921
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.1363278805
Short name T914
Test name
Test status
Simulation time 548897290 ps
CPU time 5.5 seconds
Started Jul 28 07:21:21 PM PDT 24
Finished Jul 28 07:21:27 PM PDT 24
Peak memory 217196 kb
Host smart-66b5eed8-bddb-45c5-91fa-a7dabfd9a07a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363278805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.1363278805
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.400832488
Short name T531
Test name
Test status
Simulation time 112396943 ps
CPU time 0.91 seconds
Started Jul 28 07:21:18 PM PDT 24
Finished Jul 28 07:21:19 PM PDT 24
Peak memory 207000 kb
Host smart-f65b047e-e56e-4340-b5b6-8353d6a1676b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400832488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.400832488
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.2649534819
Short name T245
Test name
Test status
Simulation time 1062055118 ps
CPU time 4.98 seconds
Started Jul 28 07:21:24 PM PDT 24
Finished Jul 28 07:21:29 PM PDT 24
Peak memory 233668 kb
Host smart-ea79beb4-0b93-483f-b967-873a5297e735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649534819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.2649534819
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.3501692887
Short name T550
Test name
Test status
Simulation time 40268375 ps
CPU time 0.76 seconds
Started Jul 28 07:21:30 PM PDT 24
Finished Jul 28 07:21:31 PM PDT 24
Peak memory 206380 kb
Host smart-86bd3ab4-0a0b-4fcd-8c87-cf658a8e635b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501692887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
3501692887
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.1318714606
Short name T597
Test name
Test status
Simulation time 1871002650 ps
CPU time 7.72 seconds
Started Jul 28 07:21:26 PM PDT 24
Finished Jul 28 07:21:33 PM PDT 24
Peak memory 225176 kb
Host smart-90c71044-1469-4089-b6b2-2126f387654b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318714606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.1318714606
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.2425311104
Short name T543
Test name
Test status
Simulation time 205683012 ps
CPU time 0.8 seconds
Started Jul 28 07:21:23 PM PDT 24
Finished Jul 28 07:21:24 PM PDT 24
Peak memory 207576 kb
Host smart-342134dc-c27c-4505-a1dc-757fd7a57c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425311104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.2425311104
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.1644084607
Short name T223
Test name
Test status
Simulation time 3292904010 ps
CPU time 35.36 seconds
Started Jul 28 07:21:27 PM PDT 24
Finished Jul 28 07:22:03 PM PDT 24
Peak memory 241900 kb
Host smart-402e86c6-05f2-4b32-9234-330e8653a418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644084607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.1644084607
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.3201183327
Short name T899
Test name
Test status
Simulation time 4445611497 ps
CPU time 64.85 seconds
Started Jul 28 07:21:26 PM PDT 24
Finished Jul 28 07:22:31 PM PDT 24
Peak memory 256264 kb
Host smart-8be7f173-2d38-45ce-b168-68addd7e22f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201183327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.3201183327
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.75156715
Short name T370
Test name
Test status
Simulation time 117794390 ps
CPU time 2.62 seconds
Started Jul 28 07:21:27 PM PDT 24
Finished Jul 28 07:21:30 PM PDT 24
Peak memory 225496 kb
Host smart-32c62cbd-7f43-4dbb-b550-8a8f35b053d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75156715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.75156715
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.1041904064
Short name T400
Test name
Test status
Simulation time 28037015046 ps
CPU time 126.19 seconds
Started Jul 28 07:21:26 PM PDT 24
Finished Jul 28 07:23:32 PM PDT 24
Peak memory 250112 kb
Host smart-9ec5b4d2-67e1-4184-8ce8-07463c8a410d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041904064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmd
s.1041904064
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/39.spi_device_intercept.808223030
Short name T895
Test name
Test status
Simulation time 147972581 ps
CPU time 3.48 seconds
Started Jul 28 07:21:20 PM PDT 24
Finished Jul 28 07:21:23 PM PDT 24
Peak memory 225392 kb
Host smart-97c94518-45de-41e0-8a88-c22fd0ff5ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808223030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.808223030
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.3617320417
Short name T946
Test name
Test status
Simulation time 2023939314 ps
CPU time 14.39 seconds
Started Jul 28 07:21:24 PM PDT 24
Finished Jul 28 07:21:38 PM PDT 24
Peak memory 241520 kb
Host smart-8ca58066-b5fa-45e8-809f-481df92c5509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617320417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.3617320417
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.2462774921
Short name T827
Test name
Test status
Simulation time 1799626432 ps
CPU time 4.89 seconds
Started Jul 28 07:21:23 PM PDT 24
Finished Jul 28 07:21:28 PM PDT 24
Peak memory 233584 kb
Host smart-6d5a3a0f-4835-48db-afda-448bb7bcdac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462774921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.2462774921
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.2381231607
Short name T417
Test name
Test status
Simulation time 2504204511 ps
CPU time 11.83 seconds
Started Jul 28 07:21:24 PM PDT 24
Finished Jul 28 07:21:36 PM PDT 24
Peak memory 225564 kb
Host smart-588b3d9a-eb02-4a5e-b379-8b23c3be7147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381231607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.2381231607
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.615615267
Short name T799
Test name
Test status
Simulation time 605149713 ps
CPU time 4.31 seconds
Started Jul 28 07:21:28 PM PDT 24
Finished Jul 28 07:21:32 PM PDT 24
Peak memory 222772 kb
Host smart-ec27c8d8-9079-458b-bc78-65c13f4dd269
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=615615267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dire
ct.615615267
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.2430319875
Short name T165
Test name
Test status
Simulation time 58809898701 ps
CPU time 328.5 seconds
Started Jul 28 07:21:28 PM PDT 24
Finished Jul 28 07:26:57 PM PDT 24
Peak memory 284144 kb
Host smart-72f7f6da-46fa-498b-83f9-887fa53bd709
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430319875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.2430319875
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.3484556047
Short name T522
Test name
Test status
Simulation time 2101906657 ps
CPU time 20.13 seconds
Started Jul 28 07:21:23 PM PDT 24
Finished Jul 28 07:21:44 PM PDT 24
Peak memory 220740 kb
Host smart-72db386f-bb58-436f-98e2-cd009cd231f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484556047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.3484556047
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.2213817607
Short name T921
Test name
Test status
Simulation time 1379527337 ps
CPU time 2.2 seconds
Started Jul 28 07:21:26 PM PDT 24
Finished Jul 28 07:21:29 PM PDT 24
Peak memory 217180 kb
Host smart-e0e114e3-e1e9-49ed-97ca-c9ecbc33472b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213817607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.2213817607
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.419617958
Short name T490
Test name
Test status
Simulation time 27124944 ps
CPU time 1.06 seconds
Started Jul 28 07:21:22 PM PDT 24
Finished Jul 28 07:21:23 PM PDT 24
Peak memory 208336 kb
Host smart-007ac679-47ef-4961-b259-46eac761035e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419617958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.419617958
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.2280999873
Short name T926
Test name
Test status
Simulation time 12596895 ps
CPU time 0.68 seconds
Started Jul 28 07:21:22 PM PDT 24
Finished Jul 28 07:21:23 PM PDT 24
Peak memory 206260 kb
Host smart-49168c6b-b2ed-4fc1-accc-ace2ba769756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280999873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.2280999873
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.1876740589
Short name T28
Test name
Test status
Simulation time 83851942865 ps
CPU time 51.76 seconds
Started Jul 28 07:21:22 PM PDT 24
Finished Jul 28 07:22:14 PM PDT 24
Peak memory 225600 kb
Host smart-d1cc1faa-d762-49ce-b87b-9b7e127f5697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876740589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.1876740589
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.637185281
Short name T905
Test name
Test status
Simulation time 62505126 ps
CPU time 0.71 seconds
Started Jul 28 07:18:38 PM PDT 24
Finished Jul 28 07:18:39 PM PDT 24
Peak memory 206400 kb
Host smart-af5007b1-294b-4420-8966-9ae6449052ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637185281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.637185281
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.3048388444
Short name T562
Test name
Test status
Simulation time 2170462123 ps
CPU time 7.68 seconds
Started Jul 28 07:18:39 PM PDT 24
Finished Jul 28 07:18:47 PM PDT 24
Peak memory 233640 kb
Host smart-3df833cd-e6a8-43b8-84d3-38bb8137733b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048388444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.3048388444
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.3760558993
Short name T797
Test name
Test status
Simulation time 22388984 ps
CPU time 0.79 seconds
Started Jul 28 07:18:32 PM PDT 24
Finished Jul 28 07:18:33 PM PDT 24
Peak memory 207188 kb
Host smart-e5a5a500-4f0a-4ac3-8eef-03c3d5f3b812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760558993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.3760558993
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.2120631501
Short name T273
Test name
Test status
Simulation time 2606738531 ps
CPU time 22.01 seconds
Started Jul 28 07:18:37 PM PDT 24
Finished Jul 28 07:18:59 PM PDT 24
Peak memory 225556 kb
Host smart-5cd6bb50-8593-41eb-851b-26d52e55146c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120631501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.2120631501
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.2434029176
Short name T63
Test name
Test status
Simulation time 97708298891 ps
CPU time 309.45 seconds
Started Jul 28 07:18:35 PM PDT 24
Finished Jul 28 07:23:45 PM PDT 24
Peak memory 264312 kb
Host smart-7bc694d6-d160-47e4-b124-1a5535801fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434029176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.2434029176
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.40481390
Short name T793
Test name
Test status
Simulation time 126926621603 ps
CPU time 332.92 seconds
Started Jul 28 07:18:36 PM PDT 24
Finished Jul 28 07:24:09 PM PDT 24
Peak memory 254748 kb
Host smart-b8b976a7-770e-48a2-8c24-f8f90e370fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40481390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle.40481390
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.272378379
Short name T323
Test name
Test status
Simulation time 883535739 ps
CPU time 18.47 seconds
Started Jul 28 07:18:35 PM PDT 24
Finished Jul 28 07:18:54 PM PDT 24
Peak memory 225504 kb
Host smart-41f9aa9c-e0de-4693-90de-241a77ad7185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272378379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.272378379
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.2640948317
Short name T733
Test name
Test status
Simulation time 29118241854 ps
CPU time 192.44 seconds
Started Jul 28 07:18:35 PM PDT 24
Finished Jul 28 07:21:47 PM PDT 24
Peak memory 240288 kb
Host smart-023bb2fa-fd31-4ecd-8f7d-15ce99c11728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640948317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds
.2640948317
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/4.spi_device_intercept.1889071747
Short name T394
Test name
Test status
Simulation time 184929071 ps
CPU time 3.1 seconds
Started Jul 28 07:18:37 PM PDT 24
Finished Jul 28 07:18:40 PM PDT 24
Peak memory 225400 kb
Host smart-0f109ed8-c027-4b47-b2ef-f8527365a10b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889071747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.1889071747
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.375926026
Short name T85
Test name
Test status
Simulation time 112686857 ps
CPU time 3.87 seconds
Started Jul 28 07:18:37 PM PDT 24
Finished Jul 28 07:18:41 PM PDT 24
Peak memory 233656 kb
Host smart-f88ee27b-1281-4ef2-8723-8d6ec4c9421b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375926026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.375926026
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.1954600139
Short name T631
Test name
Test status
Simulation time 93693762 ps
CPU time 1.14 seconds
Started Jul 28 07:18:33 PM PDT 24
Finished Jul 28 07:18:34 PM PDT 24
Peak memory 217440 kb
Host smart-3432b0ac-7ae2-4ece-8377-6b1f4115aee4
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954600139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.spi_device_mem_parity.1954600139
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.7809331
Short name T237
Test name
Test status
Simulation time 927360890 ps
CPU time 5.76 seconds
Started Jul 28 07:18:32 PM PDT 24
Finished Jul 28 07:18:38 PM PDT 24
Peak memory 225420 kb
Host smart-7d74cb27-0c6f-40ce-a976-f9138449e57c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7809331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap.7809331
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.1915610182
Short name T583
Test name
Test status
Simulation time 3495702303 ps
CPU time 9.87 seconds
Started Jul 28 07:18:32 PM PDT 24
Finished Jul 28 07:18:42 PM PDT 24
Peak memory 241464 kb
Host smart-6e236d14-a6fa-4e89-951d-513a798ffee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915610182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.1915610182
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.3187564453
Short name T566
Test name
Test status
Simulation time 1026710245 ps
CPU time 5.14 seconds
Started Jul 28 07:18:37 PM PDT 24
Finished Jul 28 07:18:42 PM PDT 24
Peak memory 223872 kb
Host smart-10835e95-57c8-4288-b344-16928256ddad
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3187564453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.3187564453
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.951630825
Short name T77
Test name
Test status
Simulation time 162789612 ps
CPU time 1.17 seconds
Started Jul 28 07:18:36 PM PDT 24
Finished Jul 28 07:18:37 PM PDT 24
Peak memory 236416 kb
Host smart-43eebaa9-f2b4-4ffc-a0c6-7cdbf46e3814
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951630825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.951630825
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.664047198
Short name T491
Test name
Test status
Simulation time 1087501927 ps
CPU time 18.37 seconds
Started Jul 28 07:18:35 PM PDT 24
Finished Jul 28 07:18:53 PM PDT 24
Peak memory 224564 kb
Host smart-d785b984-abdb-4b75-8891-eceaba5d2b5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664047198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stress
_all.664047198
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.2037407191
Short name T681
Test name
Test status
Simulation time 4742747303 ps
CPU time 2.68 seconds
Started Jul 28 07:18:32 PM PDT 24
Finished Jul 28 07:18:35 PM PDT 24
Peak memory 217464 kb
Host smart-2276884f-3451-48e0-b64e-5cc91f108e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037407191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.2037407191
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.2933046918
Short name T934
Test name
Test status
Simulation time 15323841116 ps
CPU time 6.61 seconds
Started Jul 28 07:18:32 PM PDT 24
Finished Jul 28 07:18:39 PM PDT 24
Peak memory 217236 kb
Host smart-ff668b39-85cf-4752-92a5-7c20afa0e8fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933046918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.2933046918
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.2263004389
Short name T375
Test name
Test status
Simulation time 177511968 ps
CPU time 7.79 seconds
Started Jul 28 07:18:30 PM PDT 24
Finished Jul 28 07:18:38 PM PDT 24
Peak memory 217100 kb
Host smart-88ca0264-1c61-4286-8571-729e04000860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263004389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.2263004389
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.3944307913
Short name T141
Test name
Test status
Simulation time 61548325 ps
CPU time 0.85 seconds
Started Jul 28 07:18:34 PM PDT 24
Finished Jul 28 07:18:35 PM PDT 24
Peak memory 206724 kb
Host smart-e1f0332f-1560-4232-b7a5-57c5f3642481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944307913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.3944307913
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.4072010622
Short name T938
Test name
Test status
Simulation time 8127277977 ps
CPU time 13.06 seconds
Started Jul 28 07:18:37 PM PDT 24
Finished Jul 28 07:18:50 PM PDT 24
Peak memory 233700 kb
Host smart-f97718a2-f84c-45aa-8f42-16d4c8c82346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072010622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.4072010622
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.85766803
Short name T608
Test name
Test status
Simulation time 14345143 ps
CPU time 0.74 seconds
Started Jul 28 07:21:31 PM PDT 24
Finished Jul 28 07:21:32 PM PDT 24
Peak memory 205540 kb
Host smart-b3a254df-aa7c-46df-a8e7-1add0cfd2923
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85766803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.85766803
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.1828094756
Short name T786
Test name
Test status
Simulation time 35070838 ps
CPU time 2.66 seconds
Started Jul 28 07:21:24 PM PDT 24
Finished Jul 28 07:21:27 PM PDT 24
Peak memory 233400 kb
Host smart-bc9164bc-9d58-4ffd-8e3b-d5e54f75727b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828094756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.1828094756
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.2600677580
Short name T563
Test name
Test status
Simulation time 151379067 ps
CPU time 0.81 seconds
Started Jul 28 07:21:27 PM PDT 24
Finished Jul 28 07:21:28 PM PDT 24
Peak memory 207532 kb
Host smart-668dee2b-d9a2-48a4-a8ed-2587e443620d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600677580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.2600677580
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.1947615166
Short name T284
Test name
Test status
Simulation time 55104359365 ps
CPU time 371.96 seconds
Started Jul 28 07:21:32 PM PDT 24
Finished Jul 28 07:27:44 PM PDT 24
Peak memory 258308 kb
Host smart-fa179c6c-b7e0-4065-958f-4df6b2758986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947615166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.1947615166
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.1397195289
Short name T614
Test name
Test status
Simulation time 74020895604 ps
CPU time 343.89 seconds
Started Jul 28 07:21:32 PM PDT 24
Finished Jul 28 07:27:16 PM PDT 24
Peak memory 258152 kb
Host smart-efa37420-dbc0-44d1-8cf6-65d0e892615b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397195289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.1397195289
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.3501725101
Short name T236
Test name
Test status
Simulation time 12286676154 ps
CPU time 160.38 seconds
Started Jul 28 07:21:33 PM PDT 24
Finished Jul 28 07:24:14 PM PDT 24
Peak memory 252040 kb
Host smart-39a8f843-c629-4e53-b40c-1e35eb5f3930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501725101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.3501725101
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.3703443596
Short name T489
Test name
Test status
Simulation time 6041265641 ps
CPU time 59.27 seconds
Started Jul 28 07:21:29 PM PDT 24
Finished Jul 28 07:22:29 PM PDT 24
Peak memory 250072 kb
Host smart-0e419216-f20e-4294-b6c8-418d0cb6492f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703443596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.3703443596
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.4054230430
Short name T940
Test name
Test status
Simulation time 21821572759 ps
CPU time 155.33 seconds
Started Jul 28 07:21:32 PM PDT 24
Finished Jul 28 07:24:07 PM PDT 24
Peak memory 242368 kb
Host smart-7c93053b-c1a1-429d-898e-20b7b9e7ee4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054230430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmd
s.4054230430
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/40.spi_device_intercept.1749306236
Short name T280
Test name
Test status
Simulation time 1454502492 ps
CPU time 7.42 seconds
Started Jul 28 07:21:28 PM PDT 24
Finished Jul 28 07:21:35 PM PDT 24
Peak memory 220744 kb
Host smart-e1c51724-487b-4731-9a16-6e398d7883dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749306236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.1749306236
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.2355193778
Short name T495
Test name
Test status
Simulation time 1112397707 ps
CPU time 13.74 seconds
Started Jul 28 07:21:28 PM PDT 24
Finished Jul 28 07:21:42 PM PDT 24
Peak memory 241644 kb
Host smart-cd7a1fc7-e56a-4063-b4f9-3d45a8417ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355193778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.2355193778
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.2868894372
Short name T787
Test name
Test status
Simulation time 17262708386 ps
CPU time 13.4 seconds
Started Jul 28 07:21:26 PM PDT 24
Finished Jul 28 07:21:40 PM PDT 24
Peak memory 225448 kb
Host smart-89f53172-55d3-4a73-be41-4eaad07f1e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868894372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.2868894372
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.2057128312
Short name T854
Test name
Test status
Simulation time 1365453809 ps
CPU time 5.8 seconds
Started Jul 28 07:21:28 PM PDT 24
Finished Jul 28 07:21:34 PM PDT 24
Peak memory 233552 kb
Host smart-8c979bbd-efa5-4338-9bd8-0033fa2a7dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057128312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.2057128312
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.430901032
Short name T153
Test name
Test status
Simulation time 2659988212 ps
CPU time 5.03 seconds
Started Jul 28 07:21:31 PM PDT 24
Finished Jul 28 07:21:36 PM PDT 24
Peak memory 223100 kb
Host smart-a02ce914-8070-4b2b-9006-565c751ee72e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=430901032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dire
ct.430901032
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.3921914942
Short name T332
Test name
Test status
Simulation time 544049149 ps
CPU time 9.05 seconds
Started Jul 28 07:21:26 PM PDT 24
Finished Jul 28 07:21:36 PM PDT 24
Peak memory 217244 kb
Host smart-26184223-b3cc-4939-9b5c-eb1d6f7c879b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921914942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.3921914942
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.2331940357
Short name T355
Test name
Test status
Simulation time 10669620741 ps
CPU time 26.27 seconds
Started Jul 28 07:21:31 PM PDT 24
Finished Jul 28 07:21:57 PM PDT 24
Peak memory 217224 kb
Host smart-5387e504-717d-46d8-b509-d3721404903a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331940357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.2331940357
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.222856998
Short name T373
Test name
Test status
Simulation time 13234479 ps
CPU time 0.7 seconds
Started Jul 28 07:21:28 PM PDT 24
Finished Jul 28 07:21:29 PM PDT 24
Peak memory 206292 kb
Host smart-907d6573-a5c6-4354-881e-69fe17278c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222856998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.222856998
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.1973397280
Short name T662
Test name
Test status
Simulation time 13253093 ps
CPU time 0.7 seconds
Started Jul 28 07:21:27 PM PDT 24
Finished Jul 28 07:21:28 PM PDT 24
Peak memory 206312 kb
Host smart-2d6c796d-956e-4ddf-8d55-f74160b109e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973397280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.1973397280
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.953868806
Short name T403
Test name
Test status
Simulation time 3574410610 ps
CPU time 13.15 seconds
Started Jul 28 07:21:29 PM PDT 24
Finished Jul 28 07:21:42 PM PDT 24
Peak memory 233708 kb
Host smart-ca10a032-6770-438e-99dd-3a717eda1267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953868806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.953868806
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.2978318129
Short name T578
Test name
Test status
Simulation time 33673172 ps
CPU time 0.72 seconds
Started Jul 28 07:21:38 PM PDT 24
Finished Jul 28 07:21:39 PM PDT 24
Peak memory 205456 kb
Host smart-44c6e182-dad1-4695-89c3-20e3dcc5cb2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978318129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
2978318129
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.2986557444
Short name T615
Test name
Test status
Simulation time 973699642 ps
CPU time 3.91 seconds
Started Jul 28 07:21:33 PM PDT 24
Finished Jul 28 07:21:37 PM PDT 24
Peak memory 225496 kb
Host smart-eb960580-8018-449d-808f-ea452bfafd7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986557444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.2986557444
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.2732991572
Short name T391
Test name
Test status
Simulation time 16413941 ps
CPU time 0.77 seconds
Started Jul 28 07:21:33 PM PDT 24
Finished Jul 28 07:21:34 PM PDT 24
Peak memory 207300 kb
Host smart-7040754f-5e76-46c5-8472-3f91c3b62636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732991572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.2732991572
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.2111107757
Short name T384
Test name
Test status
Simulation time 47739085 ps
CPU time 0.9 seconds
Started Jul 28 07:21:35 PM PDT 24
Finished Jul 28 07:21:36 PM PDT 24
Peak memory 216912 kb
Host smart-56fe8655-a379-4829-b91d-0ce3a4065502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111107757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.2111107757
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.3142393013
Short name T753
Test name
Test status
Simulation time 16711709017 ps
CPU time 73.48 seconds
Started Jul 28 07:21:38 PM PDT 24
Finished Jul 28 07:22:51 PM PDT 24
Peak memory 250168 kb
Host smart-03859fc1-70f4-47c7-8cff-47e3d4fa6f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142393013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.3142393013
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.31693330
Short name T553
Test name
Test status
Simulation time 860478364 ps
CPU time 8.06 seconds
Started Jul 28 07:21:38 PM PDT 24
Finished Jul 28 07:21:46 PM PDT 24
Peak memory 225524 kb
Host smart-1ac3d939-0e26-4d68-958f-2090b0ed0b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31693330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idle.31693330
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.1827025795
Short name T457
Test name
Test status
Simulation time 107755261 ps
CPU time 2.99 seconds
Started Jul 28 07:21:37 PM PDT 24
Finished Jul 28 07:21:40 PM PDT 24
Peak memory 225464 kb
Host smart-65df19c1-5656-47a5-a3ca-9843c5671a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827025795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.1827025795
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.3831580015
Short name T679
Test name
Test status
Simulation time 5783171918 ps
CPU time 56.14 seconds
Started Jul 28 07:21:37 PM PDT 24
Finished Jul 28 07:22:33 PM PDT 24
Peak memory 255924 kb
Host smart-334736d2-768e-4dc1-8a29-ca2d2af76818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831580015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmd
s.3831580015
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_intercept.1032134097
Short name T589
Test name
Test status
Simulation time 231939130 ps
CPU time 3.78 seconds
Started Jul 28 07:21:33 PM PDT 24
Finished Jul 28 07:21:37 PM PDT 24
Peak memory 225492 kb
Host smart-0b7cb007-88af-4f7f-a5aa-3a0b5fc9c5b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032134097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.1032134097
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.3757578299
Short name T225
Test name
Test status
Simulation time 5197866113 ps
CPU time 28.8 seconds
Started Jul 28 07:21:36 PM PDT 24
Finished Jul 28 07:22:05 PM PDT 24
Peak memory 250128 kb
Host smart-11858743-5dec-4459-a70b-6be829c3c846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757578299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.3757578299
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.563939071
Short name T881
Test name
Test status
Simulation time 900432224 ps
CPU time 3.55 seconds
Started Jul 28 07:21:33 PM PDT 24
Finished Jul 28 07:21:37 PM PDT 24
Peak memory 225436 kb
Host smart-dde56f59-c484-4fab-a55c-f4afa57ef155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563939071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swap
.563939071
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.1347363734
Short name T625
Test name
Test status
Simulation time 2891137689 ps
CPU time 3.34 seconds
Started Jul 28 07:21:31 PM PDT 24
Finished Jul 28 07:21:34 PM PDT 24
Peak memory 225464 kb
Host smart-bb182514-2f79-4575-95e4-4da4e17a6b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347363734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.1347363734
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.2691413112
Short name T154
Test name
Test status
Simulation time 1239895146 ps
CPU time 7.08 seconds
Started Jul 28 07:21:34 PM PDT 24
Finished Jul 28 07:21:41 PM PDT 24
Peak memory 223060 kb
Host smart-6365e8e9-2548-4ce3-b38f-5c114b50c4d9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2691413112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.2691413112
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.3849680213
Short name T167
Test name
Test status
Simulation time 356689425285 ps
CPU time 270.24 seconds
Started Jul 28 07:21:37 PM PDT 24
Finished Jul 28 07:26:07 PM PDT 24
Peak memory 282976 kb
Host smart-49981f9f-8bdc-4ebd-8549-242bed075cd9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849680213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.3849680213
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.1298720707
Short name T798
Test name
Test status
Simulation time 3005620036 ps
CPU time 22.11 seconds
Started Jul 28 07:21:32 PM PDT 24
Finished Jul 28 07:21:54 PM PDT 24
Peak memory 217344 kb
Host smart-e9edb071-2b2d-4f5d-af00-837bf8525cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298720707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.1298720707
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.1448325534
Short name T488
Test name
Test status
Simulation time 6155134885 ps
CPU time 19 seconds
Started Jul 28 07:21:35 PM PDT 24
Finished Jul 28 07:21:54 PM PDT 24
Peak memory 217300 kb
Host smart-8716f45d-7de4-4b55-b07f-1f7f16d8ec2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448325534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.1448325534
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.2638354806
Short name T750
Test name
Test status
Simulation time 41211343 ps
CPU time 0.81 seconds
Started Jul 28 07:21:32 PM PDT 24
Finished Jul 28 07:21:33 PM PDT 24
Peak memory 206764 kb
Host smart-53f3fc25-b192-41a8-a878-71a0ddde9b26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638354806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.2638354806
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.1395026795
Short name T612
Test name
Test status
Simulation time 39489165 ps
CPU time 0.8 seconds
Started Jul 28 07:21:31 PM PDT 24
Finished Jul 28 07:21:32 PM PDT 24
Peak memory 206752 kb
Host smart-0aff80af-4a26-4166-b756-1c3fec7681ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395026795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.1395026795
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.673174880
Short name T277
Test name
Test status
Simulation time 3039522566 ps
CPU time 11.56 seconds
Started Jul 28 07:21:36 PM PDT 24
Finished Jul 28 07:21:48 PM PDT 24
Peak memory 228972 kb
Host smart-c7475486-612d-4249-8df8-f9a8292c6f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673174880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.673174880
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.3869730020
Short name T970
Test name
Test status
Simulation time 77777200 ps
CPU time 0.75 seconds
Started Jul 28 07:21:40 PM PDT 24
Finished Jul 28 07:21:41 PM PDT 24
Peak memory 205496 kb
Host smart-54da8685-dbe1-4e35-b3dd-332b3127cdd3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869730020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
3869730020
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.2404670239
Short name T477
Test name
Test status
Simulation time 2812563003 ps
CPU time 5.12 seconds
Started Jul 28 07:21:41 PM PDT 24
Finished Jul 28 07:21:46 PM PDT 24
Peak memory 233624 kb
Host smart-e6fbe0dd-8283-4d3b-bee1-efaa874f753c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404670239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.2404670239
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.4049369915
Short name T561
Test name
Test status
Simulation time 15923076 ps
CPU time 0.82 seconds
Started Jul 28 07:21:36 PM PDT 24
Finished Jul 28 07:21:37 PM PDT 24
Peak memory 207252 kb
Host smart-1318d551-fbd1-47c6-a9cf-81c47744c0ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049369915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.4049369915
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.1971131716
Short name T537
Test name
Test status
Simulation time 1858595509 ps
CPU time 34 seconds
Started Jul 28 07:21:40 PM PDT 24
Finished Jul 28 07:22:15 PM PDT 24
Peak memory 250940 kb
Host smart-8d820ee0-8d1d-4a46-a706-f526d03a99b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971131716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.1971131716
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.2668285714
Short name T270
Test name
Test status
Simulation time 7514110038 ps
CPU time 85.9 seconds
Started Jul 28 07:21:43 PM PDT 24
Finished Jul 28 07:23:10 PM PDT 24
Peak memory 254936 kb
Host smart-bdc34bd2-81c1-4c53-a0c0-ace71e9b3fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668285714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.2668285714
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.492296669
Short name T683
Test name
Test status
Simulation time 4089308264 ps
CPU time 22.24 seconds
Started Jul 28 07:21:41 PM PDT 24
Finished Jul 28 07:22:04 PM PDT 24
Peak memory 220500 kb
Host smart-ddd83ce6-7acf-43c5-b368-86f05927c3cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492296669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idle
.492296669
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.1697062623
Short name T852
Test name
Test status
Simulation time 424068694 ps
CPU time 6.93 seconds
Started Jul 28 07:21:39 PM PDT 24
Finished Jul 28 07:21:46 PM PDT 24
Peak memory 238076 kb
Host smart-f8397d94-f933-42b3-9552-c907c8c6e5fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697062623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.1697062623
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_intercept.1556072169
Short name T222
Test name
Test status
Simulation time 5423760903 ps
CPU time 15.99 seconds
Started Jul 28 07:21:40 PM PDT 24
Finished Jul 28 07:21:57 PM PDT 24
Peak memory 233620 kb
Host smart-830da529-3a68-4c7a-9d81-525a38014aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556072169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.1556072169
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.1411047738
Short name T623
Test name
Test status
Simulation time 6405280161 ps
CPU time 34.41 seconds
Started Jul 28 07:21:43 PM PDT 24
Finished Jul 28 07:22:17 PM PDT 24
Peak memory 241716 kb
Host smart-868c1c78-00a8-4c06-a14c-f54e44fba5a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411047738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.1411047738
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.788746423
Short name T880
Test name
Test status
Simulation time 95243253 ps
CPU time 2.66 seconds
Started Jul 28 07:21:40 PM PDT 24
Finished Jul 28 07:21:43 PM PDT 24
Peak memory 233620 kb
Host smart-064316de-f544-4bd3-bb56-fadf7bc25de9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788746423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swap
.788746423
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.3387999235
Short name T255
Test name
Test status
Simulation time 813601592 ps
CPU time 2.5 seconds
Started Jul 28 07:21:38 PM PDT 24
Finished Jul 28 07:21:40 PM PDT 24
Peak memory 225360 kb
Host smart-bd7c73f0-83e8-41f6-b98b-71eb772143c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387999235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.3387999235
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.4155275787
Short name T539
Test name
Test status
Simulation time 2759533327 ps
CPU time 14.18 seconds
Started Jul 28 07:21:41 PM PDT 24
Finished Jul 28 07:21:56 PM PDT 24
Peak memory 222596 kb
Host smart-43daa044-4aee-43a2-bf6a-82fcf06ebd49
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4155275787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.4155275787
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.965615690
Short name T296
Test name
Test status
Simulation time 28105143949 ps
CPU time 352.55 seconds
Started Jul 28 07:21:40 PM PDT 24
Finished Jul 28 07:27:32 PM PDT 24
Peak memory 299280 kb
Host smart-71e4986e-d0d4-433d-b1b0-a598ebeaae35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965615690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stres
s_all.965615690
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.228028512
Short name T618
Test name
Test status
Simulation time 5153171699 ps
CPU time 22.27 seconds
Started Jul 28 07:21:38 PM PDT 24
Finished Jul 28 07:22:00 PM PDT 24
Peak memory 217304 kb
Host smart-cfc8aab8-0c3a-4053-a7b5-c0230cff2c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228028512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.228028512
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.4287621869
Short name T353
Test name
Test status
Simulation time 4227800439 ps
CPU time 8.29 seconds
Started Jul 28 07:21:37 PM PDT 24
Finished Jul 28 07:21:45 PM PDT 24
Peak memory 217224 kb
Host smart-b14d669a-e2a6-4573-8b45-d4a9b4fdb172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287621869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.4287621869
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.3100608369
Short name T351
Test name
Test status
Simulation time 12674842 ps
CPU time 0.68 seconds
Started Jul 28 07:21:35 PM PDT 24
Finished Jul 28 07:21:36 PM PDT 24
Peak memory 206292 kb
Host smart-380423f2-69b0-4af1-845e-7da6955dfe24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100608369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.3100608369
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.657552061
Short name T763
Test name
Test status
Simulation time 93228337 ps
CPU time 0.97 seconds
Started Jul 28 07:21:36 PM PDT 24
Finished Jul 28 07:21:37 PM PDT 24
Peak memory 207768 kb
Host smart-bc6b9ed9-a4cd-4330-affb-5698a94f696a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657552061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.657552061
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.1248516009
Short name T235
Test name
Test status
Simulation time 1094565385 ps
CPU time 3.81 seconds
Started Jul 28 07:21:42 PM PDT 24
Finished Jul 28 07:21:45 PM PDT 24
Peak memory 233600 kb
Host smart-d92af9d6-a70e-40f2-a248-dac9540606fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248516009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.1248516009
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.2482676915
Short name T336
Test name
Test status
Simulation time 43278732 ps
CPU time 0.71 seconds
Started Jul 28 07:21:51 PM PDT 24
Finished Jul 28 07:21:51 PM PDT 24
Peak memory 205508 kb
Host smart-22082916-8287-4d4f-9558-00ddf75849c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482676915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
2482676915
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.2610418883
Short name T802
Test name
Test status
Simulation time 57194585 ps
CPU time 2.14 seconds
Started Jul 28 07:21:47 PM PDT 24
Finished Jul 28 07:21:49 PM PDT 24
Peak memory 224764 kb
Host smart-fd5ff008-eada-4b4d-a707-17774460618c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610418883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.2610418883
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.3229935309
Short name T383
Test name
Test status
Simulation time 94957906 ps
CPU time 0.84 seconds
Started Jul 28 07:21:43 PM PDT 24
Finished Jul 28 07:21:45 PM PDT 24
Peak memory 207248 kb
Host smart-c2dc328b-f7a9-4ae1-9173-69ed24407dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229935309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.3229935309
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.2262997355
Short name T312
Test name
Test status
Simulation time 27683887148 ps
CPU time 94.57 seconds
Started Jul 28 07:21:49 PM PDT 24
Finished Jul 28 07:23:24 PM PDT 24
Peak memory 250084 kb
Host smart-1e1e21d0-bf74-4a32-96ee-375ca8dcc3ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262997355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.2262997355
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.3736228370
Short name T33
Test name
Test status
Simulation time 174103522461 ps
CPU time 265.25 seconds
Started Jul 28 07:21:50 PM PDT 24
Finished Jul 28 07:26:15 PM PDT 24
Peak memory 255612 kb
Host smart-16d0359d-ed0c-40a0-9412-f05817bf750f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736228370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.3736228370
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.1264189543
Short name T200
Test name
Test status
Simulation time 18673963914 ps
CPU time 154.1 seconds
Started Jul 28 07:21:49 PM PDT 24
Finished Jul 28 07:24:23 PM PDT 24
Peak memory 251028 kb
Host smart-f9d73dcb-ce38-4131-9d9a-b0a45fe92729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264189543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.1264189543
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.4195404494
Short name T428
Test name
Test status
Simulation time 1995589005 ps
CPU time 28.02 seconds
Started Jul 28 07:21:56 PM PDT 24
Finished Jul 28 07:22:25 PM PDT 24
Peak memory 225424 kb
Host smart-2d85a66e-3d54-4563-aa16-819bc3d01c54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195404494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.4195404494
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.1749079868
Short name T757
Test name
Test status
Simulation time 36447224466 ps
CPU time 209.34 seconds
Started Jul 28 07:21:50 PM PDT 24
Finished Jul 28 07:25:20 PM PDT 24
Peak memory 253676 kb
Host smart-58204ee6-ef25-4e54-b168-2161954ad72b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749079868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmd
s.1749079868
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_intercept.1668304654
Short name T822
Test name
Test status
Simulation time 4333502395 ps
CPU time 3.97 seconds
Started Jul 28 07:21:44 PM PDT 24
Finished Jul 28 07:21:48 PM PDT 24
Peak memory 225524 kb
Host smart-e20b503e-afc6-4cf8-973a-81ee648f992c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668304654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.1668304654
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.2704432254
Short name T443
Test name
Test status
Simulation time 61846805 ps
CPU time 3.17 seconds
Started Jul 28 07:21:45 PM PDT 24
Finished Jul 28 07:21:48 PM PDT 24
Peak memory 225444 kb
Host smart-4cb0feca-2b7e-41c6-88c9-3141349922f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704432254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.2704432254
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.3763337204
Short name T605
Test name
Test status
Simulation time 1185696765 ps
CPU time 7.46 seconds
Started Jul 28 07:21:44 PM PDT 24
Finished Jul 28 07:21:51 PM PDT 24
Peak memory 233564 kb
Host smart-04f5a10c-6f8c-4d1c-a7ab-3966b2ac770e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763337204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.3763337204
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.227670016
Short name T813
Test name
Test status
Simulation time 111966335 ps
CPU time 3 seconds
Started Jul 28 07:21:44 PM PDT 24
Finished Jul 28 07:21:48 PM PDT 24
Peak memory 225452 kb
Host smart-c29799f8-3f25-461d-a5b9-f3d22303af32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227670016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.227670016
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.42746048
Short name T401
Test name
Test status
Simulation time 3021886683 ps
CPU time 10.61 seconds
Started Jul 28 07:21:50 PM PDT 24
Finished Jul 28 07:22:00 PM PDT 24
Peak memory 223056 kb
Host smart-7c93a0ae-d77f-44aa-ad03-2ca6e6ff0518
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=42746048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_direc
t.42746048
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.3922649557
Short name T557
Test name
Test status
Simulation time 6112480278 ps
CPU time 9.89 seconds
Started Jul 28 07:21:45 PM PDT 24
Finished Jul 28 07:21:55 PM PDT 24
Peak memory 220736 kb
Host smart-70688387-6f05-4ede-b87a-cd72392375b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922649557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.3922649557
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.2773539805
Short name T800
Test name
Test status
Simulation time 1865388650 ps
CPU time 2.81 seconds
Started Jul 28 07:21:40 PM PDT 24
Finished Jul 28 07:21:43 PM PDT 24
Peak memory 217120 kb
Host smart-8b4ec132-253f-41ed-b629-e1ee532ae678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773539805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.2773539805
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.1468960662
Short name T638
Test name
Test status
Simulation time 115144964 ps
CPU time 1.01 seconds
Started Jul 28 07:21:44 PM PDT 24
Finished Jul 28 07:21:45 PM PDT 24
Peak memory 208808 kb
Host smart-13b342a1-e774-47ef-9d62-cdaee62e72c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468960662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.1468960662
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.3253574305
Short name T971
Test name
Test status
Simulation time 19810016 ps
CPU time 0.75 seconds
Started Jul 28 07:21:42 PM PDT 24
Finished Jul 28 07:21:43 PM PDT 24
Peak memory 206828 kb
Host smart-8e6ec175-63d4-4c8b-b354-4451c4b8e876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253574305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.3253574305
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.4216746281
Short name T3
Test name
Test status
Simulation time 4032797179 ps
CPU time 8.55 seconds
Started Jul 28 07:21:50 PM PDT 24
Finished Jul 28 07:21:59 PM PDT 24
Peak memory 233636 kb
Host smart-09756236-f471-494f-9651-877db3d01d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216746281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.4216746281
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.1217862913
Short name T138
Test name
Test status
Simulation time 40450375 ps
CPU time 0.77 seconds
Started Jul 28 07:21:52 PM PDT 24
Finished Jul 28 07:21:53 PM PDT 24
Peak memory 206052 kb
Host smart-14bcda21-59d0-4faa-9632-1032eb22233d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217862913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
1217862913
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.1842042297
Short name T838
Test name
Test status
Simulation time 725947185 ps
CPU time 4.19 seconds
Started Jul 28 07:21:54 PM PDT 24
Finished Jul 28 07:21:58 PM PDT 24
Peak memory 225432 kb
Host smart-22394673-39c8-4d17-a483-e5dc31210dbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842042297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.1842042297
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.3928962289
Short name T973
Test name
Test status
Simulation time 68043622 ps
CPU time 0.78 seconds
Started Jul 28 07:21:53 PM PDT 24
Finished Jul 28 07:21:54 PM PDT 24
Peak memory 207200 kb
Host smart-6e948b2b-d812-483e-ae68-c83e80be78bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928962289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.3928962289
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.693324922
Short name T923
Test name
Test status
Simulation time 156668802645 ps
CPU time 174.73 seconds
Started Jul 28 07:21:52 PM PDT 24
Finished Jul 28 07:24:47 PM PDT 24
Peak memory 256960 kb
Host smart-0292b9e0-2ce8-4959-8b6f-0a3b850780cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693324922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.693324922
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.77139161
Short name T610
Test name
Test status
Simulation time 6929793289 ps
CPU time 39.15 seconds
Started Jul 28 07:21:54 PM PDT 24
Finished Jul 28 07:22:33 PM PDT 24
Peak memory 225556 kb
Host smart-ed25cba4-bd5e-4e9b-96d1-735dce02661c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77139161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.77139161
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.192353866
Short name T595
Test name
Test status
Simulation time 8207426775 ps
CPU time 126.36 seconds
Started Jul 28 07:21:57 PM PDT 24
Finished Jul 28 07:24:03 PM PDT 24
Peak memory 258344 kb
Host smart-45638e53-7eff-44c3-b15b-7ac74f2c9ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192353866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idle
.192353866
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.3012628868
Short name T788
Test name
Test status
Simulation time 163476843 ps
CPU time 4.61 seconds
Started Jul 28 07:21:54 PM PDT 24
Finished Jul 28 07:21:59 PM PDT 24
Peak memory 233700 kb
Host smart-a3faf71e-a3f9-414b-b0eb-75aa69989233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012628868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.3012628868
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.2045022388
Short name T651
Test name
Test status
Simulation time 9321740733 ps
CPU time 60.67 seconds
Started Jul 28 07:21:56 PM PDT 24
Finished Jul 28 07:22:57 PM PDT 24
Peak memory 250064 kb
Host smart-674c5f6a-2234-49f1-a60c-58c57534e284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045022388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmd
s.2045022388
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/44.spi_device_intercept.194079705
Short name T234
Test name
Test status
Simulation time 433959287 ps
CPU time 5.38 seconds
Started Jul 28 07:21:49 PM PDT 24
Finished Jul 28 07:21:55 PM PDT 24
Peak memory 233588 kb
Host smart-dc19ab0c-9d54-49e2-8b3a-6ed338b9bc5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194079705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.194079705
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.3008376925
Short name T382
Test name
Test status
Simulation time 477940583 ps
CPU time 1.99 seconds
Started Jul 28 07:21:50 PM PDT 24
Finished Jul 28 07:21:52 PM PDT 24
Peak memory 224832 kb
Host smart-d33d6e9b-666a-451f-b46a-a9e1bb81d097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008376925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.3008376925
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.1470217054
Short name T219
Test name
Test status
Simulation time 262067997 ps
CPU time 4.68 seconds
Started Jul 28 07:21:50 PM PDT 24
Finished Jul 28 07:21:54 PM PDT 24
Peak memory 225372 kb
Host smart-5d990814-f86a-41be-beda-9841e5f11217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470217054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.1470217054
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.2632434207
Short name T281
Test name
Test status
Simulation time 26473894130 ps
CPU time 19.37 seconds
Started Jul 28 07:21:51 PM PDT 24
Finished Jul 28 07:22:10 PM PDT 24
Peak memory 241428 kb
Host smart-38e2c889-2c86-4314-a4d8-bd1179643006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632434207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.2632434207
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.1610378475
Short name T664
Test name
Test status
Simulation time 22826343378 ps
CPU time 12.8 seconds
Started Jul 28 07:21:48 PM PDT 24
Finished Jul 28 07:22:01 PM PDT 24
Peak memory 224112 kb
Host smart-e62bd47e-ca77-4fb7-a1cb-c0cbe1a6e938
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1610378475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.1610378475
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.445676716
Short name T430
Test name
Test status
Simulation time 57478070 ps
CPU time 0.93 seconds
Started Jul 28 07:21:53 PM PDT 24
Finished Jul 28 07:21:54 PM PDT 24
Peak memory 207232 kb
Host smart-e71c1391-1ba9-4868-96e1-aff8e2a8390c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445676716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stres
s_all.445676716
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.4267472309
Short name T34
Test name
Test status
Simulation time 4836678468 ps
CPU time 19.64 seconds
Started Jul 28 07:21:50 PM PDT 24
Finished Jul 28 07:22:10 PM PDT 24
Peak memory 217256 kb
Host smart-18a2d066-7f77-4ef6-bfdc-24d3e4ce1ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267472309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.4267472309
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.1787818182
Short name T503
Test name
Test status
Simulation time 4947915561 ps
CPU time 13.6 seconds
Started Jul 28 07:21:53 PM PDT 24
Finished Jul 28 07:22:07 PM PDT 24
Peak memory 217208 kb
Host smart-9b5239a3-b4ae-4adf-87d6-e608e8954061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787818182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.1787818182
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.3190154616
Short name T691
Test name
Test status
Simulation time 64697300 ps
CPU time 0.82 seconds
Started Jul 28 07:21:50 PM PDT 24
Finished Jul 28 07:21:51 PM PDT 24
Peak memory 207544 kb
Host smart-fbb13d84-5b2f-4bc1-a989-9bc3e83672a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190154616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.3190154616
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.2794791734
Short name T698
Test name
Test status
Simulation time 127043745 ps
CPU time 0.82 seconds
Started Jul 28 07:21:51 PM PDT 24
Finished Jul 28 07:21:52 PM PDT 24
Peak memory 206772 kb
Host smart-f8034345-660a-4be3-b3a6-90a82b1bf447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794791734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.2794791734
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.55155853
Short name T1019
Test name
Test status
Simulation time 240165143 ps
CPU time 3.1 seconds
Started Jul 28 07:21:53 PM PDT 24
Finished Jul 28 07:21:56 PM PDT 24
Peak memory 225332 kb
Host smart-66b9a89e-f099-4890-b333-28f161381c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55155853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.55155853
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.2448721718
Short name T927
Test name
Test status
Simulation time 17469195 ps
CPU time 0.73 seconds
Started Jul 28 07:21:58 PM PDT 24
Finished Jul 28 07:21:59 PM PDT 24
Peak memory 206076 kb
Host smart-1e29e804-77b3-4709-8aff-7704becaf346
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448721718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
2448721718
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.4041905389
Short name T462
Test name
Test status
Simulation time 140263682 ps
CPU time 3.03 seconds
Started Jul 28 07:21:56 PM PDT 24
Finished Jul 28 07:21:59 PM PDT 24
Peak memory 233572 kb
Host smart-e60de449-148b-42a3-bcb0-ee71b009ccc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041905389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.4041905389
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.4274882603
Short name T37
Test name
Test status
Simulation time 13191293 ps
CPU time 0.75 seconds
Started Jul 28 07:21:57 PM PDT 24
Finished Jul 28 07:21:58 PM PDT 24
Peak memory 207600 kb
Host smart-613274d9-9442-45d4-a245-7953f966e14e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274882603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.4274882603
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.1606346598
Short name T367
Test name
Test status
Simulation time 31080912 ps
CPU time 0.76 seconds
Started Jul 28 07:21:58 PM PDT 24
Finished Jul 28 07:21:59 PM PDT 24
Peak memory 216640 kb
Host smart-88a13db1-5f7e-403b-9140-aafda11c891c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606346598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.1606346598
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.2851000560
Short name T607
Test name
Test status
Simulation time 92211219637 ps
CPU time 236.45 seconds
Started Jul 28 07:21:56 PM PDT 24
Finished Jul 28 07:25:53 PM PDT 24
Peak memory 250156 kb
Host smart-9295d0e4-28a5-4791-89cd-21e0b3886062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851000560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.2851000560
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.2691906576
Short name T1015
Test name
Test status
Simulation time 35655147731 ps
CPU time 303.21 seconds
Started Jul 28 07:22:01 PM PDT 24
Finished Jul 28 07:27:04 PM PDT 24
Peak memory 257024 kb
Host smart-d201d65b-eb22-4985-b2a2-fd6b8647b816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691906576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.2691906576
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.56484037
Short name T874
Test name
Test status
Simulation time 2207250908 ps
CPU time 14.69 seconds
Started Jul 28 07:21:57 PM PDT 24
Finished Jul 28 07:22:12 PM PDT 24
Peak memory 233676 kb
Host smart-6979f09b-8807-42f1-896d-c421d21f49bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56484037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.56484037
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.3342759604
Short name T791
Test name
Test status
Simulation time 7064504433 ps
CPU time 114.82 seconds
Started Jul 28 07:21:57 PM PDT 24
Finished Jul 28 07:23:52 PM PDT 24
Peak memory 265224 kb
Host smart-d136ed77-e50b-4a03-ba9a-6513f4c183aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342759604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmd
s.3342759604
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_intercept.1396025453
Short name T594
Test name
Test status
Simulation time 1521692285 ps
CPU time 7.08 seconds
Started Jul 28 07:21:51 PM PDT 24
Finished Jul 28 07:21:59 PM PDT 24
Peak memory 233588 kb
Host smart-875f0559-edf8-424c-8d9b-133bf059c169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396025453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.1396025453
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.408853988
Short name T624
Test name
Test status
Simulation time 318889447 ps
CPU time 5.86 seconds
Started Jul 28 07:21:53 PM PDT 24
Finished Jul 28 07:21:59 PM PDT 24
Peak memory 225448 kb
Host smart-6f95cc48-99af-48df-9790-c612ef4a3406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408853988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.408853988
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.380547353
Short name T619
Test name
Test status
Simulation time 5518058317 ps
CPU time 16.69 seconds
Started Jul 28 07:21:53 PM PDT 24
Finished Jul 28 07:22:09 PM PDT 24
Peak memory 233708 kb
Host smart-d80d9082-ac55-4c3d-adcf-cd983c03fe99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380547353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swap
.380547353
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.4159002506
Short name T950
Test name
Test status
Simulation time 18017667884 ps
CPU time 14.93 seconds
Started Jul 28 07:21:54 PM PDT 24
Finished Jul 28 07:22:09 PM PDT 24
Peak memory 233696 kb
Host smart-c3637319-f895-49e3-a084-00190683a5af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159002506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.4159002506
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.1035983138
Short name T611
Test name
Test status
Simulation time 2571811881 ps
CPU time 9.76 seconds
Started Jul 28 07:21:58 PM PDT 24
Finished Jul 28 07:22:08 PM PDT 24
Peak memory 222976 kb
Host smart-772cb146-6d5f-4c80-80a7-59ec97f08c58
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1035983138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.1035983138
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.895724027
Short name T210
Test name
Test status
Simulation time 200146414659 ps
CPU time 468.1 seconds
Started Jul 28 07:21:57 PM PDT 24
Finished Jul 28 07:29:45 PM PDT 24
Peak memory 256088 kb
Host smart-ae08b0d4-1e61-443d-bd8a-ab465a2bc26c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895724027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stres
s_all.895724027
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.45084608
Short name T745
Test name
Test status
Simulation time 2201154970 ps
CPU time 32.71 seconds
Started Jul 28 07:21:52 PM PDT 24
Finished Jul 28 07:22:25 PM PDT 24
Peak memory 220156 kb
Host smart-af0ec9e5-2f5a-4d04-a920-0caa3cdc492f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45084608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.45084608
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.2560920487
Short name T918
Test name
Test status
Simulation time 720719903 ps
CPU time 2.46 seconds
Started Jul 28 07:21:55 PM PDT 24
Finished Jul 28 07:21:57 PM PDT 24
Peak memory 208728 kb
Host smart-46409c2a-01fb-4c31-87d3-b0f47e8be0d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560920487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.2560920487
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.3237540277
Short name T953
Test name
Test status
Simulation time 283116157 ps
CPU time 2.42 seconds
Started Jul 28 07:21:53 PM PDT 24
Finished Jul 28 07:21:55 PM PDT 24
Peak memory 217220 kb
Host smart-66b6866d-3796-4927-9022-d32adfc931c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237540277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.3237540277
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.1761637171
Short name T704
Test name
Test status
Simulation time 332511875 ps
CPU time 0.93 seconds
Started Jul 28 07:21:53 PM PDT 24
Finished Jul 28 07:21:55 PM PDT 24
Peak memory 206968 kb
Host smart-8c7474b4-3da7-49af-bd34-7e5dc934075c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761637171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.1761637171
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.3944846394
Short name T527
Test name
Test status
Simulation time 2608523607 ps
CPU time 11.68 seconds
Started Jul 28 07:21:58 PM PDT 24
Finished Jul 28 07:22:10 PM PDT 24
Peak memory 225512 kb
Host smart-7856b314-f8aa-4e93-924c-5ac0e45c2061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944846394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.3944846394
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.1183258944
Short name T6
Test name
Test status
Simulation time 74091745 ps
CPU time 0.71 seconds
Started Jul 28 07:22:06 PM PDT 24
Finished Jul 28 07:22:06 PM PDT 24
Peak memory 205500 kb
Host smart-d0bc948b-267f-4b4a-a24d-f8a3ab7edf11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183258944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
1183258944
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.2531489430
Short name T568
Test name
Test status
Simulation time 167584146 ps
CPU time 3.59 seconds
Started Jul 28 07:22:01 PM PDT 24
Finished Jul 28 07:22:05 PM PDT 24
Peak memory 225472 kb
Host smart-502cc8ef-584c-4dea-bdee-1cdf922aa56e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531489430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.2531489430
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.492333677
Short name T342
Test name
Test status
Simulation time 26521651 ps
CPU time 0.82 seconds
Started Jul 28 07:21:57 PM PDT 24
Finished Jul 28 07:21:59 PM PDT 24
Peak memory 207596 kb
Host smart-5de0aaf8-41cc-4b5a-8cbf-824dcc8a5e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492333677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.492333677
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.14079838
Short name T170
Test name
Test status
Simulation time 12513060492 ps
CPU time 27.28 seconds
Started Jul 28 07:22:04 PM PDT 24
Finished Jul 28 07:22:31 PM PDT 24
Peak memory 242060 kb
Host smart-3b6b6ae2-7a81-4c96-87f8-5493c5ab2081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14079838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.14079838
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.4014247805
Short name T240
Test name
Test status
Simulation time 13325490590 ps
CPU time 110.28 seconds
Started Jul 28 07:22:07 PM PDT 24
Finished Jul 28 07:23:57 PM PDT 24
Peak memory 250168 kb
Host smart-a70ab7f4-ff5e-4648-9831-e97ff200ef8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014247805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.4014247805
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.3960364874
Short name T13
Test name
Test status
Simulation time 169361121 ps
CPU time 5.09 seconds
Started Jul 28 07:22:08 PM PDT 24
Finished Jul 28 07:22:13 PM PDT 24
Peak memory 225420 kb
Host smart-77d96c7c-c416-4767-a9c0-cd416fa4d32e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960364874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.3960364874
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.2720616360
Short name T181
Test name
Test status
Simulation time 34653907319 ps
CPU time 265.93 seconds
Started Jul 28 07:22:04 PM PDT 24
Finished Jul 28 07:26:30 PM PDT 24
Peak memory 258392 kb
Host smart-e5e65d70-1fbc-4bb4-86ca-28e44272dfb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720616360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmd
s.2720616360
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_intercept.2542506719
Short name T475
Test name
Test status
Simulation time 211660310 ps
CPU time 2.24 seconds
Started Jul 28 07:21:59 PM PDT 24
Finished Jul 28 07:22:01 PM PDT 24
Peak memory 233212 kb
Host smart-4f0a31ab-fb00-40c3-8544-b01bb13ed6ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542506719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.2542506719
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.2185471798
Short name T371
Test name
Test status
Simulation time 226886121 ps
CPU time 4.77 seconds
Started Jul 28 07:21:58 PM PDT 24
Finished Jul 28 07:22:03 PM PDT 24
Peak memory 233632 kb
Host smart-05962ad4-a6ba-4e83-9086-20565e87614d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185471798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.2185471798
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.1581862264
Short name T949
Test name
Test status
Simulation time 191476378 ps
CPU time 3.9 seconds
Started Jul 28 07:21:56 PM PDT 24
Finished Jul 28 07:22:00 PM PDT 24
Peak memory 233660 kb
Host smart-b2cc6adf-8357-44bb-85d8-55d7cf995819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581862264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.1581862264
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.2260250510
Short name T586
Test name
Test status
Simulation time 503463063 ps
CPU time 3.6 seconds
Started Jul 28 07:21:55 PM PDT 24
Finished Jul 28 07:21:59 PM PDT 24
Peak memory 233616 kb
Host smart-90dbbcd6-2c06-487e-aa4b-f8a7e0d3141b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260250510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.2260250510
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.311874066
Short name T832
Test name
Test status
Simulation time 135529211 ps
CPU time 4.58 seconds
Started Jul 28 07:22:08 PM PDT 24
Finished Jul 28 07:22:12 PM PDT 24
Peak memory 223964 kb
Host smart-76092787-41bb-4c59-a84d-3ab063a20fc1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=311874066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dire
ct.311874066
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.4245410696
Short name T60
Test name
Test status
Simulation time 87995225457 ps
CPU time 233.18 seconds
Started Jul 28 07:22:03 PM PDT 24
Finished Jul 28 07:25:57 PM PDT 24
Peak memory 250332 kb
Host smart-c7a4845f-9156-4956-93d4-406e786d9435
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245410696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.4245410696
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.4130490121
Short name T330
Test name
Test status
Simulation time 633921032 ps
CPU time 2.18 seconds
Started Jul 28 07:21:58 PM PDT 24
Finished Jul 28 07:22:00 PM PDT 24
Peak memory 217272 kb
Host smart-ef10b205-7dcb-4faa-b703-80f50f0cbada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130490121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.4130490121
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.2919783839
Short name T96
Test name
Test status
Simulation time 8238592072 ps
CPU time 23.51 seconds
Started Jul 28 07:21:56 PM PDT 24
Finished Jul 28 07:22:19 PM PDT 24
Peak memory 217284 kb
Host smart-0e29da55-bd6a-4240-ad3d-2cf6b6b693aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919783839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.2919783839
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.742491694
Short name T377
Test name
Test status
Simulation time 10529889 ps
CPU time 0.7 seconds
Started Jul 28 07:21:58 PM PDT 24
Finished Jul 28 07:21:59 PM PDT 24
Peak memory 206292 kb
Host smart-8ea72d60-446b-44a0-b115-a52a74c44dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742491694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.742491694
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.1550164157
Short name T519
Test name
Test status
Simulation time 88257772 ps
CPU time 0.88 seconds
Started Jul 28 07:22:00 PM PDT 24
Finished Jul 28 07:22:01 PM PDT 24
Peak memory 207012 kb
Host smart-c6c54ee8-f81b-4889-8097-a0729ff9d99f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550164157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.1550164157
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.2718591714
Short name T871
Test name
Test status
Simulation time 678146160 ps
CPU time 5.55 seconds
Started Jul 28 07:22:01 PM PDT 24
Finished Jul 28 07:22:07 PM PDT 24
Peak memory 225480 kb
Host smart-7c1dd069-89c0-4769-bc12-326b48421926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718591714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.2718591714
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.1091376564
Short name T74
Test name
Test status
Simulation time 20924877 ps
CPU time 0.68 seconds
Started Jul 28 07:22:06 PM PDT 24
Finished Jul 28 07:22:07 PM PDT 24
Peak memory 206120 kb
Host smart-bad037c1-495d-48e8-9bb0-f0e9f340e8fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091376564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
1091376564
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.1358523461
Short name T900
Test name
Test status
Simulation time 495032175 ps
CPU time 5.86 seconds
Started Jul 28 07:22:08 PM PDT 24
Finished Jul 28 07:22:14 PM PDT 24
Peak memory 225408 kb
Host smart-57ede944-2def-4708-a915-2633028406cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358523461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.1358523461
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.2471428468
Short name T515
Test name
Test status
Simulation time 17396463 ps
CPU time 0.77 seconds
Started Jul 28 07:22:09 PM PDT 24
Finished Jul 28 07:22:10 PM PDT 24
Peak memory 206240 kb
Host smart-8b9ed66b-d5fc-4095-bd1b-30f190fd8814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471428468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.2471428468
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.4131192933
Short name T429
Test name
Test status
Simulation time 3778123117 ps
CPU time 38.88 seconds
Started Jul 28 07:22:06 PM PDT 24
Finished Jul 28 07:22:45 PM PDT 24
Peak memory 239392 kb
Host smart-484cd779-9da2-4bad-8911-618e58148ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131192933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.4131192933
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.1077836251
Short name T274
Test name
Test status
Simulation time 11381960162 ps
CPU time 69.85 seconds
Started Jul 28 07:22:08 PM PDT 24
Finished Jul 28 07:23:18 PM PDT 24
Peak memory 254000 kb
Host smart-b8978977-88c3-4a60-b49a-f07d902a95e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077836251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.1077836251
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.3778728634
Short name T315
Test name
Test status
Simulation time 1799097781 ps
CPU time 19.37 seconds
Started Jul 28 07:22:13 PM PDT 24
Finished Jul 28 07:22:32 PM PDT 24
Peak memory 237204 kb
Host smart-9047c4d3-1f6b-4f99-9439-56a6caea7a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778728634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.3778728634
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.119413215
Short name T883
Test name
Test status
Simulation time 2166333641 ps
CPU time 29.63 seconds
Started Jul 28 07:22:09 PM PDT 24
Finished Jul 28 07:22:38 PM PDT 24
Peak memory 239660 kb
Host smart-c6f31476-d39f-4126-b3e0-b05e5fa2a68a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119413215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmds
.119413215
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_intercept.1778119452
Short name T282
Test name
Test status
Simulation time 200361054 ps
CPU time 3.89 seconds
Started Jul 28 07:22:08 PM PDT 24
Finished Jul 28 07:22:11 PM PDT 24
Peak memory 225428 kb
Host smart-dded2950-0d16-43c4-850c-d4b14023feb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778119452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.1778119452
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.1230132416
Short name T961
Test name
Test status
Simulation time 40453315161 ps
CPU time 80.08 seconds
Started Jul 28 07:22:04 PM PDT 24
Finished Jul 28 07:23:24 PM PDT 24
Peak memory 241304 kb
Host smart-d07e21c7-8792-41b9-9f6a-2659336167f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230132416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.1230132416
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.2332540208
Short name T957
Test name
Test status
Simulation time 6436357917 ps
CPU time 20.11 seconds
Started Jul 28 07:22:08 PM PDT 24
Finished Jul 28 07:22:28 PM PDT 24
Peak memory 225440 kb
Host smart-9de508f8-c7e3-4507-8585-b2fa7ba3f502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332540208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.2332540208
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.3671967035
Short name T183
Test name
Test status
Simulation time 384476783 ps
CPU time 4 seconds
Started Jul 28 07:22:07 PM PDT 24
Finished Jul 28 07:22:11 PM PDT 24
Peak memory 233640 kb
Host smart-ccac2e4f-02fc-4069-8bb3-de66a55205de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671967035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.3671967035
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.3163280061
Short name T10
Test name
Test status
Simulation time 877659050 ps
CPU time 4.98 seconds
Started Jul 28 07:22:07 PM PDT 24
Finished Jul 28 07:22:12 PM PDT 24
Peak memory 223144 kb
Host smart-efdc3554-d7ee-470c-bbcd-ee57d311d483
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3163280061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.3163280061
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.1780957802
Short name T56
Test name
Test status
Simulation time 963284318 ps
CPU time 10.56 seconds
Started Jul 28 07:22:01 PM PDT 24
Finished Jul 28 07:22:12 PM PDT 24
Peak memory 220832 kb
Host smart-85dc9104-4ea3-4ce8-8b2a-886c9e4b3345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780957802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.1780957802
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.922068491
Short name T726
Test name
Test status
Simulation time 1068411606 ps
CPU time 3.44 seconds
Started Jul 28 07:22:04 PM PDT 24
Finished Jul 28 07:22:08 PM PDT 24
Peak memory 217124 kb
Host smart-280dbcf1-ad7c-4293-8caa-e599f413b837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922068491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.922068491
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.3574571605
Short name T782
Test name
Test status
Simulation time 257804893 ps
CPU time 2.79 seconds
Started Jul 28 07:22:01 PM PDT 24
Finished Jul 28 07:22:04 PM PDT 24
Peak memory 217108 kb
Host smart-2c2705e8-db67-47dd-b136-a67f0269e073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574571605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.3574571605
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.3552079573
Short name T455
Test name
Test status
Simulation time 319876697 ps
CPU time 0.96 seconds
Started Jul 28 07:22:09 PM PDT 24
Finished Jul 28 07:22:11 PM PDT 24
Peak memory 207776 kb
Host smart-576536da-9de8-4301-aeee-b4a9346aeba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552079573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.3552079573
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.3039789353
Short name T541
Test name
Test status
Simulation time 12028038632 ps
CPU time 18.73 seconds
Started Jul 28 07:22:00 PM PDT 24
Finished Jul 28 07:22:19 PM PDT 24
Peak memory 233684 kb
Host smart-8d795859-c247-413b-98ec-b04131e2d338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039789353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.3039789353
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.960366103
Short name T350
Test name
Test status
Simulation time 14593009 ps
CPU time 0.71 seconds
Started Jul 28 07:22:09 PM PDT 24
Finished Jul 28 07:22:09 PM PDT 24
Peak memory 206060 kb
Host smart-242b7d61-6cf5-4ede-bf05-e1a7e527fed2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960366103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.960366103
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.3723498680
Short name T811
Test name
Test status
Simulation time 194985246 ps
CPU time 4.83 seconds
Started Jul 28 07:22:12 PM PDT 24
Finished Jul 28 07:22:17 PM PDT 24
Peak memory 233600 kb
Host smart-d8c7048d-8050-4bd3-9008-53385160201a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723498680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.3723498680
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.1946664010
Short name T9
Test name
Test status
Simulation time 19789686 ps
CPU time 0.84 seconds
Started Jul 28 07:22:12 PM PDT 24
Finished Jul 28 07:22:13 PM PDT 24
Peak memory 207212 kb
Host smart-0b2032de-bc74-4300-917d-1dea6844a69b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946664010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.1946664010
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.421154017
Short name T514
Test name
Test status
Simulation time 74800795664 ps
CPU time 131.32 seconds
Started Jul 28 07:22:11 PM PDT 24
Finished Jul 28 07:24:23 PM PDT 24
Peak memory 250584 kb
Host smart-ba316f77-741b-4bbd-9aba-765b2c3c4326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421154017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.421154017
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.4101312263
Short name T54
Test name
Test status
Simulation time 33363836553 ps
CPU time 95.91 seconds
Started Jul 28 07:22:14 PM PDT 24
Finished Jul 28 07:23:50 PM PDT 24
Peak memory 263072 kb
Host smart-d9fc849e-54e3-4f24-918b-b0ee2edb5627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101312263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.4101312263
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.2346609418
Short name T151
Test name
Test status
Simulation time 125397212899 ps
CPU time 339.14 seconds
Started Jul 28 07:22:12 PM PDT 24
Finished Jul 28 07:27:51 PM PDT 24
Peak memory 266320 kb
Host smart-6109e7a7-6774-4008-8566-6cd3aa5b05b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346609418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.2346609418
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.1992694891
Short name T319
Test name
Test status
Simulation time 17804069285 ps
CPU time 21.9 seconds
Started Jul 28 07:22:11 PM PDT 24
Finished Jul 28 07:22:33 PM PDT 24
Peak memory 233716 kb
Host smart-93ddbec8-012b-4b65-be3a-96f950cb6f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992694891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.1992694891
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.1599053216
Short name T238
Test name
Test status
Simulation time 77966482878 ps
CPU time 260.63 seconds
Started Jul 28 07:22:11 PM PDT 24
Finished Jul 28 07:26:32 PM PDT 24
Peak memory 260748 kb
Host smart-ff73afba-3be6-4a4d-b193-02e5888c3e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599053216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmd
s.1599053216
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/48.spi_device_intercept.1581089984
Short name T419
Test name
Test status
Simulation time 76916945 ps
CPU time 2.97 seconds
Started Jul 28 07:22:08 PM PDT 24
Finished Jul 28 07:22:11 PM PDT 24
Peak memory 233652 kb
Host smart-2514f9ee-8f5f-42e6-9df1-2bf0c4511d97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581089984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.1581089984
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.1548084644
Short name T171
Test name
Test status
Simulation time 5514330388 ps
CPU time 42.99 seconds
Started Jul 28 07:22:14 PM PDT 24
Finished Jul 28 07:22:57 PM PDT 24
Peak memory 233712 kb
Host smart-d0d7149c-43e4-4c40-80ef-5845c43ccbfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548084644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.1548084644
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.3886236687
Short name T841
Test name
Test status
Simulation time 1238088749 ps
CPU time 7.65 seconds
Started Jul 28 07:22:10 PM PDT 24
Finished Jul 28 07:22:18 PM PDT 24
Peak memory 233636 kb
Host smart-12ae373b-9b2b-4270-be21-92adc01e56a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886236687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.3886236687
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.239682473
Short name T920
Test name
Test status
Simulation time 74951631 ps
CPU time 2.42 seconds
Started Jul 28 07:22:08 PM PDT 24
Finished Jul 28 07:22:10 PM PDT 24
Peak memory 224764 kb
Host smart-82a4ac64-25ce-4277-8d1a-3ec3f5367007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239682473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.239682473
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.3177454931
Short name T1026
Test name
Test status
Simulation time 1703459720 ps
CPU time 7.59 seconds
Started Jul 28 07:22:10 PM PDT 24
Finished Jul 28 07:22:18 PM PDT 24
Peak memory 222428 kb
Host smart-1e9887a6-6dd3-454d-9ff5-fbd56db7c693
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3177454931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.3177454931
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.119661628
Short name T395
Test name
Test status
Simulation time 34682277 ps
CPU time 0.91 seconds
Started Jul 28 07:22:09 PM PDT 24
Finished Jul 28 07:22:10 PM PDT 24
Peak memory 206276 kb
Host smart-d6a8e2cc-2a4b-40cf-8213-720dbd126454
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119661628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stres
s_all.119661628
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.3083038975
Short name T695
Test name
Test status
Simulation time 419180018 ps
CPU time 2.81 seconds
Started Jul 28 07:22:07 PM PDT 24
Finished Jul 28 07:22:10 PM PDT 24
Peak memory 217540 kb
Host smart-aafc3d8b-a6b9-4078-9d59-1ba33fd6936a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083038975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.3083038975
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.3380670061
Short name T357
Test name
Test status
Simulation time 1639254664 ps
CPU time 7.98 seconds
Started Jul 28 07:22:06 PM PDT 24
Finished Jul 28 07:22:14 PM PDT 24
Peak memory 217144 kb
Host smart-a7182d36-75d1-4282-9356-a4af237a5aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380670061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.3380670061
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.647627915
Short name T815
Test name
Test status
Simulation time 134220779 ps
CPU time 1.5 seconds
Started Jul 28 07:22:07 PM PDT 24
Finished Jul 28 07:22:08 PM PDT 24
Peak memory 217088 kb
Host smart-523a33f2-6527-45d7-b5c9-821265060758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647627915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.647627915
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.3249027721
Short name T772
Test name
Test status
Simulation time 57287311 ps
CPU time 0.82 seconds
Started Jul 28 07:22:07 PM PDT 24
Finished Jul 28 07:22:08 PM PDT 24
Peak memory 206848 kb
Host smart-518ae061-983a-4524-ba47-046c5324d457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249027721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.3249027721
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.3614014303
Short name T601
Test name
Test status
Simulation time 151990751 ps
CPU time 4.14 seconds
Started Jul 28 07:22:10 PM PDT 24
Finished Jul 28 07:22:14 PM PDT 24
Peak memory 233624 kb
Host smart-a9c0640a-f3bb-489a-b1cb-442c0795b5a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614014303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.3614014303
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.443433518
Short name T460
Test name
Test status
Simulation time 20474627 ps
CPU time 0.74 seconds
Started Jul 28 07:22:19 PM PDT 24
Finished Jul 28 07:22:20 PM PDT 24
Peak memory 206056 kb
Host smart-4af5a8d8-77fd-4566-8a09-98258225abe1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443433518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.443433518
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.1268781889
Short name T979
Test name
Test status
Simulation time 117650310 ps
CPU time 2.56 seconds
Started Jul 28 07:22:14 PM PDT 24
Finished Jul 28 07:22:17 PM PDT 24
Peak memory 233304 kb
Host smart-31af89da-163a-40a7-be41-21c9eee6dbf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268781889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.1268781889
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.1433741568
Short name T754
Test name
Test status
Simulation time 60315805 ps
CPU time 0.78 seconds
Started Jul 28 07:22:09 PM PDT 24
Finished Jul 28 07:22:10 PM PDT 24
Peak memory 206248 kb
Host smart-fe478d2b-d866-46f3-bb62-4741285e0fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433741568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.1433741568
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.2720018982
Short name T869
Test name
Test status
Simulation time 13532858639 ps
CPU time 41.75 seconds
Started Jul 28 07:22:19 PM PDT 24
Finished Jul 28 07:23:01 PM PDT 24
Peak memory 251708 kb
Host smart-944cf315-c50d-47ce-a210-8f365d0ddf26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720018982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.2720018982
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.4160706598
Short name T886
Test name
Test status
Simulation time 4877938103 ps
CPU time 65.07 seconds
Started Jul 28 07:22:13 PM PDT 24
Finished Jul 28 07:23:18 PM PDT 24
Peak memory 257732 kb
Host smart-5bb2f1a7-7e61-43b8-8d5c-ee090a63e505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160706598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.4160706598
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.509614594
Short name T714
Test name
Test status
Simulation time 3785219409 ps
CPU time 78.94 seconds
Started Jul 28 07:22:14 PM PDT 24
Finished Jul 28 07:23:33 PM PDT 24
Peak memory 258144 kb
Host smart-a4ea05fe-f7fa-48a3-8a1f-b2c4b33e9c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509614594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idle
.509614594
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.2077428263
Short name T175
Test name
Test status
Simulation time 2700607306 ps
CPU time 16.08 seconds
Started Jul 28 07:22:14 PM PDT 24
Finished Jul 28 07:22:31 PM PDT 24
Peak memory 250688 kb
Host smart-12fc1ee1-f7d4-4bd4-b1ed-1b8c3da491b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077428263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.2077428263
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.2376884553
Short name T866
Test name
Test status
Simulation time 2635466530 ps
CPU time 43.18 seconds
Started Jul 28 07:22:14 PM PDT 24
Finished Jul 28 07:22:58 PM PDT 24
Peak memory 240700 kb
Host smart-fa00b591-0849-4d74-ad65-b8240c3a5b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376884553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmd
s.2376884553
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/49.spi_device_intercept.2918374063
Short name T596
Test name
Test status
Simulation time 279902780 ps
CPU time 3.06 seconds
Started Jul 28 07:22:14 PM PDT 24
Finished Jul 28 07:22:18 PM PDT 24
Peak memory 233696 kb
Host smart-b3526f52-cdab-4965-94d3-7889f47c17d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918374063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.2918374063
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.1508899319
Short name T761
Test name
Test status
Simulation time 10986819485 ps
CPU time 68.97 seconds
Started Jul 28 07:22:15 PM PDT 24
Finished Jul 28 07:23:24 PM PDT 24
Peak memory 241096 kb
Host smart-b82f2acd-5b9b-43ce-8f2c-f995e3bde10b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508899319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.1508899319
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.1132108768
Short name T997
Test name
Test status
Simulation time 374859792 ps
CPU time 6.76 seconds
Started Jul 28 07:22:14 PM PDT 24
Finished Jul 28 07:22:21 PM PDT 24
Peak memory 225440 kb
Host smart-ac48b153-9b74-4b96-9034-a1c5ae755b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132108768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.1132108768
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.2540803184
Short name T410
Test name
Test status
Simulation time 479094180 ps
CPU time 3.44 seconds
Started Jul 28 07:22:13 PM PDT 24
Finished Jul 28 07:22:16 PM PDT 24
Peak memory 225408 kb
Host smart-8f45370c-b6ce-420f-9925-201ca0fbf684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540803184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.2540803184
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.727843996
Short name T560
Test name
Test status
Simulation time 415625021 ps
CPU time 6.15 seconds
Started Jul 28 07:22:19 PM PDT 24
Finished Jul 28 07:22:26 PM PDT 24
Peak memory 223176 kb
Host smart-de7b1c8e-e139-4b03-a37d-68f9e7f6fba2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=727843996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dire
ct.727843996
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.3697407035
Short name T22
Test name
Test status
Simulation time 31964520638 ps
CPU time 151.84 seconds
Started Jul 28 07:22:20 PM PDT 24
Finished Jul 28 07:24:52 PM PDT 24
Peak memory 257076 kb
Host smart-0a063b86-7f61-421c-b440-321458937de0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697407035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.3697407035
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.3543814497
Short name T423
Test name
Test status
Simulation time 103245893609 ps
CPU time 30.24 seconds
Started Jul 28 07:22:13 PM PDT 24
Finished Jul 28 07:22:44 PM PDT 24
Peak memory 217260 kb
Host smart-1c7fcce5-3be2-411a-877d-3ecadfb9e144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543814497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.3543814497
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.1846878537
Short name T755
Test name
Test status
Simulation time 1595571844 ps
CPU time 8.58 seconds
Started Jul 28 07:22:12 PM PDT 24
Finished Jul 28 07:22:21 PM PDT 24
Peak memory 217068 kb
Host smart-50ee48d9-5dcf-4acc-bcc2-dd55b045e11e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846878537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.1846878537
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.338195230
Short name T68
Test name
Test status
Simulation time 59282075 ps
CPU time 2.17 seconds
Started Jul 28 07:22:14 PM PDT 24
Finished Jul 28 07:22:16 PM PDT 24
Peak memory 208896 kb
Host smart-11151217-b673-4cdf-bddc-7f04301d5749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338195230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.338195230
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.1125226301
Short name T36
Test name
Test status
Simulation time 315265848 ps
CPU time 0.9 seconds
Started Jul 28 07:22:11 PM PDT 24
Finished Jul 28 07:22:12 PM PDT 24
Peak memory 206804 kb
Host smart-dd7a14ad-3cb3-4ecb-a48f-0f909e1eea94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125226301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.1125226301
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.1700355781
Short name T258
Test name
Test status
Simulation time 13216492651 ps
CPU time 20.78 seconds
Started Jul 28 07:22:12 PM PDT 24
Finished Jul 28 07:22:33 PM PDT 24
Peak memory 225468 kb
Host smart-a93fac14-75ee-4770-8b91-be40f10879ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700355781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.1700355781
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.185182633
Short name T569
Test name
Test status
Simulation time 61396292 ps
CPU time 0.69 seconds
Started Jul 28 07:18:40 PM PDT 24
Finished Jul 28 07:18:40 PM PDT 24
Peak memory 205656 kb
Host smart-d4d83ea0-ffba-44b3-a10e-62bc26cbb2c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185182633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.185182633
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.3930753568
Short name T808
Test name
Test status
Simulation time 114492031 ps
CPU time 2.1 seconds
Started Jul 28 07:18:39 PM PDT 24
Finished Jul 28 07:18:41 PM PDT 24
Peak memory 225548 kb
Host smart-edcdc4dc-b529-4a61-80f9-79a4c9b92c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930753568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.3930753568
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.2612259483
Short name T379
Test name
Test status
Simulation time 20321037 ps
CPU time 0.78 seconds
Started Jul 28 07:18:32 PM PDT 24
Finished Jul 28 07:18:33 PM PDT 24
Peak memory 207232 kb
Host smart-7017d9dd-dd6d-4518-98b4-42c5f6af7400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612259483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.2612259483
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.3928834469
Short name T298
Test name
Test status
Simulation time 6156014583 ps
CPU time 41.07 seconds
Started Jul 28 07:18:39 PM PDT 24
Finished Jul 28 07:19:21 PM PDT 24
Peak memory 250272 kb
Host smart-b6a10c49-a86c-4e00-9231-783f2f1ba244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928834469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.3928834469
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.1691218455
Short name T582
Test name
Test status
Simulation time 1266600481 ps
CPU time 26.49 seconds
Started Jul 28 07:18:39 PM PDT 24
Finished Jul 28 07:19:05 PM PDT 24
Peak memory 250456 kb
Host smart-7730a3c2-8650-459d-8c95-dd0bcbf6157f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691218455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.1691218455
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.2084908587
Short name T322
Test name
Test status
Simulation time 7241108166 ps
CPU time 16.21 seconds
Started Jul 28 07:18:40 PM PDT 24
Finished Jul 28 07:18:57 PM PDT 24
Peak memory 225516 kb
Host smart-1d6131e6-9f30-45e8-8a0e-8c7f9a184c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084908587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.2084908587
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.3890065730
Short name T525
Test name
Test status
Simulation time 14265512345 ps
CPU time 41.77 seconds
Started Jul 28 07:18:40 PM PDT 24
Finished Jul 28 07:19:22 PM PDT 24
Peak memory 250136 kb
Host smart-75fb4a7d-7e2b-4b86-8e0d-91c7935e0b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890065730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds
.3890065730
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/5.spi_device_intercept.148934575
Short name T716
Test name
Test status
Simulation time 120979493 ps
CPU time 2.36 seconds
Started Jul 28 07:18:40 PM PDT 24
Finished Jul 28 07:18:43 PM PDT 24
Peak memory 233288 kb
Host smart-0ca8abd8-245a-407e-89a7-f657f9dc13f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148934575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.148934575
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.1834204177
Short name T211
Test name
Test status
Simulation time 3172496517 ps
CPU time 20.75 seconds
Started Jul 28 07:18:43 PM PDT 24
Finished Jul 28 07:19:04 PM PDT 24
Peak memory 241532 kb
Host smart-29c474d8-d5b3-434f-88ff-4c08a6a0ce33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834204177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.1834204177
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.2757147972
Short name T780
Test name
Test status
Simulation time 93146683 ps
CPU time 1.03 seconds
Started Jul 28 07:18:38 PM PDT 24
Finished Jul 28 07:18:39 PM PDT 24
Peak memory 217368 kb
Host smart-34ed1ffe-2bf6-4432-afcf-00d011622206
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757147972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.spi_device_mem_parity.2757147972
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.1901857611
Short name T925
Test name
Test status
Simulation time 5491905330 ps
CPU time 10.05 seconds
Started Jul 28 07:18:41 PM PDT 24
Finished Jul 28 07:18:51 PM PDT 24
Peak memory 233700 kb
Host smart-20b11452-a2a8-4f2e-afbc-d88919265e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901857611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.1901857611
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.4293320828
Short name T372
Test name
Test status
Simulation time 6267404988 ps
CPU time 6.27 seconds
Started Jul 28 07:18:41 PM PDT 24
Finished Jul 28 07:18:47 PM PDT 24
Peak memory 233700 kb
Host smart-d1078196-14c6-4ee0-8d40-2d5e984506e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293320828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.4293320828
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.1826954358
Short name T715
Test name
Test status
Simulation time 389407977 ps
CPU time 5.23 seconds
Started Jul 28 07:18:42 PM PDT 24
Finished Jul 28 07:18:47 PM PDT 24
Peak memory 219524 kb
Host smart-6f4480cf-446c-4e0b-963e-c65a8b1719df
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1826954358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.1826954358
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.3575330959
Short name T59
Test name
Test status
Simulation time 291097933910 ps
CPU time 784.52 seconds
Started Jul 28 07:18:42 PM PDT 24
Finished Jul 28 07:31:47 PM PDT 24
Peak memory 285100 kb
Host smart-deba9713-b303-4ab7-bea8-0ae0cf89d85b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575330959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.3575330959
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.1632870217
Short name T408
Test name
Test status
Simulation time 41238919785 ps
CPU time 31.4 seconds
Started Jul 28 07:18:37 PM PDT 24
Finished Jul 28 07:19:08 PM PDT 24
Peak memory 217184 kb
Host smart-0d23d4e8-b37a-4300-894b-5fed9e1361d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632870217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.1632870217
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.337761461
Short name T1023
Test name
Test status
Simulation time 712847202 ps
CPU time 3.09 seconds
Started Jul 28 07:18:36 PM PDT 24
Finished Jul 28 07:18:40 PM PDT 24
Peak memory 217132 kb
Host smart-6703b458-654b-455d-bd32-135bbc84c79d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337761461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.337761461
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.1001629078
Short name T751
Test name
Test status
Simulation time 1005164905 ps
CPU time 6.13 seconds
Started Jul 28 07:18:41 PM PDT 24
Finished Jul 28 07:18:48 PM PDT 24
Peak memory 217204 kb
Host smart-96de6f28-8e38-4e04-84c0-80682e9dada8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001629078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.1001629078
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.3990513853
Short name T958
Test name
Test status
Simulation time 72226023 ps
CPU time 0.8 seconds
Started Jul 28 07:18:42 PM PDT 24
Finished Jul 28 07:18:43 PM PDT 24
Peak memory 206724 kb
Host smart-2abc6376-48ab-47f1-a2f5-37339f198cd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990513853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.3990513853
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.814666514
Short name T554
Test name
Test status
Simulation time 1910200458 ps
CPU time 6.84 seconds
Started Jul 28 07:18:38 PM PDT 24
Finished Jul 28 07:18:45 PM PDT 24
Peak memory 225428 kb
Host smart-b2994c7f-099a-45bb-a8eb-f7652699cc32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814666514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.814666514
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.358446667
Short name T380
Test name
Test status
Simulation time 49049762 ps
CPU time 0.76 seconds
Started Jul 28 07:18:43 PM PDT 24
Finished Jul 28 07:18:44 PM PDT 24
Peak memory 206076 kb
Host smart-1843fb02-a9ed-4c4c-b39a-b0c0ce18c922
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358446667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.358446667
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.2621841143
Short name T985
Test name
Test status
Simulation time 1027528360 ps
CPU time 4.5 seconds
Started Jul 28 07:18:44 PM PDT 24
Finished Jul 28 07:18:48 PM PDT 24
Peak memory 233636 kb
Host smart-942e4984-b4ac-402a-9105-07814b5925b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621841143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.2621841143
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.1389933544
Short name T397
Test name
Test status
Simulation time 25218180 ps
CPU time 0.78 seconds
Started Jul 28 07:18:41 PM PDT 24
Finished Jul 28 07:18:42 PM PDT 24
Peak memory 207264 kb
Host smart-43be335f-b612-4d1f-82b8-eea426763009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389933544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.1389933544
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.3503765900
Short name T891
Test name
Test status
Simulation time 26812137578 ps
CPU time 123.09 seconds
Started Jul 28 07:18:44 PM PDT 24
Finished Jul 28 07:20:47 PM PDT 24
Peak memory 268100 kb
Host smart-9a5d13ba-bbea-4033-8917-e85aab801839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503765900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.3503765900
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.2476082562
Short name T420
Test name
Test status
Simulation time 19139916826 ps
CPU time 164.24 seconds
Started Jul 28 07:18:45 PM PDT 24
Finished Jul 28 07:21:30 PM PDT 24
Peak memory 250180 kb
Host smart-d175baa5-3028-4f5b-a15c-f6e4dfe249a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476082562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.2476082562
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.1204605411
Short name T182
Test name
Test status
Simulation time 48595949911 ps
CPU time 64.77 seconds
Started Jul 28 07:18:44 PM PDT 24
Finished Jul 28 07:19:49 PM PDT 24
Peak memory 254808 kb
Host smart-60609b71-3c4b-40d7-ac2d-5fe54a2f43b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204605411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.1204605411
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.2693353116
Short name T804
Test name
Test status
Simulation time 2031177601 ps
CPU time 32.65 seconds
Started Jul 28 07:18:46 PM PDT 24
Finished Jul 28 07:19:19 PM PDT 24
Peak memory 249932 kb
Host smart-0c0bb393-381d-4753-a3c3-3df0198a6100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693353116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.2693353116
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_intercept.2009657793
Short name T101
Test name
Test status
Simulation time 6455350604 ps
CPU time 30.18 seconds
Started Jul 28 07:18:44 PM PDT 24
Finished Jul 28 07:19:14 PM PDT 24
Peak memory 225564 kb
Host smart-1c5b94e4-37cf-4e6e-91c0-ade3489a6e05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009657793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.2009657793
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.4023649141
Short name T580
Test name
Test status
Simulation time 6226926855 ps
CPU time 11.2 seconds
Started Jul 28 07:18:42 PM PDT 24
Finished Jul 28 07:18:54 PM PDT 24
Peak memory 225456 kb
Host smart-fa593f59-16fe-4786-9e2c-0a8c49321932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023649141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.4023649141
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.4019534649
Short name T43
Test name
Test status
Simulation time 59047650 ps
CPU time 1.16 seconds
Started Jul 28 07:18:41 PM PDT 24
Finished Jul 28 07:18:42 PM PDT 24
Peak memory 217400 kb
Host smart-5fb5ea08-f84a-4df9-9ea1-28386becb84b
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019534649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.spi_device_mem_parity.4019534649
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.4291946645
Short name T241
Test name
Test status
Simulation time 31666533738 ps
CPU time 10.83 seconds
Started Jul 28 07:18:45 PM PDT 24
Finished Jul 28 07:18:56 PM PDT 24
Peak memory 241600 kb
Host smart-46bdea29-8bec-4e3e-801e-8678049eb7f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291946645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.4291946645
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.653606934
Short name T916
Test name
Test status
Simulation time 3931608195 ps
CPU time 11.04 seconds
Started Jul 28 07:18:41 PM PDT 24
Finished Jul 28 07:18:53 PM PDT 24
Peak memory 233116 kb
Host smart-33e88156-37bc-4d76-a756-fe72fe8a9ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653606934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.653606934
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.1297077275
Short name T156
Test name
Test status
Simulation time 302497256 ps
CPU time 5.29 seconds
Started Jul 28 07:18:45 PM PDT 24
Finished Jul 28 07:18:50 PM PDT 24
Peak memory 223960 kb
Host smart-80cd3c5e-d8c8-4993-89f6-f5f8290eba74
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1297077275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.1297077275
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.1784927731
Short name T164
Test name
Test status
Simulation time 4565241541 ps
CPU time 92.51 seconds
Started Jul 28 07:18:44 PM PDT 24
Finished Jul 28 07:20:17 PM PDT 24
Peak memory 251216 kb
Host smart-5ccea72d-8eff-4064-b7c9-136c32d7c01d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784927731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.1784927731
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.3264723645
Short name T676
Test name
Test status
Simulation time 5275660844 ps
CPU time 35.93 seconds
Started Jul 28 07:18:40 PM PDT 24
Finished Jul 28 07:19:16 PM PDT 24
Peak memory 217236 kb
Host smart-37df4b50-d920-460e-99f0-2c79244e54c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264723645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.3264723645
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.3333234046
Short name T885
Test name
Test status
Simulation time 1065441132 ps
CPU time 3.54 seconds
Started Jul 28 07:18:43 PM PDT 24
Finished Jul 28 07:18:47 PM PDT 24
Peak memory 217168 kb
Host smart-a1c853b1-a33d-420d-b1ac-9efc6db31ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333234046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.3333234046
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.1715513735
Short name T335
Test name
Test status
Simulation time 173340661 ps
CPU time 1.3 seconds
Started Jul 28 07:18:40 PM PDT 24
Finished Jul 28 07:18:41 PM PDT 24
Peak memory 217000 kb
Host smart-7f288f4b-247a-4dfd-91fb-d793f3e78157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715513735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.1715513735
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.489786998
Short name T473
Test name
Test status
Simulation time 59272051 ps
CPU time 0.74 seconds
Started Jul 28 07:18:43 PM PDT 24
Finished Jul 28 07:18:44 PM PDT 24
Peak memory 206288 kb
Host smart-6180a6e1-0ebf-400b-9aa1-3f1a04c506cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489786998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.489786998
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.2849748647
Short name T689
Test name
Test status
Simulation time 9056801835 ps
CPU time 16.82 seconds
Started Jul 28 07:18:44 PM PDT 24
Finished Jul 28 07:19:01 PM PDT 24
Peak memory 233664 kb
Host smart-99ce0244-3056-4ecc-8fd3-4df238a75deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849748647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.2849748647
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.4208235208
Short name T592
Test name
Test status
Simulation time 13742695 ps
CPU time 0.71 seconds
Started Jul 28 07:18:50 PM PDT 24
Finished Jul 28 07:18:51 PM PDT 24
Peak memory 205484 kb
Host smart-84a4ddbd-cbae-4a7f-959d-2cf66d854a91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208235208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.4
208235208
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.2192379739
Short name T174
Test name
Test status
Simulation time 34835775 ps
CPU time 2.37 seconds
Started Jul 28 07:18:49 PM PDT 24
Finished Jul 28 07:18:51 PM PDT 24
Peak memory 233244 kb
Host smart-cca8ef69-1426-4333-b3d1-ff0bc75d8984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192379739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.2192379739
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.1696378016
Short name T1027
Test name
Test status
Simulation time 40943543 ps
CPU time 0.73 seconds
Started Jul 28 07:18:45 PM PDT 24
Finished Jul 28 07:18:46 PM PDT 24
Peak memory 206232 kb
Host smart-48934462-9ae3-4e7f-b909-9af4ac4063b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696378016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.1696378016
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.515248649
Short name T807
Test name
Test status
Simulation time 61547814680 ps
CPU time 115.41 seconds
Started Jul 28 07:18:49 PM PDT 24
Finished Jul 28 07:20:45 PM PDT 24
Peak memory 250132 kb
Host smart-4eea5aea-d2ce-470e-893c-cfb997922549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515248649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.515248649
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.1545632233
Short name T310
Test name
Test status
Simulation time 23342049964 ps
CPU time 299.48 seconds
Started Jul 28 07:18:49 PM PDT 24
Finished Jul 28 07:23:49 PM PDT 24
Peak memory 274056 kb
Host smart-7c919633-994a-4fcd-90f4-8bd1026afbaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545632233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.1545632233
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.115045309
Short name T441
Test name
Test status
Simulation time 96801413919 ps
CPU time 216.17 seconds
Started Jul 28 07:18:52 PM PDT 24
Finished Jul 28 07:22:29 PM PDT 24
Peak memory 257576 kb
Host smart-aa974032-d31e-4b7d-a34b-57d94dd5d1c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115045309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle.
115045309
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.1990248718
Short name T661
Test name
Test status
Simulation time 159947900 ps
CPU time 3.33 seconds
Started Jul 28 07:18:52 PM PDT 24
Finished Jul 28 07:18:56 PM PDT 24
Peak memory 233588 kb
Host smart-cd865a41-e9a9-4ae3-96df-07b5d17fe38d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990248718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.1990248718
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.1040169485
Short name T468
Test name
Test status
Simulation time 41175511723 ps
CPU time 18.9 seconds
Started Jul 28 07:18:49 PM PDT 24
Finished Jul 28 07:19:08 PM PDT 24
Peak memory 237144 kb
Host smart-73dd6c7f-b13f-4a28-a0d9-d25efd8c2a40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040169485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds
.1040169485
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_intercept.491316884
Short name T776
Test name
Test status
Simulation time 112297274 ps
CPU time 2.31 seconds
Started Jul 28 07:18:46 PM PDT 24
Finished Jul 28 07:18:48 PM PDT 24
Peak memory 224780 kb
Host smart-21310832-9a32-442f-9070-de65a28362c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491316884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.491316884
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.631674824
Short name T741
Test name
Test status
Simulation time 611477900 ps
CPU time 4.96 seconds
Started Jul 28 07:18:46 PM PDT 24
Finished Jul 28 07:18:51 PM PDT 24
Peak memory 233648 kb
Host smart-e4a58051-d989-4165-8a4a-d7abbaa2c237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631674824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.631674824
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.3405396965
Short name T718
Test name
Test status
Simulation time 3669307175 ps
CPU time 6.13 seconds
Started Jul 28 07:18:45 PM PDT 24
Finished Jul 28 07:18:51 PM PDT 24
Peak memory 220756 kb
Host smart-b1d51b19-7ddb-46f3-9841-906a52aaaa56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405396965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.3405396965
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.1352060513
Short name T657
Test name
Test status
Simulation time 255156549 ps
CPU time 2.64 seconds
Started Jul 28 07:18:46 PM PDT 24
Finished Jul 28 07:18:49 PM PDT 24
Peak memory 233652 kb
Host smart-ac1bf236-56be-463b-8655-1dc149bfca4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352060513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.1352060513
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.2029888789
Short name T413
Test name
Test status
Simulation time 2754683172 ps
CPU time 8.85 seconds
Started Jul 28 07:18:49 PM PDT 24
Finished Jul 28 07:18:58 PM PDT 24
Peak memory 223224 kb
Host smart-bc5b39e8-11e4-4ca8-9d5e-849ef3cec011
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2029888789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.2029888789
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.1455573066
Short name T954
Test name
Test status
Simulation time 39749732433 ps
CPU time 163.44 seconds
Started Jul 28 07:18:48 PM PDT 24
Finished Jul 28 07:21:32 PM PDT 24
Peak memory 251012 kb
Host smart-8f0cdd44-edaa-48ca-92bf-c5c565097964
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455573066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.1455573066
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.3996852527
Short name T877
Test name
Test status
Simulation time 1120078440 ps
CPU time 8.78 seconds
Started Jul 28 07:18:44 PM PDT 24
Finished Jul 28 07:18:52 PM PDT 24
Peak memory 220104 kb
Host smart-603e659e-3d32-4f35-b00d-51e346ced47e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996852527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.3996852527
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.640906173
Short name T717
Test name
Test status
Simulation time 371520908 ps
CPU time 2.48 seconds
Started Jul 28 07:18:45 PM PDT 24
Finished Jul 28 07:18:48 PM PDT 24
Peak memory 217204 kb
Host smart-caabccad-75d3-4c0d-bc3c-f2a181995461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640906173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.640906173
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.1896361333
Short name T55
Test name
Test status
Simulation time 375656533 ps
CPU time 1.44 seconds
Started Jul 28 07:18:43 PM PDT 24
Finished Jul 28 07:18:44 PM PDT 24
Peak memory 217224 kb
Host smart-f68ce30e-482e-4473-b13f-226f347ddc28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896361333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.1896361333
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.3831796153
Short name T768
Test name
Test status
Simulation time 17242278 ps
CPU time 0.75 seconds
Started Jul 28 07:18:44 PM PDT 24
Finished Jul 28 07:18:45 PM PDT 24
Peak memory 206856 kb
Host smart-3e8d106f-bba1-4dea-9b6b-d538d0c6106b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831796153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.3831796153
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.2750166289
Short name T204
Test name
Test status
Simulation time 23928723428 ps
CPU time 21.08 seconds
Started Jul 28 07:18:45 PM PDT 24
Finished Jul 28 07:19:06 PM PDT 24
Peak memory 233664 kb
Host smart-24800f9b-9c81-4c1d-884e-21e26e807cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750166289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.2750166289
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.4059858803
Short name T517
Test name
Test status
Simulation time 48463448 ps
CPU time 0.74 seconds
Started Jul 28 07:18:53 PM PDT 24
Finished Jul 28 07:18:54 PM PDT 24
Peak memory 205464 kb
Host smart-4ae88d0a-8959-49b3-ba84-80e7dc70024f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059858803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.4
059858803
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.546504622
Short name T762
Test name
Test status
Simulation time 527992714 ps
CPU time 5.48 seconds
Started Jul 28 07:18:55 PM PDT 24
Finished Jul 28 07:19:01 PM PDT 24
Peak memory 225452 kb
Host smart-7e6e0e28-ba2e-43f6-ab3c-b9cae3c0b098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546504622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.546504622
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.2917973716
Short name T930
Test name
Test status
Simulation time 55922321 ps
CPU time 0.76 seconds
Started Jul 28 07:18:52 PM PDT 24
Finished Jul 28 07:18:53 PM PDT 24
Peak memory 206184 kb
Host smart-188bf582-b08e-4afa-b94e-1ef6f3e2bd96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917973716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.2917973716
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.3517813619
Short name T207
Test name
Test status
Simulation time 13036188051 ps
CPU time 127.75 seconds
Started Jul 28 07:18:53 PM PDT 24
Finished Jul 28 07:21:01 PM PDT 24
Peak memory 268316 kb
Host smart-3ebf1ca2-e8dc-4528-a895-9dabcce0681c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517813619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.3517813619
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.2754214142
Short name T242
Test name
Test status
Simulation time 13556565121 ps
CPU time 223.62 seconds
Started Jul 28 07:18:54 PM PDT 24
Finished Jul 28 07:22:38 PM PDT 24
Peak memory 266624 kb
Host smart-e605d3f1-e816-4d62-8649-6a0a2e2c90b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754214142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.2754214142
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.633954201
Short name T311
Test name
Test status
Simulation time 336615523672 ps
CPU time 718.74 seconds
Started Jul 28 07:18:54 PM PDT 24
Finished Jul 28 07:30:53 PM PDT 24
Peak memory 274580 kb
Host smart-b2982b53-aaef-4071-aa12-2863bba2aeb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633954201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle.
633954201
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.806977372
Short name T314
Test name
Test status
Simulation time 3200627497 ps
CPU time 41.05 seconds
Started Jul 28 07:18:53 PM PDT 24
Finished Jul 28 07:19:34 PM PDT 24
Peak memory 233660 kb
Host smart-c8f896e9-4a87-41e3-89d9-10f18abeffec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806977372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.806977372
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.1901584748
Short name T232
Test name
Test status
Simulation time 516386692432 ps
CPU time 180.72 seconds
Started Jul 28 07:18:53 PM PDT 24
Finished Jul 28 07:21:54 PM PDT 24
Peak memory 250964 kb
Host smart-7a8ef8dd-4b54-427e-af27-3de3a8ff3209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901584748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds
.1901584748
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/8.spi_device_intercept.2411926547
Short name T734
Test name
Test status
Simulation time 1754040812 ps
CPU time 19.62 seconds
Started Jul 28 07:18:50 PM PDT 24
Finished Jul 28 07:19:10 PM PDT 24
Peak memory 233768 kb
Host smart-231b8f2a-1d67-4fc9-9478-57b5c579706e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411926547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.2411926547
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.2555065344
Short name T492
Test name
Test status
Simulation time 36355430831 ps
CPU time 69.01 seconds
Started Jul 28 07:18:53 PM PDT 24
Finished Jul 28 07:20:02 PM PDT 24
Peak memory 241452 kb
Host smart-143c56fc-b32d-434f-ab7a-93d99f01bec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555065344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.2555065344
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.945419041
Short name T571
Test name
Test status
Simulation time 17434110 ps
CPU time 1.07 seconds
Started Jul 28 07:18:52 PM PDT 24
Finished Jul 28 07:18:53 PM PDT 24
Peak memory 217392 kb
Host smart-9a62aa10-3741-4199-8848-3c44d9e940ef
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945419041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.spi_device_mem_parity.945419041
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.3435125681
Short name T451
Test name
Test status
Simulation time 93823632 ps
CPU time 2.11 seconds
Started Jul 28 07:18:49 PM PDT 24
Finished Jul 28 07:18:51 PM PDT 24
Peak memory 223812 kb
Host smart-c6a903a0-9c60-4b09-977d-0730129e65be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435125681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.3435125681
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.2734362215
Short name T581
Test name
Test status
Simulation time 51127471 ps
CPU time 2.17 seconds
Started Jul 28 07:18:48 PM PDT 24
Finished Jul 28 07:18:50 PM PDT 24
Peak memory 225360 kb
Host smart-983e0351-9697-4fa0-adc9-4e35467182a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734362215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.2734362215
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.642556665
Short name T663
Test name
Test status
Simulation time 1117821067 ps
CPU time 9.7 seconds
Started Jul 28 07:18:53 PM PDT 24
Finished Jul 28 07:19:03 PM PDT 24
Peak memory 224052 kb
Host smart-dba69ffa-813f-44c4-9696-8c222bd5c5ad
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=642556665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_direc
t.642556665
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.1887424497
Short name T458
Test name
Test status
Simulation time 8741965481 ps
CPU time 13.02 seconds
Started Jul 28 07:18:49 PM PDT 24
Finished Jul 28 07:19:02 PM PDT 24
Peak memory 217292 kb
Host smart-ec4f4770-f239-41bc-9611-2b4d7712802a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887424497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.1887424497
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.3555016626
Short name T770
Test name
Test status
Simulation time 7387363876 ps
CPU time 8.09 seconds
Started Jul 28 07:18:52 PM PDT 24
Finished Jul 28 07:19:01 PM PDT 24
Peak memory 217212 kb
Host smart-b85284e8-edae-4c95-b869-77db8e0de065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555016626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.3555016626
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.545736788
Short name T461
Test name
Test status
Simulation time 111865690 ps
CPU time 1.09 seconds
Started Jul 28 07:18:48 PM PDT 24
Finished Jul 28 07:18:49 PM PDT 24
Peak memory 208772 kb
Host smart-fd81bd82-9682-4729-a7ec-703156961903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545736788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.545736788
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.3349309769
Short name T835
Test name
Test status
Simulation time 158873583 ps
CPU time 0.91 seconds
Started Jul 28 07:18:50 PM PDT 24
Finished Jul 28 07:18:51 PM PDT 24
Peak memory 206756 kb
Host smart-c33a2ca3-8ec7-4669-a078-03a67049903d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349309769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.3349309769
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.1796113647
Short name T466
Test name
Test status
Simulation time 4324774730 ps
CPU time 8.23 seconds
Started Jul 28 07:18:53 PM PDT 24
Finished Jul 28 07:19:01 PM PDT 24
Peak memory 233688 kb
Host smart-edf31bf3-91d3-40b1-bdc0-d3dded9d1161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796113647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.1796113647
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.3629661153
Short name T627
Test name
Test status
Simulation time 14921729 ps
CPU time 0.77 seconds
Started Jul 28 07:19:02 PM PDT 24
Finished Jul 28 07:19:03 PM PDT 24
Peak memory 206116 kb
Host smart-a3e80ed0-24b6-4f77-928e-87304ced0964
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629661153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.3
629661153
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.258378273
Short name T1002
Test name
Test status
Simulation time 3299809557 ps
CPU time 8.27 seconds
Started Jul 28 07:18:57 PM PDT 24
Finished Jul 28 07:19:06 PM PDT 24
Peak memory 233756 kb
Host smart-4a5e7991-7cb6-4ac8-8718-44bff620a0a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258378273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.258378273
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.915584003
Short name T433
Test name
Test status
Simulation time 46853197 ps
CPU time 0.8 seconds
Started Jul 28 07:18:54 PM PDT 24
Finished Jul 28 07:18:55 PM PDT 24
Peak memory 207284 kb
Host smart-d1823da9-bfef-459f-83ae-ec86413605d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915584003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.915584003
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.845680673
Short name T376
Test name
Test status
Simulation time 11928077 ps
CPU time 0.75 seconds
Started Jul 28 07:18:58 PM PDT 24
Finished Jul 28 07:18:58 PM PDT 24
Peak memory 216636 kb
Host smart-9878cf1e-5ea1-4dc2-b7af-f50b301af956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845680673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.845680673
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.711698330
Short name T1001
Test name
Test status
Simulation time 67880805394 ps
CPU time 72.36 seconds
Started Jul 28 07:19:02 PM PDT 24
Finished Jul 28 07:20:15 PM PDT 24
Peak memory 258396 kb
Host smart-0d0ca680-d8d3-4e34-bc68-73aac74ea9f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711698330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.711698330
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.1414288948
Short name T329
Test name
Test status
Simulation time 4122837292 ps
CPU time 28.68 seconds
Started Jul 28 07:18:58 PM PDT 24
Finished Jul 28 07:19:27 PM PDT 24
Peak memory 225540 kb
Host smart-2421f2ed-747e-4336-8951-c4b2e3368290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414288948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.1414288948
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.1559241956
Short name T456
Test name
Test status
Simulation time 207277187 ps
CPU time 2.89 seconds
Started Jul 28 07:18:56 PM PDT 24
Finished Jul 28 07:18:59 PM PDT 24
Peak memory 225472 kb
Host smart-81b2a3c3-b7ad-448b-97ce-605e23c39311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559241956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.1559241956
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.2045958628
Short name T824
Test name
Test status
Simulation time 1423853795 ps
CPU time 32.12 seconds
Started Jul 28 07:18:56 PM PDT 24
Finished Jul 28 07:19:28 PM PDT 24
Peak memory 253424 kb
Host smart-daa8a5d0-decc-40a3-860d-a175c3f37b78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045958628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds
.2045958628
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_intercept.1251776150
Short name T555
Test name
Test status
Simulation time 915390419 ps
CPU time 5.09 seconds
Started Jul 28 07:18:57 PM PDT 24
Finished Jul 28 07:19:03 PM PDT 24
Peak memory 233604 kb
Host smart-f92da27c-5ad1-4207-bd89-d31e8b42a168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251776150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.1251776150
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.1091737467
Short name T518
Test name
Test status
Simulation time 5382579636 ps
CPU time 61.78 seconds
Started Jul 28 07:18:57 PM PDT 24
Finished Jul 28 07:19:59 PM PDT 24
Peak memory 225576 kb
Host smart-944363e7-d160-4c31-a4d5-6cadb245601f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091737467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.1091737467
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.1832959856
Short name T546
Test name
Test status
Simulation time 17434082 ps
CPU time 1.08 seconds
Started Jul 28 07:18:54 PM PDT 24
Finished Jul 28 07:18:55 PM PDT 24
Peak memory 217396 kb
Host smart-4ffe6f3a-1d3f-4b77-adbb-4dc77cc4d711
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832959856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.spi_device_mem_parity.1832959856
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.294834389
Short name T989
Test name
Test status
Simulation time 12161974577 ps
CPU time 17.42 seconds
Started Jul 28 07:18:58 PM PDT 24
Finished Jul 28 07:19:15 PM PDT 24
Peak memory 233676 kb
Host smart-ca94088c-d127-4c1a-b1cb-9c57f90c4c67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294834389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.294834389
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.2609977009
Short name T986
Test name
Test status
Simulation time 2952903980 ps
CPU time 10.83 seconds
Started Jul 28 07:19:03 PM PDT 24
Finished Jul 28 07:19:13 PM PDT 24
Peak memory 224032 kb
Host smart-6efd8673-dcb7-4b32-ab4b-2519665141c4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2609977009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.2609977009
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.39989715
Short name T147
Test name
Test status
Simulation time 109063803190 ps
CPU time 164.52 seconds
Started Jul 28 07:19:00 PM PDT 24
Finished Jul 28 07:21:45 PM PDT 24
Peak memory 266532 kb
Host smart-681aa753-2987-45e4-a5ab-42b66e70c07a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39989715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stress_
all.39989715
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.2225870729
Short name T509
Test name
Test status
Simulation time 2708863975 ps
CPU time 11.91 seconds
Started Jul 28 07:18:53 PM PDT 24
Finished Jul 28 07:19:05 PM PDT 24
Peak memory 220888 kb
Host smart-59838718-50b9-47bd-a463-5508b65b222a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225870729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.2225870729
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.807666273
Short name T590
Test name
Test status
Simulation time 287956363 ps
CPU time 2.39 seconds
Started Jul 28 07:18:53 PM PDT 24
Finished Jul 28 07:18:56 PM PDT 24
Peak memory 217132 kb
Host smart-8f0a78ff-ea88-44b5-a7a5-8348d700fb0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807666273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.807666273
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.1147819735
Short name T359
Test name
Test status
Simulation time 212234701 ps
CPU time 1.46 seconds
Started Jul 28 07:18:58 PM PDT 24
Finished Jul 28 07:18:59 PM PDT 24
Peak memory 217176 kb
Host smart-76e100a2-4b41-4cf3-b3fe-df3f3d92b438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147819735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.1147819735
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.2730999498
Short name T387
Test name
Test status
Simulation time 13300112 ps
CPU time 0.7 seconds
Started Jul 28 07:18:53 PM PDT 24
Finished Jul 28 07:18:54 PM PDT 24
Peak memory 206296 kb
Host smart-a94c0107-1132-458b-9fc2-fac5b180a919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730999498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.2730999498
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.1053334955
Short name T917
Test name
Test status
Simulation time 6442566733 ps
CPU time 23.43 seconds
Started Jul 28 07:18:57 PM PDT 24
Finished Jul 28 07:19:20 PM PDT 24
Peak memory 233752 kb
Host smart-360f2366-5b74-445c-96e2-90331c72652d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053334955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.1053334955
Directory /workspace/9.spi_device_upload/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%