Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2463715	1			T1	1		T2	1		T3	7873
all_values[1]	2463715	1			T1	1		T2	1		T3	7873
all_values[2]	2463715	1			T1	1		T2	1		T3	7873
all_values[3]	2463715	1			T1	1		T2	1		T3	7873
all_values[4]	2463715	1			T1	1		T2	1		T3	7873
all_values[5]	2463715	1			T1	1		T2	1		T3	7873
all_values[6]	2463715	1			T1	1		T2	1		T3	7873
all_values[7]	2463715	1			T1	1		T2	1		T3	7873

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19496294

1

T1

8

T2

8

T3

62984

auto[1]

213426

1

T5

24

T15

1323

T17

56

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19679280

1

T1

8

T2

8

T3

62916

auto[1]

30440

1

T3

68

T5

109

T13

148

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2399923	1			T1	1		T2	1		T3	7811
all_values[0]	auto[0]	auto[1]	14341	1			T3	62		T5	40		T13	72
all_values[0]	auto[1]	auto[0]	48886	1			T5	6		T15	1		T17	6
all_values[0]	auto[1]	auto[1]	565	1			T15	1		T17	4		T20	261
all_values[1]	auto[0]	auto[0]	2412943	1			T1	1		T2	1		T3	7870
all_values[1]	auto[0]	auto[1]	9742	1			T3	3		T5	40		T13	49
all_values[1]	auto[1]	auto[0]	40755	1			T5	6		T15	258		T17	2
all_values[1]	auto[1]	auto[1]	275	1			T15	5		T17	2		T20	69
all_values[2]	auto[0]	auto[0]	2437501	1			T1	1		T2	1		T3	7870
all_values[2]	auto[0]	auto[1]	3451	1			T3	3		T5	17		T13	27
all_values[2]	auto[1]	auto[0]	22497	1			T15	260		T17	7		T20	5
all_values[2]	auto[1]	auto[1]	266	1			T5	1		T15	5		T17	2
all_values[3]	auto[0]	auto[0]	2459751	1			T1	1		T2	1		T3	7873
all_values[3]	auto[0]	auto[1]	218	1			T15	5		T50	1		T17	5
all_values[3]	auto[1]	auto[0]	3560	1			T5	1		T15	255		T17	2
all_values[3]	auto[1]	auto[1]	186	1			T15	2		T17	1		T20	1
all_values[4]	auto[0]	auto[0]	2448313	1			T1	1		T2	1		T3	7873
all_values[4]	auto[0]	auto[1]	170	1			T15	4		T17	2		T20	2
all_values[4]	auto[1]	auto[0]	15063	1			T5	2		T15	258		T17	7
all_values[4]	auto[1]	auto[1]	169	1			T15	4		T17	1		T20	3
all_values[5]	auto[0]	auto[0]	2443867	1			T1	1		T2	1		T3	7873
all_values[5]	auto[0]	auto[1]	185	1			T5	1		T17	3		T20	1
all_values[5]	auto[1]	auto[0]	19513	1			T15	262		T17	3		T20	1
all_values[5]	auto[1]	auto[1]	150	1			T5	2		T15	2		T17	1
all_values[6]	auto[0]	auto[0]	2442729	1			T1	1		T2	1		T3	7873
all_values[6]	auto[0]	auto[1]	182	1			T5	3		T15	3		T17	3
all_values[6]	auto[1]	auto[0]	20626	1			T15	5		T17	6		T20	1
all_values[6]	auto[1]	auto[1]	178	1			T5	1		T15	2		T17	1
all_values[7]	auto[0]	auto[0]	2422785	1			T1	1		T2	1		T3	7873
all_values[7]	auto[0]	auto[1]	193	1			T5	2		T15	7		T20	1
all_values[7]	auto[1]	auto[0]	40568	1			T5	3		T17	4		T20	34478
all_values[7]	auto[1]	auto[1]	169	1			T5	2		T15	3		T17	7