Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	36211	1			T2	12		T3	70		T5	88
auto[SpiFlashAddrCfg]	7688	1			T3	12		T4	2		T5	37
auto[SpiFlashAddr3b]	9211	1			T3	23		T4	2		T5	59
auto[SpiFlashAddr4b]	7902	1			T3	32		T5	33		T9	15

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

35434

1

T2

12

T3

63

T4

4

auto[1]

25578

1

T3

74

T5

112

T9

59

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32500

1

T2

12

T3

79

T4

4

auto[1]

28512

1

T3

58

T5

114

T9

68

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	41125	1			T2	12		T3	87		T5	113
values[1]	1165	1			T3	3		T5	3		T9	1
values[2]	1498	1			T3	4		T5	11		T9	5
values[3]	1423	1			T5	3		T9	8		T10	3
values[4]	1544	1			T3	3		T5	5		T9	5
values[5]	1455	1			T3	4		T5	4		T9	3
values[6]	1486	1			T3	2		T5	13		T9	4
values[7]	1479	1			T3	7		T5	10		T9	10
values[8]	9837	1			T3	27		T4	4		T5	55

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28471

1

T2

12

T4

4

T5

217

auto[1]

32541

1

T3

137

T10

141

T13

111

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

57558

1

T2

12

T3

129

T4

4

write

3454

1

T3

8

T5

17

T9

7

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

19629

1

T2

12

T3

50

T4

2

valids[0x1]

41383

1

T3

87

T4

2

T5

124

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1680	1			T3	4		T5	10		T9	5
internal_process_ops[0x5a]	1568	1			T3	8		T5	5		T9	8
internal_process_ops[0x05]	21709	1			T3	20		T5	23		T9	81
internal_process_ops[0x35]	1611	1			T3	6		T5	9		T9	5
internal_process_ops[0x15]	1637	1			T3	11		T5	7		T9	4
internal_process_ops[0x03]	1042	1			T5	9		T9	1		T10	2
internal_process_ops[0x0b]	1039	1			T3	1		T5	8		T9	5
internal_process_ops[0x3b]	1006	1			T5	2		T9	6		T10	1
internal_process_ops[0x6b]	1011	1			T5	10		T9	4		T10	1
internal_process_ops[0xbb]	1038	1			T3	1		T5	9		T9	4
internal_process_ops[0xeb]	1078	1			T3	3		T5	6		T9	3

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

59364

1

T2

12

T3

131

T4

4

auto[1]

1648

1

T3

6

T5

8

T9

4

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

58458

1

T2

12

T3

132

T4

4

auto[1]

2554

1

T3

5

T5

9

T9

10

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10028

1

T2

12

T5

41

T9

93

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

4987

1

T5

40

T9

29

T33

15

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1864

1

T4

2

T5

11

T9

8

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1779

1

T5

22

T9

7

T33

7

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2271

1

T4

2

T5

33

T9

25

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2034

1

T5

22

T9

15

T33

3

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2065

1

T5

12

T9

10

T11

8

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1810

1

T5

19

T9

4

T33

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

167

1

T5

2

T9

1

T36

4

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

111

1

T5

2

T33

2

T36

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

91

1

T5

1

T36

2

T38

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

73

1

T5

2

T36

2

T38

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

124

1

T110

3

T52

2

T56

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

96

1

T5

1

T36

1

T55

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

81

1

T5

2

T9

2

T81

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

100

1

T5

1

T110

2

T52

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

100

1

T33

1

T36

1

T110

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

104

1

T5

1

T9

2

T33

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

102

1

T5

2

T33

2

T52

3

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

90

1

T5

1

T9

1

T81

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

98

1

T5

2

T36

1

T81

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

90

1

T36

3

T81

3

T55

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

90

1

T52

1

T56

2

T57

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

116

1

T9

1

T36

1

T54

2

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

12012

1

T3

33

T10

85

T13

24

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

8316

1

T3

35

T10

11

T13

39

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1601

1

T3

4

T10

6

T13

7

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1570

1

T3

8

T10

5

T13

7

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2083

1

T3

14

T10

10

T13

8

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1950

1

T3

8

T13

8

T15

24

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1676

1

T3

10

T10

8

T13

7

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1512

1

T3

17

T10

8

T13

6

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

109

1

T3

1

T13

1

T15

4

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

108

1

T10

2

T13

2

T15

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

111

1

T29

2

T44

4

T46

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

98

1

T3

1

T15

1

T29

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

131

1

T13

2

T15

1

T29

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

116

1

T10

2

T15

2

T44

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

110

1

T15

2

T44

1

T164

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

116

1

T15

2

T29

1

T164

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

126

1

T3

1

T29

1

T164

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

129

1

T10

1

T15

2

T29

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

109

1

T29

4

T44

2

T164

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

113

1

T15

1

T29

1

T44

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

116

1

T10

2

T15

3

T29

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

109

1

T15

2

T17

3

T165

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

141

1

T10

1

T164

1

T85

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

79

1

T3

5

T15

2

T17

2

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3725	1			T2	12		T5	24		T9	30
auto[0]	values[0]	valids[0x1]	14205	1			T5	89		T9	112		T12	12
auto[0]	values[1]	valids[0x1]	516	1			T5	3		T9	1		T11	4
auto[0]	values[2]	valids[0x0]	509	1			T5	6		T9	4		T33	3
auto[0]	values[2]	valids[0x1]	281	1			T5	5		T9	1		T98	2
auto[0]	values[3]	valids[0x0]	482	1			T5	2		T9	4		T11	2
auto[0]	values[3]	valids[0x1]	299	1			T5	1		T9	4		T30	4
auto[0]	values[4]	valids[0x0]	526	1			T5	4		T9	5		T36	8
auto[0]	values[4]	valids[0x1]	299	1			T5	1		T92	2		T38	1
auto[0]	values[5]	valids[0x0]	497	1			T9	3		T30	2		T36	8
auto[0]	values[5]	valids[0x1]	276	1			T5	4		T33	1		T36	6
auto[0]	values[6]	valids[0x0]	569	1			T5	8		T9	4		T36	5
auto[0]	values[6]	valids[0x1]	274	1			T5	5		T33	3		T36	3
auto[0]	values[7]	valids[0x0]	547	1			T5	8		T9	9		T11	4
auto[0]	values[7]	valids[0x1]	285	1			T5	2		T9	1		T36	2
auto[0]	values[8]	valids[0x0]	3328	1			T4	2		T5	41		T9	12
auto[0]	values[8]	valids[0x1]	1853	1			T4	2		T5	14		T9	8
auto[1]	values[0]	valids[0x0]	4294	1			T3	27		T10	26		T13	24
auto[1]	values[0]	valids[0x1]	18901	1			T3	60		T10	76		T13	51
auto[1]	values[1]	valids[0x1]	649	1			T3	3		T10	3		T13	2
auto[1]	values[2]	valids[0x0]	401	1			T10	2		T15	7		T29	1
auto[1]	values[2]	valids[0x1]	307	1			T3	4		T10	1		T13	2
auto[1]	values[3]	valids[0x0]	394	1			T13	3		T15	6		T29	3
auto[1]	values[3]	valids[0x1]	248	1			T10	3		T15	2		T29	2
auto[1]	values[4]	valids[0x0]	455	1			T3	3		T10	5		T15	1
auto[1]	values[4]	valids[0x1]	264	1			T10	1		T15	1		T29	2
auto[1]	values[5]	valids[0x0]	379	1			T3	3		T10	1		T15	2
auto[1]	values[5]	valids[0x1]	303	1			T3	1		T10	2		T13	2
auto[1]	values[6]	valids[0x0]	395	1			T3	1		T13	3		T15	3
auto[1]	values[6]	valids[0x1]	248	1			T3	1		T13	1		T15	2
auto[1]	values[7]	valids[0x0]	384	1			T3	2		T13	5		T15	2
auto[1]	values[7]	valids[0x1]	263	1			T3	5		T15	1		T29	3
auto[1]	values[8]	valids[0x0]	2744	1			T3	14		T10	8		T13	12
auto[1]	values[8]	valids[0x1]	1912	1			T3	13		T10	13		T13	6