Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3331782

1

T2

857

T3

2907

T4

1

auto[1]

32128

1

T3

17

T5

17

T9

78

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

912478

1

T2

857

T3

33

T4

1

auto[1]

2451432

1

T3

2891

T5

25307

T9

10890

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	648804	1			T3	614		T4	1		T5	9178
auto[524288:1048575]	373441	1			T2	172		T3	1261		T5	5259
auto[1048576:1572863]	363550	1			T3	7		T5	2963		T9	21
auto[1572864:2097151]	430788	1			T2	13		T3	887		T5	388
auto[2097152:2621439]	385042	1			T3	7		T5	262		T10	1
auto[2621440:3145727]	367554	1			T2	640		T3	1		T5	2994
auto[3145728:3670015]	395123	1			T3	135		T5	8		T9	10
auto[3670016:4194303]	399608	1			T2	32		T3	12		T5	4308

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2486217

1

T2

49

T3

2924

T4

1

auto[1]

877693

1

T2

808

T5

1

T9

9

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2920476

1

T2

720

T3

2537

T4

1

auto[1]

443434

1

T2

137

T3

387

T5

13

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	173046	1			T3	6		T4	1		T5	5
auto[0]	auto[0]	auto[0:524287]	auto[1]	395600	1			T3	608		T5	9161		T9	4289
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	74712	1			T2	172		T3	1		T5	6
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	236961	1			T3	1024		T5	5252		T9	2127
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	79171	1			T3	3		T5	6		T9	3
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	231594	1			T3	4		T5	2953		T9	2
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	137149	1			T2	13		T3	1		T9	5
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	237731	1			T3	747		T5	386		T9	2999
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	99273	1			T3	3		T5	6		T10	1
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	227219	1			T3	1		T5	256		T12	2831
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	74370	1			T2	503		T3	1		T5	5
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	233041	1			T5	2984		T9	258		T10	258
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	145749	1			T3	1		T5	7		T9	3
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	200388	1			T3	134		T9	1		T10	1
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	118429	1			T2	32		T5	6		T9	4
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	228141	1			T5	4301		T9	1016		T10	266
auto[0]	auto[1]	auto[0:524287]	auto[0]	984	1			T5	1		T10	1		T97	4
auto[0]	auto[1]	auto[0:524287]	auto[1]	73302	1			T5	2		T15	1381		T52	2624
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	997	1			T3	5		T5	1		T15	3
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	56392	1			T3	228		T15	1		T52	512
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	435	1			T9	1		T15	1		T29	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	49305	1			T5	4		T9	1		T15	5
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	601	1			T3	3		T9	1		T33	2
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	51730	1			T3	130		T9	1		T33	1
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	930	1			T15	1		T36	2		T52	2
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	53000	1			T36	256		T52	1215		T57	1
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	1016	1			T2	137		T9	1		T10	4
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	55823	1			T9	128		T10	1103		T15	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	577	1			T5	1		T9	1		T10	4
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	44495	1			T10	768		T29	3		T36	1775
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	926	1			T3	4		T29	1		T44	3
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	48695	1			T3	3		T29	5		T44	1002
auto[1]	auto[0]	auto[0:524287]	auto[0]	523	1			T5	2		T9	3		T13	2
auto[1]	auto[0]	auto[0:524287]	auto[1]	4654	1			T5	3		T9	25		T13	2
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	440	1			T9	1		T10	1		T13	1
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	3636	1			T9	7		T10	7		T13	9
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	374	1			T9	2		T15	2		T29	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2201	1			T9	6		T15	12		T36	28
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	423	1			T5	2		T13	2		T33	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	2540	1			T13	8		T33	2		T15	40
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	393	1			T3	1		T15	4		T44	3
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	3187	1			T3	2		T15	5		T44	30
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	397	1			T5	2		T10	1		T29	2
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	2655	1			T5	3		T10	1		T29	14
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	407	1			T9	1		T10	1		T33	2
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	3034	1			T9	4		T10	18		T33	6
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	436	1			T5	1		T9	1		T10	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	2602	1			T9	12		T10	11		T13	6
auto[1]	auto[1]	auto[0:524287]	auto[0]	100	1			T5	2		T15	4		T56	3
auto[1]	auto[1]	auto[0:524287]	auto[1]	595	1			T5	2		T15	12		T56	13
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	69	1			T3	2		T15	1		T19	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	234	1			T3	1		T87	11		T186	7
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	76	1			T9	1		T29	1		T38	2
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	394	1			T9	5		T38	5		T164	12
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	103	1			T3	1		T9	1		T33	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	511	1			T3	5		T9	9		T52	18
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	122	1			T52	1		T57	1		T17	2
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	918	1			T52	5		T57	5		T17	10
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	81	1			T15	1		T36	1		T85	3
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	171	1			T36	4		T85	17		T192	5
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	78	1			T29	1		T36	2		T164	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	395	1			T29	2		T36	21		T56	42
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	91	1			T3	1		T44	1		T38	2
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	288	1			T3	4		T44	5		T38	9

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	2017441	1			T2	47		T3	2534		T4	1
auto[0]	auto[0]	auto[1]	875133	1			T2	673		T9	3		T10	1
auto[0]	auto[1]	auto[0]	437338	1			T2	2		T3	373		T5	9
auto[0]	auto[1]	auto[1]	1870	1			T2	135		T9	1		T97	27
auto[1]	auto[0]	auto[0]	27340	1			T3	3		T5	12		T9	59
auto[1]	auto[0]	auto[1]	562	1			T5	1		T9	3		T10	3
auto[1]	auto[1]	auto[0]	4098	1			T3	14		T5	4		T9	14
auto[1]	auto[1]	auto[1]	128	1			T9	2		T15	1		T36	2