Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2463715	1			T1	1		T2	1		T3	7873
all_pins[1]	2463715	1			T1	1		T2	1		T3	7873
all_pins[2]	2463715	1			T1	1		T2	1		T3	7873
all_pins[3]	2463715	1			T1	1		T2	1		T3	7873
all_pins[4]	2463715	1			T1	1		T2	1		T3	7873
all_pins[5]	2463715	1			T1	1		T2	1		T3	7873
all_pins[6]	2463715	1			T1	1		T2	1		T3	7873
all_pins[7]	2463715	1			T1	1		T2	1		T3	7873

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	19687230	1			T1	8		T2	8		T3	62984
values[0x1]	22490	1			T5	6		T15	51		T17	19
transitions[0x0=>0x1]	21908	1			T5	5		T15	49		T17	14
transitions[0x1=>0x0]	21919	1			T5	5		T15	49		T17	14

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2463102	1			T1	1		T2	1		T3	7873
all_pins[0]	values[0x1]	613	1			T15	1		T17	4		T20	276
all_pins[0]	transitions[0x0=>0x1]	487	1			T15	1		T17	4		T20	199
all_pins[0]	transitions[0x1=>0x0]	162	1			T15	5		T17	2		T163	3
all_pins[1]	values[0x0]	2463427	1			T1	1		T2	1		T3	7873
all_pins[1]	values[0x1]	288	1			T15	5		T17	2		T20	77
all_pins[1]	transitions[0x0=>0x1]	232	1			T15	3		T17	2		T20	77
all_pins[1]	transitions[0x1=>0x0]	216	1			T5	1		T15	3		T17	2
all_pins[2]	values[0x0]	2463443	1			T1	1		T2	1		T3	7873
all_pins[2]	values[0x1]	272	1			T5	1		T15	5		T17	2
all_pins[2]	transitions[0x0=>0x1]	230	1			T5	1		T15	5		T17	1
all_pins[2]	transitions[0x1=>0x0]	144	1			T15	2		T163	4		T23	3
all_pins[3]	values[0x0]	2463529	1			T1	1		T2	1		T3	7873
all_pins[3]	values[0x1]	186	1			T15	2		T17	1		T20	1
all_pins[3]	transitions[0x0=>0x1]	140	1			T15	2		T17	1		T163	3
all_pins[3]	transitions[0x1=>0x0]	123	1			T15	4		T17	1		T20	2
all_pins[4]	values[0x0]	2463546	1			T1	1		T2	1		T3	7873
all_pins[4]	values[0x1]	169	1			T15	4		T17	1		T20	3
all_pins[4]	transitions[0x0=>0x1]	133	1			T15	4		T17	1		T20	2
all_pins[4]	transitions[0x1=>0x0]	296	1			T5	2		T15	29		T17	1
all_pins[5]	values[0x0]	2463383	1			T1	1		T2	1		T3	7873
all_pins[5]	values[0x1]	332	1			T5	2		T15	29		T17	1
all_pins[5]	transitions[0x0=>0x1]	146	1			T5	1		T15	29		T17	1
all_pins[5]	transitions[0x1=>0x0]	20275	1			T15	2		T17	1		T20	3
all_pins[6]	values[0x0]	2443254	1			T1	1		T2	1		T3	7873
all_pins[6]	values[0x1]	20461	1			T5	1		T15	2		T17	1
all_pins[6]	transitions[0x0=>0x1]	20420	1			T5	1		T15	2		T20	1
all_pins[6]	transitions[0x1=>0x0]	128	1			T5	2		T15	3		T17	6
all_pins[7]	values[0x0]	2463546	1			T1	1		T2	1		T3	7873
all_pins[7]	values[0x1]	169	1			T5	2		T15	3		T17	7
all_pins[7]	transitions[0x0=>0x1]	120	1			T5	2		T15	3		T17	4
all_pins[7]	transitions[0x1=>0x0]	575	1			T15	1		T17	1		T20	274