Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17118

1

T2

12

T4

4

T5

105

auto[1]

11353

1

T5

112

T9

59

T33

29

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3783	1			T36	82		T38	160		T52	144
values[1]	3772	1			T9	64		T97	10		T112	12
values[2]	3987	1			T2	12		T5	41		T9	40
values[3]	3797	1			T4	4		T5	61		T9	38
values[4]	3405	1			T9	56		T14	6		T36	20
values[5]	3234	1			T5	20		T98	10		T28	2
values[6]	3032	1			T5	21		T225	2		T228	2
values[7]	3461	1			T5	74		T33	32		T36	32

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3655	1			T5	63		T9	58		T111	10
values[1]	3390	1			T5	51		T9	20		T36	27
values[2]	3834	1			T5	21		T9	44		T14	6
values[3]	3809	1			T5	42		T11	16		T33	32
values[4]	3238	1			T2	12		T9	40		T33	20
values[5]	3404	1			T12	18		T36	20		T81	21
values[6]	3679	1			T4	4		T5	20		T112	12
values[7]	3462	1			T5	20		T9	36		T97	10

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	281	1			T52	6		T55	10		T57	28
auto[0]	values[0]	values[1]	261	1			T100	10		T229	13		T180	6
auto[0]	values[0]	values[2]	305	1			T38	22		T230	2		T219	13
auto[0]	values[0]	values[3]	359	1			T55	15		T231	6		T193	65
auto[0]	values[0]	values[4]	190	1			T36	7		T232	2		T101	8
auto[0]	values[0]	values[5]	220	1			T52	12		T56	39		T193	12
auto[0]	values[0]	values[6]	223	1			T36	31		T57	56		T194	10
auto[0]	values[0]	values[7]	443	1			T36	9		T99	11		T233	12
auto[0]	values[1]	values[0]	185	1			T9	10		T80	14		T17	12
auto[0]	values[1]	values[1]	216	1			T36	15		T99	6		T234	18
auto[0]	values[1]	values[2]	345	1			T9	36		T52	10		T17	14
auto[0]	values[1]	values[3]	390	1			T110	14		T19	15		T22	12
auto[0]	values[1]	values[4]	186	1			T52	15		T132	12		T194	53
auto[0]	values[1]	values[5]	504	1			T201	9		T99	12		T193	21
auto[0]	values[1]	values[6]	323	1			T112	12		T84	14		T201	13
auto[0]	values[1]	values[7]	256	1			T97	10		T36	20		T38	11
auto[0]	values[2]	values[0]	207	1			T36	15		T19	12		T35	13
auto[0]	values[2]	values[1]	228	1			T52	9		T17	29		T235	14
auto[0]	values[2]	values[2]	296	1			T186	27		T180	8		T236	4
auto[0]	values[2]	values[3]	288	1			T5	12		T52	11		T57	7
auto[0]	values[2]	values[4]	490	1			T2	12		T9	16		T33	11
auto[0]	values[2]	values[5]	254	1			T12	18		T56	16		T57	10
auto[0]	values[2]	values[6]	328	1			T5	8		T36	24		T55	15
auto[0]	values[2]	values[7]	255	1			T56	13		T178	6		T35	12
auto[0]	values[3]	values[0]	302	1			T5	13		T9	33		T111	10
auto[0]	values[3]	values[1]	241	1			T55	13		T19	15		T135	12
auto[0]	values[3]	values[2]	184	1			T5	14		T100	10		T178	14
auto[0]	values[3]	values[3]	453	1			T11	16		T99	14		T237	10
auto[0]	values[3]	values[4]	411	1			T56	14		T180	16		T238	21
auto[0]	values[3]	values[5]	296	1			T38	12		T56	7		T57	12
auto[0]	values[3]	values[6]	150	1			T4	4		T17	6		T192	9
auto[0]	values[3]	values[7]	372	1			T5	9		T81	12		T57	31
auto[0]	values[4]	values[0]	318	1			T57	6		T99	22		T193	11
auto[0]	values[4]	values[1]	177	1			T9	15		T55	14		T209	10
auto[0]	values[4]	values[2]	264	1			T14	6		T239	2		T100	15
auto[0]	values[4]	values[3]	203	1			T55	19		T56	5		T199	19
auto[0]	values[4]	values[4]	212	1			T56	40		T201	14		T178	7
auto[0]	values[4]	values[5]	164	1			T36	15		T219	8		T177	13
auto[0]	values[4]	values[6]	249	1			T52	25		T96	12		T240	22
auto[0]	values[4]	values[7]	312	1			T9	29		T241	4		T238	5
auto[0]	values[5]	values[0]	337	1			T5	13		T38	20		T56	12
auto[0]	values[5]	values[1]	250	1			T57	62		T194	11		T203	13
auto[0]	values[5]	values[2]	198	1			T226	6		T215	14		T194	15
auto[0]	values[5]	values[3]	226	1			T28	2		T36	11		T55	9
auto[0]	values[5]	values[4]	170	1			T98	10		T55	11		T56	24
auto[0]	values[5]	values[5]	117	1			T56	10		T57	7		T242	11
auto[0]	values[5]	values[6]	302	1			T36	5		T92	10		T56	35
auto[0]	values[5]	values[7]	220	1			T30	12		T55	9		T243	4
auto[0]	values[6]	values[0]	277	1			T228	2		T38	16		T52	26
auto[0]	values[6]	values[1]	261	1			T35	14		T194	10		T244	90
auto[0]	values[6]	values[2]	334	1			T55	15		T202	11		T176	8
auto[0]	values[6]	values[3]	288	1			T5	8		T225	2		T101	9
auto[0]	values[6]	values[4]	109	1			T199	11		T245	18		T206	11
auto[0]	values[6]	values[5]	208	1			T19	26		T20	13		T178	8
auto[0]	values[6]	values[6]	167	1			T57	11		T219	8		T246	2
auto[0]	values[6]	values[7]	220	1			T57	16		T207	12		T193	37
auto[0]	values[7]	values[0]	245	1			T5	13		T17	8		T20	19
auto[0]	values[7]	values[1]	327	1			T5	15		T56	57		T247	8
auto[0]	values[7]	values[2]	331	1			T36	27		T55	11		T211	10
auto[0]	values[7]	values[3]	281	1			T33	12		T210	10		T52	21
auto[0]	values[7]	values[4]	210	1			T178	20		T35	11		T203	13
auto[0]	values[7]	values[5]	294	1			T81	11		T180	10		T35	12
auto[0]	values[7]	values[6]	321	1			T99	12		T215	11		T178	8
auto[0]	values[7]	values[7]	84	1			T110	12		T248	2		T133	5
auto[1]	values[0]	values[0]	244	1			T52	76		T55	12		T57	6
auto[1]	values[0]	values[1]	165	1			T100	10		T229	7		T180	14
auto[1]	values[0]	values[2]	362	1			T38	138		T219	17		T198	22
auto[1]	values[0]	values[3]	126	1			T55	17		T193	4		T219	4
auto[1]	values[0]	values[4]	198	1			T36	14		T101	12		T215	7
auto[1]	values[0]	values[5]	133	1			T52	50		T56	7		T193	8
auto[1]	values[0]	values[6]	81	1			T36	5		T57	10		T194	10
auto[1]	values[0]	values[7]	192	1			T36	16		T99	9		T186	8
auto[1]	values[1]	values[0]	116	1			T9	10		T17	8		T100	6
auto[1]	values[1]	values[1]	214	1			T36	12		T99	14		T212	7
auto[1]	values[1]	values[2]	196	1			T9	8		T52	16		T17	6
auto[1]	values[1]	values[3]	226	1			T110	6		T19	12		T22	8
auto[1]	values[1]	values[4]	126	1			T52	5		T194	10		T203	8
auto[1]	values[1]	values[5]	221	1			T201	47		T99	8		T193	19
auto[1]	values[1]	values[6]	140	1			T201	7		T100	11		T20	7
auto[1]	values[1]	values[7]	128	1			T36	8		T38	20		T249	4
auto[1]	values[2]	values[0]	167	1			T36	7		T54	8		T19	11
auto[1]	values[2]	values[1]	197	1			T52	11		T17	16		T20	23
auto[1]	values[2]	values[2]	127	1			T186	7		T180	12		T205	13
auto[1]	values[2]	values[3]	280	1			T5	9		T52	9		T57	14
auto[1]	values[2]	values[4]	209	1			T9	24		T33	9		T133	12
auto[1]	values[2]	values[5]	216	1			T56	8		T57	22		T176	9
auto[1]	values[2]	values[6]	184	1			T5	12		T36	11		T55	12
auto[1]	values[2]	values[7]	261	1			T56	7		T178	14		T35	11
auto[1]	values[3]	values[0]	129	1			T5	7		T9	5		T110	9
auto[1]	values[3]	values[1]	124	1			T55	7		T19	7		T180	11
auto[1]	values[3]	values[2]	223	1			T5	7		T100	10		T178	6
auto[1]	values[3]	values[3]	180	1			T99	6		T250	76		T242	9
auto[1]	values[3]	values[4]	146	1			T56	6		T180	4		T238	22
auto[1]	values[3]	values[5]	177	1			T38	21		T56	13		T57	8
auto[1]	values[3]	values[6]	226	1			T17	18		T192	38		T19	12
auto[1]	values[3]	values[7]	183	1			T5	11		T81	8		T57	18
auto[1]	values[4]	values[0]	158	1			T57	14		T99	18		T193	9
auto[1]	values[4]	values[1]	206	1			T9	5		T55	6		T180	19
auto[1]	values[4]	values[2]	203	1			T100	5		T193	6		T186	9
auto[1]	values[4]	values[3]	122	1			T55	8		T56	15		T199	10
auto[1]	values[4]	values[4]	154	1			T56	9		T201	6		T178	13
auto[1]	values[4]	values[5]	152	1			T36	5		T219	34		T251	14
auto[1]	values[4]	values[6]	347	1			T52	69		T218	24		T252	7
auto[1]	values[4]	values[7]	164	1			T9	7		T238	21		T253	17
auto[1]	values[5]	values[0]	231	1			T5	7		T38	7		T56	18
auto[1]	values[5]	values[1]	206	1			T57	14		T194	9		T203	7
auto[1]	values[5]	values[2]	145	1			T215	13		T194	37		T203	28
auto[1]	values[5]	values[3]	105	1			T36	9		T55	11		T202	8
auto[1]	values[5]	values[4]	190	1			T55	9		T56	46		T254	20
auto[1]	values[5]	values[5]	137	1			T214	2		T56	11		T57	13
auto[1]	values[5]	values[6]	254	1			T36	28		T56	21		T57	30
auto[1]	values[5]	values[7]	146	1			T55	11		T178	8		T205	10
auto[1]	values[6]	values[0]	173	1			T38	17		T52	4		T203	13
auto[1]	values[6]	values[1]	89	1			T35	6		T194	10		T177	7
auto[1]	values[6]	values[2]	144	1			T55	5		T202	16		T176	12
auto[1]	values[6]	values[3]	198	1			T5	13		T101	11		T186	13
auto[1]	values[6]	values[4]	94	1			T199	9		T206	11		T59	12
auto[1]	values[6]	values[5]	102	1			T19	8		T20	11		T178	12
auto[1]	values[6]	values[6]	197	1			T57	9		T219	27		T202	13
auto[1]	values[6]	values[7]	171	1			T57	8		T193	5		T202	9
auto[1]	values[7]	values[0]	285	1			T5	10		T17	12		T20	8
auto[1]	values[7]	values[1]	228	1			T5	36		T56	4		T255	6
auto[1]	values[7]	values[2]	177	1			T36	5		T55	30		T99	7
auto[1]	values[7]	values[3]	84	1			T33	20		T52	5		T180	12
auto[1]	values[7]	values[4]	143	1			T53	10		T178	20		T35	10
auto[1]	values[7]	values[5]	209	1			T81	10		T180	10		T35	8
auto[1]	values[7]	values[6]	187	1			T99	8		T215	24		T178	12
auto[1]	values[7]	values[7]	55	1			T110	8		T133	15		T256	6