Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	433	1			T5	3		T11	4		T225	2
auto[ReadAddrCrossIntoMailbox]	306	1			T5	1		T11	4		T36	4
auto[ReadAddrCrossOutOfMailbox]	279	1			T5	3		T36	2		T110	2
auto[ReadAddrCrossAllMailbox]	207	1			T11	6		T81	1		T38	1
auto[ReadAddrOutsideMailbox]	3310	1			T5	37		T9	23		T11	2

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2220

1

T5

11

T9

14

T11

8

auto[1]

2315

1

T5

33

T9

9

T11

8

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	747	1			T5	9		T9	1		T33	2
read_ops[0x0b]	746	1			T5	8		T9	5		T11	4
read_ops[0x3b]	731	1			T5	2		T9	6		T33	1
read_ops[0x6b]	759	1			T5	10		T9	4		T11	6
read_ops[0xbb]	762	1			T5	9		T9	4		T11	4
read_ops[0xeb]	790	1			T5	6		T9	3		T11	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	33	1			T38	1		T56	1		T57	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	40	1			T5	1		T56	2		T226	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	24	1			T52	2		T56	1		T201	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	20	1			T56	2		T19	1		T186	2
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	14	1			T52	1		T135	1		T205	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	24	1			T56	2		T100	1		T135	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	14	1			T52	1		T135	2		T193	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	20	1			T56	1		T17	1		T192	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	279	1			T5	4		T9	1		T36	5
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	279	1			T5	4		T33	2		T110	3
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	38	1			T38	1		T192	1		T201	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	43	1			T55	2		T56	1		T57	2
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	27	1			T11	1		T52	1		T17	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	23	1			T11	1		T55	1		T57	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	24	1			T36	1		T110	1		T192	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	21	1			T5	1		T36	1		T56	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T11	1		T81	1		T56	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	8	1			T11	1		T57	1		T178	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	250	1			T33	2		T36	4		T38	2
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	295	1			T5	7		T9	5		T33	2
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	32	1			T55	1		T57	2		T99	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	33	1			T56	1		T215	1		T193	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	29	1			T36	2		T52	2		T17	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	27	1			T55	1		T192	1		T99	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	21	1			T52	1		T99	1		T180	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	24	1			T110	1		T56	1		T57	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T17	1		T192	1		T178	2
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	19	1			T192	1		T201	1		T178	2
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	255	1			T9	6		T33	1		T36	5
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	273	1			T5	2		T36	4		T110	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	38	1			T5	1		T201	1		T99	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	44	1			T56	2		T201	1		T219	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	29	1			T110	2		T17	1		T192	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	18	1			T56	2		T193	1		T178	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	19	1			T5	1		T56	1		T99	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	29	1			T55	1		T180	2		T257	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	22	1			T11	2		T192	1		T193	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	15	1			T11	2		T52	1		T56	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	245	1			T5	1		T9	4		T11	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	300	1			T5	7		T11	1		T36	9
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	33	1			T11	1		T57	2		T17	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	37	1			T5	1		T11	1		T56	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	24	1			T11	1		T210	1		T52	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	28	1			T5	1		T11	1		T36	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	21	1			T100	1		T135	1		T193	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	34	1			T5	1		T38	1		T55	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	23	1			T38	1		T56	1		T17	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	13	1			T52	1		T57	1		T201	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	259	1			T9	1		T33	1		T36	2
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	290	1			T5	6		T9	3		T36	4
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	34	1			T11	1		T225	1		T56	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	28	1			T11	1		T225	1		T81	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	28	1			T52	2		T56	1		T192	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	29	1			T36	1		T110	1		T57	2
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	24	1			T56	2		T57	1		T133	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	24	1			T81	1		T57	2		T99	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	14	1			T55	1		T133	1		T203	2
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	24	1			T57	1		T99	1		T20	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	332	1			T5	4		T9	2		T36	5
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	253	1			T5	2		T9	1		T33	1