Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3844	1			T5	20		T9	44		T11	16
values[1]	3192	1			T5	62		T28	2		T228	2
values[2]	3530	1			T5	41		T9	20		T36	57
values[3]	4250	1			T5	20		T9	36		T97	10
values[4]	3459	1			T2	12		T5	31		T9	20
values[5]	3118	1			T5	23		T9	38		T111	10
values[6]	3538	1			T4	4		T5	20		T12	18
values[7]	3540	1			T9	40		T36	79		T81	21

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3712	1			T2	12		T5	43		T9	56
values[1]	3428	1			T9	40		T12	18		T36	118
values[2]	3323	1			T9	20		T33	20		T98	10
values[3]	3759	1			T4	4		T5	31		T9	38
values[4]	3864	1			T5	41		T9	44		T11	16
values[5]	3558	1			T5	20		T30	12		T36	22
values[6]	2949	1			T5	61		T33	32		T28	2
values[7]	3878	1			T5	21		T36	57		T38	33

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27691

1

T2

12

T4

4

T5

209

auto[1]

780

1

T5

8

T9

4

T33

4

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	480	1			T5	20		T36	41		T110	18
auto[0]	values[0]	values[1]	288	1			T55	20		T100	19		T35	40
auto[0]	values[0]	values[2]	562	1			T33	20		T225	2		T55	19
auto[0]	values[0]	values[3]	613	1			T36	28		T38	26		T100	20
auto[0]	values[0]	values[4]	320	1			T9	44		T11	16		T112	12
auto[0]	values[0]	values[5]	278	1			T197	14		T247	8		T258	2
auto[0]	values[0]	values[6]	565	1			T33	28		T110	23		T193	74
auto[0]	values[0]	values[7]	650	1			T180	38		T194	74		T202	19
auto[0]	values[1]	values[0]	412	1			T55	19		T56	45		T192	29
auto[0]	values[1]	values[1]	323	1			T178	40		T216	4		T218	24
auto[0]	values[1]	values[2]	452	1			T209	10		T203	19		T199	54
auto[0]	values[1]	values[3]	364	1			T228	2		T53	10		T57	39
auto[0]	values[1]	values[4]	423	1			T5	20		T248	2		T57	63
auto[0]	values[1]	values[5]	418	1			T215	35		T259	6		T260	12
auto[0]	values[1]	values[6]	239	1			T5	20		T28	2		T246	2
auto[0]	values[1]	values[7]	467	1			T5	19		T17	20		T192	20
auto[0]	values[2]	values[0]	636	1			T9	20		T57	28		T186	33
auto[0]	values[2]	values[1]	434	1			T36	32		T55	27		T56	19
auto[0]	values[2]	values[2]	221	1			T56	20		T261	16		T203	20
auto[0]	values[2]	values[3]	384	1			T214	2		T230	2		T178	18
auto[0]	values[2]	values[4]	368	1			T186	31		T191	2		T253	26
auto[0]	values[2]	values[5]	648	1			T5	19		T36	21		T38	136
auto[0]	values[2]	values[6]	273	1			T5	19		T56	21		T99	18
auto[0]	values[2]	values[7]	458	1			T52	78		T133	20		T193	40
auto[0]	values[3]	values[0]	446	1			T9	36		T215	20		T193	42
auto[0]	values[3]	values[1]	707	1			T52	25		T57	20		T201	53
auto[0]	values[3]	values[2]	385	1			T98	10		T81	20		T101	18
auto[0]	values[3]	values[3]	457	1			T97	10		T253	54		T242	29
auto[0]	values[3]	values[4]	630	1			T56	70		T20	20		T262	20
auto[0]	values[3]	values[5]	561	1			T52	23		T57	34		T17	42
auto[0]	values[3]	values[6]	385	1			T5	20		T207	12		T232	2
auto[0]	values[3]	values[7]	569	1			T99	16		T133	19		T35	21
auto[0]	values[4]	values[0]	516	1			T2	12		T110	20		T52	20
auto[0]	values[4]	values[1]	278	1			T92	10		T234	18		T203	20
auto[0]	values[4]	values[2]	386	1			T9	20		T52	27		T56	97
auto[0]	values[4]	values[3]	433	1			T5	29		T14	6		T210	10
auto[0]	values[4]	values[4]	677	1			T55	40		T56	49		T57	32
auto[0]	values[4]	values[5]	384	1			T93	4		T57	75		T202	24
auto[0]	values[4]	values[6]	312	1			T263	8		T264	18		T194	25
auto[0]	values[4]	values[7]	371	1			T36	25		T181	10		T187	32
auto[0]	values[5]	values[0]	381	1			T5	23		T36	32		T52	17
auto[0]	values[5]	values[1]	536	1			T265	8		T19	22		T22	17
auto[0]	values[5]	values[2]	212	1			T100	19		T20	21		T219	29
auto[0]	values[5]	values[3]	309	1			T9	34		T38	20		T52	29
auto[0]	values[5]	values[4]	498	1			T111	10		T52	65		T100	19
auto[0]	values[5]	values[5]	393	1			T80	14		T186	31		T35	20
auto[0]	values[5]	values[6]	322	1			T22	20		T266	4		T267	12
auto[0]	values[5]	values[7]	372	1			T55	32		T199	20		T238	20
auto[0]	values[6]	values[0]	298	1			T99	39		T20	25		T35	25
auto[0]	values[6]	values[1]	351	1			T12	18		T36	36		T57	19
auto[0]	values[6]	values[2]	494	1			T38	33		T186	20		T180	20
auto[0]	values[6]	values[3]	721	1			T4	4		T55	20		T57	20
auto[0]	values[6]	values[4]	393	1			T5	20		T17	20		T178	19
auto[0]	values[6]	values[5]	435	1			T30	12		T84	14		T178	20
auto[0]	values[6]	values[6]	309	1			T199	79		T251	14		T242	33
auto[0]	values[6]	values[7]	458	1			T38	33		T57	39		T17	24
auto[0]	values[7]	values[0]	443	1			T55	26		T56	19		T193	19
auto[0]	values[7]	values[1]	429	1			T9	40		T36	41		T52	60
auto[0]	values[7]	values[2]	509	1			T56	16		T132	12		T193	20
auto[0]	values[7]	values[3]	386	1			T81	16		T38	30		T186	19
auto[0]	values[7]	values[4]	456	1			T192	47		T201	20		T19	23
auto[0]	values[7]	values[5]	340	1			T20	23		T231	6		T193	65
auto[0]	values[7]	values[6]	457	1			T193	66		T35	22		T238	24
auto[0]	values[7]	values[7]	416	1			T36	29		T17	20		T268	8
auto[1]	values[0]	values[0]	11	1			T110	2		T55	1		T17	1
auto[1]	values[0]	values[1]	6	1			T100	1		T35	1		T202	2
auto[1]	values[0]	values[2]	9	1			T55	1		T199	1		T212	1
auto[1]	values[0]	values[3]	14	1			T38	1		T19	1		T180	2
auto[1]	values[0]	values[4]	13	1			T54	2		T269	2		T142	3
auto[1]	values[0]	values[5]	4	1			T270	2		T271	1		T272	1
auto[1]	values[0]	values[6]	10	1			T33	4		T193	1		T242	1
auto[1]	values[0]	values[7]	21	1			T180	2		T194	2		T202	1
auto[1]	values[1]	values[0]	11	1			T55	1		T56	1		T203	3
auto[1]	values[1]	values[1]	12	1			T273	6		T205	1		T274	2
auto[1]	values[1]	values[2]	13	1			T203	1		T199	2		T206	1
auto[1]	values[1]	values[3]	10	1			T178	2		T35	3		T275	3
auto[1]	values[1]	values[4]	14	1			T5	1		T57	3		T142	4
auto[1]	values[1]	values[5]	8	1			T274	1		T276	1		T277	1
auto[1]	values[1]	values[6]	10	1			T212	1		T59	1		T278	6
auto[1]	values[1]	values[7]	16	1			T5	2		T99	1		T193	1
auto[1]	values[2]	values[0]	10	1			T57	1		T186	1		T194	1
auto[1]	values[2]	values[1]	14	1			T36	3		T56	1		T212	1
auto[1]	values[2]	values[2]	3	1			T253	2		T279	1		-	-
auto[1]	values[2]	values[3]	24	1			T178	2		T186	2		T194	2
auto[1]	values[2]	values[4]	6	1			T213	1		T280	2		T281	3
auto[1]	values[2]	values[5]	21	1			T5	1		T36	1		T38	4
auto[1]	values[2]	values[6]	12	1			T5	2		T99	2		T203	1
auto[1]	values[2]	values[7]	18	1			T52	4		T193	2		T253	1
auto[1]	values[3]	values[0]	8	1			T193	1		T199	3		T282	2
auto[1]	values[3]	values[1]	16	1			T52	1		T201	3		T99	1
auto[1]	values[3]	values[2]	7	1			T101	2		T271	3		T275	1
auto[1]	values[3]	values[3]	6	1			T253	1		T242	2		T283	3
auto[1]	values[3]	values[4]	16	1			T177	1		T250	1		T284	1
auto[1]	values[3]	values[5]	26	1			T52	3		T17	2		T19	3
auto[1]	values[3]	values[6]	16	1			T176	2		T213	3		T59	2
auto[1]	values[3]	values[7]	15	1			T99	4		T133	1		T35	1
auto[1]	values[4]	values[0]	25	1			T180	1		T202	2		T177	7
auto[1]	values[4]	values[1]	8	1			T282	5		T271	1		T285	2
auto[1]	values[4]	values[2]	23	1			T57	1		T99	3		T19	5
auto[1]	values[4]	values[3]	10	1			T5	2		T56	1		T194	1
auto[1]	values[4]	values[4]	21	1			T55	1		T99	1		T20	6
auto[1]	values[4]	values[5]	3	1			T57	1		T203	1		T286	1
auto[1]	values[4]	values[6]	10	1			T203	4		T287	2		T288	1
auto[1]	values[4]	values[7]	2	1			T187	1		T275	1		-	-
auto[1]	values[5]	values[0]	11	1			T36	1		T52	3		T289	1
auto[1]	values[5]	values[1]	10	1			T22	3		T250	2		T213	1
auto[1]	values[5]	values[2]	19	1			T100	1		T20	3		T219	1
auto[1]	values[5]	values[3]	8	1			T9	4		T52	1		T199	1
auto[1]	values[5]	values[4]	12	1			T52	2		T100	1		T194	1
auto[1]	values[5]	values[5]	21	1			T186	2		T35	1		T199	2
auto[1]	values[5]	values[6]	4	1			T250	2		T271	1		T290	1
auto[1]	values[5]	values[7]	10	1			T177	2		T274	2		T280	2
auto[1]	values[6]	values[0]	8	1			T99	1		T203	1		T199	1
auto[1]	values[6]	values[1]	5	1			T57	1		T193	1		T199	2
auto[1]	values[6]	values[2]	18	1			T202	1		T139	2		T253	1
auto[1]	values[6]	values[3]	8	1			T219	2		T203	2		T139	1
auto[1]	values[6]	values[4]	4	1			T178	1		T142	1		T291	2
auto[1]	values[6]	values[5]	15	1			T180	2		T202	5		T275	1
auto[1]	values[6]	values[6]	6	1			T199	1		T242	2		T292	1
auto[1]	values[6]	values[7]	15	1			T57	2		T17	1		T19	2
auto[1]	values[7]	values[0]	16	1			T55	1		T56	1		T193	1
auto[1]	values[7]	values[1]	11	1			T36	6		T52	2		T293	1
auto[1]	values[7]	values[2]	10	1			T56	4		T203	1		T139	2
auto[1]	values[7]	values[3]	12	1			T81	5		T38	1		T186	1
auto[1]	values[7]	values[4]	13	1			T186	1		T212	3		T289	1
auto[1]	values[7]	values[5]	3	1			T193	1		T294	1		T295	1
auto[1]	values[7]	values[6]	19	1			T193	3		T35	1		T238	2
auto[1]	values[7]	values[7]	20	1			T36	3		T35	3		T203	1