Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
96.77 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv



Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 14 0 14 100.00
Crosses 48 2 46 95.83


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 8 0 8 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 48 2 46 95.83 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 0 8 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 768 1 T5 4 T15 11 T17 10
all_values[1] 768 1 T5 4 T15 11 T17 10
all_values[2] 768 1 T5 4 T15 11 T17 10
all_values[3] 768 1 T5 4 T15 11 T17 10
all_values[4] 768 1 T5 4 T15 11 T17 10
all_values[5] 768 1 T5 4 T15 11 T17 10
all_values[6] 768 1 T5 4 T15 11 T17 10
all_values[7] 768 1 T5 4 T15 11 T17 10



Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3341 1 T5 15 T15 48 T17 41
auto[1] 2803 1 T5 17 T15 40 T17 39



Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2474 1 T5 18 T15 29 T17 29
auto[1] 3670 1 T5 14 T15 59 T17 51



Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3578 1 T5 22 T15 53 T17 40
auto[1] 2566 1 T5 10 T15 35 T17 40



Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 48 2 46 95.83 2
Automatically Generated Cross Bins 48 2 46 95.83 2
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Element holes
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTNUMBERSTATUS
[all_values[5]] [auto[0]] * [auto[1]] -- -- 2


Covered bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 163 1 T5 1 T163 4 T22 2
all_values[0] auto[0] auto[0] auto[1] 77 1 T15 5 T17 1 T163 1
all_values[0] auto[0] auto[1] auto[0] 125 1 T5 3 T15 1 T17 1
all_values[0] auto[0] auto[1] auto[1] 83 1 T17 1 T20 4 T163 2
all_values[0] auto[1] auto[0] auto[1] 181 1 T15 5 T17 1 T20 1
all_values[0] auto[1] auto[1] auto[1] 139 1 T17 6 T20 1 T163 4
all_values[1] auto[0] auto[0] auto[0] 167 1 T5 1 T15 1 T17 3
all_values[1] auto[0] auto[0] auto[1] 70 1 T17 1 T20 2 T163 2
all_values[1] auto[0] auto[1] auto[0] 127 1 T5 3 T15 3 T20 3
all_values[1] auto[0] auto[1] auto[1] 91 1 T15 3 T17 1 T163 1
all_values[1] auto[1] auto[0] auto[1] 151 1 T15 3 T17 4 T20 2
all_values[1] auto[1] auto[1] auto[1] 162 1 T15 1 T17 1 T20 3
all_values[2] auto[0] auto[0] auto[0] 158 1 T5 2 T15 3 T17 3
all_values[2] auto[0] auto[0] auto[1] 82 1 T20 1 T163 1 T22 1
all_values[2] auto[0] auto[1] auto[0] 108 1 T15 2 T17 2 T20 2
all_values[2] auto[0] auto[1] auto[1] 82 1 T15 1 T17 1 T20 1
all_values[2] auto[1] auto[0] auto[1] 174 1 T5 1 T17 1 T163 3
all_values[2] auto[1] auto[1] auto[1] 164 1 T5 1 T15 5 T17 3
all_values[3] auto[0] auto[0] auto[0] 153 1 T5 2 T15 2 T17 2
all_values[3] auto[0] auto[0] auto[1] 102 1 T15 2 T17 2 T163 3
all_values[3] auto[0] auto[1] auto[0] 113 1 T5 1 T15 1 T20 2
all_values[3] auto[0] auto[1] auto[1] 76 1 T15 2 T163 2 T23 1
all_values[3] auto[1] auto[0] auto[1] 179 1 T15 3 T17 4 T20 3
all_values[3] auto[1] auto[1] auto[1] 145 1 T5 1 T15 1 T17 2
all_values[4] auto[0] auto[0] auto[0] 188 1 T5 1 T15 1 T17 2
all_values[4] auto[0] auto[0] auto[1] 67 1 T15 1 T17 1 T20 1
all_values[4] auto[0] auto[1] auto[0] 140 1 T5 3 T15 2 T17 3
all_values[4] auto[0] auto[1] auto[1] 76 1 T15 2 T17 1 T20 1
all_values[4] auto[1] auto[0] auto[1] 164 1 T15 2 T17 1 T20 2
all_values[4] auto[1] auto[1] auto[1] 133 1 T15 3 T17 2 T20 3
all_values[5] auto[0] auto[0] auto[0] 234 1 T5 1 T15 3 T17 5
all_values[5] auto[0] auto[1] auto[0] 199 1 T15 6 T17 1 T20 1
all_values[5] auto[1] auto[0] auto[1] 194 1 T15 1 T17 2 T163 8
all_values[5] auto[1] auto[1] auto[1] 141 1 T5 3 T15 1 T17 2
all_values[6] auto[0] auto[0] auto[0] 167 1 T15 2 T17 3 T163 2
all_values[6] auto[0] auto[0] auto[1] 74 1 T5 2 T15 1 T20 1
all_values[6] auto[0] auto[1] auto[0] 140 1 T15 2 T17 2 T20 2
all_values[6] auto[0] auto[1] auto[1] 71 1 T15 2 T20 1 T163 2
all_values[6] auto[1] auto[0] auto[1] 170 1 T5 1 T15 2 T17 3
all_values[6] auto[1] auto[1] auto[1] 146 1 T5 1 T15 2 T17 2
all_values[7] auto[0] auto[0] auto[0] 162 1 T17 2 T20 1 T163 1
all_values[7] auto[0] auto[0] auto[1] 84 1 T5 1 T15 5 T20 1
all_values[7] auto[0] auto[1] auto[0] 130 1 T20 2 T163 6 T22 1
all_values[7] auto[0] auto[1] auto[1] 69 1 T5 1 T17 2 T20 1
all_values[7] auto[1] auto[0] auto[1] 180 1 T5 2 T15 6 T20 1
all_values[7] auto[1] auto[1] auto[1] 143 1 T17 6 T20 4 T163 6


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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