Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1900

1

T3

9

T5

8

T7

17

auto[1]

1911

1

T3

7

T5

6

T7

22

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1971

1

T3

16

T5

11

T9

2

auto[1]

1840

1

T5

3

T7

39

T8

10

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3040

1

T3

8

T5

8

T7

39

auto[1]

771

1

T3

8

T5

6

T13

1

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	709	1			T3	2		T5	3		T7	6
valid[1]	791	1			T3	4		T5	2		T7	12
valid[2]	801	1			T3	2		T5	4		T7	7
valid[3]	767	1			T3	4		T5	2		T7	9
valid[4]	743	1			T3	4		T5	3		T7	5

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	123	1			T33	2		T15	3		T29	1
auto[0]	auto[0]	valid[0]	auto[1]	180	1			T5	3		T7	5		T8	1
auto[0]	auto[0]	valid[1]	auto[0]	125	1			T3	1		T33	2		T15	1
auto[0]	auto[0]	valid[1]	auto[1]	183	1			T7	5		T31	3		T32	7
auto[0]	auto[0]	valid[2]	auto[0]	131	1			T5	1		T33	2		T29	1
auto[0]	auto[0]	valid[2]	auto[1]	200	1			T7	3		T8	2		T31	5
auto[0]	auto[0]	valid[3]	auto[0]	116	1			T3	1		T13	2		T33	1
auto[0]	auto[0]	valid[3]	auto[1]	171	1			T7	2		T31	2		T32	3
auto[0]	auto[0]	valid[4]	auto[0]	107	1			T3	2		T5	3		T9	1
auto[0]	auto[0]	valid[4]	auto[1]	173	1			T7	2		T8	4		T31	6
auto[0]	auto[1]	valid[0]	auto[0]	91	1			T13	1		T33	2		T29	1
auto[0]	auto[1]	valid[0]	auto[1]	173	1			T7	1		T31	9		T32	1
auto[0]	auto[1]	valid[1]	auto[0]	121	1			T9	1		T13	1		T15	2
auto[0]	auto[1]	valid[1]	auto[1]	184	1			T7	7		T8	1		T31	2
auto[0]	auto[1]	valid[2]	auto[0]	132	1			T3	1		T5	1		T33	2
auto[0]	auto[1]	valid[2]	auto[1]	202	1			T7	4		T8	1		T31	3
auto[0]	auto[1]	valid[3]	auto[0]	127	1			T3	1		T13	1		T33	1
auto[0]	auto[1]	valid[3]	auto[1]	189	1			T7	7		T31	1		T32	2
auto[0]	auto[1]	valid[4]	auto[0]	127	1			T3	2		T13	1		T15	1
auto[0]	auto[1]	valid[4]	auto[1]	185	1			T7	3		T8	1		T31	6
auto[1]	auto[0]	valid[0]	auto[0]	69	1			T3	1		T36	1		T81	1
auto[1]	auto[0]	valid[1]	auto[0]	92	1			T3	2		T15	1		T36	1
auto[1]	auto[0]	valid[2]	auto[0]	64	1			T5	1		T110	1		T305	1
auto[1]	auto[0]	valid[3]	auto[0]	87	1			T3	2		T13	1		T29	1
auto[1]	auto[0]	valid[4]	auto[0]	79	1			T29	1		T36	1		T81	1
auto[1]	auto[1]	valid[0]	auto[0]	73	1			T3	1		T33	2		T15	1
auto[1]	auto[1]	valid[1]	auto[0]	86	1			T3	1		T5	2		T33	2
auto[1]	auto[1]	valid[2]	auto[0]	72	1			T3	1		T5	1		T15	1
auto[1]	auto[1]	valid[3]	auto[0]	77	1			T5	2		T29	1		T36	2
auto[1]	auto[1]	valid[4]	auto[0]	72	1			T29	1		T17	1		T19	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal