Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

49499

1

T3

271

T5

370

T9

39

auto[1]

19754

1

T5

80

T7

427

T8

10

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

51403

1

T3

180

T5

301

T7

427

auto[1]

17850

1

T3

91

T5

149

T9

11

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	35446	1			T3	137		T5	240		T7	224
others[1]	5874	1			T3	24		T5	42		T7	30
others[2]	5921	1			T3	26		T5	42		T7	45
others[3]	6571	1			T3	24		T5	37		T7	36
interest[1]	3929	1			T3	11		T5	17		T7	27
interest[4]	23171	1			T3	93		T5	145		T7	160
interest[64]	11512	1			T3	49		T5	72		T7	65

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	15982	1			T3	94		T5	115		T9	16
auto[0]	auto[0]	others[1]	2715	1			T3	15		T5	20		T9	3
auto[0]	auto[0]	others[2]	2760	1			T3	17		T5	23		T9	2
auto[0]	auto[0]	others[3]	3035	1			T3	14		T5	15		T9	1
auto[0]	auto[0]	interest[1]	1814	1			T3	8		T5	12		T9	1
auto[0]	auto[0]	interest[4]	10415	1			T3	67		T5	69		T9	10
auto[0]	auto[0]	interest[64]	5343	1			T3	32		T5	36		T9	5
auto[0]	auto[1]	others[0]	10403	1			T5	50		T7	224		T8	10
auto[0]	auto[1]	others[1]	1623	1			T5	3		T7	30		T31	40
auto[0]	auto[1]	others[2]	1637	1			T5	3		T7	45		T31	51
auto[0]	auto[1]	others[3]	1828	1			T5	9		T7	36		T31	51
auto[0]	auto[1]	interest[1]	1088	1			T5	2		T7	27		T31	27
auto[0]	auto[1]	interest[4]	6905	1			T5	32		T7	160		T8	10
auto[0]	auto[1]	interest[64]	3175	1			T5	13		T7	65		T31	72
auto[1]	auto[0]	others[0]	9061	1			T3	43		T5	75		T9	6
auto[1]	auto[0]	others[1]	1536	1			T3	9		T5	19		T9	1
auto[1]	auto[0]	others[2]	1524	1			T3	9		T5	16		T13	5
auto[1]	auto[0]	others[3]	1708	1			T3	10		T5	13		T9	2
auto[1]	auto[0]	interest[1]	1027	1			T3	3		T5	3		T9	1
auto[1]	auto[0]	interest[4]	5851	1			T3	26		T5	44		T9	5
auto[1]	auto[0]	interest[64]	2994	1			T3	17		T5	23		T9	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal