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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.06 98.45 94.08 98.62 89.36 97.29 95.43 99.21


Total test records in report: 1150
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T118 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.547279470 Jul 29 04:55:08 PM PDT 24 Jul 29 04:55:15 PM PDT 24 256421028 ps
T1028 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.151561233 Jul 29 04:55:21 PM PDT 24 Jul 29 04:55:21 PM PDT 24 77231854 ps
T1029 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.1088512567 Jul 29 04:55:00 PM PDT 24 Jul 29 04:55:01 PM PDT 24 42040958 ps
T1030 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.1748668353 Jul 29 04:55:04 PM PDT 24 Jul 29 04:55:05 PM PDT 24 82934227 ps
T1031 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.630033487 Jul 29 04:54:55 PM PDT 24 Jul 29 04:54:59 PM PDT 24 245094944 ps
T115 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.1820708983 Jul 29 04:55:02 PM PDT 24 Jul 29 04:55:06 PM PDT 24 163402718 ps
T114 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.1724693178 Jul 29 04:55:04 PM PDT 24 Jul 29 04:55:08 PM PDT 24 109758603 ps
T116 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2406141411 Jul 29 04:55:38 PM PDT 24 Jul 29 04:55:42 PM PDT 24 378365345 ps
T1032 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.1524816248 Jul 29 04:55:23 PM PDT 24 Jul 29 04:55:24 PM PDT 24 15268002 ps
T124 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.2509041065 Jul 29 04:55:19 PM PDT 24 Jul 29 04:55:20 PM PDT 24 58313275 ps
T155 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3328010459 Jul 29 04:55:35 PM PDT 24 Jul 29 04:55:39 PM PDT 24 154282525 ps
T156 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2178624098 Jul 29 04:54:57 PM PDT 24 Jul 29 04:55:20 PM PDT 24 1098072145 ps
T168 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.990226399 Jul 29 04:55:22 PM PDT 24 Jul 29 04:55:29 PM PDT 24 220405704 ps
T1033 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.4198047755 Jul 29 04:55:07 PM PDT 24 Jul 29 04:55:08 PM PDT 24 17330907 ps
T157 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.90807296 Jul 29 04:55:04 PM PDT 24 Jul 29 04:55:07 PM PDT 24 193512400 ps
T1034 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.3506121389 Jul 29 04:55:19 PM PDT 24 Jul 29 04:55:21 PM PDT 24 72702623 ps
T170 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1093021030 Jul 29 04:55:17 PM PDT 24 Jul 29 04:55:32 PM PDT 24 1095701634 ps
T1035 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2488243558 Jul 29 04:55:06 PM PDT 24 Jul 29 04:55:08 PM PDT 24 29357251 ps
T166 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.1226299548 Jul 29 04:54:58 PM PDT 24 Jul 29 04:55:16 PM PDT 24 2546668614 ps
T125 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.3734654848 Jul 29 04:54:49 PM PDT 24 Jul 29 04:54:56 PM PDT 24 112270161 ps
T167 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.1409742311 Jul 29 04:55:00 PM PDT 24 Jul 29 04:55:07 PM PDT 24 209974759 ps
T89 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2847132316 Jul 29 04:54:54 PM PDT 24 Jul 29 04:54:56 PM PDT 24 145851218 ps
T1036 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.3319226887 Jul 29 04:54:55 PM PDT 24 Jul 29 04:54:56 PM PDT 24 13621331 ps
T1037 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.180792655 Jul 29 04:55:08 PM PDT 24 Jul 29 04:55:14 PM PDT 24 25204974 ps
T126 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.321901580 Jul 29 04:54:51 PM PDT 24 Jul 29 04:54:53 PM PDT 24 262659548 ps
T158 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.368738913 Jul 29 04:55:15 PM PDT 24 Jul 29 04:55:39 PM PDT 24 3199561984 ps
T1038 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.2852513200 Jul 29 04:55:10 PM PDT 24 Jul 29 04:55:11 PM PDT 24 25717496 ps
T1039 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1320020547 Jul 29 04:55:24 PM PDT 24 Jul 29 04:55:25 PM PDT 24 41617847 ps
T1040 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.3036300564 Jul 29 04:55:16 PM PDT 24 Jul 29 04:55:17 PM PDT 24 65632439 ps
T1041 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.3260365344 Jul 29 04:55:14 PM PDT 24 Jul 29 04:55:15 PM PDT 24 33106973 ps
T1042 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.143212688 Jul 29 04:55:16 PM PDT 24 Jul 29 04:55:17 PM PDT 24 14190553 ps
T1043 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.1904909709 Jul 29 04:55:12 PM PDT 24 Jul 29 04:55:13 PM PDT 24 41312825 ps
T1044 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.4259725043 Jul 29 04:54:54 PM PDT 24 Jul 29 04:54:55 PM PDT 24 66998939 ps
T127 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.205377384 Jul 29 04:54:54 PM PDT 24 Jul 29 04:55:31 PM PDT 24 2447942085 ps
T117 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.2678766106 Jul 29 04:55:03 PM PDT 24 Jul 29 04:55:08 PM PDT 24 1754001399 ps
T1045 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1085744981 Jul 29 04:55:18 PM PDT 24 Jul 29 04:55:19 PM PDT 24 18891755 ps
T169 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.339441844 Jul 29 04:55:35 PM PDT 24 Jul 29 04:55:53 PM PDT 24 1146804418 ps
T128 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3072147889 Jul 29 04:55:05 PM PDT 24 Jul 29 04:55:25 PM PDT 24 2493684882 ps
T1046 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1584533154 Jul 29 04:55:15 PM PDT 24 Jul 29 04:55:16 PM PDT 24 18626583 ps
T1047 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.2574965615 Jul 29 04:55:00 PM PDT 24 Jul 29 04:55:00 PM PDT 24 32134784 ps
T1048 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1127525675 Jul 29 04:55:02 PM PDT 24 Jul 29 04:55:07 PM PDT 24 28662027 ps
T129 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.3216814235 Jul 29 04:54:58 PM PDT 24 Jul 29 04:55:00 PM PDT 24 58434465 ps
T1049 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2018328319 Jul 29 04:55:00 PM PDT 24 Jul 29 04:55:04 PM PDT 24 66344366 ps
T1050 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.2645553689 Jul 29 04:55:10 PM PDT 24 Jul 29 04:55:11 PM PDT 24 35631982 ps
T1051 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.3639095730 Jul 29 04:55:09 PM PDT 24 Jul 29 04:55:10 PM PDT 24 16447741 ps
T172 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3718617723 Jul 29 04:55:10 PM PDT 24 Jul 29 04:55:30 PM PDT 24 813743328 ps
T1052 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.587201576 Jul 29 04:54:54 PM PDT 24 Jul 29 04:54:57 PM PDT 24 118132715 ps
T1053 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2649251918 Jul 29 04:55:31 PM PDT 24 Jul 29 04:55:35 PM PDT 24 245459677 ps
T1054 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.3645695623 Jul 29 04:55:02 PM PDT 24 Jul 29 04:55:08 PM PDT 24 198764485 ps
T1055 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.39154850 Jul 29 04:55:29 PM PDT 24 Jul 29 04:55:30 PM PDT 24 129855713 ps
T1056 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.4109584442 Jul 29 04:55:12 PM PDT 24 Jul 29 04:55:13 PM PDT 24 27288916 ps
T1057 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.501809780 Jul 29 04:55:49 PM PDT 24 Jul 29 04:55:51 PM PDT 24 51805934 ps
T1058 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1694663554 Jul 29 04:55:05 PM PDT 24 Jul 29 04:55:07 PM PDT 24 195719824 ps
T1059 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.87467890 Jul 29 04:55:23 PM PDT 24 Jul 29 04:55:25 PM PDT 24 108904949 ps
T1060 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.10111908 Jul 29 04:55:15 PM PDT 24 Jul 29 04:55:18 PM PDT 24 447293467 ps
T1061 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2525689580 Jul 29 04:55:06 PM PDT 24 Jul 29 04:55:06 PM PDT 24 41145955 ps
T1062 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.438526750 Jul 29 04:55:11 PM PDT 24 Jul 29 04:55:16 PM PDT 24 165611852 ps
T1063 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.3650437342 Jul 29 04:54:41 PM PDT 24 Jul 29 04:54:43 PM PDT 24 213386003 ps
T1064 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.2873744441 Jul 29 04:54:46 PM PDT 24 Jul 29 04:54:46 PM PDT 24 142591864 ps
T1065 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.2092235569 Jul 29 04:54:57 PM PDT 24 Jul 29 04:54:58 PM PDT 24 95363121 ps
T1066 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.1410803261 Jul 29 04:55:20 PM PDT 24 Jul 29 04:55:22 PM PDT 24 64930125 ps
T1067 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3509495751 Jul 29 04:55:11 PM PDT 24 Jul 29 04:55:16 PM PDT 24 245166791 ps
T1068 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.3770444870 Jul 29 04:55:18 PM PDT 24 Jul 29 04:55:31 PM PDT 24 890402465 ps
T1069 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.1746932239 Jul 29 04:55:33 PM PDT 24 Jul 29 04:55:37 PM PDT 24 82487587 ps
T1070 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.2261615558 Jul 29 04:55:24 PM PDT 24 Jul 29 04:55:31 PM PDT 24 107025487 ps
T171 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2201005855 Jul 29 04:55:10 PM PDT 24 Jul 29 04:55:17 PM PDT 24 106145521 ps
T90 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1337567202 Jul 29 04:55:06 PM PDT 24 Jul 29 04:55:07 PM PDT 24 18698025 ps
T1071 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.3923224189 Jul 29 04:55:27 PM PDT 24 Jul 29 04:55:28 PM PDT 24 31308253 ps
T1072 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.1677856468 Jul 29 04:55:27 PM PDT 24 Jul 29 04:55:35 PM PDT 24 3479986228 ps
T1073 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.1450613293 Jul 29 04:55:30 PM PDT 24 Jul 29 04:55:34 PM PDT 24 191181767 ps
T1074 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.726631346 Jul 29 04:55:05 PM PDT 24 Jul 29 04:55:09 PM PDT 24 694431191 ps
T1075 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.1455111560 Jul 29 04:55:12 PM PDT 24 Jul 29 04:55:13 PM PDT 24 11605847 ps
T1076 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.3557448021 Jul 29 04:55:04 PM PDT 24 Jul 29 04:55:07 PM PDT 24 43095408 ps
T1077 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.616850098 Jul 29 04:55:39 PM PDT 24 Jul 29 04:55:40 PM PDT 24 45990397 ps
T1078 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.278944718 Jul 29 04:55:06 PM PDT 24 Jul 29 04:55:06 PM PDT 24 143617888 ps
T1079 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.1649732745 Jul 29 04:54:52 PM PDT 24 Jul 29 04:54:55 PM PDT 24 91322943 ps
T1080 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.89549054 Jul 29 04:55:14 PM PDT 24 Jul 29 04:55:17 PM PDT 24 50333586 ps
T1081 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3672348673 Jul 29 04:54:55 PM PDT 24 Jul 29 04:54:56 PM PDT 24 21041003 ps
T1082 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.91894485 Jul 29 04:54:51 PM PDT 24 Jul 29 04:54:53 PM PDT 24 46464435 ps
T1083 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.3109673063 Jul 29 04:54:57 PM PDT 24 Jul 29 04:54:59 PM PDT 24 406483556 ps
T1084 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.3417239911 Jul 29 04:55:04 PM PDT 24 Jul 29 04:55:05 PM PDT 24 195445915 ps
T174 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.364763780 Jul 29 04:55:01 PM PDT 24 Jul 29 04:55:07 PM PDT 24 103355672 ps
T1085 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.3636618717 Jul 29 04:55:25 PM PDT 24 Jul 29 04:55:28 PM PDT 24 154449147 ps
T1086 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.334849769 Jul 29 04:55:07 PM PDT 24 Jul 29 04:55:10 PM PDT 24 402741239 ps
T1087 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.3214781104 Jul 29 04:55:14 PM PDT 24 Jul 29 04:55:17 PM PDT 24 42870945 ps
T1088 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.1834708904 Jul 29 04:54:45 PM PDT 24 Jul 29 04:54:46 PM PDT 24 12616292 ps
T1089 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.1959471241 Jul 29 04:55:05 PM PDT 24 Jul 29 04:55:07 PM PDT 24 327909052 ps
T1090 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1319653729 Jul 29 04:54:58 PM PDT 24 Jul 29 04:55:05 PM PDT 24 406089581 ps
T1091 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.1158399209 Jul 29 04:55:09 PM PDT 24 Jul 29 04:55:10 PM PDT 24 65970226 ps
T1092 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.379549647 Jul 29 04:55:09 PM PDT 24 Jul 29 04:55:11 PM PDT 24 62412905 ps
T1093 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.98407426 Jul 29 04:54:56 PM PDT 24 Jul 29 04:54:58 PM PDT 24 279906413 ps
T1094 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.1313427558 Jul 29 04:54:51 PM PDT 24 Jul 29 04:54:52 PM PDT 24 11481588 ps
T1095 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.3245030788 Jul 29 04:55:04 PM PDT 24 Jul 29 04:55:08 PM PDT 24 614041312 ps
T1096 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.130179617 Jul 29 04:54:56 PM PDT 24 Jul 29 04:54:57 PM PDT 24 59353514 ps
T1097 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.621838516 Jul 29 04:55:28 PM PDT 24 Jul 29 04:55:30 PM PDT 24 418010275 ps
T1098 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1439715629 Jul 29 04:54:54 PM PDT 24 Jul 29 04:54:56 PM PDT 24 46998729 ps
T1099 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.671731225 Jul 29 04:55:20 PM PDT 24 Jul 29 04:55:22 PM PDT 24 281460919 ps
T1100 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.4135966187 Jul 29 04:54:59 PM PDT 24 Jul 29 04:55:17 PM PDT 24 3944804367 ps
T1101 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.377825094 Jul 29 04:55:07 PM PDT 24 Jul 29 04:55:08 PM PDT 24 50301473 ps
T1102 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1076817057 Jul 29 04:55:05 PM PDT 24 Jul 29 04:55:06 PM PDT 24 18789035 ps
T1103 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.470731027 Jul 29 04:55:07 PM PDT 24 Jul 29 04:55:09 PM PDT 24 40469727 ps
T1104 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.645707596 Jul 29 04:55:25 PM PDT 24 Jul 29 04:55:25 PM PDT 24 12355426 ps
T1105 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3866423093 Jul 29 04:55:01 PM PDT 24 Jul 29 04:55:02 PM PDT 24 15646702 ps
T1106 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.1784338258 Jul 29 04:55:00 PM PDT 24 Jul 29 04:55:02 PM PDT 24 415215954 ps
T175 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1751397524 Jul 29 04:55:08 PM PDT 24 Jul 29 04:55:19 PM PDT 24 735260742 ps
T1107 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.378616616 Jul 29 04:55:08 PM PDT 24 Jul 29 04:55:11 PM PDT 24 87486455 ps
T1108 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.297896580 Jul 29 04:54:52 PM PDT 24 Jul 29 04:54:54 PM PDT 24 89104980 ps
T1109 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.344019562 Jul 29 04:55:01 PM PDT 24 Jul 29 04:55:18 PM PDT 24 846573219 ps
T1110 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.2651417556 Jul 29 04:54:57 PM PDT 24 Jul 29 04:55:00 PM PDT 24 467173770 ps
T1111 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.1739317385 Jul 29 04:54:58 PM PDT 24 Jul 29 04:55:10 PM PDT 24 161795981 ps
T1112 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.776608070 Jul 29 04:55:13 PM PDT 24 Jul 29 04:55:16 PM PDT 24 164392974 ps
T1113 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.339124892 Jul 29 04:55:11 PM PDT 24 Jul 29 04:55:14 PM PDT 24 230436297 ps
T1114 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.3195465350 Jul 29 04:55:11 PM PDT 24 Jul 29 04:55:13 PM PDT 24 21218228 ps
T173 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.1462475194 Jul 29 04:55:23 PM PDT 24 Jul 29 04:55:45 PM PDT 24 974347864 ps
T1115 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.606884417 Jul 29 04:55:15 PM PDT 24 Jul 29 04:55:16 PM PDT 24 51339984 ps
T1116 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.3868732585 Jul 29 04:55:27 PM PDT 24 Jul 29 04:55:28 PM PDT 24 13440798 ps
T1117 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.536738358 Jul 29 04:55:09 PM PDT 24 Jul 29 04:55:13 PM PDT 24 57679563 ps
T1118 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3067273632 Jul 29 04:55:00 PM PDT 24 Jul 29 04:55:26 PM PDT 24 1811052275 ps
T1119 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.3540513901 Jul 29 04:54:57 PM PDT 24 Jul 29 04:55:21 PM PDT 24 1228696397 ps
T1120 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.4228392982 Jul 29 04:54:55 PM PDT 24 Jul 29 04:55:27 PM PDT 24 1805325398 ps
T1121 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.2327632683 Jul 29 04:55:06 PM PDT 24 Jul 29 04:55:06 PM PDT 24 16420689 ps
T1122 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3233742725 Jul 29 04:55:11 PM PDT 24 Jul 29 04:55:14 PM PDT 24 84881277 ps
T1123 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.484850085 Jul 29 04:55:04 PM PDT 24 Jul 29 04:55:07 PM PDT 24 107267667 ps
T1124 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.277935960 Jul 29 04:55:04 PM PDT 24 Jul 29 04:55:07 PM PDT 24 55334451 ps
T1125 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.3965863735 Jul 29 04:55:08 PM PDT 24 Jul 29 04:55:11 PM PDT 24 70017947 ps
T1126 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.26044318 Jul 29 04:55:27 PM PDT 24 Jul 29 04:55:29 PM PDT 24 113990975 ps
T1127 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.682727128 Jul 29 04:55:13 PM PDT 24 Jul 29 04:55:14 PM PDT 24 31614754 ps
T1128 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.428833061 Jul 29 04:55:39 PM PDT 24 Jul 29 04:55:45 PM PDT 24 14195210 ps
T1129 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.546963862 Jul 29 04:55:01 PM PDT 24 Jul 29 04:55:04 PM PDT 24 293544869 ps
T1130 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.2657110520 Jul 29 04:54:55 PM PDT 24 Jul 29 04:54:55 PM PDT 24 19397783 ps
T1131 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2859603316 Jul 29 04:55:14 PM PDT 24 Jul 29 04:55:17 PM PDT 24 692171225 ps
T1132 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2452027655 Jul 29 04:55:07 PM PDT 24 Jul 29 04:55:08 PM PDT 24 15368576 ps
T1133 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2887035151 Jul 29 04:55:23 PM PDT 24 Jul 29 04:55:24 PM PDT 24 49666150 ps
T1134 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.1617937081 Jul 29 04:54:51 PM PDT 24 Jul 29 04:54:53 PM PDT 24 41755535 ps
T1135 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.2631666182 Jul 29 04:55:13 PM PDT 24 Jul 29 04:55:15 PM PDT 24 31701911 ps
T1136 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.4144513671 Jul 29 04:55:11 PM PDT 24 Jul 29 04:55:16 PM PDT 24 474942182 ps
T1137 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.1006226750 Jul 29 04:55:22 PM PDT 24 Jul 29 04:55:23 PM PDT 24 39965178 ps
T1138 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1433425861 Jul 29 04:55:03 PM PDT 24 Jul 29 04:55:05 PM PDT 24 82130499 ps
T1139 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.4163982822 Jul 29 04:55:27 PM PDT 24 Jul 29 04:55:32 PM PDT 24 1117286873 ps
T1140 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.3764455095 Jul 29 04:55:22 PM PDT 24 Jul 29 04:55:26 PM PDT 24 315733125 ps
T1141 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2569952687 Jul 29 04:55:03 PM PDT 24 Jul 29 04:55:06 PM PDT 24 208720644 ps
T1142 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.2133809907 Jul 29 04:54:53 PM PDT 24 Jul 29 04:54:56 PM PDT 24 358179479 ps
T1143 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1860574993 Jul 29 04:54:45 PM PDT 24 Jul 29 04:54:49 PM PDT 24 245415253 ps
T1144 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.2019200762 Jul 29 04:55:14 PM PDT 24 Jul 29 04:55:15 PM PDT 24 16334241 ps
T1145 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2736814064 Jul 29 04:55:20 PM PDT 24 Jul 29 04:55:22 PM PDT 24 52247971 ps
T1146 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.33673455 Jul 29 04:55:04 PM PDT 24 Jul 29 04:55:06 PM PDT 24 65214424 ps
T1147 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.569772593 Jul 29 04:55:21 PM PDT 24 Jul 29 04:55:22 PM PDT 24 17000898 ps
T1148 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.2835679305 Jul 29 04:54:44 PM PDT 24 Jul 29 04:54:59 PM PDT 24 615244203 ps
T1149 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.68361869 Jul 29 04:55:06 PM PDT 24 Jul 29 04:55:07 PM PDT 24 24316437 ps
T1150 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2661138164 Jul 29 04:55:01 PM PDT 24 Jul 29 04:55:01 PM PDT 24 14099869 ps

Test location /workspace/coverage/default/22.spi_device_stress_all.4094539398
Short name T5
Test name
Test status
Simulation time 371792395807 ps
CPU time 460.75 seconds
Started Jul 29 05:05:19 PM PDT 24
Finished Jul 29 05:13:00 PM PDT 24
Peak memory 255716 kb
Host smart-0e7ff2dc-03eb-4f60-a040-268804914d43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094539398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.4094539398
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.4206126230
Short name T13
Test name
Test status
Simulation time 3241645116 ps
CPU time 36.37 seconds
Started Jul 29 05:05:54 PM PDT 24
Finished Jul 29 05:06:31 PM PDT 24
Peak memory 233620 kb
Host smart-dc580ae0-116f-4415-a8e3-d4b562e33c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206126230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.4206126230
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.3319133198
Short name T17
Test name
Test status
Simulation time 855309546363 ps
CPU time 486.9 seconds
Started Jul 29 05:04:42 PM PDT 24
Finished Jul 29 05:12:49 PM PDT 24
Peak memory 268300 kb
Host smart-892b5e67-6928-42a2-bb9b-a3ab6461f966
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319133198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.3319133198
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3317934937
Short name T106
Test name
Test status
Simulation time 3805050815 ps
CPU time 23.17 seconds
Started Jul 29 04:54:55 PM PDT 24
Finished Jul 29 04:55:18 PM PDT 24
Peak memory 215428 kb
Host smart-dfc35e66-b381-47bf-a08b-2ad2e7c34188
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317934937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.3317934937
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.3676830116
Short name T57
Test name
Test status
Simulation time 44146728784 ps
CPU time 121.71 seconds
Started Jul 29 05:07:14 PM PDT 24
Finished Jul 29 05:09:16 PM PDT 24
Peak memory 264816 kb
Host smart-a9ffc50d-b60b-4a9e-a501-d4b759090483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676830116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.3676830116
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.436143901
Short name T203
Test name
Test status
Simulation time 92696039736 ps
CPU time 354.67 seconds
Started Jul 29 05:04:37 PM PDT 24
Finished Jul 29 05:10:32 PM PDT 24
Peak memory 299260 kb
Host smart-9dc3db91-6dd2-42bb-9157-0558c0437a0f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436143901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stres
s_all.436143901
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.2329808190
Short name T74
Test name
Test status
Simulation time 15787060 ps
CPU time 0.75 seconds
Started Jul 29 05:03:12 PM PDT 24
Finished Jul 29 05:03:14 PM PDT 24
Peak memory 216640 kb
Host smart-92f0f109-01ee-4294-a09e-0c7b50a97903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329808190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.2329808190
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.3634735812
Short name T36
Test name
Test status
Simulation time 39664951833 ps
CPU time 163.72 seconds
Started Jul 29 05:05:25 PM PDT 24
Finished Jul 29 05:08:09 PM PDT 24
Peak memory 268568 kb
Host smart-f4c43160-2b48-44d5-bb5a-15e8b7484c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634735812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.3634735812
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.3218588651
Short name T105
Test name
Test status
Simulation time 150295461 ps
CPU time 3.47 seconds
Started Jul 29 04:54:43 PM PDT 24
Finished Jul 29 04:54:47 PM PDT 24
Peak memory 215928 kb
Host smart-6266e6f8-4946-4690-9dbf-367595bd8a5a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218588651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.3
218588651
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.120881896
Short name T250
Test name
Test status
Simulation time 14853012150 ps
CPU time 81.01 seconds
Started Jul 29 05:05:15 PM PDT 24
Finished Jul 29 05:06:36 PM PDT 24
Peak memory 253532 kb
Host smart-90e9d6c1-f3ce-4a5b-8605-d303392d549d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120881896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stres
s_all.120881896
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.445099005
Short name T19
Test name
Test status
Simulation time 43265987621 ps
CPU time 508.39 seconds
Started Jul 29 05:06:57 PM PDT 24
Finished Jul 29 05:15:26 PM PDT 24
Peak memory 284832 kb
Host smart-0a2282d4-16f4-46a2-897a-1f01cc5072f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445099005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stres
s_all.445099005
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.3671836379
Short name T16
Test name
Test status
Simulation time 75743336 ps
CPU time 1.13 seconds
Started Jul 29 05:03:18 PM PDT 24
Finished Jul 29 05:03:19 PM PDT 24
Peak memory 235644 kb
Host smart-782250ef-41d7-4957-897e-af63f93eb3f1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671836379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.3671836379
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.635889666
Short name T147
Test name
Test status
Simulation time 1041583815 ps
CPU time 14.16 seconds
Started Jul 29 05:03:23 PM PDT 24
Finished Jul 29 05:03:37 PM PDT 24
Peak memory 225164 kb
Host smart-76b87de9-a6a6-4f54-b2d3-3a54eebc5cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635889666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.635889666
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.2737707001
Short name T199
Test name
Test status
Simulation time 181290073352 ps
CPU time 219.25 seconds
Started Jul 29 05:04:24 PM PDT 24
Finished Jul 29 05:08:03 PM PDT 24
Peak memory 272164 kb
Host smart-ca25c917-6db7-483e-a035-dd226b60fbf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737707001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.2737707001
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.2292605236
Short name T253
Test name
Test status
Simulation time 13529376017 ps
CPU time 126.69 seconds
Started Jul 29 05:05:42 PM PDT 24
Finished Jul 29 05:07:49 PM PDT 24
Peak memory 258100 kb
Host smart-be1b2232-c47c-4961-83c1-1ab2acb6cf75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292605236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.2292605236
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.336094640
Short name T178
Test name
Test status
Simulation time 30639644810 ps
CPU time 100.62 seconds
Started Jul 29 05:07:19 PM PDT 24
Finished Jul 29 05:09:00 PM PDT 24
Peak memory 256304 kb
Host smart-55bf0cbe-aa22-4796-8e62-01051bb31db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336094640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmds
.336094640
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3304248060
Short name T123
Test name
Test status
Simulation time 4745505933 ps
CPU time 28.09 seconds
Started Jul 29 04:55:15 PM PDT 24
Finished Jul 29 04:55:43 PM PDT 24
Peak memory 207468 kb
Host smart-e53c8340-1715-451a-bfae-fa61f4ef1233
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304248060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.3304248060
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.3049913146
Short name T35
Test name
Test status
Simulation time 64044034763 ps
CPU time 565.43 seconds
Started Jul 29 05:06:37 PM PDT 24
Finished Jul 29 05:16:02 PM PDT 24
Peak memory 274440 kb
Host smart-93f58126-9cb5-44d3-ad0a-dfa7d1ca875c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049913146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.3049913146
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.2069565394
Short name T277
Test name
Test status
Simulation time 20221375410 ps
CPU time 261.21 seconds
Started Jul 29 05:06:06 PM PDT 24
Finished Jul 29 05:10:28 PM PDT 24
Peak memory 270976 kb
Host smart-36adceb5-699b-43a3-a5d3-7fe2240e8bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069565394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.2069565394
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.2995521621
Short name T473
Test name
Test status
Simulation time 114488538 ps
CPU time 1.13 seconds
Started Jul 29 05:03:13 PM PDT 24
Finished Jul 29 05:03:14 PM PDT 24
Peak memory 217104 kb
Host smart-edd53037-c677-408e-89d4-25f01d61148e
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995521621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.spi_device_mem_parity.2995521621
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.3011325345
Short name T221
Test name
Test status
Simulation time 34350220881 ps
CPU time 326.9 seconds
Started Jul 29 05:03:38 PM PDT 24
Finished Jul 29 05:09:05 PM PDT 24
Peak memory 256876 kb
Host smart-a8d32dad-f4e5-41ac-ae3d-0ea586795dda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011325345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.3011325345
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.1338731503
Short name T193
Test name
Test status
Simulation time 62404867970 ps
CPU time 442.41 seconds
Started Jul 29 05:03:40 PM PDT 24
Finished Jul 29 05:11:02 PM PDT 24
Peak memory 257524 kb
Host smart-34f116fc-be58-4660-b894-8c8c67d1d3b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338731503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.1338731503
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.1657660003
Short name T177
Test name
Test status
Simulation time 207297660988 ps
CPU time 403.72 seconds
Started Jul 29 05:03:44 PM PDT 24
Finished Jul 29 05:10:28 PM PDT 24
Peak memory 268432 kb
Host smart-1e6c6a6e-ba2e-48b0-bb20-8eca7a7388a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657660003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds
.1657660003
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.3818838295
Short name T9
Test name
Test status
Simulation time 36310314106 ps
CPU time 168.22 seconds
Started Jul 29 05:04:18 PM PDT 24
Finished Jul 29 05:07:07 PM PDT 24
Peak memory 251876 kb
Host smart-8d9a8045-37e9-48fa-b1da-4ac5a42aa42e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818838295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.3818838295
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.3457003958
Short name T20
Test name
Test status
Simulation time 67226375765 ps
CPU time 327.12 seconds
Started Jul 29 05:07:02 PM PDT 24
Finished Jul 29 05:12:29 PM PDT 24
Peak memory 263324 kb
Host smart-e6e63881-8c55-49d6-839b-d6a5a0303c82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457003958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.3457003958
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.3106322278
Short name T401
Test name
Test status
Simulation time 28624170 ps
CPU time 0.71 seconds
Started Jul 29 05:03:18 PM PDT 24
Finished Jul 29 05:03:19 PM PDT 24
Peak memory 205872 kb
Host smart-5d7917b3-8b6f-47e0-b0d8-7ed4370d27f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106322278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.3
106322278
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3718617723
Short name T172
Test name
Test status
Simulation time 813743328 ps
CPU time 20.72 seconds
Started Jul 29 04:55:10 PM PDT 24
Finished Jul 29 04:55:30 PM PDT 24
Peak memory 215468 kb
Host smart-6755d33b-6ae0-477c-a8ab-6112684680dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718617723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.3718617723
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.1516697791
Short name T142
Test name
Test status
Simulation time 8470595476 ps
CPU time 161.33 seconds
Started Jul 29 05:04:25 PM PDT 24
Finished Jul 29 05:07:06 PM PDT 24
Peak memory 283752 kb
Host smart-e4b22da0-cc15-4d7f-ab41-33a14ba37c99
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516697791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.1516697791
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.2406784752
Short name T7
Test name
Test status
Simulation time 20150630297 ps
CPU time 9.37 seconds
Started Jul 29 05:04:21 PM PDT 24
Finished Jul 29 05:04:30 PM PDT 24
Peak memory 216984 kb
Host smart-db5e9369-6d3c-4ed4-b354-4a6d78c255dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406784752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.2406784752
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.4226072519
Short name T289
Test name
Test status
Simulation time 5422209432 ps
CPU time 97.71 seconds
Started Jul 29 05:05:44 PM PDT 24
Finished Jul 29 05:07:21 PM PDT 24
Peak memory 253448 kb
Host smart-9fa852c9-ebc4-479e-a503-8ceecb5e6ffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226072519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmd
s.4226072519
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2406141411
Short name T116
Test name
Test status
Simulation time 378365345 ps
CPU time 4.27 seconds
Started Jul 29 04:55:38 PM PDT 24
Finished Jul 29 04:55:42 PM PDT 24
Peak memory 215672 kb
Host smart-72f691a9-a3ca-4c16-b893-48064a73fee0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406141411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
2406141411
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.1333301432
Short name T22
Test name
Test status
Simulation time 10027043479 ps
CPU time 111.45 seconds
Started Jul 29 05:04:25 PM PDT 24
Finished Jul 29 05:06:16 PM PDT 24
Peak memory 268580 kb
Host smart-88957604-4b81-4007-8008-8458461205de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333301432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.1333301432
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.2151893144
Short name T275
Test name
Test status
Simulation time 87183961855 ps
CPU time 120.1 seconds
Started Jul 29 05:05:38 PM PDT 24
Finished Jul 29 05:07:38 PM PDT 24
Peak memory 266064 kb
Host smart-1a57eb76-edee-447d-9326-8d6545bc62da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151893144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.2151893144
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.1272989159
Short name T1017
Test name
Test status
Simulation time 743379273 ps
CPU time 15.82 seconds
Started Jul 29 05:05:39 PM PDT 24
Finished Jul 29 05:05:55 PM PDT 24
Peak memory 241620 kb
Host smart-1948abbd-eb2a-45e6-923c-1ded07ae2584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272989159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.1272989159
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.1885184101
Short name T11
Test name
Test status
Simulation time 1311247885 ps
CPU time 17.8 seconds
Started Jul 29 05:04:18 PM PDT 24
Finished Jul 29 05:04:36 PM PDT 24
Peak memory 240004 kb
Host smart-588bef11-6b2d-4c0c-85ab-123d488bb807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885184101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.1885184101
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.3540513901
Short name T1119
Test name
Test status
Simulation time 1228696397 ps
CPU time 18.93 seconds
Started Jul 29 04:54:57 PM PDT 24
Finished Jul 29 04:55:21 PM PDT 24
Peak memory 215456 kb
Host smart-f6e5c8eb-ba55-44b2-b32f-65fb53048ce2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540513901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.3540513901
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.1296081692
Short name T274
Test name
Test status
Simulation time 3501887894 ps
CPU time 65.25 seconds
Started Jul 29 05:07:02 PM PDT 24
Finished Jul 29 05:08:07 PM PDT 24
Peak memory 256244 kb
Host smart-23c98868-70b1-4f96-b060-8feaf0260cfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296081692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmd
s.1296081692
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.286335004
Short name T271
Test name
Test status
Simulation time 143763782790 ps
CPU time 231.1 seconds
Started Jul 29 05:07:22 PM PDT 24
Finished Jul 29 05:11:13 PM PDT 24
Peak memory 268352 kb
Host smart-e0e40047-c495-41ee-929f-033a4365a0b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286335004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmds
.286335004
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.3989085444
Short name T96
Test name
Test status
Simulation time 187653262 ps
CPU time 2.53 seconds
Started Jul 29 05:04:12 PM PDT 24
Finished Jul 29 05:04:15 PM PDT 24
Peak memory 233388 kb
Host smart-62700333-9173-45f0-87e7-0d791ce1dd66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989085444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.3989085444
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_intercept.752167806
Short name T84
Test name
Test status
Simulation time 1189624320 ps
CPU time 11.96 seconds
Started Jul 29 05:06:19 PM PDT 24
Finished Jul 29 05:06:31 PM PDT 24
Peak memory 225160 kb
Host smart-ff16b679-46ff-4c94-b906-1605fffbb036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752167806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.752167806
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.1389508421
Short name T40
Test name
Test status
Simulation time 65490223971 ps
CPU time 294.44 seconds
Started Jul 29 05:06:31 PM PDT 24
Finished Jul 29 05:11:25 PM PDT 24
Peak memory 256472 kb
Host smart-1de17207-ee08-4e5f-9bb8-6e1ce2f2bfe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389508421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.1389508421
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1751397524
Short name T175
Test name
Test status
Simulation time 735260742 ps
CPU time 10.79 seconds
Started Jul 29 04:55:08 PM PDT 24
Finished Jul 29 04:55:19 PM PDT 24
Peak memory 215436 kb
Host smart-e69f136b-f65d-4664-a4b9-8baefc3cfab6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751397524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.1751397524
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.339441844
Short name T169
Test name
Test status
Simulation time 1146804418 ps
CPU time 18.57 seconds
Started Jul 29 04:55:35 PM PDT 24
Finished Jul 29 04:55:53 PM PDT 24
Peak memory 215460 kb
Host smart-0aeab9c6-17b6-4a06-bf50-5553e04ddd4d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339441844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device
_tl_intg_err.339441844
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.3574897646
Short name T79
Test name
Test status
Simulation time 12243088002 ps
CPU time 24.64 seconds
Started Jul 29 05:03:23 PM PDT 24
Finished Jul 29 05:03:47 PM PDT 24
Peak memory 216984 kb
Host smart-e2ea488d-6103-400b-9d64-646bead0392e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574897646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.3574897646
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.1022506782
Short name T187
Test name
Test status
Simulation time 7683872345 ps
CPU time 56.53 seconds
Started Jul 29 05:04:14 PM PDT 24
Finished Jul 29 05:05:10 PM PDT 24
Peak memory 249820 kb
Host smart-cee2dbde-a99d-440e-809b-4d1e4fd74841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022506782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.1022506782
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.2144772483
Short name T183
Test name
Test status
Simulation time 125979496592 ps
CPU time 297.04 seconds
Started Jul 29 05:04:31 PM PDT 24
Finished Jul 29 05:09:29 PM PDT 24
Peak memory 250904 kb
Host smart-3292cb34-866a-41d7-8d1a-b1bb59b9477f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144772483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.2144772483
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.2057570844
Short name T296
Test name
Test status
Simulation time 255662838 ps
CPU time 8.98 seconds
Started Jul 29 05:04:58 PM PDT 24
Finished Jul 29 05:05:08 PM PDT 24
Peak memory 241388 kb
Host smart-3faad3ba-017c-4c3a-ad3e-9a03061b561f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057570844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.2057570844
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.2111311365
Short name T281
Test name
Test status
Simulation time 124113942288 ps
CPU time 548.86 seconds
Started Jul 29 05:05:22 PM PDT 24
Finished Jul 29 05:14:31 PM PDT 24
Peak memory 264596 kb
Host smart-21946dbc-e6fd-4819-8d15-5f5b012b4e5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111311365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.2111311365
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.2991400958
Short name T283
Test name
Test status
Simulation time 56993087085 ps
CPU time 389.35 seconds
Started Jul 29 05:07:08 PM PDT 24
Finished Jul 29 05:13:38 PM PDT 24
Peak memory 249808 kb
Host smart-60ecefca-5816-4a97-95c0-b751ec7f735c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991400958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmd
s.2991400958
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.3602216661
Short name T314
Test name
Test status
Simulation time 3895321121 ps
CPU time 28.41 seconds
Started Jul 29 05:07:27 PM PDT 24
Finished Jul 29 05:07:55 PM PDT 24
Peak memory 249920 kb
Host smart-60c0b744-0a5d-4930-b81d-4ed8f9569f21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602216661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.3602216661
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_intercept.272521550
Short name T91
Test name
Test status
Simulation time 19617439181 ps
CPU time 27.59 seconds
Started Jul 29 05:05:54 PM PDT 24
Finished Jul 29 05:06:22 PM PDT 24
Peak memory 225376 kb
Host smart-d7994201-8af9-4e4b-b562-6d522ebb68ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272521550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.272521550
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.536738358
Short name T1117
Test name
Test status
Simulation time 57679563 ps
CPU time 3.49 seconds
Started Jul 29 04:55:09 PM PDT 24
Finished Jul 29 04:55:13 PM PDT 24
Peak memory 215724 kb
Host smart-6c6052ae-6edc-47fb-8311-a6aaa0bf0be1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536738358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.536738358
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1337567202
Short name T90
Test name
Test status
Simulation time 18698025 ps
CPU time 1.15 seconds
Started Jul 29 04:55:06 PM PDT 24
Finished Jul 29 04:55:07 PM PDT 24
Peak memory 216400 kb
Host smart-af2f1160-c59d-464c-bdf0-e57b3919ec67
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337567202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.1337567202
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.3734654848
Short name T125
Test name
Test status
Simulation time 112270161 ps
CPU time 7.07 seconds
Started Jul 29 04:54:49 PM PDT 24
Finished Jul 29 04:54:56 PM PDT 24
Peak memory 215376 kb
Host smart-42ed4bf8-72a0-420d-bbdb-086c940b89b0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734654848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.3734654848
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1173482587
Short name T122
Test name
Test status
Simulation time 3250710889 ps
CPU time 42.69 seconds
Started Jul 29 04:54:58 PM PDT 24
Finished Jul 29 04:55:41 PM PDT 24
Peak memory 207252 kb
Host smart-f6674a7c-f6c3-4940-97f4-dd9649b87ed6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173482587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.1173482587
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2847132316
Short name T89
Test name
Test status
Simulation time 145851218 ps
CPU time 0.96 seconds
Started Jul 29 04:54:54 PM PDT 24
Finished Jul 29 04:54:56 PM PDT 24
Peak memory 207060 kb
Host smart-c63f199d-4df0-4d55-849c-5ea62f229f60
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847132316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.2847132316
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1860574993
Short name T1143
Test name
Test status
Simulation time 245415253 ps
CPU time 3.63 seconds
Started Jul 29 04:54:45 PM PDT 24
Finished Jul 29 04:54:49 PM PDT 24
Peak memory 217736 kb
Host smart-28e2d0c5-9dc8-4dcd-b6ca-fd84039413ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860574993 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.1860574993
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.3216814235
Short name T129
Test name
Test status
Simulation time 58434465 ps
CPU time 1.82 seconds
Started Jul 29 04:54:58 PM PDT 24
Finished Jul 29 04:55:00 PM PDT 24
Peak memory 215428 kb
Host smart-0fa66427-6d00-4668-ae2f-bac67ca9861a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216814235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.3
216814235
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.3036300564
Short name T1040
Test name
Test status
Simulation time 65632439 ps
CPU time 0.72 seconds
Started Jul 29 04:55:16 PM PDT 24
Finished Jul 29 04:55:17 PM PDT 24
Peak memory 203856 kb
Host smart-6522f27d-2924-4297-9cf7-d45b9172e3d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036300564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.3
036300564
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.1739317385
Short name T1111
Test name
Test status
Simulation time 161795981 ps
CPU time 1.71 seconds
Started Jul 29 04:54:58 PM PDT 24
Finished Jul 29 04:55:10 PM PDT 24
Peak memory 215488 kb
Host smart-36a82c94-98ac-4081-8895-d9a38e5d5be4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739317385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.1739317385
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.398208539
Short name T1023
Test name
Test status
Simulation time 11182539 ps
CPU time 0.67 seconds
Started Jul 29 04:54:50 PM PDT 24
Finished Jul 29 04:54:51 PM PDT 24
Peak memory 203816 kb
Host smart-819422f2-596c-4fa5-ac2d-05ce6ea6b3bd
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398208539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_mem
_walk.398208539
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.630033487
Short name T1031
Test name
Test status
Simulation time 245094944 ps
CPU time 4.12 seconds
Started Jul 29 04:54:55 PM PDT 24
Finished Jul 29 04:54:59 PM PDT 24
Peak memory 215368 kb
Host smart-154e9603-fcbb-4df4-83cf-a3db64fdbf4c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630033487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sp
i_device_same_csr_outstanding.630033487
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.3650437342
Short name T1063
Test name
Test status
Simulation time 213386003 ps
CPU time 2.03 seconds
Started Jul 29 04:54:41 PM PDT 24
Finished Jul 29 04:54:43 PM PDT 24
Peak memory 216972 kb
Host smart-84f9ad73-784e-48e4-a924-1e0121256510
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650437342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.3
650437342
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.4135966187
Short name T1100
Test name
Test status
Simulation time 3944804367 ps
CPU time 17.46 seconds
Started Jul 29 04:54:59 PM PDT 24
Finished Jul 29 04:55:17 PM PDT 24
Peak memory 215600 kb
Host smart-68376821-9b8e-4a71-9793-a3ee951b78a1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135966187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.4135966187
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.4228392982
Short name T1120
Test name
Test status
Simulation time 1805325398 ps
CPU time 26.84 seconds
Started Jul 29 04:54:55 PM PDT 24
Finished Jul 29 04:55:27 PM PDT 24
Peak memory 207128 kb
Host smart-9a3c77f3-8827-40a4-bf4c-4a8115b79023
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228392982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.4228392982
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.4259725043
Short name T1044
Test name
Test status
Simulation time 66998939 ps
CPU time 0.93 seconds
Started Jul 29 04:54:54 PM PDT 24
Finished Jul 29 04:54:55 PM PDT 24
Peak memory 207000 kb
Host smart-566d9470-5070-4c4b-9d81-bd61a57cf525
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259725043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.4259725043
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.277935960
Short name T1124
Test name
Test status
Simulation time 55334451 ps
CPU time 3.56 seconds
Started Jul 29 04:55:04 PM PDT 24
Finished Jul 29 04:55:07 PM PDT 24
Peak memory 217516 kb
Host smart-fb355399-fc92-4578-892d-42ee47c578c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277935960 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.277935960
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.1776826268
Short name T119
Test name
Test status
Simulation time 92386344 ps
CPU time 2.44 seconds
Started Jul 29 04:55:17 PM PDT 24
Finished Jul 29 04:55:19 PM PDT 24
Peak memory 215388 kb
Host smart-e81584b7-dc03-46ba-a009-a92ec648a540
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776826268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.1
776826268
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.4271693940
Short name T1021
Test name
Test status
Simulation time 173052754 ps
CPU time 0.71 seconds
Started Jul 29 04:54:57 PM PDT 24
Finished Jul 29 04:54:58 PM PDT 24
Peak memory 203948 kb
Host smart-fc368776-2c00-422d-9352-e285b740ebd3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271693940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.4
271693940
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.91894485
Short name T1082
Test name
Test status
Simulation time 46464435 ps
CPU time 2.06 seconds
Started Jul 29 04:54:51 PM PDT 24
Finished Jul 29 04:54:53 PM PDT 24
Peak memory 215680 kb
Host smart-868a64ff-cc55-4f5d-95e7-ee20465be93a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91894485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi
_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_d
evice_mem_partial_access.91894485
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.1834708904
Short name T1088
Test name
Test status
Simulation time 12616292 ps
CPU time 0.66 seconds
Started Jul 29 04:54:45 PM PDT 24
Finished Jul 29 04:54:46 PM PDT 24
Peak memory 203804 kb
Host smart-c5410480-95c5-4bfa-bdcb-22419235d558
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834708904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.1834708904
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.379549647
Short name T1092
Test name
Test status
Simulation time 62412905 ps
CPU time 1.91 seconds
Started Jul 29 04:55:09 PM PDT 24
Finished Jul 29 04:55:11 PM PDT 24
Peak memory 215420 kb
Host smart-5766f7bd-d738-4427-9cee-e079be18850a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379549647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sp
i_device_same_csr_outstanding.379549647
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.3645695623
Short name T1054
Test name
Test status
Simulation time 198764485 ps
CPU time 5.72 seconds
Started Jul 29 04:55:02 PM PDT 24
Finished Jul 29 04:55:08 PM PDT 24
Peak memory 215700 kb
Host smart-26061899-ee8b-4b09-a97d-3b3ee4f9cd31
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645695623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.3
645695623
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2178624098
Short name T156
Test name
Test status
Simulation time 1098072145 ps
CPU time 23.64 seconds
Started Jul 29 04:54:57 PM PDT 24
Finished Jul 29 04:55:20 PM PDT 24
Peak memory 215640 kb
Host smart-6b44c45f-5d4f-4346-9255-3ee26fd26c7e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178624098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.2178624098
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3328010459
Short name T155
Test name
Test status
Simulation time 154282525 ps
CPU time 3.74 seconds
Started Jul 29 04:55:35 PM PDT 24
Finished Jul 29 04:55:39 PM PDT 24
Peak memory 217492 kb
Host smart-401f9942-aacc-48cb-afe9-032d6f8822f8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328010459 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.3328010459
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.621838516
Short name T1097
Test name
Test status
Simulation time 418010275 ps
CPU time 1.34 seconds
Started Jul 29 04:55:28 PM PDT 24
Finished Jul 29 04:55:30 PM PDT 24
Peak memory 207256 kb
Host smart-0934329d-2299-4790-bc53-670a17704704
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621838516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.621838516
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.151561233
Short name T1028
Test name
Test status
Simulation time 77231854 ps
CPU time 0.7 seconds
Started Jul 29 04:55:21 PM PDT 24
Finished Jul 29 04:55:21 PM PDT 24
Peak memory 204152 kb
Host smart-ce069493-eb31-447b-bb6d-6efa2fb94dac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151561233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.151561233
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.3417239911
Short name T1084
Test name
Test status
Simulation time 195445915 ps
CPU time 1.71 seconds
Started Jul 29 04:55:04 PM PDT 24
Finished Jul 29 04:55:05 PM PDT 24
Peak memory 215356 kb
Host smart-cc833118-b63e-4f5f-a38f-6abfe9366ff5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417239911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.3417239911
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.1410803261
Short name T1066
Test name
Test status
Simulation time 64930125 ps
CPU time 1.95 seconds
Started Jul 29 04:55:20 PM PDT 24
Finished Jul 29 04:55:22 PM PDT 24
Peak memory 216472 kb
Host smart-94444790-7afd-4aad-a272-9b778e726760
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410803261 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.1410803261
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.3965863735
Short name T1125
Test name
Test status
Simulation time 70017947 ps
CPU time 2.38 seconds
Started Jul 29 04:55:08 PM PDT 24
Finished Jul 29 04:55:11 PM PDT 24
Peak memory 215464 kb
Host smart-11b46916-40e5-4897-9308-43d22904984b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965863735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
3965863735
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.2852513200
Short name T1038
Test name
Test status
Simulation time 25717496 ps
CPU time 0.75 seconds
Started Jul 29 04:55:10 PM PDT 24
Finished Jul 29 04:55:11 PM PDT 24
Peak memory 203920 kb
Host smart-e40a3bb3-a86e-4d01-af20-b8d52a99b539
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852513200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
2852513200
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.90807296
Short name T157
Test name
Test status
Simulation time 193512400 ps
CPU time 2.91 seconds
Started Jul 29 04:55:04 PM PDT 24
Finished Jul 29 04:55:07 PM PDT 24
Peak memory 215464 kb
Host smart-5481b157-d78d-48ae-be80-bd4f019b4fa5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90807296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sp
i_device_same_csr_outstanding.90807296
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.2133809907
Short name T1142
Test name
Test status
Simulation time 358179479 ps
CPU time 3.03 seconds
Started Jul 29 04:54:53 PM PDT 24
Finished Jul 29 04:54:56 PM PDT 24
Peak memory 215780 kb
Host smart-81ab071b-d0ac-4e5a-af93-025ff6cb468f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133809907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
2133809907
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2201005855
Short name T171
Test name
Test status
Simulation time 106145521 ps
CPU time 6.68 seconds
Started Jul 29 04:55:10 PM PDT 24
Finished Jul 29 04:55:17 PM PDT 24
Peak memory 215296 kb
Host smart-73b5cfc9-d42f-49ab-a885-2c987e2f4c41
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201005855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.2201005855
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3509495751
Short name T1067
Test name
Test status
Simulation time 245166791 ps
CPU time 4 seconds
Started Jul 29 04:55:11 PM PDT 24
Finished Jul 29 04:55:16 PM PDT 24
Peak memory 217624 kb
Host smart-5943157b-962b-41d9-a7a1-bdc5c0bfba9f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509495751 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.3509495751
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.3214781104
Short name T1087
Test name
Test status
Simulation time 42870945 ps
CPU time 1.88 seconds
Started Jul 29 04:55:14 PM PDT 24
Finished Jul 29 04:55:17 PM PDT 24
Peak memory 215264 kb
Host smart-7a4bc6c4-0832-48a5-8284-7f9475fa2c8c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214781104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
3214781104
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.4237254947
Short name T1020
Test name
Test status
Simulation time 12345178 ps
CPU time 0.7 seconds
Started Jul 29 04:55:03 PM PDT 24
Finished Jul 29 04:55:04 PM PDT 24
Peak memory 203844 kb
Host smart-bd027a9a-8362-4d25-8b64-639131f865b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237254947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
4237254947
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.339124892
Short name T1113
Test name
Test status
Simulation time 230436297 ps
CPU time 1.91 seconds
Started Jul 29 04:55:11 PM PDT 24
Finished Jul 29 04:55:14 PM PDT 24
Peak memory 215460 kb
Host smart-28adc9d1-bf14-447b-b6cd-a121597dcc85
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339124892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.s
pi_device_same_csr_outstanding.339124892
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.671731225
Short name T1099
Test name
Test status
Simulation time 281460919 ps
CPU time 1.82 seconds
Started Jul 29 04:55:20 PM PDT 24
Finished Jul 29 04:55:22 PM PDT 24
Peak memory 215820 kb
Host smart-e2ce9a6a-dc85-4a42-a198-3bbb0e3bd2d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671731225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.671731225
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.368738913
Short name T158
Test name
Test status
Simulation time 3199561984 ps
CPU time 22.69 seconds
Started Jul 29 04:55:15 PM PDT 24
Finished Jul 29 04:55:39 PM PDT 24
Peak memory 215780 kb
Host smart-03f3fd73-6596-4d7f-881c-9a44e55c09d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368738913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device
_tl_intg_err.368738913
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.776608070
Short name T1112
Test name
Test status
Simulation time 164392974 ps
CPU time 2.44 seconds
Started Jul 29 04:55:13 PM PDT 24
Finished Jul 29 04:55:16 PM PDT 24
Peak memory 216800 kb
Host smart-5b67317a-1aa1-4581-9749-dc5f6c3e8a38
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776608070 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.776608070
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.378616616
Short name T1107
Test name
Test status
Simulation time 87486455 ps
CPU time 2.42 seconds
Started Jul 29 04:55:08 PM PDT 24
Finished Jul 29 04:55:11 PM PDT 24
Peak memory 215720 kb
Host smart-fd9b7e40-c80d-4d48-bddf-26872ebd6729
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378616616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.378616616
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.645707596
Short name T1104
Test name
Test status
Simulation time 12355426 ps
CPU time 0.68 seconds
Started Jul 29 04:55:25 PM PDT 24
Finished Jul 29 04:55:25 PM PDT 24
Peak memory 203840 kb
Host smart-a86609d7-1fd3-4379-9d26-605f7a1bd073
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645707596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.645707596
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.2651417556
Short name T1110
Test name
Test status
Simulation time 467173770 ps
CPU time 3.01 seconds
Started Jul 29 04:54:57 PM PDT 24
Finished Jul 29 04:55:00 PM PDT 24
Peak memory 215344 kb
Host smart-df9adbd5-1207-4a39-bbfc-73f622d4ea1d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651417556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.2651417556
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.1724693178
Short name T114
Test name
Test status
Simulation time 109758603 ps
CPU time 3.41 seconds
Started Jul 29 04:55:04 PM PDT 24
Finished Jul 29 04:55:08 PM PDT 24
Peak memory 215620 kb
Host smart-08a75dd1-ae1d-4b5d-a906-0526f155343a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724693178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
1724693178
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.1784338258
Short name T1106
Test name
Test status
Simulation time 415215954 ps
CPU time 2.51 seconds
Started Jul 29 04:55:00 PM PDT 24
Finished Jul 29 04:55:02 PM PDT 24
Peak memory 216480 kb
Host smart-de27be0b-a34f-4ed2-b3a6-5097c5ea92b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784338258 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.1784338258
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.2631666182
Short name T1135
Test name
Test status
Simulation time 31701911 ps
CPU time 1.93 seconds
Started Jul 29 04:55:13 PM PDT 24
Finished Jul 29 04:55:15 PM PDT 24
Peak memory 207148 kb
Host smart-1b38769d-8b18-457d-aeb9-96006b027b74
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631666182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
2631666182
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.3195465350
Short name T1114
Test name
Test status
Simulation time 21218228 ps
CPU time 0.78 seconds
Started Jul 29 04:55:11 PM PDT 24
Finished Jul 29 04:55:13 PM PDT 24
Peak memory 204328 kb
Host smart-eed1ea57-d195-4207-a306-35d3d536e438
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195465350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
3195465350
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.1746932239
Short name T1069
Test name
Test status
Simulation time 82487587 ps
CPU time 3.74 seconds
Started Jul 29 04:55:33 PM PDT 24
Finished Jul 29 04:55:37 PM PDT 24
Peak memory 215400 kb
Host smart-8f3164a5-d980-40fb-9e45-d5177ddbf4e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746932239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.1746932239
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.1649732745
Short name T1079
Test name
Test status
Simulation time 91322943 ps
CPU time 2.72 seconds
Started Jul 29 04:54:52 PM PDT 24
Finished Jul 29 04:54:55 PM PDT 24
Peak memory 215708 kb
Host smart-7e31dca0-ccc5-4f23-b515-b37e70e9391f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649732745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
1649732745
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.3770444870
Short name T1068
Test name
Test status
Simulation time 890402465 ps
CPU time 13.22 seconds
Started Jul 29 04:55:18 PM PDT 24
Finished Jul 29 04:55:31 PM PDT 24
Peak memory 215584 kb
Host smart-7514f0cc-cbff-4439-84aa-28510f8e3e53
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770444870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.3770444870
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.547279470
Short name T118
Test name
Test status
Simulation time 256421028 ps
CPU time 1.71 seconds
Started Jul 29 04:55:08 PM PDT 24
Finished Jul 29 04:55:15 PM PDT 24
Peak memory 215312 kb
Host smart-a1f6944d-4d7a-4c4e-8edb-5750df40eb5c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547279470 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.547279470
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.3636618717
Short name T1085
Test name
Test status
Simulation time 154449147 ps
CPU time 2.43 seconds
Started Jul 29 04:55:25 PM PDT 24
Finished Jul 29 04:55:28 PM PDT 24
Peak memory 207292 kb
Host smart-91635731-f2ec-4869-bc65-786c7bda4b9f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636618717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
3636618717
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.569772593
Short name T1147
Test name
Test status
Simulation time 17000898 ps
CPU time 0.68 seconds
Started Jul 29 04:55:21 PM PDT 24
Finished Jul 29 04:55:22 PM PDT 24
Peak memory 203788 kb
Host smart-8a25ee32-edea-4823-9a7f-bd10013bbaa6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569772593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.569772593
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2559167102
Short name T153
Test name
Test status
Simulation time 144997232 ps
CPU time 3.25 seconds
Started Jul 29 04:55:13 PM PDT 24
Finished Jul 29 04:55:17 PM PDT 24
Peak memory 215676 kb
Host smart-03acc587-7c03-4216-8971-249807c86c75
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559167102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.2559167102
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.10111908
Short name T1060
Test name
Test status
Simulation time 447293467 ps
CPU time 2.6 seconds
Started Jul 29 04:55:15 PM PDT 24
Finished Jul 29 04:55:18 PM PDT 24
Peak memory 215660 kb
Host smart-283b5777-e15a-457d-a1b5-42c80457f3d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10111908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.10111908
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.501809780
Short name T1057
Test name
Test status
Simulation time 51805934 ps
CPU time 1.58 seconds
Started Jul 29 04:55:49 PM PDT 24
Finished Jul 29 04:55:51 PM PDT 24
Peak memory 215484 kb
Host smart-2b753cf8-6584-4048-9c38-23c29f0378af
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501809780 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.501809780
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.3557448021
Short name T1076
Test name
Test status
Simulation time 43095408 ps
CPU time 2.69 seconds
Started Jul 29 04:55:04 PM PDT 24
Finished Jul 29 04:55:07 PM PDT 24
Peak memory 215436 kb
Host smart-7e6e8566-e5d0-49b4-9d62-f0563e3b6b91
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557448021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
3557448021
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.2645553689
Short name T1050
Test name
Test status
Simulation time 35631982 ps
CPU time 0.68 seconds
Started Jul 29 04:55:10 PM PDT 24
Finished Jul 29 04:55:11 PM PDT 24
Peak memory 203840 kb
Host smart-bbf6d3ab-aa68-4ba0-8d3f-28b43f225b02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645553689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
2645553689
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.1450613293
Short name T1073
Test name
Test status
Simulation time 191181767 ps
CPU time 3.77 seconds
Started Jul 29 04:55:30 PM PDT 24
Finished Jul 29 04:55:34 PM PDT 24
Peak memory 215344 kb
Host smart-c53d5632-fde4-49ab-a326-059964a585e0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450613293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.1450613293
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.2611601991
Short name T113
Test name
Test status
Simulation time 848559333 ps
CPU time 4.83 seconds
Started Jul 29 04:55:25 PM PDT 24
Finished Jul 29 04:55:30 PM PDT 24
Peak memory 216728 kb
Host smart-7479a1cd-9ba8-4120-a6d5-7d4d01b8ac0e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611601991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
2611601991
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.4125511108
Short name T108
Test name
Test status
Simulation time 2146875763 ps
CPU time 15.35 seconds
Started Jul 29 04:55:19 PM PDT 24
Finished Jul 29 04:55:34 PM PDT 24
Peak memory 215536 kb
Host smart-f87087bc-bba9-46d7-810e-3683d2396c40
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125511108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.4125511108
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1103996060
Short name T102
Test name
Test status
Simulation time 26370198 ps
CPU time 1.87 seconds
Started Jul 29 04:55:28 PM PDT 24
Finished Jul 29 04:55:30 PM PDT 24
Peak memory 215456 kb
Host smart-75a9c2ac-c099-4192-b34a-eb2dc6b2d1f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103996060 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.1103996060
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.2092235569
Short name T1065
Test name
Test status
Simulation time 95363121 ps
CPU time 1.76 seconds
Started Jul 29 04:54:57 PM PDT 24
Finished Jul 29 04:54:58 PM PDT 24
Peak memory 215340 kb
Host smart-e6397e62-0be8-4aa1-94ab-6011d8d510fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092235569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
2092235569
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.1748668353
Short name T1030
Test name
Test status
Simulation time 82934227 ps
CPU time 0.75 seconds
Started Jul 29 04:55:04 PM PDT 24
Finished Jul 29 04:55:05 PM PDT 24
Peak memory 203884 kb
Host smart-5d605203-f19e-419d-8b8f-c776ee5eb810
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748668353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
1748668353
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.546963862
Short name T1129
Test name
Test status
Simulation time 293544869 ps
CPU time 3.01 seconds
Started Jul 29 04:55:01 PM PDT 24
Finished Jul 29 04:55:04 PM PDT 24
Peak memory 215448 kb
Host smart-921bd5fa-9e24-4c39-a519-fd7cd933c68b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546963862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.s
pi_device_same_csr_outstanding.546963862
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.4163982822
Short name T1139
Test name
Test status
Simulation time 1117286873 ps
CPU time 4.26 seconds
Started Jul 29 04:55:27 PM PDT 24
Finished Jul 29 04:55:32 PM PDT 24
Peak memory 215660 kb
Host smart-0f55c08c-0884-4094-bb94-7488c0785e9e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163982822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
4163982822
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1093021030
Short name T170
Test name
Test status
Simulation time 1095701634 ps
CPU time 14.6 seconds
Started Jul 29 04:55:17 PM PDT 24
Finished Jul 29 04:55:32 PM PDT 24
Peak memory 215516 kb
Host smart-76b06b41-1be3-46fa-8698-ef5fb8156ccf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093021030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.1093021030
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.836249751
Short name T109
Test name
Test status
Simulation time 137443830 ps
CPU time 3.93 seconds
Started Jul 29 04:55:25 PM PDT 24
Finished Jul 29 04:55:29 PM PDT 24
Peak memory 217976 kb
Host smart-889e2e83-40c6-453b-874c-4779967234eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836249751 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.836249751
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.87467890
Short name T1059
Test name
Test status
Simulation time 108904949 ps
CPU time 2.07 seconds
Started Jul 29 04:55:23 PM PDT 24
Finished Jul 29 04:55:25 PM PDT 24
Peak memory 207192 kb
Host smart-86900e2c-d49b-4263-9c44-d7e1c3abcac5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87467890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.87467890
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.3319226887
Short name T1036
Test name
Test status
Simulation time 13621331 ps
CPU time 0.75 seconds
Started Jul 29 04:54:55 PM PDT 24
Finished Jul 29 04:54:56 PM PDT 24
Peak memory 203876 kb
Host smart-1085f22f-0316-422f-8750-af524b866ae2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319226887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
3319226887
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.3506121389
Short name T1034
Test name
Test status
Simulation time 72702623 ps
CPU time 1.71 seconds
Started Jul 29 04:55:19 PM PDT 24
Finished Jul 29 04:55:21 PM PDT 24
Peak memory 215460 kb
Host smart-9fb9da40-0380-471c-a800-8fe815cfdc94
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506121389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.3506121389
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.4144513671
Short name T1136
Test name
Test status
Simulation time 474942182 ps
CPU time 3.73 seconds
Started Jul 29 04:55:11 PM PDT 24
Finished Jul 29 04:55:16 PM PDT 24
Peak memory 215644 kb
Host smart-46e8501e-c8e4-4ea0-b39b-0bd6cdff9a39
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144513671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
4144513671
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.990226399
Short name T168
Test name
Test status
Simulation time 220405704 ps
CPU time 6.73 seconds
Started Jul 29 04:55:22 PM PDT 24
Finished Jul 29 04:55:29 PM PDT 24
Peak memory 215588 kb
Host smart-74b29c70-5d75-4dfc-8866-cc712860ec1b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990226399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device
_tl_intg_err.990226399
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.334849769
Short name T1086
Test name
Test status
Simulation time 402741239 ps
CPU time 2.79 seconds
Started Jul 29 04:55:07 PM PDT 24
Finished Jul 29 04:55:10 PM PDT 24
Peak memory 216852 kb
Host smart-4406f5e1-3986-4d98-8d27-4bcc77ebe71c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334849769 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.334849769
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1320020547
Short name T1039
Test name
Test status
Simulation time 41617847 ps
CPU time 1.38 seconds
Started Jul 29 04:55:24 PM PDT 24
Finished Jul 29 04:55:25 PM PDT 24
Peak memory 207160 kb
Host smart-9711b2dc-c9a4-4c04-880c-3afb124c44cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320020547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
1320020547
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1085744981
Short name T1045
Test name
Test status
Simulation time 18891755 ps
CPU time 0.75 seconds
Started Jul 29 04:55:18 PM PDT 24
Finished Jul 29 04:55:19 PM PDT 24
Peak memory 203972 kb
Host smart-69f99a65-772e-4673-8f5e-ca1076b15ba1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085744981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
1085744981
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2018328319
Short name T1049
Test name
Test status
Simulation time 66344366 ps
CPU time 3.79 seconds
Started Jul 29 04:55:00 PM PDT 24
Finished Jul 29 04:55:04 PM PDT 24
Peak memory 215484 kb
Host smart-22777acb-50b3-42ce-af9c-f5380127945e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018328319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.2018328319
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.1462475194
Short name T173
Test name
Test status
Simulation time 974347864 ps
CPU time 22.44 seconds
Started Jul 29 04:55:23 PM PDT 24
Finished Jul 29 04:55:45 PM PDT 24
Peak memory 216932 kb
Host smart-aac6be77-f925-4321-9342-d7e6382f3769
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462475194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.1462475194
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.344019562
Short name T1109
Test name
Test status
Simulation time 846573219 ps
CPU time 16.9 seconds
Started Jul 29 04:55:01 PM PDT 24
Finished Jul 29 04:55:18 PM PDT 24
Peak memory 215764 kb
Host smart-5b5ed0e5-edc1-408a-9796-15cc25ca547b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344019562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_aliasing.344019562
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3672348673
Short name T1081
Test name
Test status
Simulation time 21041003 ps
CPU time 1.02 seconds
Started Jul 29 04:54:55 PM PDT 24
Finished Jul 29 04:54:56 PM PDT 24
Peak memory 206980 kb
Host smart-52184816-1686-414f-beb1-df0e5b86d267
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672348673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.3672348673
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2736814064
Short name T1145
Test name
Test status
Simulation time 52247971 ps
CPU time 1.75 seconds
Started Jul 29 04:55:20 PM PDT 24
Finished Jul 29 04:55:22 PM PDT 24
Peak memory 216416 kb
Host smart-2b3c1e80-6a2b-4932-a229-611878af2a29
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736814064 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.2736814064
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.587201576
Short name T1052
Test name
Test status
Simulation time 118132715 ps
CPU time 2.6 seconds
Started Jul 29 04:54:54 PM PDT 24
Finished Jul 29 04:54:57 PM PDT 24
Peak memory 215316 kb
Host smart-eb8b5a7f-40e1-4d8a-9371-ed4a0ab4cc66
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587201576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.587201576
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.1904909709
Short name T1043
Test name
Test status
Simulation time 41312825 ps
CPU time 0.74 seconds
Started Jul 29 04:55:12 PM PDT 24
Finished Jul 29 04:55:13 PM PDT 24
Peak memory 204200 kb
Host smart-c69ab68f-06b8-4143-a72d-0041bf782c66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904909709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.1
904909709
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2809494268
Short name T121
Test name
Test status
Simulation time 58324963 ps
CPU time 1.9 seconds
Started Jul 29 04:54:52 PM PDT 24
Finished Jul 29 04:54:54 PM PDT 24
Peak memory 215508 kb
Host smart-2bc24430-5396-4c8b-959b-af0f1c92a49a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809494268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.2809494268
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.606884417
Short name T1115
Test name
Test status
Simulation time 51339984 ps
CPU time 0.66 seconds
Started Jul 29 04:55:15 PM PDT 24
Finished Jul 29 04:55:16 PM PDT 24
Peak memory 203768 kb
Host smart-676f69ec-f3b9-48f7-ae91-077d73c8f6e5
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606884417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_mem
_walk.606884417
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.98407426
Short name T1093
Test name
Test status
Simulation time 279906413 ps
CPU time 1.85 seconds
Started Jul 29 04:54:56 PM PDT 24
Finished Jul 29 04:54:58 PM PDT 24
Peak memory 215324 kb
Host smart-ff226ec0-f26c-49fe-aca4-d09d796b7fe4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98407426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_same_csr_outstanding.98407426
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.2678766106
Short name T117
Test name
Test status
Simulation time 1754001399 ps
CPU time 5.24 seconds
Started Jul 29 04:55:03 PM PDT 24
Finished Jul 29 04:55:08 PM PDT 24
Peak memory 215756 kb
Host smart-03be539b-6fd6-4a0a-8e10-037072028e85
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678766106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.2
678766106
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1319653729
Short name T1090
Test name
Test status
Simulation time 406089581 ps
CPU time 6.69 seconds
Started Jul 29 04:54:58 PM PDT 24
Finished Jul 29 04:55:05 PM PDT 24
Peak memory 215828 kb
Host smart-e3374ee0-68ce-4fd8-87b0-85feb61603e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319653729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.1319653729
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.68361869
Short name T1149
Test name
Test status
Simulation time 24316437 ps
CPU time 0.69 seconds
Started Jul 29 04:55:06 PM PDT 24
Finished Jul 29 04:55:07 PM PDT 24
Peak memory 204216 kb
Host smart-a4988d33-0fd5-4851-b7cd-8a02ec6b1757
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68361869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.68361869
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.1455111560
Short name T1075
Test name
Test status
Simulation time 11605847 ps
CPU time 0.74 seconds
Started Jul 29 04:55:12 PM PDT 24
Finished Jul 29 04:55:13 PM PDT 24
Peak memory 203916 kb
Host smart-e48add62-1799-449d-8330-3b51d1380fcc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455111560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
1455111560
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3866423093
Short name T1105
Test name
Test status
Simulation time 15646702 ps
CPU time 0.68 seconds
Started Jul 29 04:55:01 PM PDT 24
Finished Jul 29 04:55:02 PM PDT 24
Peak memory 203904 kb
Host smart-56888edd-4ca9-4984-803e-05122a22c152
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866423093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
3866423093
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2661138164
Short name T1150
Test name
Test status
Simulation time 14099869 ps
CPU time 0.72 seconds
Started Jul 29 04:55:01 PM PDT 24
Finished Jul 29 04:55:01 PM PDT 24
Peak memory 204184 kb
Host smart-5b575347-7b22-474f-91ac-2bfc434527d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661138164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
2661138164
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.2019200762
Short name T1144
Test name
Test status
Simulation time 16334241 ps
CPU time 0.7 seconds
Started Jul 29 04:55:14 PM PDT 24
Finished Jul 29 04:55:15 PM PDT 24
Peak memory 204252 kb
Host smart-364ffb23-9b27-49d9-87b7-5ecf7dc7b67b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019200762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
2019200762
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.682727128
Short name T1127
Test name
Test status
Simulation time 31614754 ps
CPU time 0.71 seconds
Started Jul 29 04:55:13 PM PDT 24
Finished Jul 29 04:55:14 PM PDT 24
Peak memory 203900 kb
Host smart-b4cc6c01-8301-466b-a170-16894039a257
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682727128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.682727128
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2887035151
Short name T1133
Test name
Test status
Simulation time 49666150 ps
CPU time 0.66 seconds
Started Jul 29 04:55:23 PM PDT 24
Finished Jul 29 04:55:24 PM PDT 24
Peak memory 203956 kb
Host smart-3558de20-ff2e-4baa-9ee9-8ea2f1a032c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887035151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
2887035151
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.1524816248
Short name T1032
Test name
Test status
Simulation time 15268002 ps
CPU time 0.74 seconds
Started Jul 29 04:55:23 PM PDT 24
Finished Jul 29 04:55:24 PM PDT 24
Peak memory 203884 kb
Host smart-c7dbaf6b-6167-4bab-a5d6-f367b8fb4a7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524816248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
1524816248
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.3868732585
Short name T1116
Test name
Test status
Simulation time 13440798 ps
CPU time 0.71 seconds
Started Jul 29 04:55:27 PM PDT 24
Finished Jul 29 04:55:28 PM PDT 24
Peak memory 203868 kb
Host smart-3165a56d-6008-4462-9acd-a887d34b50c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868732585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
3868732585
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.4109584442
Short name T1056
Test name
Test status
Simulation time 27288916 ps
CPU time 0.76 seconds
Started Jul 29 04:55:12 PM PDT 24
Finished Jul 29 04:55:13 PM PDT 24
Peak memory 203920 kb
Host smart-d054a87f-f58c-4735-90d8-65403aed1cf6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109584442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
4109584442
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.2835679305
Short name T1148
Test name
Test status
Simulation time 615244203 ps
CPU time 14.88 seconds
Started Jul 29 04:54:44 PM PDT 24
Finished Jul 29 04:54:59 PM PDT 24
Peak memory 215300 kb
Host smart-d27baf5e-221a-45ed-a444-de2a9e5a0fdb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835679305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.2835679305
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3067273632
Short name T1118
Test name
Test status
Simulation time 1811052275 ps
CPU time 26.5 seconds
Started Jul 29 04:55:00 PM PDT 24
Finished Jul 29 04:55:26 PM PDT 24
Peak memory 207184 kb
Host smart-36393ab5-3036-455d-8acf-a393b474e32d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067273632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.3067273632
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.26044318
Short name T1126
Test name
Test status
Simulation time 113990975 ps
CPU time 2.49 seconds
Started Jul 29 04:55:27 PM PDT 24
Finished Jul 29 04:55:29 PM PDT 24
Peak memory 216524 kb
Host smart-ade88a12-778c-4d4f-9a20-8456e5f7bd4b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26044318 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.26044318
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1433425861
Short name T1138
Test name
Test status
Simulation time 82130499 ps
CPU time 1.29 seconds
Started Jul 29 04:55:03 PM PDT 24
Finished Jul 29 04:55:05 PM PDT 24
Peak memory 215380 kb
Host smart-57ce2280-afb6-4189-946e-645464081e27
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433425861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.1
433425861
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.2574965615
Short name T1047
Test name
Test status
Simulation time 32134784 ps
CPU time 0.71 seconds
Started Jul 29 04:55:00 PM PDT 24
Finished Jul 29 04:55:00 PM PDT 24
Peak memory 203888 kb
Host smart-4fc6ce35-1fee-4fba-9e50-1eb68415bdbe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574965615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.2
574965615
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.1617937081
Short name T1134
Test name
Test status
Simulation time 41755535 ps
CPU time 1.99 seconds
Started Jul 29 04:54:51 PM PDT 24
Finished Jul 29 04:54:53 PM PDT 24
Peak memory 215336 kb
Host smart-5f09abab-341b-42c1-9a03-7da765999105
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617937081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.1617937081
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1127525675
Short name T1048
Test name
Test status
Simulation time 28662027 ps
CPU time 0.64 seconds
Started Jul 29 04:55:02 PM PDT 24
Finished Jul 29 04:55:07 PM PDT 24
Peak memory 203912 kb
Host smart-e3426e28-58b1-40b8-8024-75f50a1636df
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127525675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.1127525675
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1439715629
Short name T1098
Test name
Test status
Simulation time 46998729 ps
CPU time 1.66 seconds
Started Jul 29 04:54:54 PM PDT 24
Finished Jul 29 04:54:56 PM PDT 24
Peak memory 206968 kb
Host smart-514bfce9-4099-4e1c-a3b3-7b8bf4172ce0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439715629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.1439715629
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.348025481
Short name T107
Test name
Test status
Simulation time 129603950 ps
CPU time 3.31 seconds
Started Jul 29 04:55:11 PM PDT 24
Finished Jul 29 04:55:15 PM PDT 24
Peak memory 215708 kb
Host smart-e6e25c51-4788-4823-a379-b316348e6e15
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348025481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.348025481
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.1677856468
Short name T1072
Test name
Test status
Simulation time 3479986228 ps
CPU time 7.17 seconds
Started Jul 29 04:55:27 PM PDT 24
Finished Jul 29 04:55:35 PM PDT 24
Peak memory 216064 kb
Host smart-a6cd44e0-0094-44b2-90a0-ef9ef768a14b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677856468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.1677856468
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.428833061
Short name T1128
Test name
Test status
Simulation time 14195210 ps
CPU time 0.74 seconds
Started Jul 29 04:55:39 PM PDT 24
Finished Jul 29 04:55:45 PM PDT 24
Peak memory 203824 kb
Host smart-8208cdf5-14b0-499f-99f9-bc204e778965
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428833061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.428833061
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.3639095730
Short name T1051
Test name
Test status
Simulation time 16447741 ps
CPU time 0.73 seconds
Started Jul 29 04:55:09 PM PDT 24
Finished Jul 29 04:55:10 PM PDT 24
Peak memory 203896 kb
Host smart-b4770afa-f9ce-4848-8838-1f3948176a2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639095730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
3639095730
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.3260365344
Short name T1041
Test name
Test status
Simulation time 33106973 ps
CPU time 0.76 seconds
Started Jul 29 04:55:14 PM PDT 24
Finished Jul 29 04:55:15 PM PDT 24
Peak memory 203992 kb
Host smart-5d282f0c-c864-49da-a521-750220a71383
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260365344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
3260365344
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.143212688
Short name T1042
Test name
Test status
Simulation time 14190553 ps
CPU time 0.74 seconds
Started Jul 29 04:55:16 PM PDT 24
Finished Jul 29 04:55:17 PM PDT 24
Peak memory 203884 kb
Host smart-b8415c05-56c0-4d69-93c6-5e8035752369
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143212688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.143212688
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.3075115102
Short name T1027
Test name
Test status
Simulation time 72149491 ps
CPU time 0.72 seconds
Started Jul 29 04:55:06 PM PDT 24
Finished Jul 29 04:55:06 PM PDT 24
Peak memory 203940 kb
Host smart-29645eb3-92dc-40c4-bbc3-0946a4bfd9db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075115102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
3075115102
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.3923224189
Short name T1071
Test name
Test status
Simulation time 31308253 ps
CPU time 0.67 seconds
Started Jul 29 04:55:27 PM PDT 24
Finished Jul 29 04:55:28 PM PDT 24
Peak memory 203908 kb
Host smart-9789de0a-c0d5-4f0b-9bb6-00aeccad6e97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923224189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
3923224189
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.1006226750
Short name T1137
Test name
Test status
Simulation time 39965178 ps
CPU time 0.69 seconds
Started Jul 29 04:55:22 PM PDT 24
Finished Jul 29 04:55:23 PM PDT 24
Peak memory 203848 kb
Host smart-d25bd7a3-ce68-4cca-bc26-1e97713b6a22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006226750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
1006226750
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.2295034153
Short name T1022
Test name
Test status
Simulation time 15738059 ps
CPU time 0.75 seconds
Started Jul 29 04:55:09 PM PDT 24
Finished Jul 29 04:55:09 PM PDT 24
Peak memory 203872 kb
Host smart-1cb1d40c-7c54-4312-a678-0371d614b766
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295034153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
2295034153
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.39154850
Short name T1055
Test name
Test status
Simulation time 129855713 ps
CPU time 0.69 seconds
Started Jul 29 04:55:29 PM PDT 24
Finished Jul 29 04:55:30 PM PDT 24
Peak memory 203984 kb
Host smart-adda2eb8-1320-43af-9439-7433d9e7725f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39154850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.39154850
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1076817057
Short name T1102
Test name
Test status
Simulation time 18789035 ps
CPU time 0.69 seconds
Started Jul 29 04:55:05 PM PDT 24
Finished Jul 29 04:55:06 PM PDT 24
Peak memory 203852 kb
Host smart-fd238a70-f6e5-41bc-b1ae-2cddcfeea5c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076817057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
1076817057
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3072147889
Short name T128
Test name
Test status
Simulation time 2493684882 ps
CPU time 20.77 seconds
Started Jul 29 04:55:05 PM PDT 24
Finished Jul 29 04:55:25 PM PDT 24
Peak memory 215484 kb
Host smart-b7215a47-249a-488a-ae04-5d8abd7bb114
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072147889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.3072147889
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.205377384
Short name T127
Test name
Test status
Simulation time 2447942085 ps
CPU time 36.48 seconds
Started Jul 29 04:54:54 PM PDT 24
Finished Jul 29 04:55:31 PM PDT 24
Peak memory 207328 kb
Host smart-5fbb9b94-76a2-4075-9ed9-545eb97b8e96
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205377384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_bit_bash.205377384
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.270891048
Short name T88
Test name
Test status
Simulation time 22065817 ps
CPU time 1.35 seconds
Started Jul 29 04:54:55 PM PDT 24
Finished Jul 29 04:54:57 PM PDT 24
Peak memory 216396 kb
Host smart-39868f1e-899c-408d-a3a9-20aaf4b21746
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270891048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_hw_reset.270891048
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1413252424
Short name T103
Test name
Test status
Simulation time 237739331 ps
CPU time 2.76 seconds
Started Jul 29 04:55:15 PM PDT 24
Finished Jul 29 04:55:18 PM PDT 24
Peak memory 218480 kb
Host smart-9e9f7212-2f4f-4ee6-93e2-aacf81389c04
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413252424 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.1413252424
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.297896580
Short name T1108
Test name
Test status
Simulation time 89104980 ps
CPU time 1.94 seconds
Started Jul 29 04:54:52 PM PDT 24
Finished Jul 29 04:54:54 PM PDT 24
Peak memory 215412 kb
Host smart-9c92c307-7d15-403e-9029-0dececdaceb4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297896580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.297896580
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.130179617
Short name T1096
Test name
Test status
Simulation time 59353514 ps
CPU time 0.74 seconds
Started Jul 29 04:54:56 PM PDT 24
Finished Jul 29 04:54:57 PM PDT 24
Peak memory 204208 kb
Host smart-858d948b-b72e-4010-8d03-87d48740ab41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130179617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.130179617
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.3376523190
Short name T120
Test name
Test status
Simulation time 18950163 ps
CPU time 1.27 seconds
Started Jul 29 04:55:07 PM PDT 24
Finished Jul 29 04:55:08 PM PDT 24
Peak memory 215432 kb
Host smart-530c7551-0fe9-4177-884e-2216d8a38840
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376523190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.3376523190
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.2657110520
Short name T1130
Test name
Test status
Simulation time 19397783 ps
CPU time 0.64 seconds
Started Jul 29 04:54:55 PM PDT 24
Finished Jul 29 04:54:55 PM PDT 24
Peak memory 203792 kb
Host smart-4911ca1f-cd30-4442-a986-55415e213c6f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657110520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.2657110520
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2857982007
Short name T154
Test name
Test status
Simulation time 510141490 ps
CPU time 3.1 seconds
Started Jul 29 04:54:45 PM PDT 24
Finished Jul 29 04:54:48 PM PDT 24
Peak memory 215684 kb
Host smart-b8f66201-4a28-4fd9-97fe-7093d221507b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857982007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.2857982007
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.3109673063
Short name T1083
Test name
Test status
Simulation time 406483556 ps
CPU time 2.44 seconds
Started Jul 29 04:54:57 PM PDT 24
Finished Jul 29 04:54:59 PM PDT 24
Peak memory 215584 kb
Host smart-3f078fc7-0744-452d-bf7a-177bd6bab0ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109673063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.3
109673063
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2933235230
Short name T104
Test name
Test status
Simulation time 576326412 ps
CPU time 14.09 seconds
Started Jul 29 04:55:04 PM PDT 24
Finished Jul 29 04:55:18 PM PDT 24
Peak memory 215400 kb
Host smart-5492046c-3f9c-4a44-a29b-2e47c3374327
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933235230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.2933235230
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2525689580
Short name T1061
Test name
Test status
Simulation time 41145955 ps
CPU time 0.72 seconds
Started Jul 29 04:55:06 PM PDT 24
Finished Jul 29 04:55:06 PM PDT 24
Peak memory 203896 kb
Host smart-077c906e-1435-4008-83b5-1354187e69e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525689580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
2525689580
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.278944718
Short name T1078
Test name
Test status
Simulation time 143617888 ps
CPU time 0.67 seconds
Started Jul 29 04:55:06 PM PDT 24
Finished Jul 29 04:55:06 PM PDT 24
Peak memory 203896 kb
Host smart-e202c670-6cb3-42ac-91e2-6c4c49d69db5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278944718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.278944718
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.4198047755
Short name T1033
Test name
Test status
Simulation time 17330907 ps
CPU time 0.74 seconds
Started Jul 29 04:55:07 PM PDT 24
Finished Jul 29 04:55:08 PM PDT 24
Peak memory 203900 kb
Host smart-a6352d53-5ef0-4ebe-a8ef-30632e9cf5a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198047755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
4198047755
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.1158399209
Short name T1091
Test name
Test status
Simulation time 65970226 ps
CPU time 0.66 seconds
Started Jul 29 04:55:09 PM PDT 24
Finished Jul 29 04:55:10 PM PDT 24
Peak memory 203816 kb
Host smart-c0d71715-c92c-460f-8bd6-4a7335dd6156
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158399209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
1158399209
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1584533154
Short name T1046
Test name
Test status
Simulation time 18626583 ps
CPU time 0.8 seconds
Started Jul 29 04:55:15 PM PDT 24
Finished Jul 29 04:55:16 PM PDT 24
Peak memory 203928 kb
Host smart-6ded97cc-5a9a-413e-9af2-9c0ad1295349
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584533154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
1584533154
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.1088512567
Short name T1029
Test name
Test status
Simulation time 42040958 ps
CPU time 0.77 seconds
Started Jul 29 04:55:00 PM PDT 24
Finished Jul 29 04:55:01 PM PDT 24
Peak memory 203844 kb
Host smart-16e8e95c-b5e3-4289-8a0c-672b080f4a43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088512567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
1088512567
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.2327632683
Short name T1121
Test name
Test status
Simulation time 16420689 ps
CPU time 0.75 seconds
Started Jul 29 04:55:06 PM PDT 24
Finished Jul 29 04:55:06 PM PDT 24
Peak memory 203832 kb
Host smart-94249b64-66aa-4d68-adba-ca3022e7d262
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327632683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
2327632683
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.1892576202
Short name T1024
Test name
Test status
Simulation time 23920457 ps
CPU time 0.69 seconds
Started Jul 29 04:55:21 PM PDT 24
Finished Jul 29 04:55:27 PM PDT 24
Peak memory 203848 kb
Host smart-40f9f2af-fdf8-4dbc-9ea4-9f012a480b78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892576202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
1892576202
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.616850098
Short name T1077
Test name
Test status
Simulation time 45990397 ps
CPU time 0.74 seconds
Started Jul 29 04:55:39 PM PDT 24
Finished Jul 29 04:55:40 PM PDT 24
Peak memory 203988 kb
Host smart-5714d0c7-34b4-4dae-953b-d49fd7c99e8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616850098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.616850098
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.377825094
Short name T1101
Test name
Test status
Simulation time 50301473 ps
CPU time 0.71 seconds
Started Jul 29 04:55:07 PM PDT 24
Finished Jul 29 04:55:08 PM PDT 24
Peak memory 204156 kb
Host smart-0620b77e-2010-4c04-856f-f0435d3f55c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377825094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.377825094
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1694663554
Short name T1058
Test name
Test status
Simulation time 195719824 ps
CPU time 1.72 seconds
Started Jul 29 04:55:05 PM PDT 24
Finished Jul 29 04:55:07 PM PDT 24
Peak memory 215316 kb
Host smart-80849c53-3ecb-43fb-a01b-3845b03ecfb0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694663554 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.1694663554
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.2509041065
Short name T124
Test name
Test status
Simulation time 58313275 ps
CPU time 1.15 seconds
Started Jul 29 04:55:19 PM PDT 24
Finished Jul 29 04:55:20 PM PDT 24
Peak memory 207212 kb
Host smart-352cf02e-3c14-44a8-9f97-17ebbefe239e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509041065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.2
509041065
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.2873744441
Short name T1064
Test name
Test status
Simulation time 142591864 ps
CPU time 0.73 seconds
Started Jul 29 04:54:46 PM PDT 24
Finished Jul 29 04:54:46 PM PDT 24
Peak memory 204512 kb
Host smart-6c27b577-47e2-4844-a3d6-e45959b40fda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873744441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.2
873744441
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.3764455095
Short name T1140
Test name
Test status
Simulation time 315733125 ps
CPU time 4.09 seconds
Started Jul 29 04:55:22 PM PDT 24
Finished Jul 29 04:55:26 PM PDT 24
Peak memory 215416 kb
Host smart-2d8d9196-4552-433c-80d9-8334fa92852d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764455095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.3764455095
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.1959471241
Short name T1089
Test name
Test status
Simulation time 327909052 ps
CPU time 2.18 seconds
Started Jul 29 04:55:05 PM PDT 24
Finished Jul 29 04:55:07 PM PDT 24
Peak memory 215652 kb
Host smart-a53a4c3b-6c34-4354-9b8b-059b7093110a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959471241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.1
959471241
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3233742725
Short name T1122
Test name
Test status
Simulation time 84881277 ps
CPU time 2.46 seconds
Started Jul 29 04:55:11 PM PDT 24
Finished Jul 29 04:55:14 PM PDT 24
Peak memory 215688 kb
Host smart-79fb9173-100c-4a16-a187-757f413fc488
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233742725 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.3233742725
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.484850085
Short name T1123
Test name
Test status
Simulation time 107267667 ps
CPU time 2.56 seconds
Started Jul 29 04:55:04 PM PDT 24
Finished Jul 29 04:55:07 PM PDT 24
Peak memory 215412 kb
Host smart-74098a9f-3be5-4120-8b76-5c0470dddde0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484850085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.484850085
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.1440383515
Short name T1025
Test name
Test status
Simulation time 26846278 ps
CPU time 0.68 seconds
Started Jul 29 04:55:02 PM PDT 24
Finished Jul 29 04:55:03 PM PDT 24
Peak memory 203868 kb
Host smart-5a1fa049-758c-4b74-9b82-1dd5c6be7d37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440383515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.1
440383515
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.639897171
Short name T1026
Test name
Test status
Simulation time 160631925 ps
CPU time 3.92 seconds
Started Jul 29 04:55:24 PM PDT 24
Finished Jul 29 04:55:28 PM PDT 24
Peak memory 215420 kb
Host smart-939a6083-511a-45dd-9777-0471c4db20e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639897171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sp
i_device_same_csr_outstanding.639897171
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.1820708983
Short name T115
Test name
Test status
Simulation time 163402718 ps
CPU time 3.64 seconds
Started Jul 29 04:55:02 PM PDT 24
Finished Jul 29 04:55:06 PM PDT 24
Peak memory 215580 kb
Host smart-9a93963c-352f-4f78-8e53-a618b6ee35f4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820708983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.1
820708983
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.2261615558
Short name T1070
Test name
Test status
Simulation time 107025487 ps
CPU time 6.35 seconds
Started Jul 29 04:55:24 PM PDT 24
Finished Jul 29 04:55:31 PM PDT 24
Peak memory 215408 kb
Host smart-9d1250a5-4844-47d5-ae3c-f601fb6b79ad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261615558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.2261615558
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.438526750
Short name T1062
Test name
Test status
Simulation time 165611852 ps
CPU time 3.87 seconds
Started Jul 29 04:55:11 PM PDT 24
Finished Jul 29 04:55:16 PM PDT 24
Peak memory 217076 kb
Host smart-00b69e0f-e8d3-474a-873f-d4dcb3b83f47
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438526750 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.438526750
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.470731027
Short name T1103
Test name
Test status
Simulation time 40469727 ps
CPU time 1.4 seconds
Started Jul 29 04:55:07 PM PDT 24
Finished Jul 29 04:55:09 PM PDT 24
Peak memory 207284 kb
Host smart-aa6a9bb5-d8a6-4643-b851-652d5abd617e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470731027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.470731027
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.1313427558
Short name T1094
Test name
Test status
Simulation time 11481588 ps
CPU time 0.68 seconds
Started Jul 29 04:54:51 PM PDT 24
Finished Jul 29 04:54:52 PM PDT 24
Peak memory 203780 kb
Host smart-432c50d9-1aba-4a11-b8a5-d28ba984ee8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313427558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.1
313427558
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.3245030788
Short name T1095
Test name
Test status
Simulation time 614041312 ps
CPU time 4.01 seconds
Started Jul 29 04:55:04 PM PDT 24
Finished Jul 29 04:55:08 PM PDT 24
Peak memory 215304 kb
Host smart-a1c3a608-e511-43d0-b93f-ca6d2e3b0563
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245030788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.3245030788
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.1226299548
Short name T166
Test name
Test status
Simulation time 2546668614 ps
CPU time 18.49 seconds
Started Jul 29 04:54:58 PM PDT 24
Finished Jul 29 04:55:16 PM PDT 24
Peak memory 215604 kb
Host smart-9017559c-39ce-4e98-8236-afb204f9f782
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226299548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.1226299548
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2859603316
Short name T1131
Test name
Test status
Simulation time 692171225 ps
CPU time 3.62 seconds
Started Jul 29 04:55:14 PM PDT 24
Finished Jul 29 04:55:17 PM PDT 24
Peak memory 218712 kb
Host smart-387a13a8-e8b3-4ee0-89c4-21e4d10e66fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859603316 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.2859603316
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.33673455
Short name T1146
Test name
Test status
Simulation time 65214424 ps
CPU time 1.83 seconds
Started Jul 29 04:55:04 PM PDT 24
Finished Jul 29 04:55:06 PM PDT 24
Peak memory 207292 kb
Host smart-76dfae70-1917-4dfd-bb48-db2ec4402b66
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33673455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.33673455
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.180792655
Short name T1037
Test name
Test status
Simulation time 25204974 ps
CPU time 0.76 seconds
Started Jul 29 04:55:08 PM PDT 24
Finished Jul 29 04:55:14 PM PDT 24
Peak memory 203844 kb
Host smart-c440f2aa-4d46-4923-9c86-d555ff5fc813
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180792655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.180792655
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2488243558
Short name T1035
Test name
Test status
Simulation time 29357251 ps
CPU time 1.84 seconds
Started Jul 29 04:55:06 PM PDT 24
Finished Jul 29 04:55:08 PM PDT 24
Peak memory 215360 kb
Host smart-29cef30c-055d-4824-b0c4-b2fe8a62d75f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488243558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.2488243558
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.726631346
Short name T1074
Test name
Test status
Simulation time 694431191 ps
CPU time 4.45 seconds
Started Jul 29 04:55:05 PM PDT 24
Finished Jul 29 04:55:09 PM PDT 24
Peak memory 215496 kb
Host smart-c28f00d1-0d5a-412f-88c8-380031c4846f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726631346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.726631346
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.1409742311
Short name T167
Test name
Test status
Simulation time 209974759 ps
CPU time 7.03 seconds
Started Jul 29 04:55:00 PM PDT 24
Finished Jul 29 04:55:07 PM PDT 24
Peak memory 216184 kb
Host smart-7454a943-76e7-4ae6-b3c2-047e73a5d95b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409742311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.1409742311
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2649251918
Short name T1053
Test name
Test status
Simulation time 245459677 ps
CPU time 3.68 seconds
Started Jul 29 04:55:31 PM PDT 24
Finished Jul 29 04:55:35 PM PDT 24
Peak memory 217184 kb
Host smart-472d3e51-3492-4a08-a8bd-43b7888e5532
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649251918 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.2649251918
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.321901580
Short name T126
Test name
Test status
Simulation time 262659548 ps
CPU time 1.4 seconds
Started Jul 29 04:54:51 PM PDT 24
Finished Jul 29 04:54:53 PM PDT 24
Peak memory 207184 kb
Host smart-e74328a5-12cd-4e01-bef1-c4b5348df75b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321901580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.321901580
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2452027655
Short name T1132
Test name
Test status
Simulation time 15368576 ps
CPU time 0.73 seconds
Started Jul 29 04:55:07 PM PDT 24
Finished Jul 29 04:55:08 PM PDT 24
Peak memory 204184 kb
Host smart-160f7992-68e6-4ae2-ad9c-be4577af5e2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452027655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.2
452027655
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2569952687
Short name T1141
Test name
Test status
Simulation time 208720644 ps
CPU time 2.69 seconds
Started Jul 29 04:55:03 PM PDT 24
Finished Jul 29 04:55:06 PM PDT 24
Peak memory 215460 kb
Host smart-0ee6e876-4455-4a3d-81d1-932421b3a6bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569952687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.2569952687
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.89549054
Short name T1080
Test name
Test status
Simulation time 50333586 ps
CPU time 3.27 seconds
Started Jul 29 04:55:14 PM PDT 24
Finished Jul 29 04:55:17 PM PDT 24
Peak memory 215644 kb
Host smart-59a56a72-2f51-4351-9aa4-390e10fe50b1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89549054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.89549054
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.364763780
Short name T174
Test name
Test status
Simulation time 103355672 ps
CPU time 6.2 seconds
Started Jul 29 04:55:01 PM PDT 24
Finished Jul 29 04:55:07 PM PDT 24
Peak memory 215324 kb
Host smart-f9a58915-726b-4aed-881f-bc6aca8ba226
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364763780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_
tl_intg_err.364763780
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.3138878675
Short name T695
Test name
Test status
Simulation time 2057238239 ps
CPU time 5.87 seconds
Started Jul 29 05:03:19 PM PDT 24
Finished Jul 29 05:03:25 PM PDT 24
Peak memory 225184 kb
Host smart-ea632702-1d72-432b-8098-e8b8769f80dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138878675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.3138878675
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.2641758281
Short name T751
Test name
Test status
Simulation time 103980206 ps
CPU time 0.79 seconds
Started Jul 29 05:03:13 PM PDT 24
Finished Jul 29 05:03:14 PM PDT 24
Peak memory 207256 kb
Host smart-20d7fcd5-1621-47b5-b19e-a545bc88f5d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641758281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.2641758281
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.218175338
Short name T85
Test name
Test status
Simulation time 63990808687 ps
CPU time 211.86 seconds
Started Jul 29 05:03:18 PM PDT 24
Finished Jul 29 05:06:50 PM PDT 24
Peak memory 257980 kb
Host smart-e42b19c6-6372-4120-9e4d-a101208290bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218175338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.218175338
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.750139398
Short name T697
Test name
Test status
Simulation time 59469367484 ps
CPU time 224.38 seconds
Started Jul 29 05:03:17 PM PDT 24
Finished Jul 29 05:07:02 PM PDT 24
Peak memory 257372 kb
Host smart-07745ae2-4e2a-4d56-8476-a209ef84f256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750139398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.750139398
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.1985522565
Short name T593
Test name
Test status
Simulation time 2120582523 ps
CPU time 13.05 seconds
Started Jul 29 05:03:20 PM PDT 24
Finished Jul 29 05:03:33 PM PDT 24
Peak memory 237060 kb
Host smart-a4327a3c-19e4-4ca5-9b6f-c88f78c95155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985522565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.1985522565
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.1660634866
Short name T633
Test name
Test status
Simulation time 500826829 ps
CPU time 10.15 seconds
Started Jul 29 05:03:18 PM PDT 24
Finished Jul 29 05:03:29 PM PDT 24
Peak memory 237404 kb
Host smart-e1175bed-84ec-432a-a2cb-9fc914f71559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660634866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.1660634866
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.1956903093
Short name T200
Test name
Test status
Simulation time 58994698498 ps
CPU time 129.2 seconds
Started Jul 29 05:03:19 PM PDT 24
Finished Jul 29 05:05:28 PM PDT 24
Peak memory 255964 kb
Host smart-c841e249-4f2b-4aad-b395-f6b38a30c979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956903093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds
.1956903093
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_intercept.613387425
Short name T347
Test name
Test status
Simulation time 9532221951 ps
CPU time 20.03 seconds
Started Jul 29 05:03:19 PM PDT 24
Finished Jul 29 05:03:39 PM PDT 24
Peak memory 233552 kb
Host smart-39784107-2b88-4fd2-ab18-8d35e29b6358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613387425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.613387425
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.3267825009
Short name T378
Test name
Test status
Simulation time 4806434970 ps
CPU time 16.19 seconds
Started Jul 29 05:03:17 PM PDT 24
Finished Jul 29 05:03:33 PM PDT 24
Peak memory 233404 kb
Host smart-a4c4a12a-9b31-45f5-977e-5688e747575c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267825009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.3267825009
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.1125561544
Short name T984
Test name
Test status
Simulation time 5387527760 ps
CPU time 6.06 seconds
Started Jul 29 05:03:19 PM PDT 24
Finished Jul 29 05:03:25 PM PDT 24
Peak memory 233420 kb
Host smart-9f3d1962-4919-4997-98d7-f2f3b27c12c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125561544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.1125561544
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.1147130823
Short name T495
Test name
Test status
Simulation time 1383130381 ps
CPU time 3.93 seconds
Started Jul 29 05:03:23 PM PDT 24
Finished Jul 29 05:03:27 PM PDT 24
Peak memory 225216 kb
Host smart-47a20135-6272-4823-a525-f1e3a5ead5a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147130823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.1147130823
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.2885116119
Short name T610
Test name
Test status
Simulation time 1825769855 ps
CPU time 10.11 seconds
Started Jul 29 05:03:18 PM PDT 24
Finished Jul 29 05:03:28 PM PDT 24
Peak memory 219868 kb
Host smart-f834c667-210d-4205-a2d9-82ec9a9a358c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2885116119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.2885116119
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.4145417758
Short name T631
Test name
Test status
Simulation time 98708603 ps
CPU time 1.17 seconds
Started Jul 29 05:03:18 PM PDT 24
Finished Jul 29 05:03:20 PM PDT 24
Peak memory 207688 kb
Host smart-f5295db9-aad6-4b47-8974-3333356ac511
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145417758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.4145417758
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.35036987
Short name T605
Test name
Test status
Simulation time 872207319 ps
CPU time 11.56 seconds
Started Jul 29 05:03:14 PM PDT 24
Finished Jul 29 05:03:25 PM PDT 24
Peak memory 216964 kb
Host smart-8be731f6-d536-4fc2-b9b9-1d2e08771d2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35036987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.35036987
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.1490968508
Short name T649
Test name
Test status
Simulation time 13745912953 ps
CPU time 14.61 seconds
Started Jul 29 05:03:12 PM PDT 24
Finished Jul 29 05:03:27 PM PDT 24
Peak memory 217040 kb
Host smart-852f439a-5542-467f-aca9-00c21e4f67e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490968508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.1490968508
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.2516061448
Short name T521
Test name
Test status
Simulation time 119360949 ps
CPU time 0.67 seconds
Started Jul 29 05:03:19 PM PDT 24
Finished Jul 29 05:03:19 PM PDT 24
Peak memory 206064 kb
Host smart-994306b2-751d-459c-9539-a6b58acb7ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516061448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.2516061448
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.1895089071
Short name T504
Test name
Test status
Simulation time 84150739 ps
CPU time 0.88 seconds
Started Jul 29 05:03:18 PM PDT 24
Finished Jul 29 05:03:19 PM PDT 24
Peak memory 206628 kb
Host smart-77878e91-3eb4-472b-b5d5-fdbb08f1b09b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895089071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.1895089071
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.2218412313
Short name T757
Test name
Test status
Simulation time 899710979 ps
CPU time 9.15 seconds
Started Jul 29 05:03:18 PM PDT 24
Finished Jul 29 05:03:27 PM PDT 24
Peak memory 241208 kb
Host smart-4dd0e911-09b0-4ebc-8f0c-816701013740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218412313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.2218412313
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.3937261152
Short name T795
Test name
Test status
Simulation time 27302203 ps
CPU time 0.72 seconds
Started Jul 29 05:03:23 PM PDT 24
Finished Jul 29 05:03:24 PM PDT 24
Peak memory 205812 kb
Host smart-7f10f5b7-dce7-43ed-b6ae-1aa0819bbdd2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937261152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.3
937261152
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.2028301186
Short name T321
Test name
Test status
Simulation time 480706584 ps
CPU time 5.31 seconds
Started Jul 29 05:03:25 PM PDT 24
Finished Jul 29 05:03:30 PM PDT 24
Peak memory 225240 kb
Host smart-c1e445ec-69c9-42da-b8d2-2519467670d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028301186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.2028301186
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.308869724
Short name T763
Test name
Test status
Simulation time 15099074 ps
CPU time 0.78 seconds
Started Jul 29 05:03:23 PM PDT 24
Finished Jul 29 05:03:24 PM PDT 24
Peak memory 206324 kb
Host smart-2a2021b1-6e2a-48d3-ae9f-a9bc21614c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308869724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.308869724
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.2288415338
Short name T712
Test name
Test status
Simulation time 65139634 ps
CPU time 0.77 seconds
Started Jul 29 05:03:27 PM PDT 24
Finished Jul 29 05:03:28 PM PDT 24
Peak memory 216460 kb
Host smart-98ef0df5-ff2b-46bd-8d26-b60a558c0ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288415338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.2288415338
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.3249280125
Short name T817
Test name
Test status
Simulation time 18029256295 ps
CPU time 217.39 seconds
Started Jul 29 05:03:27 PM PDT 24
Finished Jul 29 05:07:04 PM PDT 24
Peak memory 257564 kb
Host smart-1345ba11-51d4-4f6d-afc1-a6e6c8e84350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249280125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.3249280125
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.2787889555
Short name T640
Test name
Test status
Simulation time 25556874140 ps
CPU time 241.38 seconds
Started Jul 29 05:03:27 PM PDT 24
Finished Jul 29 05:07:28 PM PDT 24
Peak memory 267660 kb
Host smart-c49cc320-6a78-4540-88a1-08f67875a25e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787889555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.2787889555
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.1295603865
Short name T276
Test name
Test status
Simulation time 142112040268 ps
CPU time 471.45 seconds
Started Jul 29 05:03:23 PM PDT 24
Finished Jul 29 05:11:15 PM PDT 24
Peak memory 257596 kb
Host smart-bdd852fb-882b-4201-aa1f-255c1ed043a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295603865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds
.1295603865
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/1.spi_device_intercept.2414657098
Short name T132
Test name
Test status
Simulation time 990035802 ps
CPU time 14.3 seconds
Started Jul 29 05:03:26 PM PDT 24
Finished Jul 29 05:03:41 PM PDT 24
Peak memory 233444 kb
Host smart-d6349beb-d3dc-4f84-a2d9-eb013a762928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414657098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.2414657098
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.2690566733
Short name T383
Test name
Test status
Simulation time 65205032 ps
CPU time 2.49 seconds
Started Jul 29 05:03:24 PM PDT 24
Finished Jul 29 05:03:27 PM PDT 24
Peak memory 233384 kb
Host smart-0b9b588b-3ad1-43dd-8e9f-715e2abb5a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690566733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.2690566733
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.1514707840
Short name T652
Test name
Test status
Simulation time 14404353 ps
CPU time 1.03 seconds
Started Jul 29 05:03:19 PM PDT 24
Finished Jul 29 05:03:20 PM PDT 24
Peak memory 218520 kb
Host smart-2fe4f8f0-1e45-42eb-a5b7-c0a25aad2067
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514707840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.spi_device_mem_parity.1514707840
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.1833719219
Short name T54
Test name
Test status
Simulation time 6846181116 ps
CPU time 21.36 seconds
Started Jul 29 05:03:25 PM PDT 24
Finished Jul 29 05:03:47 PM PDT 24
Peak memory 241488 kb
Host smart-5e1609e3-3057-439e-a82f-ede15bded21f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833719219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.1833719219
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.330926125
Short name T991
Test name
Test status
Simulation time 930684556 ps
CPU time 2.64 seconds
Started Jul 29 05:03:18 PM PDT 24
Finished Jul 29 05:03:20 PM PDT 24
Peak memory 225132 kb
Host smart-6204e86f-18b6-4d2e-9e35-5f651c2b0ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330926125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.330926125
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.651111143
Short name T644
Test name
Test status
Simulation time 1352710404 ps
CPU time 9.41 seconds
Started Jul 29 05:03:25 PM PDT 24
Finished Jul 29 05:03:34 PM PDT 24
Peak memory 220364 kb
Host smart-4ed4a204-c6ba-41a9-929b-46578c7194b4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=651111143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_direc
t.651111143
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.1368573584
Short name T78
Test name
Test status
Simulation time 157169184 ps
CPU time 1.18 seconds
Started Jul 29 05:03:23 PM PDT 24
Finished Jul 29 05:03:24 PM PDT 24
Peak memory 235464 kb
Host smart-ac708e2f-25c6-4057-b038-b31f3cc64acf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368573584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.1368573584
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.2399830397
Short name T563
Test name
Test status
Simulation time 73118018 ps
CPU time 1.22 seconds
Started Jul 29 05:03:23 PM PDT 24
Finished Jul 29 05:03:25 PM PDT 24
Peak memory 207376 kb
Host smart-d2b158c0-d9a9-4d05-be74-f6eeb6bbba07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399830397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.2399830397
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.3670443709
Short name T332
Test name
Test status
Simulation time 62339788 ps
CPU time 0.69 seconds
Started Jul 29 05:03:18 PM PDT 24
Finished Jul 29 05:03:19 PM PDT 24
Peak memory 206092 kb
Host smart-eb1b5767-0a88-43fb-abb2-9566ac1fdff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670443709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.3670443709
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.1832975200
Short name T954
Test name
Test status
Simulation time 55180440 ps
CPU time 0.97 seconds
Started Jul 29 05:03:19 PM PDT 24
Finished Jul 29 05:03:20 PM PDT 24
Peak memory 207420 kb
Host smart-09e2e40b-40fb-4e2c-be30-b22578925354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832975200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.1832975200
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.3628161644
Short name T327
Test name
Test status
Simulation time 87173684 ps
CPU time 0.98 seconds
Started Jul 29 05:03:17 PM PDT 24
Finished Jul 29 05:03:19 PM PDT 24
Peak memory 207632 kb
Host smart-e96a2e20-16bd-4e15-af6d-d938cebd8137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628161644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.3628161644
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.1307773489
Short name T4
Test name
Test status
Simulation time 550488158 ps
CPU time 2.53 seconds
Started Jul 29 05:03:27 PM PDT 24
Finished Jul 29 05:03:29 PM PDT 24
Peak memory 225192 kb
Host smart-6356e2af-7864-4b84-ae7d-677cee893ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307773489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.1307773489
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.3429315402
Short name T664
Test name
Test status
Simulation time 13205980 ps
CPU time 0.69 seconds
Started Jul 29 05:04:14 PM PDT 24
Finished Jul 29 05:04:15 PM PDT 24
Peak memory 206168 kb
Host smart-6db8014a-fe5f-4c45-ae7c-d2ef731a01e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429315402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
3429315402
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.2937947853
Short name T835
Test name
Test status
Simulation time 356635216 ps
CPU time 2.61 seconds
Started Jul 29 05:04:08 PM PDT 24
Finished Jul 29 05:04:10 PM PDT 24
Peak memory 225176 kb
Host smart-2a1e79e9-11c8-423c-a7a7-11e3f6f1ee26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937947853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.2937947853
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.2262175839
Short name T766
Test name
Test status
Simulation time 157725823 ps
CPU time 0.75 seconds
Started Jul 29 05:04:00 PM PDT 24
Finished Jul 29 05:04:00 PM PDT 24
Peak memory 207436 kb
Host smart-ca040f6f-aa65-4662-bb1c-dd96ca425e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262175839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.2262175839
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.99925533
Short name T195
Test name
Test status
Simulation time 79828388957 ps
CPU time 96.95 seconds
Started Jul 29 05:04:07 PM PDT 24
Finished Jul 29 05:05:44 PM PDT 24
Peak memory 249856 kb
Host smart-9cb22379-015f-42f3-8b6b-8061453f716c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99925533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.99925533
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.3050215889
Short name T497
Test name
Test status
Simulation time 12258610935 ps
CPU time 125.47 seconds
Started Jul 29 05:04:05 PM PDT 24
Finished Jul 29 05:06:11 PM PDT 24
Peak memory 253492 kb
Host smart-2b578ee6-6865-49bc-aeb5-41dd67f194a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050215889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.3050215889
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.3630103107
Short name T29
Test name
Test status
Simulation time 8248935095 ps
CPU time 83.07 seconds
Started Jul 29 05:04:06 PM PDT 24
Finished Jul 29 05:05:29 PM PDT 24
Peak memory 249892 kb
Host smart-f1bf2bfb-3064-4b69-8e82-0ffdfd02a498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630103107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.3630103107
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.3208107067
Short name T724
Test name
Test status
Simulation time 1192783389 ps
CPU time 12.61 seconds
Started Jul 29 05:04:08 PM PDT 24
Finished Jul 29 05:04:21 PM PDT 24
Peak memory 235560 kb
Host smart-d7729385-68db-403f-acce-49139303f73d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208107067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.3208107067
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.1213267165
Short name T872
Test name
Test status
Simulation time 5376017366 ps
CPU time 63.79 seconds
Started Jul 29 05:04:06 PM PDT 24
Finished Jul 29 05:05:10 PM PDT 24
Peak memory 249912 kb
Host smart-17e85027-0d8b-4909-8a6d-84e5407388a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213267165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmd
s.1213267165
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/10.spi_device_intercept.864816263
Short name T549
Test name
Test status
Simulation time 117057126 ps
CPU time 3.84 seconds
Started Jul 29 05:04:07 PM PDT 24
Finished Jul 29 05:04:11 PM PDT 24
Peak memory 233412 kb
Host smart-bb70b184-da8b-43a9-9bbd-4756b9e70007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864816263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.864816263
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.2338064229
Short name T1004
Test name
Test status
Simulation time 988572117 ps
CPU time 13.03 seconds
Started Jul 29 05:04:06 PM PDT 24
Finished Jul 29 05:04:19 PM PDT 24
Peak memory 233488 kb
Host smart-e097b625-2994-4525-81b3-8a1ca70e9007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338064229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.2338064229
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.2612039138
Short name T43
Test name
Test status
Simulation time 89126043 ps
CPU time 1.11 seconds
Started Jul 29 05:04:05 PM PDT 24
Finished Jul 29 05:04:06 PM PDT 24
Peak memory 217116 kb
Host smart-fa48c32b-8581-46f9-9ec2-0179aa6bc38e
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612039138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.spi_device_mem_parity.2612039138
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.527045872
Short name T273
Test name
Test status
Simulation time 16708122687 ps
CPU time 24.23 seconds
Started Jul 29 05:04:06 PM PDT 24
Finished Jul 29 05:04:31 PM PDT 24
Peak memory 233344 kb
Host smart-446c93aa-60f0-4e47-8c43-2bbc713a753f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527045872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swap
.527045872
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.2335236015
Short name T455
Test name
Test status
Simulation time 1809798692 ps
CPU time 10.72 seconds
Started Jul 29 05:04:09 PM PDT 24
Finished Jul 29 05:04:20 PM PDT 24
Peak memory 233408 kb
Host smart-208b5c49-07a6-47b2-9304-d7fabe4a18b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335236015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.2335236015
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.474680737
Short name T616
Test name
Test status
Simulation time 331740861 ps
CPU time 4.62 seconds
Started Jul 29 05:04:05 PM PDT 24
Finished Jul 29 05:04:10 PM PDT 24
Peak memory 223632 kb
Host smart-49d1a8a3-816d-4014-85c2-4268cd2c2597
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=474680737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dire
ct.474680737
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.3956463631
Short name T206
Test name
Test status
Simulation time 43520333048 ps
CPU time 470.99 seconds
Started Jul 29 05:04:06 PM PDT 24
Finished Jul 29 05:11:57 PM PDT 24
Peak memory 281936 kb
Host smart-8fda02e3-d364-40ec-961d-425daaa2918c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956463631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.3956463631
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.173455417
Short name T309
Test name
Test status
Simulation time 7277274602 ps
CPU time 19.57 seconds
Started Jul 29 05:04:08 PM PDT 24
Finished Jul 29 05:04:27 PM PDT 24
Peak memory 220576 kb
Host smart-f93ab49f-849d-494e-a7dd-291297b8d7cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173455417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.173455417
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.239286506
Short name T568
Test name
Test status
Simulation time 40505232474 ps
CPU time 25 seconds
Started Jul 29 05:04:06 PM PDT 24
Finished Jul 29 05:04:31 PM PDT 24
Peak memory 217100 kb
Host smart-8acd94dc-6450-4d90-98e7-59c3188aa6c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239286506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.239286506
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.2500842966
Short name T45
Test name
Test status
Simulation time 46758784 ps
CPU time 1.34 seconds
Started Jul 29 05:04:06 PM PDT 24
Finished Jul 29 05:04:08 PM PDT 24
Peak memory 217052 kb
Host smart-2861c661-3f85-4a3b-8998-3dc0f45aefd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500842966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.2500842966
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.3212288998
Short name T950
Test name
Test status
Simulation time 161398763 ps
CPU time 0.87 seconds
Started Jul 29 05:04:06 PM PDT 24
Finished Jul 29 05:04:07 PM PDT 24
Peak memory 207556 kb
Host smart-ddb1d72a-720b-4b13-9fb9-502eeb0f0be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212288998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.3212288998
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.3923915300
Short name T465
Test name
Test status
Simulation time 40494901991 ps
CPU time 11.71 seconds
Started Jul 29 05:04:06 PM PDT 24
Finished Jul 29 05:04:18 PM PDT 24
Peak memory 225244 kb
Host smart-25550487-b64d-42f5-959e-3f8825b39acf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923915300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.3923915300
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.3182710781
Short name T624
Test name
Test status
Simulation time 41557219 ps
CPU time 0.73 seconds
Started Jul 29 05:04:12 PM PDT 24
Finished Jul 29 05:04:13 PM PDT 24
Peak memory 206228 kb
Host smart-70381fcc-4772-4a27-acfc-474b263945f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182710781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
3182710781
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.1465324437
Short name T851
Test name
Test status
Simulation time 48294583 ps
CPU time 0.77 seconds
Started Jul 29 05:04:13 PM PDT 24
Finished Jul 29 05:04:13 PM PDT 24
Peak memory 207040 kb
Host smart-f9e5264c-46dd-48ca-b44d-0ebfa9c72b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465324437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.1465324437
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.1349527921
Short name T242
Test name
Test status
Simulation time 4376378008 ps
CPU time 76.73 seconds
Started Jul 29 05:04:14 PM PDT 24
Finished Jul 29 05:05:31 PM PDT 24
Peak memory 268868 kb
Host smart-b2cef02e-fdcd-473a-bad1-8a8094b112f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349527921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.1349527921
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.92416475
Short name T110
Test name
Test status
Simulation time 9080696219 ps
CPU time 92.13 seconds
Started Jul 29 05:04:15 PM PDT 24
Finished Jul 29 05:05:47 PM PDT 24
Peak memory 241556 kb
Host smart-16e48d05-914d-4d24-af5f-14e72b520c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92416475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idle.92416475
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.4014038177
Short name T911
Test name
Test status
Simulation time 407833456 ps
CPU time 10.97 seconds
Started Jul 29 05:04:14 PM PDT 24
Finished Jul 29 05:04:25 PM PDT 24
Peak memory 234740 kb
Host smart-95fb063a-ff11-4ed0-a7e7-104c293a7559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014038177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.4014038177
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.3157288273
Short name T99
Test name
Test status
Simulation time 66532384745 ps
CPU time 171.72 seconds
Started Jul 29 05:04:14 PM PDT 24
Finished Jul 29 05:07:06 PM PDT 24
Peak memory 254648 kb
Host smart-6e70a5fd-4631-4038-b2e8-d0403537bf6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157288273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmd
s.3157288273
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_intercept.1932187689
Short name T718
Test name
Test status
Simulation time 283945625 ps
CPU time 3.2 seconds
Started Jul 29 05:04:16 PM PDT 24
Finished Jul 29 05:04:19 PM PDT 24
Peak memory 225252 kb
Host smart-8daee233-5a89-4f11-8dd8-f186a270d7f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932187689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.1932187689
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.1977444020
Short name T217
Test name
Test status
Simulation time 13598317791 ps
CPU time 68.32 seconds
Started Jul 29 05:04:15 PM PDT 24
Finished Jul 29 05:05:23 PM PDT 24
Peak memory 233500 kb
Host smart-1f9564fd-c69c-4334-a52c-3004b0c6274d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977444020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.1977444020
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.4025682662
Short name T484
Test name
Test status
Simulation time 34749894 ps
CPU time 1.13 seconds
Started Jul 29 05:04:15 PM PDT 24
Finished Jul 29 05:04:16 PM PDT 24
Peak memory 217220 kb
Host smart-e6329405-aece-4dc3-9e25-91acc13e1ac4
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025682662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.spi_device_mem_parity.4025682662
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.1105387371
Short name T249
Test name
Test status
Simulation time 180242372 ps
CPU time 3.02 seconds
Started Jul 29 05:04:15 PM PDT 24
Finished Jul 29 05:04:18 PM PDT 24
Peak memory 233388 kb
Host smart-6efaac09-ec06-4142-b3b7-3041b199945b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105387371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.1105387371
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.15514697
Short name T471
Test name
Test status
Simulation time 5243871911 ps
CPU time 9.67 seconds
Started Jul 29 05:04:12 PM PDT 24
Finished Jul 29 05:04:22 PM PDT 24
Peak memory 225172 kb
Host smart-f0c2c0fc-be73-48c1-b567-dc75ece484d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15514697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.15514697
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.1001098899
Short name T873
Test name
Test status
Simulation time 199407050 ps
CPU time 6.05 seconds
Started Jul 29 05:04:13 PM PDT 24
Finished Jul 29 05:04:19 PM PDT 24
Peak memory 222664 kb
Host smart-fae7ac68-9352-4a7b-bbbc-b5bd3e29e6f2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1001098899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.1001098899
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.1009869182
Short name T692
Test name
Test status
Simulation time 33626566540 ps
CPU time 77.74 seconds
Started Jul 29 05:04:12 PM PDT 24
Finished Jul 29 05:05:29 PM PDT 24
Peak memory 251324 kb
Host smart-54b7a971-6473-4668-9642-396448015d04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009869182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.1009869182
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.2213252803
Short name T788
Test name
Test status
Simulation time 38184667172 ps
CPU time 30.05 seconds
Started Jul 29 05:04:12 PM PDT 24
Finished Jul 29 05:04:42 PM PDT 24
Peak memory 217088 kb
Host smart-2767eb37-427e-4a70-bc0f-57a7dd04c4c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213252803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.2213252803
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.493806309
Short name T500
Test name
Test status
Simulation time 4598098445 ps
CPU time 7.97 seconds
Started Jul 29 05:04:13 PM PDT 24
Finished Jul 29 05:04:21 PM PDT 24
Peak memory 217020 kb
Host smart-6fbfa41b-fbb1-43d1-ab3f-bb890ee542a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493806309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.493806309
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.3276190559
Short name T490
Test name
Test status
Simulation time 66704377 ps
CPU time 0.68 seconds
Started Jul 29 05:04:13 PM PDT 24
Finished Jul 29 05:04:14 PM PDT 24
Peak memory 206108 kb
Host smart-cb007dad-4163-4a87-843e-939a9d3fb7f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276190559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.3276190559
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.3161909390
Short name T329
Test name
Test status
Simulation time 72813055 ps
CPU time 0.93 seconds
Started Jul 29 05:04:16 PM PDT 24
Finished Jul 29 05:04:17 PM PDT 24
Peak memory 206612 kb
Host smart-b3dd3deb-0566-426a-b16f-125973b2e25c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161909390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.3161909390
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.2831774477
Short name T65
Test name
Test status
Simulation time 4895435671 ps
CPU time 13.07 seconds
Started Jul 29 05:04:14 PM PDT 24
Finished Jul 29 05:04:27 PM PDT 24
Peak memory 233524 kb
Host smart-6c8cfbc2-0c5a-4443-bf18-7d913e63ea60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831774477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.2831774477
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.710392971
Short name T807
Test name
Test status
Simulation time 28198030 ps
CPU time 0.68 seconds
Started Jul 29 05:04:19 PM PDT 24
Finished Jul 29 05:04:20 PM PDT 24
Peak memory 206148 kb
Host smart-a057772f-3802-4f31-95f8-9e3e7ec38397
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710392971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.710392971
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.2261557621
Short name T412
Test name
Test status
Simulation time 2732544830 ps
CPU time 16.53 seconds
Started Jul 29 05:04:19 PM PDT 24
Finished Jul 29 05:04:36 PM PDT 24
Peak memory 225268 kb
Host smart-2b881ed2-dd86-4676-93d9-68b1090aea60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261557621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.2261557621
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.2492427357
Short name T569
Test name
Test status
Simulation time 31403794 ps
CPU time 0.77 seconds
Started Jul 29 05:04:19 PM PDT 24
Finished Jul 29 05:04:20 PM PDT 24
Peak memory 207432 kb
Host smart-e982afa5-ae84-4be5-8a59-6a5308fea34c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492427357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.2492427357
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.3500472277
Short name T10
Test name
Test status
Simulation time 102298364633 ps
CPU time 82.06 seconds
Started Jul 29 05:04:17 PM PDT 24
Finished Jul 29 05:05:39 PM PDT 24
Peak memory 240820 kb
Host smart-28d31c6f-52e6-4436-9472-9521eb2cca1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500472277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.3500472277
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.1174784013
Short name T194
Test name
Test status
Simulation time 21310548439 ps
CPU time 117.63 seconds
Started Jul 29 05:04:20 PM PDT 24
Finished Jul 29 05:06:18 PM PDT 24
Peak memory 257488 kb
Host smart-d0730d06-bb31-4b01-baae-58123c435551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174784013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.1174784013
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.720132889
Short name T1018
Test name
Test status
Simulation time 405383539 ps
CPU time 3.29 seconds
Started Jul 29 05:04:21 PM PDT 24
Finished Jul 29 05:04:25 PM PDT 24
Peak memory 225216 kb
Host smart-611fa83b-cc3c-4bc0-9734-9601f148609a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720132889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.720132889
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.2266525522
Short name T6
Test name
Test status
Simulation time 23298995 ps
CPU time 0.74 seconds
Started Jul 29 05:04:20 PM PDT 24
Finished Jul 29 05:04:21 PM PDT 24
Peak memory 216432 kb
Host smart-b193c99b-d235-439f-bee1-e7f95fc21155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266525522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmd
s.2266525522
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_intercept.1526630390
Short name T658
Test name
Test status
Simulation time 597692114 ps
CPU time 4.51 seconds
Started Jul 29 05:04:20 PM PDT 24
Finished Jul 29 05:04:25 PM PDT 24
Peak memory 225208 kb
Host smart-16738dbe-86d5-4cd0-a2fe-7f9f68be956d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526630390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.1526630390
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.252202652
Short name T257
Test name
Test status
Simulation time 2306939274 ps
CPU time 19.99 seconds
Started Jul 29 05:04:24 PM PDT 24
Finished Jul 29 05:04:44 PM PDT 24
Peak memory 233536 kb
Host smart-90ac7d21-de56-4670-a6a6-1a008dd31980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252202652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.252202652
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.1436256922
Short name T981
Test name
Test status
Simulation time 17492869 ps
CPU time 1.08 seconds
Started Jul 29 05:04:20 PM PDT 24
Finished Jul 29 05:04:21 PM PDT 24
Peak memory 217144 kb
Host smart-c4557c11-cf77-4203-abec-3f5080c2d325
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436256922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.spi_device_mem_parity.1436256922
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.216794429
Short name T626
Test name
Test status
Simulation time 8591628536 ps
CPU time 11.11 seconds
Started Jul 29 05:04:20 PM PDT 24
Finished Jul 29 05:04:31 PM PDT 24
Peak memory 238532 kb
Host smart-d7632696-4a25-4fa2-b7a2-b60800981b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216794429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swap
.216794429
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.4245646673
Short name T611
Test name
Test status
Simulation time 4650822997 ps
CPU time 9.93 seconds
Started Jul 29 05:04:20 PM PDT 24
Finished Jul 29 05:04:30 PM PDT 24
Peak memory 225160 kb
Host smart-6026c3dc-51a5-4cd8-9d19-3862e0ed1013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245646673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.4245646673
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.1648233328
Short name T777
Test name
Test status
Simulation time 2120529536 ps
CPU time 6.76 seconds
Started Jul 29 05:04:25 PM PDT 24
Finished Jul 29 05:04:32 PM PDT 24
Peak memory 219360 kb
Host smart-7757ea48-f1f6-40fb-8fe1-76c0b83a2e90
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1648233328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.1648233328
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.415387245
Short name T825
Test name
Test status
Simulation time 194005136 ps
CPU time 0.99 seconds
Started Jul 29 05:04:22 PM PDT 24
Finished Jul 29 05:04:24 PM PDT 24
Peak memory 207204 kb
Host smart-d22c6d18-4e5d-4c46-9640-8c16bf5c51d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415387245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stres
s_all.415387245
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.533257191
Short name T641
Test name
Test status
Simulation time 1685426190 ps
CPU time 3.06 seconds
Started Jul 29 05:04:18 PM PDT 24
Finished Jul 29 05:04:22 PM PDT 24
Peak memory 216952 kb
Host smart-c5fd85f9-fc25-43da-8334-732bcd2b070c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533257191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.533257191
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.2812299926
Short name T1
Test name
Test status
Simulation time 13749392 ps
CPU time 0.72 seconds
Started Jul 29 05:04:18 PM PDT 24
Finished Jul 29 05:04:19 PM PDT 24
Peak memory 206184 kb
Host smart-c34d9132-3d96-46bd-8c12-81fb98540b6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812299926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.2812299926
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.2610861901
Short name T772
Test name
Test status
Simulation time 58967111 ps
CPU time 3.26 seconds
Started Jul 29 05:04:20 PM PDT 24
Finished Jul 29 05:04:24 PM PDT 24
Peak memory 217052 kb
Host smart-ad175506-54c5-4b9a-9aeb-e60fb859c27e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610861901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.2610861901
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.2835446609
Short name T990
Test name
Test status
Simulation time 31515418 ps
CPU time 0.83 seconds
Started Jul 29 05:04:18 PM PDT 24
Finished Jul 29 05:04:19 PM PDT 24
Peak memory 206576 kb
Host smart-c0ddfa73-2b7c-470e-8d37-77d8e17861a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835446609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.2835446609
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.2512235216
Short name T938
Test name
Test status
Simulation time 195851590 ps
CPU time 3.29 seconds
Started Jul 29 05:04:24 PM PDT 24
Finished Jul 29 05:04:28 PM PDT 24
Peak memory 225272 kb
Host smart-58a11318-1799-4dd1-9c14-785aea7fef0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512235216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.2512235216
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.1291960426
Short name T572
Test name
Test status
Simulation time 20781816 ps
CPU time 0.83 seconds
Started Jul 29 05:04:25 PM PDT 24
Finished Jul 29 05:04:26 PM PDT 24
Peak memory 205840 kb
Host smart-3846dc23-3bc7-42e2-b44f-02248175406a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291960426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
1291960426
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.1541935174
Short name T678
Test name
Test status
Simulation time 416404847 ps
CPU time 5.14 seconds
Started Jul 29 05:04:21 PM PDT 24
Finished Jul 29 05:04:27 PM PDT 24
Peak memory 225124 kb
Host smart-e6e6d176-87c7-4752-8a7f-0c885d198e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541935174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.1541935174
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.1573115039
Short name T875
Test name
Test status
Simulation time 65956826 ps
CPU time 0.78 seconds
Started Jul 29 05:04:20 PM PDT 24
Finished Jul 29 05:04:21 PM PDT 24
Peak memory 207420 kb
Host smart-0b105f25-4440-423d-bbee-863a0f118390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573115039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.1573115039
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.1248004718
Short name T810
Test name
Test status
Simulation time 4726400946 ps
CPU time 40.39 seconds
Started Jul 29 05:04:26 PM PDT 24
Finished Jul 29 05:05:07 PM PDT 24
Peak memory 252440 kb
Host smart-20931e82-1b3a-4c8b-b304-b800af31b08b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248004718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.1248004718
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.2217905333
Short name T514
Test name
Test status
Simulation time 61092208946 ps
CPU time 143.86 seconds
Started Jul 29 05:04:25 PM PDT 24
Finished Jul 29 05:06:49 PM PDT 24
Peak memory 241620 kb
Host smart-85206b4b-b133-4677-b52f-d929a5803791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217905333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.2217905333
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.582934126
Short name T293
Test name
Test status
Simulation time 7901268855 ps
CPU time 106.71 seconds
Started Jul 29 05:04:26 PM PDT 24
Finished Jul 29 05:06:13 PM PDT 24
Peak memory 249924 kb
Host smart-efffe2c5-39d2-42d0-9aca-cf6c5229fbd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582934126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idle
.582934126
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.1960541840
Short name T818
Test name
Test status
Simulation time 515163927 ps
CPU time 6.76 seconds
Started Jul 29 05:04:18 PM PDT 24
Finished Jul 29 05:04:24 PM PDT 24
Peak memory 234252 kb
Host smart-8295bc5a-faad-46ed-9884-9d25fa78bce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960541840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.1960541840
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.2890304246
Short name T101
Test name
Test status
Simulation time 12865742511 ps
CPU time 80.26 seconds
Started Jul 29 05:04:24 PM PDT 24
Finished Jul 29 05:05:45 PM PDT 24
Peak memory 249944 kb
Host smart-419b911b-b902-4ef0-9039-eed2dc6f95d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890304246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmd
s.2890304246
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/13.spi_device_intercept.1035815071
Short name T680
Test name
Test status
Simulation time 9068648943 ps
CPU time 7.12 seconds
Started Jul 29 05:04:21 PM PDT 24
Finished Jul 29 05:04:28 PM PDT 24
Peak memory 233424 kb
Host smart-09cce30c-7be2-4b03-b2a1-bb3f022a9255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035815071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.1035815071
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.2072838565
Short name T975
Test name
Test status
Simulation time 20610388 ps
CPU time 1.09 seconds
Started Jul 29 05:04:23 PM PDT 24
Finished Jul 29 05:04:24 PM PDT 24
Peak memory 217196 kb
Host smart-b9dd101f-27fe-402c-b0b8-8798c531965e
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072838565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.spi_device_mem_parity.2072838565
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.218800060
Short name T745
Test name
Test status
Simulation time 4024664288 ps
CPU time 13.26 seconds
Started Jul 29 05:04:17 PM PDT 24
Finished Jul 29 05:04:30 PM PDT 24
Peak memory 241344 kb
Host smart-86228ea2-eff1-4b9f-81a6-3a165de0f231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218800060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swap
.218800060
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.71461238
Short name T717
Test name
Test status
Simulation time 41384032349 ps
CPU time 12.65 seconds
Started Jul 29 05:04:23 PM PDT 24
Finished Jul 29 05:04:36 PM PDT 24
Peak memory 241336 kb
Host smart-17ae27a9-c2e1-4ed5-9b71-d5a7abd33a5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71461238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.71461238
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.3303241996
Short name T149
Test name
Test status
Simulation time 3496046284 ps
CPU time 10.96 seconds
Started Jul 29 05:04:19 PM PDT 24
Finished Jul 29 05:04:30 PM PDT 24
Peak memory 223352 kb
Host smart-a4de7723-f4c5-4008-9d75-965adc833d52
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3303241996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.3303241996
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.4278199959
Short name T397
Test name
Test status
Simulation time 1061287663 ps
CPU time 16.46 seconds
Started Jul 29 05:04:21 PM PDT 24
Finished Jul 29 05:04:38 PM PDT 24
Peak memory 216888 kb
Host smart-be08f470-16ae-434a-bc1f-d317cc18e33f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278199959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.4278199959
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.3819504375
Short name T528
Test name
Test status
Simulation time 24161338 ps
CPU time 1.36 seconds
Started Jul 29 05:04:20 PM PDT 24
Finished Jul 29 05:04:22 PM PDT 24
Peak memory 216912 kb
Host smart-146456e2-eb3b-48a5-b6c0-d4679cb8294f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819504375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.3819504375
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.3494385605
Short name T366
Test name
Test status
Simulation time 253379318 ps
CPU time 0.91 seconds
Started Jul 29 05:04:18 PM PDT 24
Finished Jul 29 05:04:19 PM PDT 24
Peak memory 206472 kb
Host smart-bca8afd6-1a54-46a3-b720-f6e783588db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494385605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.3494385605
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.3231294838
Short name T233
Test name
Test status
Simulation time 3938852951 ps
CPU time 5.81 seconds
Started Jul 29 05:04:18 PM PDT 24
Finished Jul 29 05:04:24 PM PDT 24
Peak memory 225232 kb
Host smart-1c1ed6a2-3865-4d0b-9dc2-af2039177f58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231294838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.3231294838
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.1366105630
Short name T856
Test name
Test status
Simulation time 21206103 ps
CPU time 0.75 seconds
Started Jul 29 05:04:25 PM PDT 24
Finished Jul 29 05:04:26 PM PDT 24
Peak memory 205324 kb
Host smart-43dc8793-094c-48b0-b6e1-c18b6a069cb3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366105630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
1366105630
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.1342314648
Short name T2
Test name
Test status
Simulation time 1034746924 ps
CPU time 5.14 seconds
Started Jul 29 05:04:25 PM PDT 24
Finished Jul 29 05:04:30 PM PDT 24
Peak memory 225260 kb
Host smart-f65261e4-7cd4-4647-9561-37ea87648f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342314648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.1342314648
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.366155189
Short name T349
Test name
Test status
Simulation time 56399958 ps
CPU time 0.78 seconds
Started Jul 29 05:04:25 PM PDT 24
Finished Jul 29 05:04:26 PM PDT 24
Peak memory 207076 kb
Host smart-f5062cc8-4d9a-4886-a0ad-c64278953d4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366155189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.366155189
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.2351042066
Short name T61
Test name
Test status
Simulation time 10923058087 ps
CPU time 52.64 seconds
Started Jul 29 05:04:26 PM PDT 24
Finished Jul 29 05:05:19 PM PDT 24
Peak memory 254860 kb
Host smart-f2a7470d-9977-4f30-b555-523c12bd6324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351042066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.2351042066
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.862815344
Short name T868
Test name
Test status
Simulation time 47818366395 ps
CPU time 471.37 seconds
Started Jul 29 05:04:25 PM PDT 24
Finished Jul 29 05:12:17 PM PDT 24
Peak memory 273004 kb
Host smart-aab665c5-052a-4436-86de-c4048bd6c738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862815344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.862815344
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.2756029217
Short name T791
Test name
Test status
Simulation time 871249159 ps
CPU time 15.24 seconds
Started Jul 29 05:04:24 PM PDT 24
Finished Jul 29 05:04:40 PM PDT 24
Peak memory 241676 kb
Host smart-cc4c8a81-ce24-4be5-a0e7-ebcc5d26213b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756029217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.2756029217
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.304014212
Short name T133
Test name
Test status
Simulation time 53389758751 ps
CPU time 95.96 seconds
Started Jul 29 05:04:25 PM PDT 24
Finished Jul 29 05:06:01 PM PDT 24
Peak memory 249868 kb
Host smart-d96421e0-15eb-45f1-9843-01cf650f5c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304014212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmds
.304014212
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_intercept.1793168341
Short name T268
Test name
Test status
Simulation time 195965770 ps
CPU time 4.2 seconds
Started Jul 29 05:04:25 PM PDT 24
Finished Jul 29 05:04:29 PM PDT 24
Peak memory 225168 kb
Host smart-24e0b875-6235-43a0-b519-dd606bb40544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793168341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.1793168341
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.2967524220
Short name T974
Test name
Test status
Simulation time 3254345853 ps
CPU time 36.68 seconds
Started Jul 29 05:04:25 PM PDT 24
Finished Jul 29 05:05:01 PM PDT 24
Peak memory 250052 kb
Host smart-5dafbbcb-cef6-4226-923d-500255dcee13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967524220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.2967524220
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.2049882176
Short name T623
Test name
Test status
Simulation time 49256109 ps
CPU time 1.05 seconds
Started Jul 29 05:04:25 PM PDT 24
Finished Jul 29 05:04:26 PM PDT 24
Peak memory 217128 kb
Host smart-13ef099f-4bfd-45c0-971a-1acf637a0815
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049882176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.spi_device_mem_parity.2049882176
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.1052671362
Short name T955
Test name
Test status
Simulation time 8428782514 ps
CPU time 15.84 seconds
Started Jul 29 05:04:25 PM PDT 24
Finished Jul 29 05:04:41 PM PDT 24
Peak memory 233536 kb
Host smart-158a1e9f-197d-41e4-9a24-ec0c16bc2791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052671362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.1052671362
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.3767609070
Short name T388
Test name
Test status
Simulation time 1767217156 ps
CPU time 7.56 seconds
Started Jul 29 05:04:25 PM PDT 24
Finished Jul 29 05:04:33 PM PDT 24
Peak memory 225180 kb
Host smart-ff6a34aa-4ead-4ae2-9648-da8980727395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767609070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.3767609070
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.3173067842
Short name T690
Test name
Test status
Simulation time 982707394 ps
CPU time 9.68 seconds
Started Jul 29 05:04:25 PM PDT 24
Finished Jul 29 05:04:35 PM PDT 24
Peak memory 222988 kb
Host smart-0ce55625-b30a-418f-9c34-6c00bf736fdc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3173067842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.3173067842
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.3366356646
Short name T63
Test name
Test status
Simulation time 11121370196 ps
CPU time 12.04 seconds
Started Jul 29 05:04:24 PM PDT 24
Finished Jul 29 05:04:37 PM PDT 24
Peak memory 217000 kb
Host smart-2c4f1f3e-28a1-47d5-86d1-c41cd596d075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366356646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.3366356646
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.2092620289
Short name T729
Test name
Test status
Simulation time 11228368900 ps
CPU time 15.33 seconds
Started Jul 29 05:04:24 PM PDT 24
Finished Jul 29 05:04:39 PM PDT 24
Peak memory 217104 kb
Host smart-c58c1db1-0202-4995-87c0-c5b3e07fe9f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092620289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.2092620289
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.2898993449
Short name T655
Test name
Test status
Simulation time 764863405 ps
CPU time 3.09 seconds
Started Jul 29 05:04:26 PM PDT 24
Finished Jul 29 05:04:29 PM PDT 24
Peak memory 216928 kb
Host smart-3fcbde7d-f0aa-45db-ad31-38d90d6641ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898993449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.2898993449
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.4130089899
Short name T372
Test name
Test status
Simulation time 151271464 ps
CPU time 0.73 seconds
Started Jul 29 05:04:25 PM PDT 24
Finished Jul 29 05:04:26 PM PDT 24
Peak memory 206612 kb
Host smart-743ae19f-d3ca-4398-931b-be86e6c0e0da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130089899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.4130089899
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.1979131367
Short name T815
Test name
Test status
Simulation time 5533934627 ps
CPU time 12.56 seconds
Started Jul 29 05:04:25 PM PDT 24
Finished Jul 29 05:04:38 PM PDT 24
Peak memory 233500 kb
Host smart-d4faa6a9-c2d4-42a2-91aa-e537862ea73e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979131367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.1979131367
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.512910223
Short name T880
Test name
Test status
Simulation time 25985648 ps
CPU time 0.7 seconds
Started Jul 29 05:04:36 PM PDT 24
Finished Jul 29 05:04:37 PM PDT 24
Peak memory 205836 kb
Host smart-5e9d5ad3-8dc7-44ae-ab76-b2d5489c954d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512910223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.512910223
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.923363086
Short name T553
Test name
Test status
Simulation time 7252184584 ps
CPU time 16.32 seconds
Started Jul 29 05:04:33 PM PDT 24
Finished Jul 29 05:04:49 PM PDT 24
Peak memory 225336 kb
Host smart-086656ef-489a-4f75-a0f2-bb3430a67f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923363086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.923363086
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.4164341385
Short name T793
Test name
Test status
Simulation time 95899656 ps
CPU time 0.79 seconds
Started Jul 29 05:04:26 PM PDT 24
Finished Jul 29 05:04:27 PM PDT 24
Peak memory 207404 kb
Host smart-68e5ae01-47a4-4f7e-a7f6-62910c8e3dbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164341385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.4164341385
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.1775421670
Short name T971
Test name
Test status
Simulation time 27442097034 ps
CPU time 217.04 seconds
Started Jul 29 05:04:31 PM PDT 24
Finished Jul 29 05:08:08 PM PDT 24
Peak memory 272636 kb
Host smart-1da31101-c92e-4153-8b94-df0ab768fdfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775421670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.1775421670
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.2699229784
Short name T294
Test name
Test status
Simulation time 54401341341 ps
CPU time 414.05 seconds
Started Jul 29 05:04:29 PM PDT 24
Finished Jul 29 05:11:23 PM PDT 24
Peak memory 265820 kb
Host smart-ca0fe016-7d93-4098-97f0-297776900685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699229784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.2699229784
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.2162955561
Short name T865
Test name
Test status
Simulation time 1663637251 ps
CPU time 17.1 seconds
Started Jul 29 05:04:36 PM PDT 24
Finished Jul 29 05:04:53 PM PDT 24
Peak memory 249828 kb
Host smart-5f5a5bdb-72f4-48f1-994f-cb1f3388dca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162955561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.2162955561
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.1951346082
Short name T188
Test name
Test status
Simulation time 4782076839 ps
CPU time 20.68 seconds
Started Jul 29 05:04:31 PM PDT 24
Finished Jul 29 05:04:52 PM PDT 24
Peak memory 241596 kb
Host smart-d36f3c08-b29d-4bf8-bd23-23d8356e50fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951346082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmd
s.1951346082
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/15.spi_device_intercept.2733665213
Short name T733
Test name
Test status
Simulation time 3251713646 ps
CPU time 9.8 seconds
Started Jul 29 05:04:32 PM PDT 24
Finished Jul 29 05:04:42 PM PDT 24
Peak memory 225256 kb
Host smart-48260989-d626-4937-b54a-ae6ec790e15d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733665213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.2733665213
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.2181505975
Short name T643
Test name
Test status
Simulation time 8522651136 ps
CPU time 75.18 seconds
Started Jul 29 05:04:31 PM PDT 24
Finished Jul 29 05:05:46 PM PDT 24
Peak memory 250756 kb
Host smart-838ad10c-195e-40b9-83cb-9b094ac2dabe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181505975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.2181505975
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.3899994983
Short name T906
Test name
Test status
Simulation time 80770876 ps
CPU time 1.18 seconds
Started Jul 29 05:04:26 PM PDT 24
Finished Jul 29 05:04:28 PM PDT 24
Peak memory 217216 kb
Host smart-9385bbb2-81fe-476a-8905-b705af218cea
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899994983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.3899994983
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.195203743
Short name T584
Test name
Test status
Simulation time 1531285780 ps
CPU time 4.04 seconds
Started Jul 29 05:04:31 PM PDT 24
Finished Jul 29 05:04:35 PM PDT 24
Peak memory 233372 kb
Host smart-77fd8430-71c5-4f88-8dc6-2e4248b2f42b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195203743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swap
.195203743
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.3559787494
Short name T258
Test name
Test status
Simulation time 113743883 ps
CPU time 3.21 seconds
Started Jul 29 05:04:31 PM PDT 24
Finished Jul 29 05:04:35 PM PDT 24
Peak memory 233432 kb
Host smart-25fcff99-e0b7-4792-b3bb-9ba60b561d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559787494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.3559787494
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.3795599391
Short name T694
Test name
Test status
Simulation time 168983650 ps
CPU time 5.35 seconds
Started Jul 29 05:04:31 PM PDT 24
Finished Jul 29 05:04:37 PM PDT 24
Peak memory 223624 kb
Host smart-1819d163-e195-4530-a781-003aa4aefb18
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3795599391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.3795599391
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.2626279658
Short name T533
Test name
Test status
Simulation time 94805525538 ps
CPU time 211.04 seconds
Started Jul 29 05:04:30 PM PDT 24
Finished Jul 29 05:08:01 PM PDT 24
Peak memory 251648 kb
Host smart-6753e0fc-65c6-49c4-95ca-2d8b02e536ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626279658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.2626279658
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.732977632
Short name T377
Test name
Test status
Simulation time 3039036780 ps
CPU time 28.32 seconds
Started Jul 29 05:04:26 PM PDT 24
Finished Jul 29 05:04:55 PM PDT 24
Peak memory 217296 kb
Host smart-cd8b35b6-17eb-4aa1-a8cf-eaec094bdbe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732977632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.732977632
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.3430625445
Short name T948
Test name
Test status
Simulation time 3830310821 ps
CPU time 4.07 seconds
Started Jul 29 05:04:24 PM PDT 24
Finished Jul 29 05:04:28 PM PDT 24
Peak memory 217064 kb
Host smart-58004278-dfa5-4f25-8bb1-ecb757b2bd33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430625445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.3430625445
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.3766920414
Short name T941
Test name
Test status
Simulation time 194805863 ps
CPU time 2.63 seconds
Started Jul 29 05:04:26 PM PDT 24
Finished Jul 29 05:04:29 PM PDT 24
Peak memory 216956 kb
Host smart-55742f0a-6c74-4220-a9a4-360722c35f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766920414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.3766920414
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.3784333167
Short name T799
Test name
Test status
Simulation time 84417483 ps
CPU time 0.77 seconds
Started Jul 29 05:04:23 PM PDT 24
Finished Jul 29 05:04:24 PM PDT 24
Peak memory 206620 kb
Host smart-f90e971b-8683-4872-b51c-ad66fbfe03b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784333167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.3784333167
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.3501173460
Short name T530
Test name
Test status
Simulation time 358545301 ps
CPU time 2.16 seconds
Started Jul 29 05:04:36 PM PDT 24
Finished Jul 29 05:04:38 PM PDT 24
Peak memory 223608 kb
Host smart-34373232-e05b-42b4-a59f-8f8e346614d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501173460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.3501173460
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.2658979359
Short name T540
Test name
Test status
Simulation time 16705163 ps
CPU time 0.76 seconds
Started Jul 29 05:04:39 PM PDT 24
Finished Jul 29 05:04:40 PM PDT 24
Peak memory 205200 kb
Host smart-8d90ed7a-ca39-4a80-b354-7ea63545cde0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658979359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
2658979359
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.2108968529
Short name T864
Test name
Test status
Simulation time 2629313073 ps
CPU time 12.7 seconds
Started Jul 29 05:04:37 PM PDT 24
Finished Jul 29 05:04:50 PM PDT 24
Peak memory 233464 kb
Host smart-4f1ab654-ee9a-4dd2-b88a-0653684cc840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108968529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.2108968529
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.188972660
Short name T527
Test name
Test status
Simulation time 30573361 ps
CPU time 0.78 seconds
Started Jul 29 05:04:32 PM PDT 24
Finished Jul 29 05:04:33 PM PDT 24
Peak memory 206272 kb
Host smart-c7468410-87de-4816-9386-6f04f1cae5c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188972660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.188972660
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.688968047
Short name T886
Test name
Test status
Simulation time 10169831402 ps
CPU time 134.15 seconds
Started Jul 29 05:04:38 PM PDT 24
Finished Jul 29 05:06:52 PM PDT 24
Peak memory 265368 kb
Host smart-c6a0a027-7314-4a48-9fff-537336ab7795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688968047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.688968047
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.1886736593
Short name T613
Test name
Test status
Simulation time 25247557371 ps
CPU time 83.05 seconds
Started Jul 29 05:04:36 PM PDT 24
Finished Jul 29 05:06:00 PM PDT 24
Peak memory 253432 kb
Host smart-adc46672-5d3b-487f-a41e-8d545658c873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886736593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.1886736593
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.1860087934
Short name T656
Test name
Test status
Simulation time 13086149601 ps
CPU time 80.28 seconds
Started Jul 29 05:04:39 PM PDT 24
Finished Jul 29 05:05:59 PM PDT 24
Peak memory 264136 kb
Host smart-3adf4387-fbb7-4f57-8543-15b622b2521a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860087934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.1860087934
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.791116072
Short name T303
Test name
Test status
Simulation time 280417069 ps
CPU time 4.46 seconds
Started Jul 29 05:04:37 PM PDT 24
Finished Jul 29 05:04:41 PM PDT 24
Peak memory 225140 kb
Host smart-d6c2fbae-3acc-43af-8176-1704af56d675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791116072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.791116072
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.3926615843
Short name T100
Test name
Test status
Simulation time 182445179740 ps
CPU time 271.74 seconds
Started Jul 29 05:04:38 PM PDT 24
Finished Jul 29 05:09:10 PM PDT 24
Peak memory 253680 kb
Host smart-1f7c2173-5899-43f6-a181-f419d9182d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926615843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmd
s.3926615843
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/16.spi_device_intercept.272245236
Short name T567
Test name
Test status
Simulation time 934788970 ps
CPU time 5.73 seconds
Started Jul 29 05:04:37 PM PDT 24
Finished Jul 29 05:04:43 PM PDT 24
Peak memory 225172 kb
Host smart-fec8bcca-0f31-4af2-95cf-468f69782c92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272245236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.272245236
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.3912285673
Short name T892
Test name
Test status
Simulation time 10590715033 ps
CPU time 34.98 seconds
Started Jul 29 05:04:41 PM PDT 24
Finished Jul 29 05:05:16 PM PDT 24
Peak memory 225188 kb
Host smart-69fe14b8-6d7b-4b7d-8238-991c98dd82ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912285673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.3912285673
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.1289564297
Short name T42
Test name
Test status
Simulation time 43958396 ps
CPU time 1.05 seconds
Started Jul 29 05:04:35 PM PDT 24
Finished Jul 29 05:04:36 PM PDT 24
Peak memory 217228 kb
Host smart-9a1223b9-cc94-409a-8bd6-8f803a448d6c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289564297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.spi_device_mem_parity.1289564297
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.3030897791
Short name T440
Test name
Test status
Simulation time 2413778609 ps
CPU time 6.63 seconds
Started Jul 29 05:04:41 PM PDT 24
Finished Jul 29 05:04:47 PM PDT 24
Peak memory 233428 kb
Host smart-716320a6-5039-4209-8da7-3adee4ee03c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030897791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.3030897791
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.2545117011
Short name T630
Test name
Test status
Simulation time 12416288626 ps
CPU time 9.92 seconds
Started Jul 29 05:04:39 PM PDT 24
Finished Jul 29 05:04:49 PM PDT 24
Peak memory 225180 kb
Host smart-927d3232-9dfe-458b-afeb-4b7f87dc7e26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545117011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.2545117011
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.2004528594
Short name T152
Test name
Test status
Simulation time 183429965 ps
CPU time 5.28 seconds
Started Jul 29 05:04:41 PM PDT 24
Finished Jul 29 05:04:46 PM PDT 24
Peak memory 222772 kb
Host smart-e758ee22-54e1-4bfd-b75c-4c692ca385a9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2004528594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.2004528594
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.2014256955
Short name T619
Test name
Test status
Simulation time 4938176372 ps
CPU time 9.5 seconds
Started Jul 29 05:04:32 PM PDT 24
Finished Jul 29 05:04:41 PM PDT 24
Peak memory 217000 kb
Host smart-7edfdfa8-8266-489d-9a15-11ad0dcef4b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014256955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.2014256955
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.506769745
Short name T705
Test name
Test status
Simulation time 1840718859 ps
CPU time 4.34 seconds
Started Jul 29 05:04:32 PM PDT 24
Finished Jul 29 05:04:37 PM PDT 24
Peak memory 216868 kb
Host smart-ae101a40-ef0d-4972-b961-a74a4691419b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506769745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.506769745
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.4007940979
Short name T395
Test name
Test status
Simulation time 128117317 ps
CPU time 8.08 seconds
Started Jul 29 05:04:40 PM PDT 24
Finished Jul 29 05:04:48 PM PDT 24
Peak memory 217020 kb
Host smart-34035bb8-bbb7-40e4-b19a-7d3c303ccbfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007940979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.4007940979
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.1609947853
Short name T930
Test name
Test status
Simulation time 38348839 ps
CPU time 0.69 seconds
Started Jul 29 05:04:30 PM PDT 24
Finished Jul 29 05:04:31 PM PDT 24
Peak memory 206012 kb
Host smart-8ee11457-9fe5-4c1f-b5e2-2a6603cb2065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609947853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.1609947853
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.1048424189
Short name T222
Test name
Test status
Simulation time 27947173538 ps
CPU time 14.52 seconds
Started Jul 29 05:04:38 PM PDT 24
Finished Jul 29 05:04:52 PM PDT 24
Peak memory 241264 kb
Host smart-7d4dcf00-efeb-4c26-876f-629dd4108a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048424189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.1048424189
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.642829195
Short name T696
Test name
Test status
Simulation time 14110526 ps
CPU time 0.73 seconds
Started Jul 29 05:04:43 PM PDT 24
Finished Jul 29 05:04:44 PM PDT 24
Peak memory 206236 kb
Host smart-18d722d5-b680-49a6-b0a2-8675d3c838d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642829195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.642829195
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.3571376457
Short name T701
Test name
Test status
Simulation time 64359559 ps
CPU time 2.48 seconds
Started Jul 29 05:04:43 PM PDT 24
Finished Jul 29 05:04:45 PM PDT 24
Peak memory 233000 kb
Host smart-091a5670-f564-4959-8e5e-b00a80afdade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571376457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.3571376457
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.3865225758
Short name T547
Test name
Test status
Simulation time 19058888 ps
CPU time 0.76 seconds
Started Jul 29 05:04:39 PM PDT 24
Finished Jul 29 05:04:40 PM PDT 24
Peak memory 206368 kb
Host smart-02aee410-41b4-4350-8ad1-2c80bc9b3fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865225758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.3865225758
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.866436474
Short name T905
Test name
Test status
Simulation time 24949121749 ps
CPU time 89.46 seconds
Started Jul 29 05:04:43 PM PDT 24
Finished Jul 29 05:06:13 PM PDT 24
Peak memory 266232 kb
Host smart-7f3e4918-813e-4411-abd5-bf9aa44f9962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866436474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.866436474
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.2914854364
Short name T728
Test name
Test status
Simulation time 6479026379 ps
CPU time 62.02 seconds
Started Jul 29 05:04:44 PM PDT 24
Finished Jul 29 05:05:46 PM PDT 24
Peak memory 234632 kb
Host smart-5a47188c-f756-4073-84f0-5051aeabf901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914854364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.2914854364
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.20305516
Short name T196
Test name
Test status
Simulation time 177836087029 ps
CPU time 829.26 seconds
Started Jul 29 05:04:43 PM PDT 24
Finished Jul 29 05:18:33 PM PDT 24
Peak memory 274252 kb
Host smart-e21b3b36-4547-4306-b0f6-4aacebda8f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20305516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idle.20305516
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.1981154387
Short name T612
Test name
Test status
Simulation time 24111305400 ps
CPU time 45.38 seconds
Started Jul 29 05:04:42 PM PDT 24
Finished Jul 29 05:05:27 PM PDT 24
Peak memory 241660 kb
Host smart-4005c83a-c8b9-4453-8705-94212c2272b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981154387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.1981154387
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.1518150890
Short name T940
Test name
Test status
Simulation time 1094732629 ps
CPU time 24.9 seconds
Started Jul 29 05:04:42 PM PDT 24
Finished Jul 29 05:05:07 PM PDT 24
Peak memory 252728 kb
Host smart-64f01668-f10b-46eb-80c7-23929de0b2d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518150890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmd
s.1518150890
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/17.spi_device_intercept.631799475
Short name T509
Test name
Test status
Simulation time 2282011893 ps
CPU time 12.9 seconds
Started Jul 29 05:04:42 PM PDT 24
Finished Jul 29 05:04:56 PM PDT 24
Peak memory 233700 kb
Host smart-4b60ca50-5f20-4d85-a2d6-5b8e2858f47c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631799475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.631799475
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.3218283710
Short name T574
Test name
Test status
Simulation time 19934082898 ps
CPU time 59.87 seconds
Started Jul 29 05:04:44 PM PDT 24
Finished Jul 29 05:05:44 PM PDT 24
Peak memory 249940 kb
Host smart-e754aeeb-0c40-40da-870a-e9bbe7cb7aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218283710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.3218283710
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.1944270033
Short name T1000
Test name
Test status
Simulation time 25334599 ps
CPU time 1.02 seconds
Started Jul 29 05:04:37 PM PDT 24
Finished Jul 29 05:04:38 PM PDT 24
Peak memory 218364 kb
Host smart-ed5f677e-ca6e-47d3-880f-619e3b7e6830
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944270033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.spi_device_mem_parity.1944270033
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.1839745800
Short name T523
Test name
Test status
Simulation time 111438192 ps
CPU time 1.99 seconds
Started Jul 29 05:04:44 PM PDT 24
Finished Jul 29 05:04:46 PM PDT 24
Peak memory 225256 kb
Host smart-64734fbd-4c04-480f-a9dd-e7d3ada0bc32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839745800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.1839745800
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.2137054938
Short name T404
Test name
Test status
Simulation time 711945295 ps
CPU time 4.34 seconds
Started Jul 29 05:04:42 PM PDT 24
Finished Jul 29 05:04:46 PM PDT 24
Peak memory 225252 kb
Host smart-33a1f20c-b908-4187-b2d8-ec53e7f2433c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137054938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.2137054938
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.23560532
Short name T647
Test name
Test status
Simulation time 2134551133 ps
CPU time 12.47 seconds
Started Jul 29 05:04:43 PM PDT 24
Finished Jul 29 05:04:55 PM PDT 24
Peak memory 220696 kb
Host smart-56a31aa6-0ec2-4b35-9769-f61d9ceb5eff
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=23560532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_direc
t.23560532
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.3560040616
Short name T811
Test name
Test status
Simulation time 1547807917 ps
CPU time 9.85 seconds
Started Jul 29 05:04:38 PM PDT 24
Finished Jul 29 05:04:48 PM PDT 24
Peak memory 217024 kb
Host smart-f135fbe0-50f8-46d3-a7c4-b3e212b4881d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560040616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.3560040616
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.4191698837
Short name T82
Test name
Test status
Simulation time 2386828922 ps
CPU time 2.9 seconds
Started Jul 29 05:04:39 PM PDT 24
Finished Jul 29 05:04:42 PM PDT 24
Peak memory 216716 kb
Host smart-c1870538-473c-4ede-8e29-0ce9c1ede9f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191698837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.4191698837
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.2061089411
Short name T393
Test name
Test status
Simulation time 210532577 ps
CPU time 1.01 seconds
Started Jul 29 05:04:42 PM PDT 24
Finished Jul 29 05:04:44 PM PDT 24
Peak memory 207264 kb
Host smart-9f8114da-d114-41b7-a15f-182696ee794c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061089411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.2061089411
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.4107890327
Short name T337
Test name
Test status
Simulation time 120208823 ps
CPU time 0.85 seconds
Started Jul 29 05:04:43 PM PDT 24
Finished Jul 29 05:04:44 PM PDT 24
Peak memory 206560 kb
Host smart-864518e0-fdfd-4823-8484-3b82a093258b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107890327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.4107890327
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.3060802078
Short name T837
Test name
Test status
Simulation time 3137437614 ps
CPU time 12.67 seconds
Started Jul 29 05:04:42 PM PDT 24
Finished Jul 29 05:04:54 PM PDT 24
Peak memory 233440 kb
Host smart-f0a71eab-56be-4bf5-a070-af431545d181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060802078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.3060802078
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.718651491
Short name T675
Test name
Test status
Simulation time 12608534 ps
CPU time 0.71 seconds
Started Jul 29 05:04:47 PM PDT 24
Finished Jul 29 05:04:48 PM PDT 24
Peak memory 206200 kb
Host smart-16690a8d-6da6-44be-a69f-a31f76464149
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718651491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.718651491
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.1953194224
Short name T247
Test name
Test status
Simulation time 1030810291 ps
CPU time 8.35 seconds
Started Jul 29 05:04:48 PM PDT 24
Finished Jul 29 05:04:57 PM PDT 24
Peak memory 225108 kb
Host smart-903be9ee-4f05-49b3-8043-d76d64b8d143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953194224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.1953194224
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.4052476568
Short name T24
Test name
Test status
Simulation time 235607258 ps
CPU time 0.8 seconds
Started Jul 29 05:04:41 PM PDT 24
Finished Jul 29 05:04:42 PM PDT 24
Peak memory 207392 kb
Host smart-606422cc-06f1-4201-9832-ef063b1a432f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052476568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.4052476568
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.2037541135
Short name T56
Test name
Test status
Simulation time 69926479678 ps
CPU time 439.14 seconds
Started Jul 29 05:04:52 PM PDT 24
Finished Jul 29 05:12:11 PM PDT 24
Peak memory 258104 kb
Host smart-bf239c27-93b7-45f0-a190-21f5ea35f62a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037541135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.2037541135
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.2558445454
Short name T428
Test name
Test status
Simulation time 1934659444 ps
CPU time 26.78 seconds
Started Jul 29 05:04:51 PM PDT 24
Finished Jul 29 05:05:18 PM PDT 24
Peak memory 241668 kb
Host smart-c4ad1b74-1cac-4331-aa23-4b77f3f0ffcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558445454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.2558445454
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.3039894399
Short name T164
Test name
Test status
Simulation time 16851972105 ps
CPU time 148.77 seconds
Started Jul 29 05:04:48 PM PDT 24
Finished Jul 29 05:07:17 PM PDT 24
Peak memory 252772 kb
Host smart-a8b608a4-6c75-4999-bdc1-0ec310efccfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039894399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.3039894399
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.4221601589
Short name T49
Test name
Test status
Simulation time 305612158 ps
CPU time 5.25 seconds
Started Jul 29 05:04:50 PM PDT 24
Finished Jul 29 05:04:56 PM PDT 24
Peak memory 234380 kb
Host smart-a2d1167d-b6fb-45b0-8694-687528b3d4bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221601589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.4221601589
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.1139734438
Short name T348
Test name
Test status
Simulation time 7937357825 ps
CPU time 14.44 seconds
Started Jul 29 05:04:46 PM PDT 24
Finished Jul 29 05:05:01 PM PDT 24
Peak memory 225092 kb
Host smart-80f9224b-a839-4499-83c5-47af9d1c9f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139734438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmd
s.1139734438
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/18.spi_device_intercept.34133203
Short name T614
Test name
Test status
Simulation time 6082866662 ps
CPU time 12.89 seconds
Started Jul 29 05:04:47 PM PDT 24
Finished Jul 29 05:05:00 PM PDT 24
Peak memory 225280 kb
Host smart-7a5f4c6e-dc85-4285-b71a-d409c24bc8e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34133203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.34133203
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.3947779904
Short name T625
Test name
Test status
Simulation time 14803646666 ps
CPU time 14.03 seconds
Started Jul 29 05:04:49 PM PDT 24
Finished Jul 29 05:05:03 PM PDT 24
Peak memory 225236 kb
Host smart-a9d1f147-6c8e-4c9c-8c99-c9ce6da987df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947779904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.3947779904
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.2404061580
Short name T546
Test name
Test status
Simulation time 184662521 ps
CPU time 1.05 seconds
Started Jul 29 05:04:43 PM PDT 24
Finished Jul 29 05:04:45 PM PDT 24
Peak memory 218420 kb
Host smart-3868c547-69dd-4146-b465-fc4dac4dacb9
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404061580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.spi_device_mem_parity.2404061580
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.2965533342
Short name T556
Test name
Test status
Simulation time 13748038967 ps
CPU time 11.61 seconds
Started Jul 29 05:04:54 PM PDT 24
Finished Jul 29 05:05:05 PM PDT 24
Peak memory 225332 kb
Host smart-f56261e1-65d1-4abd-8e26-1c63a5b0a86e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965533342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.2965533342
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.1034698659
Short name T797
Test name
Test status
Simulation time 204377113 ps
CPU time 2.15 seconds
Started Jul 29 05:04:48 PM PDT 24
Finished Jul 29 05:04:50 PM PDT 24
Peak memory 225192 kb
Host smart-825513d5-0491-4d6b-b41e-c56071c5ec26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034698659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.1034698659
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.2521233563
Short name T976
Test name
Test status
Simulation time 180104066 ps
CPU time 5.3 seconds
Started Jul 29 05:04:51 PM PDT 24
Finished Jul 29 05:04:57 PM PDT 24
Peak memory 222864 kb
Host smart-fb883dbb-3ba5-4f94-a863-a8de80528eec
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2521233563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.2521233563
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.3523842303
Short name T23
Test name
Test status
Simulation time 193568673 ps
CPU time 1.06 seconds
Started Jul 29 05:04:48 PM PDT 24
Finished Jul 29 05:04:49 PM PDT 24
Peak memory 207580 kb
Host smart-fc8ae797-97a7-4849-a31a-a8a89fa6968e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523842303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.3523842303
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.1494308488
Short name T650
Test name
Test status
Simulation time 822348612 ps
CPU time 4.11 seconds
Started Jul 29 05:04:51 PM PDT 24
Finished Jul 29 05:04:55 PM PDT 24
Peak memory 216928 kb
Host smart-1020469a-ddf2-4280-ae51-494b675ec81b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494308488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.1494308488
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.4065723973
Short name T381
Test name
Test status
Simulation time 25613242441 ps
CPU time 18.46 seconds
Started Jul 29 05:04:48 PM PDT 24
Finished Jul 29 05:05:06 PM PDT 24
Peak memory 216988 kb
Host smart-54b03440-fd01-486d-a0df-f7c930467aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065723973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.4065723973
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.427055831
Short name T405
Test name
Test status
Simulation time 397342124 ps
CPU time 1.65 seconds
Started Jul 29 05:04:48 PM PDT 24
Finished Jul 29 05:04:50 PM PDT 24
Peak memory 216920 kb
Host smart-417f5f37-db18-4b0b-bb3e-4359b0e46875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427055831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.427055831
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.2358115035
Short name T909
Test name
Test status
Simulation time 25137498 ps
CPU time 0.73 seconds
Started Jul 29 05:04:50 PM PDT 24
Finished Jul 29 05:04:51 PM PDT 24
Peak memory 206508 kb
Host smart-4e3f36b4-3fd8-4818-88f1-d7319ff6eddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358115035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.2358115035
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.2171466176
Short name T482
Test name
Test status
Simulation time 1784538315 ps
CPU time 10.02 seconds
Started Jul 29 05:04:50 PM PDT 24
Finished Jul 29 05:05:00 PM PDT 24
Peak memory 229156 kb
Host smart-2a094ac3-f72f-408c-956c-327f33ab7709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171466176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.2171466176
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.3415700758
Short name T566
Test name
Test status
Simulation time 32709421 ps
CPU time 0.71 seconds
Started Jul 29 05:04:54 PM PDT 24
Finished Jul 29 05:04:55 PM PDT 24
Peak memory 205868 kb
Host smart-d4673fdd-6654-4fd8-9c64-f7b50efb4fef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415700758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
3415700758
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.2555831977
Short name T552
Test name
Test status
Simulation time 154229545 ps
CPU time 2.79 seconds
Started Jul 29 05:04:56 PM PDT 24
Finished Jul 29 05:04:59 PM PDT 24
Peak memory 225136 kb
Host smart-bcdc0a81-48e8-4bcc-845a-7bc7f95ead93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555831977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.2555831977
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.2774907711
Short name T520
Test name
Test status
Simulation time 23336338 ps
CPU time 0.78 seconds
Started Jul 29 05:04:54 PM PDT 24
Finished Jul 29 05:04:55 PM PDT 24
Peak memory 205976 kb
Host smart-c58cffa4-6f9e-4e1f-821f-92f618416f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774907711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.2774907711
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.339004918
Short name T441
Test name
Test status
Simulation time 6903164239 ps
CPU time 64.53 seconds
Started Jul 29 05:04:57 PM PDT 24
Finished Jul 29 05:06:01 PM PDT 24
Peak memory 256104 kb
Host smart-4a5983ae-3d12-4f67-a6fa-bd0b6407d709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339004918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.339004918
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.2069351190
Short name T143
Test name
Test status
Simulation time 164010788189 ps
CPU time 368.85 seconds
Started Jul 29 05:04:55 PM PDT 24
Finished Jul 29 05:11:04 PM PDT 24
Peak memory 256620 kb
Host smart-08b7f570-3cb1-44f4-ba54-25dedb226aa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069351190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.2069351190
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.3045590528
Short name T831
Test name
Test status
Simulation time 8416288660 ps
CPU time 137.79 seconds
Started Jul 29 05:04:54 PM PDT 24
Finished Jul 29 05:07:12 PM PDT 24
Peak memory 251604 kb
Host smart-47294e81-8aba-40f4-b423-bb2784c057aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045590528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.3045590528
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.4291816141
Short name T852
Test name
Test status
Simulation time 63380862695 ps
CPU time 216.03 seconds
Started Jul 29 05:04:54 PM PDT 24
Finished Jul 29 05:08:31 PM PDT 24
Peak memory 253908 kb
Host smart-06e51720-3116-42d4-a236-c8cd461a27f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291816141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmd
s.4291816141
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_intercept.1434445066
Short name T794
Test name
Test status
Simulation time 3016334007 ps
CPU time 26.92 seconds
Started Jul 29 05:04:56 PM PDT 24
Finished Jul 29 05:05:23 PM PDT 24
Peak memory 225328 kb
Host smart-cc16b11c-6b60-4666-8cdf-066db9393b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434445066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.1434445066
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.375655528
Short name T860
Test name
Test status
Simulation time 100457201223 ps
CPU time 63.12 seconds
Started Jul 29 05:04:55 PM PDT 24
Finished Jul 29 05:05:59 PM PDT 24
Peak memory 241744 kb
Host smart-de6710b2-90c4-41fe-b6d1-1591c5a8f4e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375655528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.375655528
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.2491581825
Short name T398
Test name
Test status
Simulation time 110992914 ps
CPU time 1.08 seconds
Started Jul 29 05:04:54 PM PDT 24
Finished Jul 29 05:04:56 PM PDT 24
Peak memory 218364 kb
Host smart-ea01e828-1af5-47e7-8be0-bf6becdef64f
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491581825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.spi_device_mem_parity.2491581825
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.3272551884
Short name T214
Test name
Test status
Simulation time 39496338 ps
CPU time 2.11 seconds
Started Jul 29 05:04:56 PM PDT 24
Finished Jul 29 05:04:59 PM PDT 24
Peak memory 225220 kb
Host smart-7f676f30-bfb7-4b6d-a53f-26a29ff69682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272551884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.3272551884
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.948156251
Short name T245
Test name
Test status
Simulation time 881640969 ps
CPU time 10.14 seconds
Started Jul 29 05:04:54 PM PDT 24
Finished Jul 29 05:05:04 PM PDT 24
Peak memory 233476 kb
Host smart-3f940af2-24ad-45c1-b29b-2759bb2ba10e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948156251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.948156251
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.3946465405
Short name T907
Test name
Test status
Simulation time 202604853 ps
CPU time 3.5 seconds
Started Jul 29 05:04:56 PM PDT 24
Finished Jul 29 05:04:59 PM PDT 24
Peak memory 220532 kb
Host smart-9844677c-0f55-495b-8f91-5c82469f17a8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3946465405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.3946465405
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.2033440156
Short name T922
Test name
Test status
Simulation time 229493328 ps
CPU time 1.09 seconds
Started Jul 29 05:04:58 PM PDT 24
Finished Jul 29 05:04:59 PM PDT 24
Peak memory 207504 kb
Host smart-c8d9b180-9f38-4e9d-a52f-f8cb1a1c8360
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033440156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.2033440156
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.883108351
Short name T571
Test name
Test status
Simulation time 6460786664 ps
CPU time 25.54 seconds
Started Jul 29 05:04:53 PM PDT 24
Finished Jul 29 05:05:19 PM PDT 24
Peak memory 217124 kb
Host smart-0e4a820e-17b8-4be5-939e-16eff0386483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883108351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.883108351
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.43139063
Short name T1014
Test name
Test status
Simulation time 3460047288 ps
CPU time 12.63 seconds
Started Jul 29 05:04:56 PM PDT 24
Finished Jul 29 05:05:08 PM PDT 24
Peak memory 216932 kb
Host smart-85009eff-435c-4ed4-acc7-0a57cc2e0381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43139063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.43139063
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.2956687345
Short name T317
Test name
Test status
Simulation time 132595056 ps
CPU time 0.83 seconds
Started Jul 29 05:04:55 PM PDT 24
Finished Jul 29 05:04:56 PM PDT 24
Peak memory 206576 kb
Host smart-8cdc0130-9446-4528-8f24-98297aa61193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956687345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.2956687345
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.1599869375
Short name T673
Test name
Test status
Simulation time 98743754 ps
CPU time 0.95 seconds
Started Jul 29 05:04:54 PM PDT 24
Finished Jul 29 05:04:55 PM PDT 24
Peak memory 206472 kb
Host smart-6f672d31-fa9d-4636-a3ea-11ab09303618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599869375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.1599869375
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.3019709349
Short name T785
Test name
Test status
Simulation time 180016402 ps
CPU time 2.56 seconds
Started Jul 29 05:04:55 PM PDT 24
Finished Jul 29 05:04:58 PM PDT 24
Peak memory 233396 kb
Host smart-fca01515-b0bc-4641-a026-88903f48ce8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019709349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.3019709349
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.4155599312
Short name T672
Test name
Test status
Simulation time 31248444 ps
CPU time 0.72 seconds
Started Jul 29 05:03:34 PM PDT 24
Finished Jul 29 05:03:35 PM PDT 24
Peak memory 206144 kb
Host smart-1d4d01e9-c111-4202-8776-07b6934d3fab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155599312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.4
155599312
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.2281961140
Short name T382
Test name
Test status
Simulation time 79549401 ps
CPU time 2.22 seconds
Started Jul 29 05:03:32 PM PDT 24
Finished Jul 29 05:03:34 PM PDT 24
Peak memory 224692 kb
Host smart-3d3c42c4-eaab-48a3-a613-419a2aace90f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281961140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.2281961140
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.2868249172
Short name T583
Test name
Test status
Simulation time 33903710 ps
CPU time 0.8 seconds
Started Jul 29 05:03:26 PM PDT 24
Finished Jul 29 05:03:27 PM PDT 24
Peak memory 206060 kb
Host smart-b31151cf-6d4a-4dbe-9b90-c2367a3aec2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868249172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.2868249172
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.1094824915
Short name T192
Test name
Test status
Simulation time 41329273024 ps
CPU time 72.59 seconds
Started Jul 29 05:03:34 PM PDT 24
Finished Jul 29 05:04:47 PM PDT 24
Peak memory 236536 kb
Host smart-8a021e77-7a0c-461e-a2f9-da7a997bd2d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094824915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.1094824915
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.318417654
Short name T205
Test name
Test status
Simulation time 12823426243 ps
CPU time 100.76 seconds
Started Jul 29 05:03:32 PM PDT 24
Finished Jul 29 05:05:13 PM PDT 24
Peak memory 254964 kb
Host smart-4b4d09df-36d0-4acf-9ee9-144c781f6a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318417654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.318417654
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.945427829
Short name T288
Test name
Test status
Simulation time 19265743709 ps
CPU time 132.32 seconds
Started Jul 29 05:03:33 PM PDT 24
Finished Jul 29 05:05:46 PM PDT 24
Peak memory 250124 kb
Host smart-42ed583c-d83a-4b57-94ff-1b5a4a6a5f23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945427829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle.
945427829
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.2121145853
Short name T839
Test name
Test status
Simulation time 14483105074 ps
CPU time 51.48 seconds
Started Jul 29 05:03:33 PM PDT 24
Finished Jul 29 05:04:25 PM PDT 24
Peak memory 239336 kb
Host smart-e7caa6df-b838-48be-8de7-0eda43fa4435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121145853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.2121145853
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.470247012
Short name T942
Test name
Test status
Simulation time 3666267247 ps
CPU time 42.79 seconds
Started Jul 29 05:03:31 PM PDT 24
Finished Jul 29 05:04:14 PM PDT 24
Peak memory 255876 kb
Host smart-07c566ee-40cf-4e72-b438-79f9eae81af0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470247012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds.
470247012
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_intercept.3793445681
Short name T927
Test name
Test status
Simulation time 6967804397 ps
CPU time 25.12 seconds
Started Jul 29 05:03:25 PM PDT 24
Finished Jul 29 05:03:50 PM PDT 24
Peak memory 225296 kb
Host smart-1942aea6-fde4-449d-896f-f255d3c72234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793445681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.3793445681
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.3220719589
Short name T503
Test name
Test status
Simulation time 79248217 ps
CPU time 2.6 seconds
Started Jul 29 05:03:27 PM PDT 24
Finished Jul 29 05:03:30 PM PDT 24
Peak memory 233416 kb
Host smart-93579a35-eff4-40e3-8b25-788a19d1babb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220719589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.3220719589
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.2973460856
Short name T41
Test name
Test status
Simulation time 30550512 ps
CPU time 1.08 seconds
Started Jul 29 05:03:24 PM PDT 24
Finished Jul 29 05:03:25 PM PDT 24
Peak memory 217124 kb
Host smart-3a52b007-52b8-4028-9391-27474ea544ca
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973460856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.spi_device_mem_parity.2973460856
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.2617678564
Short name T218
Test name
Test status
Simulation time 6598433444 ps
CPU time 20.12 seconds
Started Jul 29 05:03:23 PM PDT 24
Finished Jul 29 05:03:44 PM PDT 24
Peak memory 233380 kb
Host smart-3c1f8163-a4f2-4026-ab4c-e563f3d20fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617678564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.2617678564
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.1918036898
Short name T197
Test name
Test status
Simulation time 3089913120 ps
CPU time 5.47 seconds
Started Jul 29 05:03:22 PM PDT 24
Finished Jul 29 05:03:28 PM PDT 24
Peak memory 225164 kb
Host smart-9e28f46d-8eb8-49c3-9c9f-93306dc76bb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918036898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.1918036898
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.4208852198
Short name T727
Test name
Test status
Simulation time 3640843677 ps
CPU time 11.04 seconds
Started Jul 29 05:03:32 PM PDT 24
Finished Jul 29 05:03:43 PM PDT 24
Peak memory 222612 kb
Host smart-50b5b3ea-e46d-4490-9463-88c27bd74749
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4208852198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.4208852198
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.2182911767
Short name T76
Test name
Test status
Simulation time 372003426 ps
CPU time 1.24 seconds
Started Jul 29 05:03:39 PM PDT 24
Finished Jul 29 05:03:40 PM PDT 24
Peak memory 236672 kb
Host smart-8456f434-9847-4ae3-80ab-ce59d209e308
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182911767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.2182911767
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.3210113099
Short name T456
Test name
Test status
Simulation time 197219873 ps
CPU time 1.07 seconds
Started Jul 29 05:03:32 PM PDT 24
Finished Jul 29 05:03:33 PM PDT 24
Peak memory 207508 kb
Host smart-b5ac83c3-781d-44ee-857f-fc37456d0e04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210113099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.3210113099
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.3954481433
Short name T953
Test name
Test status
Simulation time 72816591956 ps
CPU time 22.98 seconds
Started Jul 29 05:03:23 PM PDT 24
Finished Jul 29 05:03:46 PM PDT 24
Peak memory 217204 kb
Host smart-02a091bb-25c9-48a7-b58e-5408070daf6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954481433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.3954481433
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.2929748076
Short name T980
Test name
Test status
Simulation time 750292901 ps
CPU time 5.89 seconds
Started Jul 29 05:03:29 PM PDT 24
Finished Jul 29 05:03:35 PM PDT 24
Peak memory 216932 kb
Host smart-48a5f6c6-2a49-41a8-99de-f1f97f015654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929748076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.2929748076
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.1541555130
Short name T356
Test name
Test status
Simulation time 235927171 ps
CPU time 4.77 seconds
Started Jul 29 05:03:25 PM PDT 24
Finished Jul 29 05:03:30 PM PDT 24
Peak memory 216940 kb
Host smart-82947259-999b-4477-8d1c-b4b90a1a856f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541555130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.1541555130
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.3937728380
Short name T34
Test name
Test status
Simulation time 48528589 ps
CPU time 0.75 seconds
Started Jul 29 05:03:25 PM PDT 24
Finished Jul 29 05:03:26 PM PDT 24
Peak memory 206600 kb
Host smart-362354cc-4d65-4585-9c2e-f2cf5db83765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937728380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.3937728380
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.2591463911
Short name T806
Test name
Test status
Simulation time 3279390112 ps
CPU time 17.86 seconds
Started Jul 29 05:03:27 PM PDT 24
Finished Jul 29 05:03:45 PM PDT 24
Peak memory 253696 kb
Host smart-35532647-21e3-46cc-9242-65e46eac31c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591463911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.2591463911
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.1080416845
Short name T71
Test name
Test status
Simulation time 16728842 ps
CPU time 0.7 seconds
Started Jul 29 05:05:06 PM PDT 24
Finished Jul 29 05:05:07 PM PDT 24
Peak memory 205836 kb
Host smart-bd73b856-cc98-4c54-9730-ef5412900958
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080416845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
1080416845
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.2358681870
Short name T635
Test name
Test status
Simulation time 38238215 ps
CPU time 2.35 seconds
Started Jul 29 05:05:01 PM PDT 24
Finished Jul 29 05:05:03 PM PDT 24
Peak memory 233420 kb
Host smart-f285d073-f77e-46e1-9a52-18056f662f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358681870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.2358681870
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.1565528357
Short name T779
Test name
Test status
Simulation time 201582533 ps
CPU time 0.77 seconds
Started Jul 29 05:04:54 PM PDT 24
Finished Jul 29 05:04:55 PM PDT 24
Peak memory 207272 kb
Host smart-624c05e2-1286-46f4-ba0a-4d78d075d61a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565528357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.1565528357
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.1164793993
Short name T606
Test name
Test status
Simulation time 77867159 ps
CPU time 0.86 seconds
Started Jul 29 05:05:04 PM PDT 24
Finished Jul 29 05:05:05 PM PDT 24
Peak memory 216612 kb
Host smart-f1bb4d0a-71a1-4e9b-a903-9a9b640e01ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164793993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.1164793993
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.4230100371
Short name T559
Test name
Test status
Simulation time 28758598165 ps
CPU time 89.52 seconds
Started Jul 29 05:05:02 PM PDT 24
Finished Jul 29 05:06:31 PM PDT 24
Peak memory 255036 kb
Host smart-40cc83ce-2219-4783-8049-b8a91950e5c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230100371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.4230100371
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.50387848
Short name T978
Test name
Test status
Simulation time 53130020375 ps
CPU time 263.59 seconds
Started Jul 29 05:05:04 PM PDT 24
Finished Jul 29 05:09:28 PM PDT 24
Peak memory 267368 kb
Host smart-c1b88dac-7997-4ffd-b518-65b9a3661f95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50387848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idle.50387848
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.2275300368
Short name T920
Test name
Test status
Simulation time 2886990265 ps
CPU time 47.18 seconds
Started Jul 29 05:05:02 PM PDT 24
Finished Jul 29 05:05:49 PM PDT 24
Peak memory 241668 kb
Host smart-c1db3ac4-da80-4d7e-94bf-2b04dcfb9488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275300368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.2275300368
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.713411245
Short name T600
Test name
Test status
Simulation time 38557350031 ps
CPU time 99.73 seconds
Started Jul 29 05:05:02 PM PDT 24
Finished Jul 29 05:06:42 PM PDT 24
Peak memory 258024 kb
Host smart-cea641a8-01f6-48cc-9002-1da04f5b17aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713411245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmds
.713411245
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/20.spi_device_intercept.318280380
Short name T755
Test name
Test status
Simulation time 74815430 ps
CPU time 3.03 seconds
Started Jul 29 05:05:02 PM PDT 24
Finished Jul 29 05:05:05 PM PDT 24
Peak memory 233492 kb
Host smart-c662ad40-ece0-40db-b101-0735c6d59bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318280380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.318280380
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.3163440662
Short name T739
Test name
Test status
Simulation time 64432235 ps
CPU time 2.1 seconds
Started Jul 29 05:05:02 PM PDT 24
Finished Jul 29 05:05:04 PM PDT 24
Peak memory 233444 kb
Host smart-95aabc12-5c0c-4d98-aa90-f7d3167c12c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163440662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.3163440662
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.1026060251
Short name T53
Test name
Test status
Simulation time 903452885 ps
CPU time 5.71 seconds
Started Jul 29 05:05:03 PM PDT 24
Finished Jul 29 05:05:09 PM PDT 24
Peak memory 240332 kb
Host smart-9461dd7c-17eb-4bbb-84fd-32e19fb43d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026060251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.1026060251
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.3942836470
Short name T185
Test name
Test status
Simulation time 304283723 ps
CPU time 4.93 seconds
Started Jul 29 05:05:05 PM PDT 24
Finished Jul 29 05:05:10 PM PDT 24
Peak memory 233484 kb
Host smart-efaaa330-823b-46a6-ac88-bf91090074bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942836470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.3942836470
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.4240983204
Short name T979
Test name
Test status
Simulation time 1348418308 ps
CPU time 5.52 seconds
Started Jul 29 05:05:09 PM PDT 24
Finished Jul 29 05:05:14 PM PDT 24
Peak memory 219524 kb
Host smart-2c7427fd-c2c2-441b-9dc2-c78f9c2dfc69
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4240983204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.4240983204
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.3812335612
Short name T812
Test name
Test status
Simulation time 57344355280 ps
CPU time 142.61 seconds
Started Jul 29 05:05:01 PM PDT 24
Finished Jul 29 05:07:24 PM PDT 24
Peak memory 258196 kb
Host smart-948e8da7-a55e-48c6-a576-cafbed1cbcd6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812335612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.3812335612
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.3437195894
Short name T781
Test name
Test status
Simulation time 4555551590 ps
CPU time 12.9 seconds
Started Jul 29 05:04:57 PM PDT 24
Finished Jul 29 05:05:10 PM PDT 24
Peak memory 217060 kb
Host smart-eae5c739-d44e-4523-9a04-33a6b30f8ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437195894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.3437195894
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.3519640342
Short name T328
Test name
Test status
Simulation time 108729523848 ps
CPU time 16.81 seconds
Started Jul 29 05:04:54 PM PDT 24
Finished Jul 29 05:05:11 PM PDT 24
Peak memory 217124 kb
Host smart-bfafef65-9666-47ac-94d6-57b611c3b458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519640342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.3519640342
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.937873321
Short name T472
Test name
Test status
Simulation time 32052954 ps
CPU time 0.85 seconds
Started Jul 29 05:05:01 PM PDT 24
Finished Jul 29 05:05:02 PM PDT 24
Peak memory 206512 kb
Host smart-e7d3d560-9915-4a38-a91f-67c9a4d07fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937873321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.937873321
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.2059137217
Short name T575
Test name
Test status
Simulation time 19369188 ps
CPU time 0.77 seconds
Started Jul 29 05:05:04 PM PDT 24
Finished Jul 29 05:05:05 PM PDT 24
Peak memory 206488 kb
Host smart-62a07994-b1a8-4e31-87e3-d2decf25639e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059137217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.2059137217
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.1959448881
Short name T703
Test name
Test status
Simulation time 420828940 ps
CPU time 3.96 seconds
Started Jul 29 05:05:01 PM PDT 24
Finished Jul 29 05:05:05 PM PDT 24
Peak memory 233408 kb
Host smart-f3ad1dac-fcca-477f-b1aa-cae546f3bf21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959448881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.1959448881
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.3447643152
Short name T857
Test name
Test status
Simulation time 25903805 ps
CPU time 0.72 seconds
Started Jul 29 05:05:08 PM PDT 24
Finished Jul 29 05:05:09 PM PDT 24
Peak memory 205312 kb
Host smart-23718d72-18bf-4046-a727-56c8f9642365
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447643152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
3447643152
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.3724427143
Short name T957
Test name
Test status
Simulation time 154925177 ps
CPU time 2.74 seconds
Started Jul 29 05:05:07 PM PDT 24
Finished Jul 29 05:05:10 PM PDT 24
Peak memory 233404 kb
Host smart-97e9becd-d0e9-44db-9a70-6883df1763e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724427143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.3724427143
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.3864541747
Short name T421
Test name
Test status
Simulation time 26120306 ps
CPU time 0.81 seconds
Started Jul 29 05:05:04 PM PDT 24
Finished Jul 29 05:05:05 PM PDT 24
Peak memory 207300 kb
Host smart-1f631def-57a8-422c-a6bd-5cf816e18a5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864541747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.3864541747
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.971340701
Short name T208
Test name
Test status
Simulation time 23177386854 ps
CPU time 177.02 seconds
Started Jul 29 05:05:07 PM PDT 24
Finished Jul 29 05:08:04 PM PDT 24
Peak memory 258272 kb
Host smart-19002dcd-5f63-4304-89e7-d283e4046651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971340701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.971340701
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.485722668
Short name T3
Test name
Test status
Simulation time 7276991256 ps
CPU time 89.88 seconds
Started Jul 29 05:05:08 PM PDT 24
Finished Jul 29 05:06:38 PM PDT 24
Peak memory 255424 kb
Host smart-8f12a426-b9a0-4a0f-b70a-e9794b15c197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485722668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.485722668
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.3258568562
Short name T202
Test name
Test status
Simulation time 65316403755 ps
CPU time 224.13 seconds
Started Jul 29 05:05:09 PM PDT 24
Finished Jul 29 05:08:53 PM PDT 24
Peak memory 265608 kb
Host smart-cd6f768f-0e22-46d4-a9cb-717af6566fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258568562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.3258568562
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.2255584004
Short name T304
Test name
Test status
Simulation time 4686530245 ps
CPU time 17.22 seconds
Started Jul 29 05:05:08 PM PDT 24
Finished Jul 29 05:05:26 PM PDT 24
Peak memory 233524 kb
Host smart-b2bb4c39-b302-4868-9a5c-1de432bf30bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255584004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.2255584004
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.361789616
Short name T903
Test name
Test status
Simulation time 14706820600 ps
CPU time 55.46 seconds
Started Jul 29 05:05:08 PM PDT 24
Finished Jul 29 05:06:03 PM PDT 24
Peak memory 251940 kb
Host smart-e6d242c5-da80-4307-a8e4-c0c1d8b04e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361789616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmds
.361789616
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_intercept.2315077377
Short name T517
Test name
Test status
Simulation time 6340896356 ps
CPU time 9.25 seconds
Started Jul 29 05:05:05 PM PDT 24
Finished Jul 29 05:05:15 PM PDT 24
Peak memory 233484 kb
Host smart-0c3e91cd-38bd-4cd3-b0c4-3fece8953a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315077377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.2315077377
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.2484710350
Short name T522
Test name
Test status
Simulation time 7004389699 ps
CPU time 56.47 seconds
Started Jul 29 05:05:02 PM PDT 24
Finished Jul 29 05:05:59 PM PDT 24
Peak memory 236860 kb
Host smart-fdd9f4cd-5c48-4028-bf6c-1e3ebe7f8e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484710350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.2484710350
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.1859038460
Short name T1001
Test name
Test status
Simulation time 94817139 ps
CPU time 2.92 seconds
Started Jul 29 05:05:02 PM PDT 24
Finished Jul 29 05:05:05 PM PDT 24
Peak memory 233324 kb
Host smart-8149d316-1e25-4872-8bc5-efc46c953424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859038460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.1859038460
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.3642614056
Short name T30
Test name
Test status
Simulation time 6432752882 ps
CPU time 17.78 seconds
Started Jul 29 05:05:01 PM PDT 24
Finished Jul 29 05:05:19 PM PDT 24
Peak memory 240360 kb
Host smart-e1dbb086-5d31-4033-8603-a0ba8a609cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642614056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.3642614056
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.3268764995
Short name T416
Test name
Test status
Simulation time 638772698 ps
CPU time 7.12 seconds
Started Jul 29 05:05:09 PM PDT 24
Finished Jul 29 05:05:17 PM PDT 24
Peak memory 222844 kb
Host smart-fb7dc28d-3beb-4b90-8270-6cb6ea6586ca
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3268764995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.3268764995
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.1024162588
Short name T931
Test name
Test status
Simulation time 26042885658 ps
CPU time 44.9 seconds
Started Jul 29 05:05:08 PM PDT 24
Finished Jul 29 05:05:53 PM PDT 24
Peak memory 241632 kb
Host smart-e4d5c38b-61e6-4a2d-aaa7-d227a68a387f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024162588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.1024162588
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.3772368232
Short name T313
Test name
Test status
Simulation time 1675138774 ps
CPU time 21.61 seconds
Started Jul 29 05:05:05 PM PDT 24
Finished Jul 29 05:05:27 PM PDT 24
Peak memory 217068 kb
Host smart-0c4c0bc0-3eb9-4199-abdc-dbd5f29338da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772368232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.3772368232
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.3461773306
Short name T711
Test name
Test status
Simulation time 2004950237 ps
CPU time 6.84 seconds
Started Jul 29 05:05:05 PM PDT 24
Finished Jul 29 05:05:11 PM PDT 24
Peak memory 216952 kb
Host smart-46f32d55-b5ec-4c3e-a6fd-efdb239de3a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461773306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.3461773306
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.4250766078
Short name T474
Test name
Test status
Simulation time 32067596 ps
CPU time 0.69 seconds
Started Jul 29 05:05:06 PM PDT 24
Finished Jul 29 05:05:06 PM PDT 24
Peak memory 206156 kb
Host smart-7b84d214-c441-46e7-a496-9b73739f05c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250766078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.4250766078
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.155961791
Short name T877
Test name
Test status
Simulation time 119035952 ps
CPU time 0.83 seconds
Started Jul 29 05:05:02 PM PDT 24
Finished Jul 29 05:05:03 PM PDT 24
Peak memory 206560 kb
Host smart-04c29d9c-1ed4-4d38-adfe-919190e6ae33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155961791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.155961791
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.1185709550
Short name T234
Test name
Test status
Simulation time 2863192820 ps
CPU time 10.48 seconds
Started Jul 29 05:05:10 PM PDT 24
Finished Jul 29 05:05:21 PM PDT 24
Peak memory 225288 kb
Host smart-6d121a26-56bf-4f4a-ad07-c0b0857430e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185709550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.1185709550
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.2369778145
Short name T431
Test name
Test status
Simulation time 23525937 ps
CPU time 0.75 seconds
Started Jul 29 05:05:15 PM PDT 24
Finished Jul 29 05:05:15 PM PDT 24
Peak memory 205288 kb
Host smart-6c3d533e-fb9a-4cec-856d-4e20eff5e142
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369778145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
2369778145
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.1649032843
Short name T419
Test name
Test status
Simulation time 138170576 ps
CPU time 3.51 seconds
Started Jul 29 05:05:07 PM PDT 24
Finished Jul 29 05:05:11 PM PDT 24
Peak memory 233416 kb
Host smart-0ec26bbe-3558-4aa5-bfcf-560c08ef3839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649032843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.1649032843
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.229992431
Short name T333
Test name
Test status
Simulation time 18678245 ps
CPU time 0.77 seconds
Started Jul 29 05:05:07 PM PDT 24
Finished Jul 29 05:05:08 PM PDT 24
Peak memory 207104 kb
Host smart-de036285-d93a-4990-a545-e0c9c1e6d520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229992431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.229992431
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.427982795
Short name T272
Test name
Test status
Simulation time 9165526475 ps
CPU time 111.4 seconds
Started Jul 29 05:05:08 PM PDT 24
Finished Jul 29 05:06:59 PM PDT 24
Peak memory 255168 kb
Host smart-074981c4-76b3-47a3-aecc-23ff3cecc3fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427982795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.427982795
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.3786344069
Short name T993
Test name
Test status
Simulation time 4164603674 ps
CPU time 73.42 seconds
Started Jul 29 05:05:09 PM PDT 24
Finished Jul 29 05:06:22 PM PDT 24
Peak memory 241772 kb
Host smart-aaad12e5-3194-4843-ace9-a22d47aa2ba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786344069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.3786344069
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.2160298569
Short name T1011
Test name
Test status
Simulation time 8099149227 ps
CPU time 55.29 seconds
Started Jul 29 05:05:13 PM PDT 24
Finished Jul 29 05:06:09 PM PDT 24
Peak memory 249996 kb
Host smart-ae2b1522-dd46-4907-99f3-110afa66de5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160298569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.2160298569
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.3685058892
Short name T323
Test name
Test status
Simulation time 557602978 ps
CPU time 3.92 seconds
Started Jul 29 05:05:09 PM PDT 24
Finished Jul 29 05:05:13 PM PDT 24
Peak memory 225200 kb
Host smart-573f52fa-2eba-40a4-a2d3-79930e521376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685058892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.3685058892
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.866515534
Short name T723
Test name
Test status
Simulation time 14557618196 ps
CPU time 80.53 seconds
Started Jul 29 05:05:08 PM PDT 24
Finished Jul 29 05:06:29 PM PDT 24
Peak memory 256584 kb
Host smart-da527fad-743f-4118-8007-2f90bc437eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866515534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmds
.866515534
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_intercept.1279639779
Short name T241
Test name
Test status
Simulation time 1194827475 ps
CPU time 9.19 seconds
Started Jul 29 05:05:10 PM PDT 24
Finished Jul 29 05:05:20 PM PDT 24
Peak memory 225212 kb
Host smart-4a816d8a-4b8b-4533-8f4f-a9d28d22163f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279639779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.1279639779
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.2429035630
Short name T392
Test name
Test status
Simulation time 14416261286 ps
CPU time 18.38 seconds
Started Jul 29 05:05:08 PM PDT 24
Finished Jul 29 05:05:27 PM PDT 24
Peak memory 249812 kb
Host smart-ef8c793f-03b6-405f-a065-9132af592148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429035630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.2429035630
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.2868649512
Short name T945
Test name
Test status
Simulation time 34673348408 ps
CPU time 12.49 seconds
Started Jul 29 05:05:08 PM PDT 24
Finished Jul 29 05:05:20 PM PDT 24
Peak memory 225176 kb
Host smart-94e6309a-e0bf-4c4a-8d03-d60d73b348cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868649512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.2868649512
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.1250920275
Short name T414
Test name
Test status
Simulation time 15253669660 ps
CPU time 22.77 seconds
Started Jul 29 05:05:08 PM PDT 24
Finished Jul 29 05:05:31 PM PDT 24
Peak memory 233432 kb
Host smart-0a43ae24-2397-4624-b674-73af78896a79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250920275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.1250920275
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.1976918074
Short name T351
Test name
Test status
Simulation time 2026904350 ps
CPU time 3.8 seconds
Started Jul 29 05:05:09 PM PDT 24
Finished Jul 29 05:05:13 PM PDT 24
Peak memory 219528 kb
Host smart-8707df4b-2b54-4c80-b86e-e2abf8d0faea
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1976918074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.1976918074
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.797126549
Short name T426
Test name
Test status
Simulation time 4171865400 ps
CPU time 14.79 seconds
Started Jul 29 05:05:08 PM PDT 24
Finished Jul 29 05:05:23 PM PDT 24
Peak memory 217252 kb
Host smart-67c0970f-e717-4715-9682-4c44d47a3ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797126549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.797126549
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.3471720307
Short name T387
Test name
Test status
Simulation time 1410249003 ps
CPU time 5.65 seconds
Started Jul 29 05:05:08 PM PDT 24
Finished Jul 29 05:05:14 PM PDT 24
Peak memory 216988 kb
Host smart-4bb4b808-b343-431c-aef3-11b856395555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471720307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.3471720307
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.3903841686
Short name T506
Test name
Test status
Simulation time 140230260 ps
CPU time 3.39 seconds
Started Jul 29 05:05:09 PM PDT 24
Finished Jul 29 05:05:12 PM PDT 24
Peak memory 216936 kb
Host smart-037bff51-7a94-490a-a24a-98466886324a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903841686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.3903841686
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.320508692
Short name T518
Test name
Test status
Simulation time 116503784 ps
CPU time 0.85 seconds
Started Jul 29 05:05:10 PM PDT 24
Finished Jul 29 05:05:11 PM PDT 24
Peak memory 206616 kb
Host smart-b6f972af-7851-47f0-b05c-928fa20e12f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320508692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.320508692
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.2030724442
Short name T932
Test name
Test status
Simulation time 2193573016 ps
CPU time 9.49 seconds
Started Jul 29 05:05:09 PM PDT 24
Finished Jul 29 05:05:18 PM PDT 24
Peak memory 225164 kb
Host smart-d97c257a-40b2-404a-894d-2e2ef455d5c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030724442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.2030724442
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.2870317483
Short name T802
Test name
Test status
Simulation time 17131941 ps
CPU time 0.72 seconds
Started Jul 29 05:05:18 PM PDT 24
Finished Jul 29 05:05:19 PM PDT 24
Peak memory 205884 kb
Host smart-3b2a47f3-bc44-4344-bdec-4e6d19d7291c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870317483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
2870317483
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.1830673483
Short name T826
Test name
Test status
Simulation time 215173173 ps
CPU time 2.95 seconds
Started Jul 29 05:05:14 PM PDT 24
Finished Jul 29 05:05:17 PM PDT 24
Peak memory 233432 kb
Host smart-0d3b1b41-3a67-4176-bddd-f519dd4a2423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830673483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.1830673483
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.1322841269
Short name T832
Test name
Test status
Simulation time 18766497 ps
CPU time 0.81 seconds
Started Jul 29 05:05:15 PM PDT 24
Finished Jul 29 05:05:16 PM PDT 24
Peak memory 206988 kb
Host smart-e24efbae-727f-4696-aea0-13cbac3f44d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322841269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.1322841269
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.57378209
Short name T136
Test name
Test status
Simulation time 32568182028 ps
CPU time 236.58 seconds
Started Jul 29 05:05:15 PM PDT 24
Finished Jul 29 05:09:12 PM PDT 24
Peak memory 265168 kb
Host smart-9c8a1f3a-8b89-4f80-9966-0dc16a087922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57378209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.57378209
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.3259670978
Short name T588
Test name
Test status
Simulation time 25278202989 ps
CPU time 93.8 seconds
Started Jul 29 05:05:16 PM PDT 24
Finished Jul 29 05:06:50 PM PDT 24
Peak memory 249880 kb
Host smart-b9e2c368-a00f-4f42-b1ce-6cd81fd8f4b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259670978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.3259670978
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.2584693528
Short name T551
Test name
Test status
Simulation time 2156257744 ps
CPU time 9.02 seconds
Started Jul 29 05:05:16 PM PDT 24
Finished Jul 29 05:05:25 PM PDT 24
Peak memory 218488 kb
Host smart-d483f3fa-f4d0-46d5-94d8-b966feb50eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584693528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.2584693528
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.3381594044
Short name T442
Test name
Test status
Simulation time 76103969 ps
CPU time 2.37 seconds
Started Jul 29 05:05:19 PM PDT 24
Finished Jul 29 05:05:21 PM PDT 24
Peak memory 225288 kb
Host smart-02e39ef3-2c28-455f-92a4-e86025b5c56a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381594044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.3381594044
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.2842690972
Short name T339
Test name
Test status
Simulation time 29017456215 ps
CPU time 94.1 seconds
Started Jul 29 05:05:15 PM PDT 24
Finished Jul 29 05:06:49 PM PDT 24
Peak memory 241700 kb
Host smart-8bf6720d-d011-4903-8888-537a359bd38d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842690972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmd
s.2842690972
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/23.spi_device_intercept.1594063908
Short name T961
Test name
Test status
Simulation time 452344735 ps
CPU time 6.23 seconds
Started Jul 29 05:05:19 PM PDT 24
Finished Jul 29 05:05:25 PM PDT 24
Peak memory 225212 kb
Host smart-f7634309-3d06-4858-acc2-a488755879da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594063908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.1594063908
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.907173409
Short name T843
Test name
Test status
Simulation time 341303507 ps
CPU time 4.36 seconds
Started Jul 29 05:05:18 PM PDT 24
Finished Jul 29 05:05:23 PM PDT 24
Peak memory 225236 kb
Host smart-09475ef8-c946-4359-86d5-b5f91b88efa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907173409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.907173409
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.2731737167
Short name T1016
Test name
Test status
Simulation time 40046471080 ps
CPU time 17.86 seconds
Started Jul 29 05:05:15 PM PDT 24
Finished Jul 29 05:05:33 PM PDT 24
Peak memory 233516 kb
Host smart-58a96d9a-c632-4631-9957-6458a5622f5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731737167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.2731737167
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.2088492560
Short name T1002
Test name
Test status
Simulation time 1550088515 ps
CPU time 6.86 seconds
Started Jul 29 05:05:15 PM PDT 24
Finished Jul 29 05:05:22 PM PDT 24
Peak memory 225156 kb
Host smart-ee6f7fac-3d92-40a7-9a04-f4cf6c4a0ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088492560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.2088492560
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.104851826
Short name T900
Test name
Test status
Simulation time 2520024442 ps
CPU time 12.42 seconds
Started Jul 29 05:05:15 PM PDT 24
Finished Jul 29 05:05:27 PM PDT 24
Peak memory 221136 kb
Host smart-ed64c48b-2c51-4626-804d-f0a5f0ca167b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=104851826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dire
ct.104851826
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.2153662642
Short name T409
Test name
Test status
Simulation time 2267905783 ps
CPU time 21.15 seconds
Started Jul 29 05:05:19 PM PDT 24
Finished Jul 29 05:05:40 PM PDT 24
Peak memory 216988 kb
Host smart-2c716ceb-0a9a-4867-afdb-5e48f3d47dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153662642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.2153662642
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.770540111
Short name T380
Test name
Test status
Simulation time 774968798 ps
CPU time 2.52 seconds
Started Jul 29 05:05:15 PM PDT 24
Finished Jul 29 05:05:18 PM PDT 24
Peak memory 216896 kb
Host smart-1e4261c9-cc07-4129-b1ed-8944d83ae669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770540111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.770540111
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.1551091654
Short name T848
Test name
Test status
Simulation time 19146238 ps
CPU time 1.22 seconds
Started Jul 29 05:05:14 PM PDT 24
Finished Jul 29 05:05:15 PM PDT 24
Peak memory 216904 kb
Host smart-f3f794db-23d9-415c-8da0-fc09e9c490c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551091654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.1551091654
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.3913074350
Short name T439
Test name
Test status
Simulation time 121971615 ps
CPU time 0.76 seconds
Started Jul 29 05:05:16 PM PDT 24
Finished Jul 29 05:05:17 PM PDT 24
Peak memory 206480 kb
Host smart-340cac13-9d63-4a3b-a747-7407e1c63010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913074350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.3913074350
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.268855636
Short name T1005
Test name
Test status
Simulation time 808924114 ps
CPU time 2.9 seconds
Started Jul 29 05:05:15 PM PDT 24
Finished Jul 29 05:05:18 PM PDT 24
Peak memory 225276 kb
Host smart-9b0e5c0e-b0d7-4a7a-aae3-85ee6279d8f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268855636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.268855636
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.3286830284
Short name T960
Test name
Test status
Simulation time 13570508 ps
CPU time 0.71 seconds
Started Jul 29 05:05:24 PM PDT 24
Finished Jul 29 05:05:24 PM PDT 24
Peak memory 205748 kb
Host smart-10184935-9db7-4a6c-8dc1-034a5751b474
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286830284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
3286830284
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.2026458060
Short name T369
Test name
Test status
Simulation time 86494810 ps
CPU time 3.13 seconds
Started Jul 29 05:05:24 PM PDT 24
Finished Jul 29 05:05:27 PM PDT 24
Peak memory 225120 kb
Host smart-9fe4f1f2-5177-45f7-9467-55854e3c4bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026458060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.2026458060
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.2392789819
Short name T734
Test name
Test status
Simulation time 22769125 ps
CPU time 0.82 seconds
Started Jul 29 05:05:24 PM PDT 24
Finished Jul 29 05:05:25 PM PDT 24
Peak memory 206972 kb
Host smart-9e0ba636-9951-4886-9ab8-e5ade04d0257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392789819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.2392789819
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.3207011495
Short name T657
Test name
Test status
Simulation time 14453665 ps
CPU time 0.79 seconds
Started Jul 29 05:05:23 PM PDT 24
Finished Jul 29 05:05:24 PM PDT 24
Peak memory 216436 kb
Host smart-9db97d82-ea32-46ec-8f4a-400300c259e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207011495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.3207011495
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.1205571951
Short name T312
Test name
Test status
Simulation time 3727528373 ps
CPU time 22.13 seconds
Started Jul 29 05:05:24 PM PDT 24
Finished Jul 29 05:05:47 PM PDT 24
Peak memory 218384 kb
Host smart-404c5c61-9b3f-496b-97ac-af4acc09609f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205571951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.1205571951
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.1592139590
Short name T301
Test name
Test status
Simulation time 470212202 ps
CPU time 13.72 seconds
Started Jul 29 05:05:24 PM PDT 24
Finished Jul 29 05:05:38 PM PDT 24
Peak memory 233368 kb
Host smart-fc415ff5-a3d7-4f3e-8f0f-3de66ed8476f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592139590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.1592139590
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.1157854032
Short name T282
Test name
Test status
Simulation time 27206674371 ps
CPU time 71.55 seconds
Started Jul 29 05:05:22 PM PDT 24
Finished Jul 29 05:06:34 PM PDT 24
Peak memory 257284 kb
Host smart-0372acbb-b687-4122-8f76-2cf336ffc11b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157854032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmd
s.1157854032
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/24.spi_device_intercept.4182650046
Short name T654
Test name
Test status
Simulation time 1775764293 ps
CPU time 18.1 seconds
Started Jul 29 05:05:23 PM PDT 24
Finished Jul 29 05:05:42 PM PDT 24
Peak memory 233408 kb
Host smart-537de36f-a732-4dcf-81c4-536e0654368d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182650046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.4182650046
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.1692435515
Short name T460
Test name
Test status
Simulation time 1385621192 ps
CPU time 11.06 seconds
Started Jul 29 05:05:23 PM PDT 24
Finished Jul 29 05:05:34 PM PDT 24
Peak memory 249644 kb
Host smart-31e7a4b1-7b5f-4b55-a5ba-b99895fa85fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692435515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.1692435515
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.4148624101
Short name T895
Test name
Test status
Simulation time 1145680551 ps
CPU time 5.67 seconds
Started Jul 29 05:05:23 PM PDT 24
Finished Jul 29 05:05:29 PM PDT 24
Peak memory 240952 kb
Host smart-14a4763f-02eb-4655-b0c7-4bb73174d5c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148624101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.4148624101
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.1464230654
Short name T524
Test name
Test status
Simulation time 2017276160 ps
CPU time 14.29 seconds
Started Jul 29 05:05:24 PM PDT 24
Finished Jul 29 05:05:38 PM PDT 24
Peak memory 225300 kb
Host smart-95a437c9-9679-4c66-b2e6-3c869546f55d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464230654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.1464230654
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.2791619908
Short name T407
Test name
Test status
Simulation time 458937047 ps
CPU time 5.86 seconds
Started Jul 29 05:05:25 PM PDT 24
Finished Jul 29 05:05:31 PM PDT 24
Peak memory 223708 kb
Host smart-539935cb-43d5-4af1-9547-290f2413270a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2791619908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.2791619908
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.3005400618
Short name T305
Test name
Test status
Simulation time 5108133881 ps
CPU time 27.07 seconds
Started Jul 29 05:05:22 PM PDT 24
Finished Jul 29 05:05:50 PM PDT 24
Peak memory 217240 kb
Host smart-b91f62eb-02a0-444d-8e8a-02695efefcaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005400618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.3005400618
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.270170940
Short name T134
Test name
Test status
Simulation time 6522178666 ps
CPU time 19.99 seconds
Started Jul 29 05:05:24 PM PDT 24
Finished Jul 29 05:05:44 PM PDT 24
Peak memory 217100 kb
Host smart-162ac598-f904-4f0f-8159-d198a6b3b7b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270170940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.270170940
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.2576093652
Short name T823
Test name
Test status
Simulation time 117773037 ps
CPU time 1.69 seconds
Started Jul 29 05:05:23 PM PDT 24
Finished Jul 29 05:05:24 PM PDT 24
Peak memory 216972 kb
Host smart-147eb2cc-f8a0-45ba-9538-c98acf59365d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576093652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.2576093652
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.2100965593
Short name T27
Test name
Test status
Simulation time 89746716 ps
CPU time 0.94 seconds
Started Jul 29 05:05:25 PM PDT 24
Finished Jul 29 05:05:26 PM PDT 24
Peak memory 206612 kb
Host smart-3b0953d1-1090-4fd1-b815-4fb970019cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100965593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.2100965593
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.1264214248
Short name T666
Test name
Test status
Simulation time 230527146 ps
CPU time 4.06 seconds
Started Jul 29 05:05:24 PM PDT 24
Finished Jul 29 05:05:28 PM PDT 24
Peak memory 225248 kb
Host smart-d5e96c76-b876-4ee0-ac26-9a4a975b6d66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264214248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.1264214248
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.3742828868
Short name T686
Test name
Test status
Simulation time 12869885 ps
CPU time 0.69 seconds
Started Jul 29 05:05:38 PM PDT 24
Finished Jul 29 05:05:39 PM PDT 24
Peak memory 205756 kb
Host smart-5fad20cb-7991-49ac-bfaf-d33e20164677
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742828868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
3742828868
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.2215055837
Short name T735
Test name
Test status
Simulation time 129736285 ps
CPU time 2.48 seconds
Started Jul 29 05:05:39 PM PDT 24
Finished Jul 29 05:05:41 PM PDT 24
Peak memory 233284 kb
Host smart-9607cea3-6d1a-42e2-b153-62f8fab20927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215055837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.2215055837
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.1681082774
Short name T770
Test name
Test status
Simulation time 20622318 ps
CPU time 0.82 seconds
Started Jul 29 05:05:25 PM PDT 24
Finished Jul 29 05:05:26 PM PDT 24
Peak memory 207320 kb
Host smart-ed24edd2-979a-4439-afde-0d6e42293678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681082774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.1681082774
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.199169014
Short name T822
Test name
Test status
Simulation time 5958674552 ps
CPU time 57.65 seconds
Started Jul 29 05:05:35 PM PDT 24
Finished Jul 29 05:06:33 PM PDT 24
Peak memory 256784 kb
Host smart-86c91d16-f83b-414d-8a6d-fc500b4902ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199169014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.199169014
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.2654835143
Short name T951
Test name
Test status
Simulation time 48331650003 ps
CPU time 77.22 seconds
Started Jul 29 05:05:39 PM PDT 24
Finished Jul 29 05:06:57 PM PDT 24
Peak memory 225312 kb
Host smart-13903780-29af-402c-abe6-49b6e5f72581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654835143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.2654835143
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.3968714567
Short name T1008
Test name
Test status
Simulation time 94177154139 ps
CPU time 398.67 seconds
Started Jul 29 05:05:40 PM PDT 24
Finished Jul 29 05:12:19 PM PDT 24
Peak memory 249868 kb
Host smart-3450624d-e8c9-4298-9854-30e096382398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968714567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.3968714567
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.507437930
Short name T302
Test name
Test status
Simulation time 213045523 ps
CPU time 7.49 seconds
Started Jul 29 05:05:40 PM PDT 24
Finished Jul 29 05:05:48 PM PDT 24
Peak memory 233364 kb
Host smart-654b1a75-04d2-4a1a-a0ee-f6e813fad8d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507437930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.507437930
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.2142731621
Short name T595
Test name
Test status
Simulation time 5202449806 ps
CPU time 33.61 seconds
Started Jul 29 05:05:39 PM PDT 24
Finished Jul 29 05:06:12 PM PDT 24
Peak memory 250508 kb
Host smart-9cd7cc62-6395-4615-8c18-5ae397924b13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142731621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmd
s.2142731621
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_intercept.254213231
Short name T422
Test name
Test status
Simulation time 219118609 ps
CPU time 4.65 seconds
Started Jul 29 05:05:37 PM PDT 24
Finished Jul 29 05:05:41 PM PDT 24
Peak memory 233332 kb
Host smart-896b1906-8a47-4b91-837e-184fc26fde57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254213231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.254213231
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.3332780077
Short name T543
Test name
Test status
Simulation time 10438015242 ps
CPU time 37.67 seconds
Started Jul 29 05:05:39 PM PDT 24
Finished Jul 29 05:06:17 PM PDT 24
Peak memory 225376 kb
Host smart-52733710-c453-4213-bf26-3eed6022a022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332780077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.3332780077
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.1445128997
Short name T869
Test name
Test status
Simulation time 9412570731 ps
CPU time 15.64 seconds
Started Jul 29 05:05:35 PM PDT 24
Finished Jul 29 05:05:50 PM PDT 24
Peak memory 233452 kb
Host smart-71cc217d-4b41-4231-b547-ec4b3a3e39a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445128997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.1445128997
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.2250710528
Short name T683
Test name
Test status
Simulation time 601102278 ps
CPU time 3.33 seconds
Started Jul 29 05:05:37 PM PDT 24
Finished Jul 29 05:05:41 PM PDT 24
Peak memory 225204 kb
Host smart-25b8a561-e462-43c4-887a-1994c718c22c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250710528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.2250710528
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.738996089
Short name T682
Test name
Test status
Simulation time 2754341966 ps
CPU time 14.59 seconds
Started Jul 29 05:05:39 PM PDT 24
Finished Jul 29 05:05:54 PM PDT 24
Peak memory 221204 kb
Host smart-5e8ece55-d751-4a7c-9bce-3db935171b6a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=738996089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dire
ct.738996089
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.1777822445
Short name T15
Test name
Test status
Simulation time 7532754069 ps
CPU time 136.33 seconds
Started Jul 29 05:05:36 PM PDT 24
Finished Jul 29 05:07:53 PM PDT 24
Peak memory 252680 kb
Host smart-c6b8291d-c209-46f2-9515-f94ae26ceec3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777822445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.1777822445
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.3289680675
Short name T715
Test name
Test status
Simulation time 14783517714 ps
CPU time 16.46 seconds
Started Jul 29 05:05:39 PM PDT 24
Finished Jul 29 05:05:56 PM PDT 24
Peak memory 217064 kb
Host smart-8aa06551-40be-43c6-8913-c62e80aa5c7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289680675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.3289680675
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.2457017224
Short name T315
Test name
Test status
Simulation time 1045575147 ps
CPU time 5.3 seconds
Started Jul 29 05:05:25 PM PDT 24
Finished Jul 29 05:05:30 PM PDT 24
Peak memory 216884 kb
Host smart-80dbaf0e-3c52-43b0-bb82-061a96fb06f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457017224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.2457017224
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.256626486
Short name T485
Test name
Test status
Simulation time 177915579 ps
CPU time 2.44 seconds
Started Jul 29 05:05:38 PM PDT 24
Finished Jul 29 05:05:40 PM PDT 24
Peak memory 217016 kb
Host smart-f63f0c25-4753-42af-96c1-2d2b5f5ad1e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256626486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.256626486
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.3696856225
Short name T891
Test name
Test status
Simulation time 26396542 ps
CPU time 0.73 seconds
Started Jul 29 05:05:38 PM PDT 24
Finished Jul 29 05:05:38 PM PDT 24
Peak memory 206516 kb
Host smart-a2d6bf2a-11f2-4660-a5bc-2c8b71a69dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696856225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.3696856225
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.190464606
Short name T189
Test name
Test status
Simulation time 2884030445 ps
CPU time 8.48 seconds
Started Jul 29 05:05:38 PM PDT 24
Finished Jul 29 05:05:47 PM PDT 24
Peak memory 233484 kb
Host smart-7be2d407-e57b-4561-84f9-314de009bafe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190464606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.190464606
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.3366265941
Short name T352
Test name
Test status
Simulation time 61448085 ps
CPU time 0.72 seconds
Started Jul 29 05:05:36 PM PDT 24
Finished Jul 29 05:05:37 PM PDT 24
Peak memory 205788 kb
Host smart-e0697c61-d487-4bec-b495-6e943784bf7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366265941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
3366265941
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.4236231691
Short name T730
Test name
Test status
Simulation time 582413024 ps
CPU time 3.53 seconds
Started Jul 29 05:05:36 PM PDT 24
Finished Jul 29 05:05:40 PM PDT 24
Peak memory 233416 kb
Host smart-40242980-eda1-44b6-a02b-bc1a41997678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236231691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.4236231691
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.410101039
Short name T338
Test name
Test status
Simulation time 15034937 ps
CPU time 0.8 seconds
Started Jul 29 05:05:36 PM PDT 24
Finished Jul 29 05:05:37 PM PDT 24
Peak memory 207032 kb
Host smart-881d6c93-8256-4b97-bb62-a55e2c071a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410101039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.410101039
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.1872465841
Short name T334
Test name
Test status
Simulation time 42173668 ps
CPU time 0.77 seconds
Started Jul 29 05:05:37 PM PDT 24
Finished Jul 29 05:05:38 PM PDT 24
Peak memory 216472 kb
Host smart-b22d0ad7-7707-4657-b9d2-181d815372de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872465841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.1872465841
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.1003974689
Short name T229
Test name
Test status
Simulation time 8619166698 ps
CPU time 76.89 seconds
Started Jul 29 05:05:38 PM PDT 24
Finished Jul 29 05:06:55 PM PDT 24
Peak memory 225576 kb
Host smart-392723ab-cbfc-4066-a4a1-698546caf25a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003974689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.1003974689
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.1320062632
Short name T706
Test name
Test status
Simulation time 22160961158 ps
CPU time 20.04 seconds
Started Jul 29 05:05:36 PM PDT 24
Finished Jul 29 05:05:56 PM PDT 24
Peak memory 241716 kb
Host smart-c023c862-57ba-4e33-a31e-b87b1da52a41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320062632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmd
s.1320062632
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_intercept.2542776005
Short name T225
Test name
Test status
Simulation time 880735144 ps
CPU time 10.31 seconds
Started Jul 29 05:05:40 PM PDT 24
Finished Jul 29 05:05:50 PM PDT 24
Peak memory 229004 kb
Host smart-7c8ef099-cd61-4f82-99d7-b8c121016faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542776005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.2542776005
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.2826868219
Short name T740
Test name
Test status
Simulation time 1092012425 ps
CPU time 3.78 seconds
Started Jul 29 05:05:39 PM PDT 24
Finished Jul 29 05:05:43 PM PDT 24
Peak memory 225244 kb
Host smart-42fb96a3-5b14-481b-a363-55f9dd307422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826868219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.2826868219
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.3439975859
Short name T418
Test name
Test status
Simulation time 92319385 ps
CPU time 2.6 seconds
Started Jul 29 05:05:37 PM PDT 24
Finished Jul 29 05:05:40 PM PDT 24
Peak memory 233032 kb
Host smart-186390ed-567a-4872-b425-3501620ddca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439975859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.3439975859
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.2334629526
Short name T767
Test name
Test status
Simulation time 2237560135 ps
CPU time 7.96 seconds
Started Jul 29 05:05:38 PM PDT 24
Finished Jul 29 05:05:46 PM PDT 24
Peak memory 225476 kb
Host smart-a66f8531-7cc3-470b-8436-39e5e0fbeade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334629526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.2334629526
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.1533145208
Short name T700
Test name
Test status
Simulation time 613439679 ps
CPU time 3.42 seconds
Started Jul 29 05:05:38 PM PDT 24
Finished Jul 29 05:05:41 PM PDT 24
Peak memory 222172 kb
Host smart-9fbf9263-a5d3-4d7b-ac3e-0a8fb15d82eb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1533145208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.1533145208
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.4014332470
Short name T1015
Test name
Test status
Simulation time 8297682300 ps
CPU time 102.51 seconds
Started Jul 29 05:05:37 PM PDT 24
Finished Jul 29 05:07:20 PM PDT 24
Peak memory 250020 kb
Host smart-529aa235-bba6-411a-af90-db6f0da85626
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014332470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.4014332470
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.971174410
Short name T548
Test name
Test status
Simulation time 31624678007 ps
CPU time 38.09 seconds
Started Jul 29 05:05:36 PM PDT 24
Finished Jul 29 05:06:14 PM PDT 24
Peak memory 216912 kb
Host smart-f3d8411f-f314-4270-88a5-ed759931ba22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971174410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.971174410
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.680281879
Short name T25
Test name
Test status
Simulation time 4621524891 ps
CPU time 10.97 seconds
Started Jul 29 05:05:38 PM PDT 24
Finished Jul 29 05:05:49 PM PDT 24
Peak memory 217160 kb
Host smart-dc1f1ee4-51d3-4552-a722-45dc7098d560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680281879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.680281879
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.2491669841
Short name T508
Test name
Test status
Simulation time 20362105 ps
CPU time 0.69 seconds
Started Jul 29 05:05:37 PM PDT 24
Finished Jul 29 05:05:38 PM PDT 24
Peak memory 206132 kb
Host smart-e5c77f19-e7cd-4cb1-a5c8-43492d0ad1bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491669841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.2491669841
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.683846106
Short name T756
Test name
Test status
Simulation time 175768201 ps
CPU time 0.77 seconds
Started Jul 29 05:05:36 PM PDT 24
Finished Jul 29 05:05:37 PM PDT 24
Peak memory 206468 kb
Host smart-cfcdce53-c374-4c22-b212-d6e6cecc756d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683846106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.683846106
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.342623404
Short name T780
Test name
Test status
Simulation time 6881410944 ps
CPU time 7.75 seconds
Started Jul 29 05:05:39 PM PDT 24
Finished Jul 29 05:05:47 PM PDT 24
Peak memory 233444 kb
Host smart-e5875a46-affa-489e-97f8-b2dd0cda59c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342623404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.342623404
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.3185988871
Short name T72
Test name
Test status
Simulation time 12501779 ps
CPU time 0.74 seconds
Started Jul 29 05:05:41 PM PDT 24
Finished Jul 29 05:05:42 PM PDT 24
Peak memory 206228 kb
Host smart-cd066728-e683-47bc-96e2-ee4896a39199
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185988871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
3185988871
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.562044580
Short name T937
Test name
Test status
Simulation time 1032884525 ps
CPU time 10.85 seconds
Started Jul 29 05:05:44 PM PDT 24
Finished Jul 29 05:05:55 PM PDT 24
Peak memory 225252 kb
Host smart-ddadd703-4876-4348-bae9-9a0422f59585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562044580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.562044580
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.4200146459
Short name T659
Test name
Test status
Simulation time 35967102 ps
CPU time 0.77 seconds
Started Jul 29 05:05:37 PM PDT 24
Finished Jul 29 05:05:37 PM PDT 24
Peak memory 207000 kb
Host smart-9522a9bd-e146-492a-90f0-2a2697087e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200146459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.4200146459
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.2739228545
Short name T935
Test name
Test status
Simulation time 30911399776 ps
CPU time 55.9 seconds
Started Jul 29 05:05:41 PM PDT 24
Finished Jul 29 05:06:37 PM PDT 24
Peak memory 225248 kb
Host smart-82745ecc-e8b1-4415-841b-0b04b146a20d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739228545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.2739228545
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.2242709234
Short name T165
Test name
Test status
Simulation time 82966095052 ps
CPU time 193.58 seconds
Started Jul 29 05:05:44 PM PDT 24
Finished Jul 29 05:08:57 PM PDT 24
Peak memory 255976 kb
Host smart-8f3febaa-2472-400c-baaf-88a9e40de485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242709234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.2242709234
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.655714221
Short name T350
Test name
Test status
Simulation time 284185900 ps
CPU time 3.28 seconds
Started Jul 29 05:05:40 PM PDT 24
Finished Jul 29 05:05:44 PM PDT 24
Peak memory 225128 kb
Host smart-febf057c-27a1-4076-811c-cbf484a1716c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655714221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.655714221
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_intercept.4287316536
Short name T432
Test name
Test status
Simulation time 4525931945 ps
CPU time 10.61 seconds
Started Jul 29 05:05:44 PM PDT 24
Finished Jul 29 05:05:55 PM PDT 24
Peak memory 233452 kb
Host smart-bc6ac39a-b54b-4551-b7d6-272e0b898d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287316536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.4287316536
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.3142505556
Short name T854
Test name
Test status
Simulation time 424021163 ps
CPU time 4.38 seconds
Started Jul 29 05:05:41 PM PDT 24
Finished Jul 29 05:05:45 PM PDT 24
Peak memory 225224 kb
Host smart-dbba7b22-2b89-4e8e-850d-cacb84b2a0d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142505556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.3142505556
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.3036118409
Short name T198
Test name
Test status
Simulation time 13947337548 ps
CPU time 14.58 seconds
Started Jul 29 05:05:42 PM PDT 24
Finished Jul 29 05:05:56 PM PDT 24
Peak memory 235616 kb
Host smart-4d5db8cd-34f1-4f45-b0bc-85b814525bc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036118409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.3036118409
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.1888183686
Short name T699
Test name
Test status
Simulation time 4566222838 ps
CPU time 5.87 seconds
Started Jul 29 05:05:39 PM PDT 24
Finished Jul 29 05:05:45 PM PDT 24
Peak memory 233548 kb
Host smart-65763844-6659-4a91-a1fd-5ad55d34ee1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888183686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.1888183686
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.228469743
Short name T841
Test name
Test status
Simulation time 2377196482 ps
CPU time 3.3 seconds
Started Jul 29 05:05:43 PM PDT 24
Finished Jul 29 05:05:46 PM PDT 24
Peak memory 219948 kb
Host smart-9b5eeabd-26fe-44fb-824d-96abe22d215b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=228469743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dire
ct.228469743
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.4197260964
Short name T1003
Test name
Test status
Simulation time 189447109380 ps
CPU time 560.92 seconds
Started Jul 29 05:05:41 PM PDT 24
Finished Jul 29 05:15:02 PM PDT 24
Peak memory 273680 kb
Host smart-ef39ca0a-2d58-4522-9338-67317d38d3ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197260964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.4197260964
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.4033932837
Short name T307
Test name
Test status
Simulation time 2151832009 ps
CPU time 12.49 seconds
Started Jul 29 05:05:38 PM PDT 24
Finished Jul 29 05:05:51 PM PDT 24
Peak memory 217076 kb
Host smart-cd6f3546-762e-4c07-b738-282ef42c2e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033932837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.4033932837
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.4185670009
Short name T437
Test name
Test status
Simulation time 54271162915 ps
CPU time 21.38 seconds
Started Jul 29 05:05:39 PM PDT 24
Finished Jul 29 05:06:01 PM PDT 24
Peak memory 217008 kb
Host smart-2f929745-edbc-4665-a769-49fd1bf83c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185670009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.4185670009
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.3816940250
Short name T768
Test name
Test status
Simulation time 39507122 ps
CPU time 1.08 seconds
Started Jul 29 05:05:39 PM PDT 24
Finished Jul 29 05:05:40 PM PDT 24
Peak memory 208556 kb
Host smart-913b40d6-f101-4bdc-866a-59fe7700a442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816940250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.3816940250
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.2718701136
Short name T720
Test name
Test status
Simulation time 84472263 ps
CPU time 0.88 seconds
Started Jul 29 05:05:38 PM PDT 24
Finished Jul 29 05:05:39 PM PDT 24
Peak memory 206588 kb
Host smart-45be178f-4ff5-4bb1-9ecc-5b54d1ee6c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718701136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.2718701136
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.740069932
Short name T211
Test name
Test status
Simulation time 2118789434 ps
CPU time 4.83 seconds
Started Jul 29 05:05:43 PM PDT 24
Finished Jul 29 05:05:48 PM PDT 24
Peak memory 225252 kb
Host smart-6c1b2566-8f51-4d7d-acaa-88458d839394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740069932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.740069932
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.2281879683
Short name T389
Test name
Test status
Simulation time 13634076 ps
CPU time 0.67 seconds
Started Jul 29 05:05:52 PM PDT 24
Finished Jul 29 05:05:53 PM PDT 24
Peak memory 205860 kb
Host smart-362dcc3d-6fcc-43a3-8751-1623f0b12729
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281879683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
2281879683
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.1462175920
Short name T97
Test name
Test status
Simulation time 275452297 ps
CPU time 2.9 seconds
Started Jul 29 05:05:52 PM PDT 24
Finished Jul 29 05:05:55 PM PDT 24
Peak memory 233472 kb
Host smart-ec14af96-6a8e-4a06-9e4d-0b0ec26acfdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462175920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.1462175920
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.3822390566
Short name T850
Test name
Test status
Simulation time 17610778 ps
CPU time 0.77 seconds
Started Jul 29 05:05:41 PM PDT 24
Finished Jul 29 05:05:42 PM PDT 24
Peak memory 207084 kb
Host smart-051b32f6-9612-4122-bc17-565058bed852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822390566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.3822390566
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.51966815
Short name T417
Test name
Test status
Simulation time 21214081790 ps
CPU time 65.75 seconds
Started Jul 29 05:05:47 PM PDT 24
Finished Jul 29 05:06:53 PM PDT 24
Peak memory 241756 kb
Host smart-1fe78e9e-ff3d-45ad-8c82-4da5034154eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51966815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.51966815
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.2222450830
Short name T39
Test name
Test status
Simulation time 32216112817 ps
CPU time 336.47 seconds
Started Jul 29 05:05:47 PM PDT 24
Finished Jul 29 05:11:24 PM PDT 24
Peak memory 273164 kb
Host smart-17252576-dd32-447a-a92c-3f8a242f7b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222450830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.2222450830
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.282034735
Short name T1007
Test name
Test status
Simulation time 110845072270 ps
CPU time 524.32 seconds
Started Jul 29 05:05:48 PM PDT 24
Finished Jul 29 05:14:32 PM PDT 24
Peak memory 257660 kb
Host smart-25488f53-319b-42b1-a1ae-f1b22080e9a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282034735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idle
.282034735
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.1433704348
Short name T608
Test name
Test status
Simulation time 58393844 ps
CPU time 2.82 seconds
Started Jul 29 05:05:49 PM PDT 24
Finished Jul 29 05:05:52 PM PDT 24
Peak memory 225264 kb
Host smart-1085e45f-bd13-40ba-a975-c5f9e77c92f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433704348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.1433704348
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.4094010530
Short name T269
Test name
Test status
Simulation time 104079955579 ps
CPU time 161.94 seconds
Started Jul 29 05:05:47 PM PDT 24
Finished Jul 29 05:08:29 PM PDT 24
Peak memory 249836 kb
Host smart-50cf10f4-e88b-422f-b89a-5fd0f23f6704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094010530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmd
s.4094010530
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_intercept.1203355667
Short name T987
Test name
Test status
Simulation time 328492134 ps
CPU time 2.27 seconds
Started Jul 29 05:05:48 PM PDT 24
Finished Jul 29 05:05:51 PM PDT 24
Peak memory 225216 kb
Host smart-ba8022ba-9cba-4b3a-b103-c1d3390c0e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203355667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.1203355667
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.1028085534
Short name T596
Test name
Test status
Simulation time 556089483 ps
CPU time 3.81 seconds
Started Jul 29 05:05:48 PM PDT 24
Finished Jul 29 05:05:52 PM PDT 24
Peak memory 225296 kb
Host smart-e1096c0b-e42a-4253-8d77-12ac2d7524ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028085534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.1028085534
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.474875636
Short name T936
Test name
Test status
Simulation time 8752604711 ps
CPU time 26.46 seconds
Started Jul 29 05:05:41 PM PDT 24
Finished Jul 29 05:06:07 PM PDT 24
Peak memory 233500 kb
Host smart-cdbd976d-7205-4660-a72b-d792badf27bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474875636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swap
.474875636
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.1969031706
Short name T579
Test name
Test status
Simulation time 115964503 ps
CPU time 2.32 seconds
Started Jul 29 05:05:46 PM PDT 24
Finished Jul 29 05:05:48 PM PDT 24
Peak memory 233008 kb
Host smart-207bb868-bfb3-4ac5-9f80-87e9e4776461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969031706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.1969031706
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.3875955109
Short name T599
Test name
Test status
Simulation time 1347495739 ps
CPU time 10.18 seconds
Started Jul 29 05:05:47 PM PDT 24
Finished Jul 29 05:05:57 PM PDT 24
Peak memory 220992 kb
Host smart-83d1ed69-4ac1-4f12-9463-52d6de4b5893
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3875955109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.3875955109
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.3012240077
Short name T830
Test name
Test status
Simulation time 29176448885 ps
CPU time 56.12 seconds
Started Jul 29 05:05:56 PM PDT 24
Finished Jul 29 05:06:52 PM PDT 24
Peak memory 249924 kb
Host smart-8e01c0fe-d35c-4df4-93d1-23de3df7ec26
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012240077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.3012240077
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.4134058145
Short name T499
Test name
Test status
Simulation time 6474524332 ps
CPU time 29.75 seconds
Started Jul 29 05:05:41 PM PDT 24
Finished Jul 29 05:06:11 PM PDT 24
Peak memory 217052 kb
Host smart-8d6f5d17-a58d-443f-8ac4-11a1580cbb6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134058145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.4134058145
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.1525320532
Short name T531
Test name
Test status
Simulation time 2230501953 ps
CPU time 3.75 seconds
Started Jul 29 05:05:45 PM PDT 24
Finished Jul 29 05:05:49 PM PDT 24
Peak memory 216944 kb
Host smart-0353f582-94c3-43fd-97d1-f8a0df9ab223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525320532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.1525320532
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.2521708174
Short name T354
Test name
Test status
Simulation time 17775915 ps
CPU time 0.78 seconds
Started Jul 29 05:05:45 PM PDT 24
Finished Jul 29 05:05:46 PM PDT 24
Peak memory 206504 kb
Host smart-43268a06-5500-4622-b112-a66151210a20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521708174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.2521708174
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.2477130691
Short name T83
Test name
Test status
Simulation time 141414715 ps
CPU time 0.88 seconds
Started Jul 29 05:05:45 PM PDT 24
Finished Jul 29 05:05:46 PM PDT 24
Peak memory 206996 kb
Host smart-1b8a31e8-446d-4b04-8d60-19517e311457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477130691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.2477130691
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.2902479184
Short name T754
Test name
Test status
Simulation time 1951327713 ps
CPU time 9.5 seconds
Started Jul 29 05:05:52 PM PDT 24
Finished Jul 29 05:06:02 PM PDT 24
Peak memory 240716 kb
Host smart-a5119e1b-9796-4d69-b5a9-39041f1e4c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902479184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.2902479184
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.1158122042
Short name T782
Test name
Test status
Simulation time 11092894 ps
CPU time 0.71 seconds
Started Jul 29 05:05:56 PM PDT 24
Finished Jul 29 05:05:57 PM PDT 24
Peak memory 205872 kb
Host smart-404009e5-b826-493a-99a8-7ffa2fbf695a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158122042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
1158122042
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.1418149415
Short name T243
Test name
Test status
Simulation time 177488049 ps
CPU time 2.75 seconds
Started Jul 29 05:05:59 PM PDT 24
Finished Jul 29 05:06:02 PM PDT 24
Peak memory 233456 kb
Host smart-20494237-f597-4345-966a-acec6ffd24cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418149415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.1418149415
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.4019510480
Short name T648
Test name
Test status
Simulation time 32182755 ps
CPU time 0.79 seconds
Started Jul 29 05:05:47 PM PDT 24
Finished Jul 29 05:05:48 PM PDT 24
Peak memory 207056 kb
Host smart-d32684ec-4c7b-4c0e-9a79-c1f87eb76fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019510480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.4019510480
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.221106378
Short name T290
Test name
Test status
Simulation time 21777746734 ps
CPU time 83.49 seconds
Started Jul 29 05:05:54 PM PDT 24
Finished Jul 29 05:07:18 PM PDT 24
Peak memory 239236 kb
Host smart-a9eb237f-5f8d-4161-bd90-9dc89ce27f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221106378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.221106378
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.1521165071
Short name T946
Test name
Test status
Simulation time 3981755017 ps
CPU time 88.79 seconds
Started Jul 29 05:06:02 PM PDT 24
Finished Jul 29 05:07:31 PM PDT 24
Peak memory 260948 kb
Host smart-c718c702-f473-4709-97b4-7585f26fc0e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521165071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.1521165071
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.1640909137
Short name T849
Test name
Test status
Simulation time 12172557430 ps
CPU time 28.33 seconds
Started Jul 29 05:05:55 PM PDT 24
Finished Jul 29 05:06:23 PM PDT 24
Peak memory 225352 kb
Host smart-bd6835b9-8b19-4c27-8104-55991eddcb19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640909137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.1640909137
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.1915577612
Short name T176
Test name
Test status
Simulation time 13627260892 ps
CPU time 102.57 seconds
Started Jul 29 05:05:54 PM PDT 24
Finished Jul 29 05:07:37 PM PDT 24
Peak memory 241656 kb
Host smart-126b4ca8-1c2f-4ec9-bc97-177abeea609f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915577612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmd
s.1915577612
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_intercept.3361143307
Short name T748
Test name
Test status
Simulation time 1831715425 ps
CPU time 4.9 seconds
Started Jul 29 05:05:50 PM PDT 24
Finished Jul 29 05:05:55 PM PDT 24
Peak memory 225200 kb
Host smart-b926731d-c8f6-45d2-9b83-cb60b6df76e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361143307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.3361143307
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.103471794
Short name T135
Test name
Test status
Simulation time 15102048456 ps
CPU time 113.52 seconds
Started Jul 29 05:05:52 PM PDT 24
Finished Jul 29 05:07:45 PM PDT 24
Peak memory 241328 kb
Host smart-44d714ae-4406-4b74-b545-299c443375c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103471794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.103471794
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.3499995770
Short name T834
Test name
Test status
Simulation time 331729467 ps
CPU time 5.41 seconds
Started Jul 29 05:05:50 PM PDT 24
Finished Jul 29 05:05:56 PM PDT 24
Peak memory 233448 kb
Host smart-221bb13b-2486-4eeb-940b-06fae106e9aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499995770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.3499995770
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.1264212685
Short name T429
Test name
Test status
Simulation time 15243335641 ps
CPU time 12.01 seconds
Started Jul 29 05:05:53 PM PDT 24
Finished Jul 29 05:06:05 PM PDT 24
Peak memory 225328 kb
Host smart-a48dea92-9398-4b8e-b1a9-f55ffd408aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264212685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.1264212685
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.3347336
Short name T457
Test name
Test status
Simulation time 1344184199 ps
CPU time 18.99 seconds
Started Jul 29 05:05:55 PM PDT 24
Finished Jul 29 05:06:14 PM PDT 24
Peak memory 220628 kb
Host smart-d671757c-9e0e-4b06-b746-9a416ac9a041
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3347336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_direct.3347336
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.1002838132
Short name T160
Test name
Test status
Simulation time 5999438388 ps
CPU time 36.78 seconds
Started Jul 29 05:05:55 PM PDT 24
Finished Jul 29 05:06:32 PM PDT 24
Peak memory 249964 kb
Host smart-ca78a06a-de88-448b-9488-226f9882cfca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002838132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.1002838132
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.737615727
Short name T846
Test name
Test status
Simulation time 5902577836 ps
CPU time 36.82 seconds
Started Jul 29 05:05:53 PM PDT 24
Finished Jul 29 05:06:30 PM PDT 24
Peak memory 220656 kb
Host smart-8a919108-3fbe-4bda-826a-eca077957501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737615727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.737615727
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.3678279716
Short name T952
Test name
Test status
Simulation time 576417795 ps
CPU time 2.19 seconds
Started Jul 29 05:05:56 PM PDT 24
Finished Jul 29 05:05:58 PM PDT 24
Peak memory 216708 kb
Host smart-3f381460-dbdd-4cc4-96e1-b3481c0f20a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678279716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.3678279716
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.4070795949
Short name T319
Test name
Test status
Simulation time 144618473 ps
CPU time 7.87 seconds
Started Jul 29 05:05:48 PM PDT 24
Finished Jul 29 05:05:56 PM PDT 24
Peak memory 216892 kb
Host smart-90332402-be1b-4f24-a629-ef58809a9542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070795949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.4070795949
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.1716089991
Short name T587
Test name
Test status
Simulation time 168482046 ps
CPU time 0.74 seconds
Started Jul 29 05:05:56 PM PDT 24
Finished Jul 29 05:05:57 PM PDT 24
Peak memory 206552 kb
Host smart-2198ef74-b79b-4953-be3a-f0f39f42f978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716089991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.1716089991
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.3796035115
Short name T983
Test name
Test status
Simulation time 3719733405 ps
CPU time 11.77 seconds
Started Jul 29 05:05:48 PM PDT 24
Finished Jul 29 05:06:00 PM PDT 24
Peak memory 233480 kb
Host smart-140db737-badf-429c-b440-1fe09688b3b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796035115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.3796035115
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.3430816722
Short name T722
Test name
Test status
Simulation time 34171664 ps
CPU time 0.72 seconds
Started Jul 29 05:03:38 PM PDT 24
Finished Jul 29 05:03:39 PM PDT 24
Peak memory 205788 kb
Host smart-b7a7b0e1-572e-4b0a-8c1f-65f4eba2258a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430816722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.3
430816722
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.3597159520
Short name T324
Test name
Test status
Simulation time 36119139 ps
CPU time 2.48 seconds
Started Jul 29 05:03:33 PM PDT 24
Finished Jul 29 05:03:36 PM PDT 24
Peak memory 233084 kb
Host smart-d9e2c16d-8b7c-4c8d-942a-1857ee67dad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597159520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.3597159520
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.3873622265
Short name T70
Test name
Test status
Simulation time 37178385 ps
CPU time 0.82 seconds
Started Jul 29 05:03:31 PM PDT 24
Finished Jul 29 05:03:32 PM PDT 24
Peak memory 206944 kb
Host smart-2818145b-5bfe-4462-ace5-72ac02f4bb97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873622265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.3873622265
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.3977983949
Short name T470
Test name
Test status
Simulation time 111689066922 ps
CPU time 153.19 seconds
Started Jul 29 05:03:36 PM PDT 24
Finished Jul 29 05:06:09 PM PDT 24
Peak memory 255388 kb
Host smart-1432f870-a370-4161-9f98-f8984a368e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977983949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.3977983949
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.298432782
Short name T270
Test name
Test status
Simulation time 38350772828 ps
CPU time 197.47 seconds
Started Jul 29 05:03:41 PM PDT 24
Finished Jul 29 05:06:59 PM PDT 24
Peak memory 249980 kb
Host smart-60cfa31a-78cc-42e3-a14f-ca86ea0358b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298432782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.298432782
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.968284155
Short name T771
Test name
Test status
Simulation time 634865828 ps
CPU time 5.58 seconds
Started Jul 29 05:03:39 PM PDT 24
Finished Jul 29 05:03:45 PM PDT 24
Peak memory 225252 kb
Host smart-0e0f71c5-40e8-4059-a651-92d91a4870f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968284155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.968284155
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.2267742223
Short name T992
Test name
Test status
Simulation time 1684786000 ps
CPU time 32.23 seconds
Started Jul 29 05:03:36 PM PDT 24
Finished Jul 29 05:04:09 PM PDT 24
Peak memory 249796 kb
Host smart-d5abdd2d-cc24-4119-807d-b420c3223620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267742223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds
.2267742223
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_intercept.3235632037
Short name T787
Test name
Test status
Simulation time 5618740446 ps
CPU time 17.21 seconds
Started Jul 29 05:03:32 PM PDT 24
Finished Jul 29 05:03:50 PM PDT 24
Peak memory 225192 kb
Host smart-f67f469e-b829-439a-92e0-dd0df5906af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235632037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.3235632037
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.321956986
Short name T921
Test name
Test status
Simulation time 12690506407 ps
CPU time 120.18 seconds
Started Jul 29 05:03:31 PM PDT 24
Finished Jul 29 05:05:32 PM PDT 24
Peak memory 240608 kb
Host smart-90f9a291-4326-4d23-a282-0ab873ba3c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321956986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.321956986
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.3935829625
Short name T592
Test name
Test status
Simulation time 56929903 ps
CPU time 1.09 seconds
Started Jul 29 05:03:32 PM PDT 24
Finished Jul 29 05:03:33 PM PDT 24
Peak memory 217008 kb
Host smart-c21b8de5-0a58-4428-b269-8c8068bbb917
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935829625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.spi_device_mem_parity.3935829625
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.884831298
Short name T536
Test name
Test status
Simulation time 90434415 ps
CPU time 2.2 seconds
Started Jul 29 05:03:31 PM PDT 24
Finished Jul 29 05:03:34 PM PDT 24
Peak memory 223720 kb
Host smart-53d94ef5-3e53-430c-be83-aedbde916142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884831298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap.
884831298
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.1490219261
Short name T902
Test name
Test status
Simulation time 166303378 ps
CPU time 2.09 seconds
Started Jul 29 05:03:34 PM PDT 24
Finished Jul 29 05:03:36 PM PDT 24
Peak memory 225200 kb
Host smart-8544813a-9d1e-454e-aa66-4a54e344d89e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490219261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.1490219261
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.1250132795
Short name T968
Test name
Test status
Simulation time 1558796556 ps
CPU time 6.53 seconds
Started Jul 29 05:03:37 PM PDT 24
Finished Jul 29 05:03:43 PM PDT 24
Peak memory 219536 kb
Host smart-af648269-d6d0-488a-a649-b6e5e9834d0f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1250132795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.1250132795
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.1633667313
Short name T77
Test name
Test status
Simulation time 55487285 ps
CPU time 1.09 seconds
Started Jul 29 05:03:38 PM PDT 24
Finished Jul 29 05:03:39 PM PDT 24
Peak memory 235556 kb
Host smart-6522a9b3-6f98-458f-a787-2c81b943deab
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633667313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.1633667313
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.2089452645
Short name T897
Test name
Test status
Simulation time 8769418268 ps
CPU time 82.78 seconds
Started Jul 29 05:03:51 PM PDT 24
Finished Jul 29 05:05:14 PM PDT 24
Peak memory 249676 kb
Host smart-12995e7f-83ff-4903-80ed-f723daf962dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089452645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.2089452645
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.281058972
Short name T444
Test name
Test status
Simulation time 2010114783 ps
CPU time 11.03 seconds
Started Jul 29 05:03:31 PM PDT 24
Finished Jul 29 05:03:42 PM PDT 24
Peak memory 217004 kb
Host smart-34301084-91fa-481d-b9a0-398ea70e47b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281058972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.281058972
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.1139591668
Short name T438
Test name
Test status
Simulation time 9789525419 ps
CPU time 14.54 seconds
Started Jul 29 05:03:32 PM PDT 24
Finished Jul 29 05:03:47 PM PDT 24
Peak memory 217024 kb
Host smart-bd86fa0c-7bc2-4587-a104-071dfb806bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139591668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.1139591668
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.3796204222
Short name T433
Test name
Test status
Simulation time 602207134 ps
CPU time 2.88 seconds
Started Jul 29 05:03:31 PM PDT 24
Finished Jul 29 05:03:34 PM PDT 24
Peak memory 216936 kb
Host smart-a2b572b4-214d-40c2-97a4-6d614af45636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796204222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.3796204222
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.691348692
Short name T325
Test name
Test status
Simulation time 68386590 ps
CPU time 0.77 seconds
Started Jul 29 05:03:31 PM PDT 24
Finished Jul 29 05:03:32 PM PDT 24
Peak memory 206456 kb
Host smart-c245bd2d-c160-4479-878f-cb3a5faba686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691348692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.691348692
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.572368820
Short name T637
Test name
Test status
Simulation time 22128546503 ps
CPU time 6.85 seconds
Started Jul 29 05:03:31 PM PDT 24
Finished Jul 29 05:03:38 PM PDT 24
Peak memory 233484 kb
Host smart-17467e38-08f3-4575-84ae-712bbb71c191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572368820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.572368820
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.385107965
Short name T784
Test name
Test status
Simulation time 46029897 ps
CPU time 0.73 seconds
Started Jul 29 05:06:06 PM PDT 24
Finished Jul 29 05:06:07 PM PDT 24
Peak memory 205232 kb
Host smart-05d0fc03-58b5-4d5d-b2b6-61294d809f43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385107965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.385107965
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.1771211204
Short name T93
Test name
Test status
Simulation time 521557353 ps
CPU time 7.4 seconds
Started Jul 29 05:05:53 PM PDT 24
Finished Jul 29 05:06:01 PM PDT 24
Peak memory 225192 kb
Host smart-8684e84a-a11a-4b9a-acd9-3ef0e719e217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771211204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.1771211204
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.4265260523
Short name T480
Test name
Test status
Simulation time 51666738 ps
CPU time 0.83 seconds
Started Jul 29 05:05:55 PM PDT 24
Finished Jul 29 05:05:56 PM PDT 24
Peak memory 207376 kb
Host smart-38a20d88-1697-4d70-9f8a-90d641f73ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265260523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.4265260523
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.1417532214
Short name T227
Test name
Test status
Simulation time 46557942300 ps
CPU time 57.66 seconds
Started Jul 29 05:06:03 PM PDT 24
Finished Jul 29 05:07:01 PM PDT 24
Peak memory 249848 kb
Host smart-08490cdb-f73b-4f97-a70e-080231406083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417532214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.1417532214
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.349402502
Short name T186
Test name
Test status
Simulation time 166145828211 ps
CPU time 233.81 seconds
Started Jul 29 05:06:06 PM PDT 24
Finished Jul 29 05:10:00 PM PDT 24
Peak memory 255712 kb
Host smart-f16f09d1-3ada-4f10-b7e3-76de0a90ade5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349402502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.349402502
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.3345830816
Short name T963
Test name
Test status
Simulation time 211705127 ps
CPU time 2.76 seconds
Started Jul 29 05:06:09 PM PDT 24
Finished Jul 29 05:06:12 PM PDT 24
Peak memory 233464 kb
Host smart-0d604505-7613-49b3-b827-686cd1a86cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345830816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.3345830816
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.2021423527
Short name T972
Test name
Test status
Simulation time 25359146820 ps
CPU time 186.5 seconds
Started Jul 29 05:05:59 PM PDT 24
Finished Jul 29 05:09:06 PM PDT 24
Peak memory 257032 kb
Host smart-60f86b9a-8fc4-495b-848e-230ba61d2ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021423527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmd
s.2021423527
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.2334044024
Short name T534
Test name
Test status
Simulation time 8544569571 ps
CPU time 26.33 seconds
Started Jul 29 05:05:56 PM PDT 24
Finished Jul 29 05:06:22 PM PDT 24
Peak memory 234996 kb
Host smart-213a1ecf-10aa-4fad-94df-cb7b128a6d26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334044024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.2334044024
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.2542510978
Short name T486
Test name
Test status
Simulation time 157214246 ps
CPU time 2.17 seconds
Started Jul 29 05:05:53 PM PDT 24
Finished Jul 29 05:05:56 PM PDT 24
Peak memory 223424 kb
Host smart-ba4f9cc8-075b-422b-a79d-10e3eadb5aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542510978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.2542510978
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.873247273
Short name T28
Test name
Test status
Simulation time 480508639 ps
CPU time 3.16 seconds
Started Jul 29 05:05:55 PM PDT 24
Finished Jul 29 05:05:59 PM PDT 24
Peak memory 233416 kb
Host smart-f5a0d167-d16a-42b0-8d7d-f54735283418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873247273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.873247273
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.2746421033
Short name T698
Test name
Test status
Simulation time 177603222 ps
CPU time 3.63 seconds
Started Jul 29 05:05:58 PM PDT 24
Finished Jul 29 05:06:02 PM PDT 24
Peak memory 220324 kb
Host smart-7d755215-e88b-4f1e-bd9a-15f36c25ff4a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2746421033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.2746421033
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.58087376
Short name T145
Test name
Test status
Simulation time 8058807587 ps
CPU time 78.03 seconds
Started Jul 29 05:06:04 PM PDT 24
Finished Jul 29 05:07:22 PM PDT 24
Peak memory 238328 kb
Host smart-57a2ae9b-e8a2-4142-9654-d6ce49e9eb0f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58087376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stress
_all.58087376
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.3696901621
Short name T973
Test name
Test status
Simulation time 15622081776 ps
CPU time 40.69 seconds
Started Jul 29 05:05:59 PM PDT 24
Finished Jul 29 05:06:40 PM PDT 24
Peak memory 217096 kb
Host smart-6e74ea02-e039-4ff5-844d-ece24e0495e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696901621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.3696901621
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.2422846537
Short name T451
Test name
Test status
Simulation time 35535362063 ps
CPU time 13.12 seconds
Started Jul 29 05:05:58 PM PDT 24
Finished Jul 29 05:06:11 PM PDT 24
Peak memory 217028 kb
Host smart-a7e585f0-ecc5-4194-a524-3c56d551bd50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422846537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.2422846537
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.3046947317
Short name T620
Test name
Test status
Simulation time 74393089 ps
CPU time 2.05 seconds
Started Jul 29 05:05:53 PM PDT 24
Finished Jul 29 05:05:55 PM PDT 24
Peak memory 216876 kb
Host smart-e0a97ebc-e039-4c68-acb2-d8e7d1b1ef9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046947317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.3046947317
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.3052262325
Short name T778
Test name
Test status
Simulation time 175782498 ps
CPU time 0.94 seconds
Started Jul 29 05:05:55 PM PDT 24
Finished Jul 29 05:05:56 PM PDT 24
Peak memory 206900 kb
Host smart-9d853abd-8b1d-4cf1-b303-b47acb73be8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052262325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.3052262325
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.3657302723
Short name T320
Test name
Test status
Simulation time 32522761 ps
CPU time 2.51 seconds
Started Jul 29 05:05:59 PM PDT 24
Finished Jul 29 05:06:02 PM PDT 24
Peak memory 233048 kb
Host smart-bc16474e-4b80-4e87-ad38-75741b0b3f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657302723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.3657302723
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.1320830448
Short name T669
Test name
Test status
Simulation time 19441063 ps
CPU time 0.7 seconds
Started Jul 29 05:06:07 PM PDT 24
Finished Jul 29 05:06:08 PM PDT 24
Peak memory 205256 kb
Host smart-345ffb4d-5438-4e58-9102-83405077d568
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320830448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
1320830448
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.802143953
Short name T228
Test name
Test status
Simulation time 1130998546 ps
CPU time 5.32 seconds
Started Jul 29 05:06:09 PM PDT 24
Finished Jul 29 05:06:14 PM PDT 24
Peak memory 233460 kb
Host smart-e23a720d-b8fe-4237-930c-1161cdccbcb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802143953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.802143953
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.963039993
Short name T871
Test name
Test status
Simulation time 53971317 ps
CPU time 0.8 seconds
Started Jul 29 05:06:00 PM PDT 24
Finished Jul 29 05:06:01 PM PDT 24
Peak memory 207376 kb
Host smart-de447d22-3d13-4163-96d0-980136151e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963039993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.963039993
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.3987971783
Short name T52
Test name
Test status
Simulation time 37239755161 ps
CPU time 73.53 seconds
Started Jul 29 05:06:10 PM PDT 24
Finished Jul 29 05:07:23 PM PDT 24
Peak memory 255920 kb
Host smart-4ac1fd61-311f-40c1-a3b6-9215cfef6b0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987971783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.3987971783
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.2448390526
Short name T668
Test name
Test status
Simulation time 7883325790 ps
CPU time 130.29 seconds
Started Jul 29 05:06:06 PM PDT 24
Finished Jul 29 05:08:17 PM PDT 24
Peak memory 257584 kb
Host smart-e16c2c43-eb38-497e-bd54-846de63a9efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448390526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.2448390526
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.183622706
Short name T716
Test name
Test status
Simulation time 11978025491 ps
CPU time 74.16 seconds
Started Jul 29 05:06:07 PM PDT 24
Finished Jul 29 05:07:22 PM PDT 24
Peak memory 256728 kb
Host smart-2a5d5e9d-2f5b-478f-b197-1baf17af5c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183622706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idle
.183622706
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.1368440133
Short name T62
Test name
Test status
Simulation time 933063127 ps
CPU time 7.91 seconds
Started Jul 29 05:06:06 PM PDT 24
Finished Jul 29 05:06:14 PM PDT 24
Peak memory 233364 kb
Host smart-67aba939-0b16-4870-9107-78f07497eb06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368440133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.1368440133
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.1919404573
Short name T402
Test name
Test status
Simulation time 5922372064 ps
CPU time 14.53 seconds
Started Jul 29 05:06:10 PM PDT 24
Finished Jul 29 05:06:24 PM PDT 24
Peak memory 241656 kb
Host smart-ecd2f237-3141-4f64-ae0e-b0c601a3ff68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919404573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmd
s.1919404573
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/31.spi_device_intercept.1508017189
Short name T679
Test name
Test status
Simulation time 369141049 ps
CPU time 3.37 seconds
Started Jul 29 05:06:07 PM PDT 24
Finished Jul 29 05:06:10 PM PDT 24
Peak memory 225264 kb
Host smart-8c53ed8f-c39e-4ecd-966c-228d8af0d4ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508017189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.1508017189
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.700965679
Short name T1006
Test name
Test status
Simulation time 19326243462 ps
CPU time 71.53 seconds
Started Jul 29 05:06:01 PM PDT 24
Finished Jul 29 05:07:13 PM PDT 24
Peak memory 233388 kb
Host smart-e8157cac-a368-48c8-a41a-552d9306057f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700965679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.700965679
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.2303253206
Short name T896
Test name
Test status
Simulation time 1275952962 ps
CPU time 5.91 seconds
Started Jul 29 05:06:02 PM PDT 24
Finished Jul 29 05:06:08 PM PDT 24
Peak memory 233368 kb
Host smart-eee1800c-bc77-4a68-bfec-1d1f3da1abde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303253206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.2303253206
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.1358516299
Short name T988
Test name
Test status
Simulation time 2092914352 ps
CPU time 4.9 seconds
Started Jul 29 05:06:07 PM PDT 24
Finished Jul 29 05:06:12 PM PDT 24
Peak memory 233520 kb
Host smart-256da0b5-4472-4e6e-937c-a099b7103c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358516299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.1358516299
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.2379170260
Short name T67
Test name
Test status
Simulation time 438052114 ps
CPU time 6.55 seconds
Started Jul 29 05:06:05 PM PDT 24
Finished Jul 29 05:06:12 PM PDT 24
Peak memory 223748 kb
Host smart-61bc8656-554e-4089-a096-b14fc6ba2262
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2379170260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.2379170260
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.2054285290
Short name T285
Test name
Test status
Simulation time 232288260667 ps
CPU time 482.07 seconds
Started Jul 29 05:06:06 PM PDT 24
Finished Jul 29 05:14:08 PM PDT 24
Peak memory 283024 kb
Host smart-c4cf606e-3e17-43ba-ac0a-adb9ecc2eb1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054285290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.2054285290
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.1226648146
Short name T390
Test name
Test status
Simulation time 4273906970 ps
CPU time 13.2 seconds
Started Jul 29 05:06:06 PM PDT 24
Finished Jul 29 05:06:19 PM PDT 24
Peak memory 217048 kb
Host smart-14bc19c8-b21f-4401-bb85-56096a7b45b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226648146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.1226648146
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.2087027846
Short name T411
Test name
Test status
Simulation time 8489443243 ps
CPU time 8.54 seconds
Started Jul 29 05:05:59 PM PDT 24
Finished Jul 29 05:06:08 PM PDT 24
Peak memory 217028 kb
Host smart-2c100ff9-b11a-48df-8fc4-2fcf1a1295a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087027846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.2087027846
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.2332942984
Short name T879
Test name
Test status
Simulation time 59511660 ps
CPU time 1.08 seconds
Started Jul 29 05:06:01 PM PDT 24
Finished Jul 29 05:06:02 PM PDT 24
Peak memory 208560 kb
Host smart-58deac12-2f56-4658-9061-aa50feebefaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332942984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.2332942984
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.1670011872
Short name T769
Test name
Test status
Simulation time 179698466 ps
CPU time 0.73 seconds
Started Jul 29 05:06:04 PM PDT 24
Finished Jul 29 05:06:05 PM PDT 24
Peak memory 206504 kb
Host smart-adb909fc-02a2-433f-b181-be576d7595cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670011872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.1670011872
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.816772110
Short name T923
Test name
Test status
Simulation time 5624225194 ps
CPU time 12.21 seconds
Started Jul 29 05:06:03 PM PDT 24
Finished Jul 29 05:06:15 PM PDT 24
Peak memory 241352 kb
Host smart-644f4b8e-c6a8-4e38-b6d9-1e2aea93fa0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816772110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.816772110
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.3692150192
Short name T890
Test name
Test status
Simulation time 11621267 ps
CPU time 0.74 seconds
Started Jul 29 05:06:15 PM PDT 24
Finished Jul 29 05:06:16 PM PDT 24
Peak memory 206100 kb
Host smart-468a4867-0389-4372-b798-f4a2588046ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692150192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
3692150192
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.2247075805
Short name T239
Test name
Test status
Simulation time 120801750 ps
CPU time 2.51 seconds
Started Jul 29 05:06:13 PM PDT 24
Finished Jul 29 05:06:15 PM PDT 24
Peak memory 233424 kb
Host smart-c4037c51-bc69-4fe5-82d1-d66e19f09616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247075805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.2247075805
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.3064972382
Short name T496
Test name
Test status
Simulation time 227430978 ps
CPU time 0.77 seconds
Started Jul 29 05:06:09 PM PDT 24
Finished Jul 29 05:06:10 PM PDT 24
Peak memory 206056 kb
Host smart-735b7dec-cff2-4ef7-b633-e6eeb4ab54dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064972382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.3064972382
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.3976967992
Short name T603
Test name
Test status
Simulation time 12386499 ps
CPU time 0.73 seconds
Started Jul 29 05:06:17 PM PDT 24
Finished Jul 29 05:06:18 PM PDT 24
Peak memory 216380 kb
Host smart-e4a3d137-23c6-45d4-b15a-7291a7556d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976967992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.3976967992
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.2568773536
Short name T790
Test name
Test status
Simulation time 10265752293 ps
CPU time 52.02 seconds
Started Jul 29 05:06:13 PM PDT 24
Finished Jul 29 05:07:05 PM PDT 24
Peak memory 251336 kb
Host smart-8f9a70cc-6375-4c08-902e-1737f36495a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568773536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.2568773536
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.958944096
Short name T622
Test name
Test status
Simulation time 3507711020 ps
CPU time 47.58 seconds
Started Jul 29 05:06:13 PM PDT 24
Finished Jul 29 05:07:00 PM PDT 24
Peak memory 241740 kb
Host smart-d41954a9-7095-4df7-977b-2bbee74b7b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958944096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idle
.958944096
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.872353820
Short name T999
Test name
Test status
Simulation time 10404485776 ps
CPU time 13.65 seconds
Started Jul 29 05:06:17 PM PDT 24
Finished Jul 29 05:06:31 PM PDT 24
Peak memory 233420 kb
Host smart-12d2a686-7a5e-49ae-8e1e-703e989aab5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872353820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.872353820
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.3366055904
Short name T373
Test name
Test status
Simulation time 6780774496 ps
CPU time 38.28 seconds
Started Jul 29 05:06:17 PM PDT 24
Finished Jul 29 05:06:56 PM PDT 24
Peak memory 251864 kb
Host smart-4bbe0f4d-6baa-4b34-99b6-bf5d97df3701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366055904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmd
s.3366055904
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_intercept.3195237288
Short name T796
Test name
Test status
Simulation time 558576508 ps
CPU time 6.31 seconds
Started Jul 29 05:06:13 PM PDT 24
Finished Jul 29 05:06:19 PM PDT 24
Peak memory 233656 kb
Host smart-4e206e2c-106b-47ec-b9cc-c97016900ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195237288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.3195237288
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.1071385892
Short name T98
Test name
Test status
Simulation time 9294391543 ps
CPU time 16.98 seconds
Started Jul 29 05:06:18 PM PDT 24
Finished Jul 29 05:06:35 PM PDT 24
Peak memory 241428 kb
Host smart-1571ad55-14db-4bbb-b680-06d3264c297e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071385892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.1071385892
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.1679430791
Short name T762
Test name
Test status
Simulation time 4059235304 ps
CPU time 6.33 seconds
Started Jul 29 05:06:07 PM PDT 24
Finished Jul 29 05:06:14 PM PDT 24
Peak memory 225272 kb
Host smart-5ff046b6-a537-4600-8c6e-1f6336fa1512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679430791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.1679430791
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.2117911646
Short name T737
Test name
Test status
Simulation time 15493663207 ps
CPU time 25.47 seconds
Started Jul 29 05:06:07 PM PDT 24
Finished Jul 29 05:06:32 PM PDT 24
Peak memory 241632 kb
Host smart-50ef2eb9-0b76-4c39-b096-f91537d651ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117911646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.2117911646
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.1581889656
Short name T564
Test name
Test status
Simulation time 567485413 ps
CPU time 6.97 seconds
Started Jul 29 05:06:17 PM PDT 24
Finished Jul 29 05:06:24 PM PDT 24
Peak memory 223696 kb
Host smart-dd9f419f-162e-481e-b1cf-e5cf80184a17
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1581889656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.1581889656
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.2869738265
Short name T18
Test name
Test status
Simulation time 168797077 ps
CPU time 1.03 seconds
Started Jul 29 05:06:13 PM PDT 24
Finished Jul 29 05:06:14 PM PDT 24
Peak memory 207292 kb
Host smart-d0815f03-4095-4169-b4f2-e26e31cfaae3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869738265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.2869738265
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.3577644615
Short name T306
Test name
Test status
Simulation time 2675334456 ps
CPU time 23.89 seconds
Started Jul 29 05:06:07 PM PDT 24
Finished Jul 29 05:06:31 PM PDT 24
Peak memory 217368 kb
Host smart-aa5fda9b-b1c5-408b-8fb5-fbd28a5a6860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577644615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.3577644615
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.2406234782
Short name T591
Test name
Test status
Simulation time 5660823040 ps
CPU time 15.28 seconds
Started Jul 29 05:06:09 PM PDT 24
Finished Jul 29 05:06:24 PM PDT 24
Peak memory 216960 kb
Host smart-319d40a0-9387-4d7a-a8e6-5b06539faf4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406234782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.2406234782
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.1652768451
Short name T435
Test name
Test status
Simulation time 111123107 ps
CPU time 1.67 seconds
Started Jul 29 05:06:08 PM PDT 24
Finished Jul 29 05:06:10 PM PDT 24
Peak memory 216856 kb
Host smart-634315c3-872f-407b-bab2-797cf7381811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652768451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.1652768451
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.2107298990
Short name T665
Test name
Test status
Simulation time 56708750 ps
CPU time 0.76 seconds
Started Jul 29 05:06:07 PM PDT 24
Finished Jul 29 05:06:08 PM PDT 24
Peak memory 206464 kb
Host smart-0d9f50c0-9e84-4765-b072-57c5b7dd767d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107298990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.2107298990
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.2920564595
Short name T962
Test name
Test status
Simulation time 492212484 ps
CPU time 2.13 seconds
Started Jul 29 05:06:13 PM PDT 24
Finished Jul 29 05:06:16 PM PDT 24
Peak memory 224744 kb
Host smart-cf0925e7-b0b3-4d9e-8203-8d508f2f858c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920564595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.2920564595
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.1036231293
Short name T731
Test name
Test status
Simulation time 15322459 ps
CPU time 0.76 seconds
Started Jul 29 05:06:23 PM PDT 24
Finished Jul 29 05:06:23 PM PDT 24
Peak memory 206148 kb
Host smart-e0e6d2ff-51df-44c6-a8da-500078108ad5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036231293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
1036231293
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.1765806242
Short name T469
Test name
Test status
Simulation time 712760975 ps
CPU time 9.72 seconds
Started Jul 29 05:06:19 PM PDT 24
Finished Jul 29 05:06:29 PM PDT 24
Peak memory 233352 kb
Host smart-8c975b54-3c76-40bb-afe2-6536d24a5c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765806242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.1765806242
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.3713049405
Short name T396
Test name
Test status
Simulation time 63709542 ps
CPU time 0.76 seconds
Started Jul 29 05:06:14 PM PDT 24
Finished Jul 29 05:06:14 PM PDT 24
Peak memory 206992 kb
Host smart-57857186-3050-4c6c-a0e9-a9d5ca628f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713049405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.3713049405
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.98386695
Short name T427
Test name
Test status
Simulation time 22294163851 ps
CPU time 134.29 seconds
Started Jul 29 05:06:20 PM PDT 24
Finished Jul 29 05:08:35 PM PDT 24
Peak memory 257416 kb
Host smart-219da43a-2e53-4bc0-8d4a-0e841c9a3f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98386695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.98386695
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.562038566
Short name T308
Test name
Test status
Simulation time 5473165662 ps
CPU time 25.58 seconds
Started Jul 29 05:06:18 PM PDT 24
Finished Jul 29 05:06:43 PM PDT 24
Peak memory 225396 kb
Host smart-4e5880f8-e936-4b34-a96d-bd03896c8202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562038566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.562038566
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.1771890873
Short name T139
Test name
Test status
Simulation time 8544021158 ps
CPU time 73.7 seconds
Started Jul 29 05:06:19 PM PDT 24
Finished Jul 29 05:07:33 PM PDT 24
Peak memory 256332 kb
Host smart-e38664bc-f6ab-40a7-b30c-ae80ffcf3c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771890873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.1771890873
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.1359328706
Short name T855
Test name
Test status
Simulation time 1033602547 ps
CPU time 6.08 seconds
Started Jul 29 05:06:19 PM PDT 24
Finished Jul 29 05:06:25 PM PDT 24
Peak memory 241532 kb
Host smart-ab16c0ae-c3e5-4009-b222-d683899fc424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359328706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.1359328706
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.1121332534
Short name T179
Test name
Test status
Simulation time 15028286631 ps
CPU time 63.76 seconds
Started Jul 29 05:06:20 PM PDT 24
Finished Jul 29 05:07:23 PM PDT 24
Peak memory 241680 kb
Host smart-f80be5c3-50b7-4487-8c68-759ef0c60c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121332534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmd
s.1121332534
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.513635016
Short name T265
Test name
Test status
Simulation time 8175539422 ps
CPU time 26.22 seconds
Started Jul 29 05:06:19 PM PDT 24
Finished Jul 29 05:06:45 PM PDT 24
Peak memory 233512 kb
Host smart-392f5822-6061-459a-ad49-91a27b9b679f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513635016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.513635016
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.1587310289
Short name T761
Test name
Test status
Simulation time 911294605 ps
CPU time 5.55 seconds
Started Jul 29 05:06:18 PM PDT 24
Finished Jul 29 05:06:23 PM PDT 24
Peak memory 225236 kb
Host smart-3e8dd98f-b0e6-4d75-9cfc-82235ae09388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587310289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.1587310289
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.1007663502
Short name T765
Test name
Test status
Simulation time 47193810285 ps
CPU time 24.76 seconds
Started Jul 29 05:06:18 PM PDT 24
Finished Jul 29 05:06:43 PM PDT 24
Peak memory 233464 kb
Host smart-7ea59e61-e7a2-4521-9ab7-4febfe5969e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007663502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.1007663502
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.2059060560
Short name T357
Test name
Test status
Simulation time 3376926510 ps
CPU time 4.85 seconds
Started Jul 29 05:06:20 PM PDT 24
Finished Jul 29 05:06:25 PM PDT 24
Peak memory 223716 kb
Host smart-0c20f2ad-252f-4a42-a34a-d67380ab1b55
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2059060560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.2059060560
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.412408608
Short name T526
Test name
Test status
Simulation time 4973650722 ps
CPU time 98.98 seconds
Started Jul 29 05:06:18 PM PDT 24
Finished Jul 29 05:07:57 PM PDT 24
Peak memory 256496 kb
Host smart-0bde09fe-de5e-4c1d-925a-b5f0dbb5d96f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412408608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stres
s_all.412408608
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.1875962739
Short name T476
Test name
Test status
Simulation time 1282777201 ps
CPU time 9.31 seconds
Started Jul 29 05:06:20 PM PDT 24
Finished Jul 29 05:06:30 PM PDT 24
Peak memory 220336 kb
Host smart-9ca662cb-fea3-4428-a8b0-d3f131fd41f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875962739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.1875962739
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.4025200842
Short name T331
Test name
Test status
Simulation time 6424789657 ps
CPU time 21.72 seconds
Started Jul 29 05:06:19 PM PDT 24
Finished Jul 29 05:06:41 PM PDT 24
Peak memory 217076 kb
Host smart-32793fb8-3807-47a6-a630-0daf33a0e755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025200842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.4025200842
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.1834710859
Short name T479
Test name
Test status
Simulation time 219974443 ps
CPU time 3.78 seconds
Started Jul 29 05:06:19 PM PDT 24
Finished Jul 29 05:06:23 PM PDT 24
Peak memory 216988 kb
Host smart-35b57d22-b071-44c3-afaa-4fd9c1c1e4e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834710859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.1834710859
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.623543320
Short name T384
Test name
Test status
Simulation time 18901329 ps
CPU time 0.78 seconds
Started Jul 29 05:06:18 PM PDT 24
Finished Jul 29 05:06:19 PM PDT 24
Peak memory 206608 kb
Host smart-98f8d270-d7a4-4f18-b541-97543f40318f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623543320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.623543320
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.1287376304
Short name T515
Test name
Test status
Simulation time 382619854 ps
CPU time 2.36 seconds
Started Jul 29 05:06:19 PM PDT 24
Finished Jul 29 05:06:22 PM PDT 24
Peak memory 224180 kb
Host smart-a4c9b98d-9633-41cb-a3f0-1fe658e1b880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287376304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.1287376304
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.2429565862
Short name T359
Test name
Test status
Simulation time 37926152 ps
CPU time 0.72 seconds
Started Jul 29 05:06:27 PM PDT 24
Finished Jul 29 05:06:27 PM PDT 24
Peak memory 205800 kb
Host smart-5e9a0c64-6e1a-462e-8396-0526183e5b59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429565862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
2429565862
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.2548030518
Short name T562
Test name
Test status
Simulation time 171649605 ps
CPU time 3.08 seconds
Started Jul 29 05:06:26 PM PDT 24
Finished Jul 29 05:06:29 PM PDT 24
Peak memory 225268 kb
Host smart-a3cb8fef-4eae-4e04-9147-3fdb6c5bb865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548030518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.2548030518
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.321103288
Short name T997
Test name
Test status
Simulation time 46279630 ps
CPU time 0.8 seconds
Started Jul 29 05:06:19 PM PDT 24
Finished Jul 29 05:06:20 PM PDT 24
Peak memory 207100 kb
Host smart-4f783d85-823b-45df-a122-dd8a91a85881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321103288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.321103288
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.1151164402
Short name T399
Test name
Test status
Simulation time 35031463 ps
CPU time 0.75 seconds
Started Jul 29 05:06:25 PM PDT 24
Finished Jul 29 05:06:26 PM PDT 24
Peak memory 216504 kb
Host smart-bea19702-6224-4f59-9b2a-2b76a73d815a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151164402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.1151164402
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.3127228136
Short name T947
Test name
Test status
Simulation time 6541909400 ps
CPU time 8.21 seconds
Started Jul 29 05:06:28 PM PDT 24
Finished Jul 29 05:06:36 PM PDT 24
Peak memory 218416 kb
Host smart-751883ad-d5ac-4bd1-b53f-81564479c8c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127228136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.3127228136
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.2459669525
Short name T262
Test name
Test status
Simulation time 2352382083 ps
CPU time 21.11 seconds
Started Jul 29 05:06:24 PM PDT 24
Finished Jul 29 05:06:46 PM PDT 24
Peak memory 233572 kb
Host smart-c1de8059-cf8a-49b7-85ad-ee191ee1c49f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459669525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.2459669525
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.2386060016
Short name T48
Test name
Test status
Simulation time 316943732 ps
CPU time 2.71 seconds
Started Jul 29 05:06:25 PM PDT 24
Finished Jul 29 05:06:28 PM PDT 24
Peak memory 225240 kb
Host smart-60655988-5719-4000-8529-ff8e8b4d2ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386060016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.2386060016
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.1755787284
Short name T904
Test name
Test status
Simulation time 6883681866 ps
CPU time 26.6 seconds
Started Jul 29 05:06:25 PM PDT 24
Finished Jul 29 05:06:52 PM PDT 24
Peak memory 251132 kb
Host smart-81ee4470-8688-4248-9828-e5c44bdc6eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755787284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmd
s.1755787284
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/34.spi_device_intercept.1061550939
Short name T92
Test name
Test status
Simulation time 1792448273 ps
CPU time 10.75 seconds
Started Jul 29 05:06:29 PM PDT 24
Finished Jul 29 05:06:40 PM PDT 24
Peak memory 225300 kb
Host smart-76cb0f94-0485-4d57-a6ff-9e0dce5671ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061550939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.1061550939
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.1794190742
Short name T12
Test name
Test status
Simulation time 22563538301 ps
CPU time 15.98 seconds
Started Jul 29 05:06:31 PM PDT 24
Finished Jul 29 05:06:47 PM PDT 24
Peak memory 233504 kb
Host smart-eeeecf21-17cb-4313-95cc-300c8bcaedd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794190742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.1794190742
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.4125758386
Short name T674
Test name
Test status
Simulation time 1085496672 ps
CPU time 6.83 seconds
Started Jul 29 05:06:26 PM PDT 24
Finished Jul 29 05:06:33 PM PDT 24
Peak memory 241364 kb
Host smart-5329486e-fca2-43d8-8419-46a7a27f02ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125758386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.4125758386
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.1506029357
Short name T702
Test name
Test status
Simulation time 4041237118 ps
CPU time 9.31 seconds
Started Jul 29 05:06:24 PM PDT 24
Finished Jul 29 05:06:33 PM PDT 24
Peak memory 233712 kb
Host smart-f56c281e-1eac-45b5-b00f-cd775242c0b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506029357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.1506029357
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.3522047545
Short name T51
Test name
Test status
Simulation time 147786810 ps
CPU time 3.48 seconds
Started Jul 29 05:06:24 PM PDT 24
Finished Jul 29 05:06:28 PM PDT 24
Peak memory 223680 kb
Host smart-8af08837-b781-4f3b-8407-06a0d82d73f2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3522047545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.3522047545
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.1509526122
Short name T970
Test name
Test status
Simulation time 58889599550 ps
CPU time 344.67 seconds
Started Jul 29 05:06:31 PM PDT 24
Finished Jul 29 05:12:16 PM PDT 24
Peak memory 267376 kb
Host smart-15f8bd04-3b19-40d3-9101-989168e88e8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509526122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.1509526122
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.1760247760
Short name T677
Test name
Test status
Simulation time 7742689099 ps
CPU time 18.56 seconds
Started Jul 29 05:06:19 PM PDT 24
Finished Jul 29 05:06:38 PM PDT 24
Peak memory 217028 kb
Host smart-d17ac6b3-487e-472d-b0cd-bda0874d40fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760247760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.1760247760
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.1831772803
Short name T775
Test name
Test status
Simulation time 50357416294 ps
CPU time 13.84 seconds
Started Jul 29 05:06:20 PM PDT 24
Finished Jul 29 05:06:34 PM PDT 24
Peak memory 216956 kb
Host smart-5437dd24-6d20-4461-b7ab-2761e48a27cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831772803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.1831772803
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.2825436753
Short name T645
Test name
Test status
Simulation time 57187366 ps
CPU time 0.68 seconds
Started Jul 29 05:06:23 PM PDT 24
Finished Jul 29 05:06:24 PM PDT 24
Peak memory 206028 kb
Host smart-3cb83fbf-4f50-46b4-aa3d-a834a203d346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825436753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.2825436753
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.2255207359
Short name T394
Test name
Test status
Simulation time 232214724 ps
CPU time 0.86 seconds
Started Jul 29 05:06:21 PM PDT 24
Finished Jul 29 05:06:22 PM PDT 24
Peak memory 206504 kb
Host smart-7762dd74-fcc7-4432-95ee-f6697d54fb72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255207359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.2255207359
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.1627746369
Short name T181
Test name
Test status
Simulation time 5346993934 ps
CPU time 8.51 seconds
Started Jul 29 05:06:32 PM PDT 24
Finished Jul 29 05:06:40 PM PDT 24
Peak memory 225304 kb
Host smart-6d8179b2-d5ce-4b23-8bbc-6def1f7a1c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627746369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.1627746369
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.1843150304
Short name T537
Test name
Test status
Simulation time 17482785 ps
CPU time 0.7 seconds
Started Jul 29 05:06:30 PM PDT 24
Finished Jul 29 05:06:31 PM PDT 24
Peak memory 205320 kb
Host smart-fc559391-4c0a-4e06-81d0-ee1ce0032861
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843150304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
1843150304
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.2824584663
Short name T95
Test name
Test status
Simulation time 495296626 ps
CPU time 4.05 seconds
Started Jul 29 05:06:27 PM PDT 24
Finished Jul 29 05:06:31 PM PDT 24
Peak memory 233440 kb
Host smart-b8a9a854-ade1-4d72-a684-5392ae690e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824584663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.2824584663
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.3297083055
Short name T681
Test name
Test status
Simulation time 81933395 ps
CPU time 0.74 seconds
Started Jul 29 05:06:30 PM PDT 24
Finished Jul 29 05:06:31 PM PDT 24
Peak memory 206096 kb
Host smart-412029c1-5e9f-4909-b09a-069581164533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297083055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.3297083055
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.4214121672
Short name T131
Test name
Test status
Simulation time 3114553099 ps
CPU time 8.72 seconds
Started Jul 29 05:06:24 PM PDT 24
Finished Jul 29 05:06:32 PM PDT 24
Peak memory 234444 kb
Host smart-5a77a7ed-70df-4f1e-8d6c-beb832db3fcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214121672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.4214121672
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.2721761033
Short name T219
Test name
Test status
Simulation time 11591621889 ps
CPU time 84.16 seconds
Started Jul 29 05:06:26 PM PDT 24
Finished Jul 29 05:07:50 PM PDT 24
Peak memory 257516 kb
Host smart-e5b2e359-1784-4bbe-867c-c87f7e99e288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721761033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.2721761033
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.781248168
Short name T545
Test name
Test status
Simulation time 56086430 ps
CPU time 2.21 seconds
Started Jul 29 05:06:25 PM PDT 24
Finished Jul 29 05:06:27 PM PDT 24
Peak memory 225192 kb
Host smart-5b0fe6cc-4133-4e17-a3f4-a9a455891b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781248168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.781248168
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_intercept.40456951
Short name T216
Test name
Test status
Simulation time 903663377 ps
CPU time 3.84 seconds
Started Jul 29 05:06:25 PM PDT 24
Finished Jul 29 05:06:29 PM PDT 24
Peak memory 225280 kb
Host smart-fbf97390-965f-486f-b2a1-5d5a9f568374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40456951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.40456951
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.1068990592
Short name T819
Test name
Test status
Simulation time 5062890486 ps
CPU time 25.32 seconds
Started Jul 29 05:06:31 PM PDT 24
Finished Jul 29 05:06:57 PM PDT 24
Peak memory 233536 kb
Host smart-2c7faf61-f25a-4ff7-80ce-4810462c5618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068990592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.1068990592
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.4036729594
Short name T814
Test name
Test status
Simulation time 12723132839 ps
CPU time 15.36 seconds
Started Jul 29 05:06:27 PM PDT 24
Finished Jul 29 05:06:42 PM PDT 24
Peak memory 240888 kb
Host smart-70329af3-f04c-4d70-afa1-d365c53e7211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036729594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.4036729594
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.3102648099
Short name T876
Test name
Test status
Simulation time 6759136973 ps
CPU time 21.08 seconds
Started Jul 29 05:06:25 PM PDT 24
Finished Jul 29 05:06:46 PM PDT 24
Peak memory 241480 kb
Host smart-3a83df3b-7027-489b-a9ed-b4e7138b6cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102648099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.3102648099
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.778496834
Short name T410
Test name
Test status
Simulation time 19429290657 ps
CPU time 9.17 seconds
Started Jul 29 05:06:26 PM PDT 24
Finished Jul 29 05:06:35 PM PDT 24
Peak memory 219608 kb
Host smart-e6b6b9c0-1ac9-41b5-a9fb-e3301adb8f70
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=778496834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dire
ct.778496834
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.813179937
Short name T741
Test name
Test status
Simulation time 54723744 ps
CPU time 1.14 seconds
Started Jul 29 05:06:31 PM PDT 24
Finished Jul 29 05:06:32 PM PDT 24
Peak memory 207604 kb
Host smart-042ad7fc-c7e3-4c77-b7dd-740eb8018a28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813179937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stres
s_all.813179937
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.4183949401
Short name T742
Test name
Test status
Simulation time 50737133615 ps
CPU time 22.7 seconds
Started Jul 29 05:06:24 PM PDT 24
Finished Jul 29 05:06:47 PM PDT 24
Peak memory 217132 kb
Host smart-59e7ee91-c7eb-4827-8afa-f9e7046272e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183949401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.4183949401
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.1087191097
Short name T693
Test name
Test status
Simulation time 6871994927 ps
CPU time 11.98 seconds
Started Jul 29 05:06:29 PM PDT 24
Finished Jul 29 05:06:41 PM PDT 24
Peak memory 217088 kb
Host smart-57f9f6bf-e846-486c-8826-d99be20946cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087191097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.1087191097
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.1453296394
Short name T353
Test name
Test status
Simulation time 95754000 ps
CPU time 1.32 seconds
Started Jul 29 05:06:31 PM PDT 24
Finished Jul 29 05:06:33 PM PDT 24
Peak memory 216752 kb
Host smart-09f72830-c864-4a52-8655-8ac93e280774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453296394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.1453296394
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.142344383
Short name T130
Test name
Test status
Simulation time 76358296 ps
CPU time 0.81 seconds
Started Jul 29 05:06:25 PM PDT 24
Finished Jul 29 05:06:26 PM PDT 24
Peak memory 206556 kb
Host smart-93082a62-f196-4818-a14e-9573fcdbc98a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142344383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.142344383
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.1336143006
Short name T237
Test name
Test status
Simulation time 3776470330 ps
CPU time 7.14 seconds
Started Jul 29 05:06:26 PM PDT 24
Finished Jul 29 05:06:33 PM PDT 24
Peak memory 225276 kb
Host smart-d312fdc9-8277-47cb-b146-8754fe6f8732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336143006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.1336143006
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.2342595579
Short name T786
Test name
Test status
Simulation time 43622139 ps
CPU time 0.71 seconds
Started Jul 29 05:06:38 PM PDT 24
Finished Jul 29 05:06:39 PM PDT 24
Peak memory 205244 kb
Host smart-5d5d528f-70cb-408f-8b3e-90321d56a101
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342595579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
2342595579
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.2310957298
Short name T458
Test name
Test status
Simulation time 2590296856 ps
CPU time 3.89 seconds
Started Jul 29 05:06:35 PM PDT 24
Finished Jul 29 05:06:39 PM PDT 24
Peak memory 225384 kb
Host smart-10898dfa-ee17-4402-8649-fe9917f0a165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310957298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.2310957298
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.1153856579
Short name T760
Test name
Test status
Simulation time 18403569 ps
CPU time 0.83 seconds
Started Jul 29 05:06:29 PM PDT 24
Finished Jul 29 05:06:30 PM PDT 24
Peak memory 206964 kb
Host smart-24ac4426-2458-4a93-93d2-9ff396685215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153856579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.1153856579
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.2890020535
Short name T943
Test name
Test status
Simulation time 8102682350 ps
CPU time 16.13 seconds
Started Jul 29 05:06:28 PM PDT 24
Finished Jul 29 05:06:44 PM PDT 24
Peak memory 233676 kb
Host smart-995dae32-2a3e-408d-9b31-7bf7f1cc99f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890020535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.2890020535
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.3671149190
Short name T81
Test name
Test status
Simulation time 14919371921 ps
CPU time 125.49 seconds
Started Jul 29 05:06:29 PM PDT 24
Finished Jul 29 05:08:34 PM PDT 24
Peak memory 258024 kb
Host smart-e59d0ea4-17e0-46d1-ad52-69768db16b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671149190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.3671149190
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.2981888633
Short name T224
Test name
Test status
Simulation time 97265373706 ps
CPU time 265.15 seconds
Started Jul 29 05:06:32 PM PDT 24
Finished Jul 29 05:10:58 PM PDT 24
Peak memory 257560 kb
Host smart-1811e8e8-4149-4da3-8981-d39838d2fc37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981888633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.2981888633
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.1559931037
Short name T557
Test name
Test status
Simulation time 1621471492 ps
CPU time 24.1 seconds
Started Jul 29 05:06:29 PM PDT 24
Finished Jul 29 05:06:54 PM PDT 24
Peak memory 225276 kb
Host smart-9b67b448-5f06-41c6-8ca4-ce6bd46552dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559931037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.1559931037
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.2096031171
Short name T913
Test name
Test status
Simulation time 59403026575 ps
CPU time 116.56 seconds
Started Jul 29 05:06:29 PM PDT 24
Finished Jul 29 05:08:26 PM PDT 24
Peak memory 254728 kb
Host smart-5e916acb-0ba8-486e-b172-600b37047dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096031171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmd
s.2096031171
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_intercept.4168238784
Short name T191
Test name
Test status
Simulation time 280524176 ps
CPU time 2.12 seconds
Started Jul 29 05:06:31 PM PDT 24
Finished Jul 29 05:06:33 PM PDT 24
Peak memory 225164 kb
Host smart-ceb59d02-8457-4421-bc65-77acf4baffc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168238784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.4168238784
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.326170500
Short name T804
Test name
Test status
Simulation time 21323635080 ps
CPU time 28.64 seconds
Started Jul 29 05:06:35 PM PDT 24
Finished Jul 29 05:07:03 PM PDT 24
Peak memory 233564 kb
Host smart-5cce9712-c2d3-4a9d-a6be-54394e21795e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326170500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.326170500
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.528452879
Short name T609
Test name
Test status
Simulation time 17970699047 ps
CPU time 7.97 seconds
Started Jul 29 05:06:29 PM PDT 24
Finished Jul 29 05:06:37 PM PDT 24
Peak memory 233452 kb
Host smart-7d9c550a-6597-4515-a2fb-0025c468acd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528452879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swap
.528452879
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.2015005688
Short name T758
Test name
Test status
Simulation time 5598890986 ps
CPU time 6.64 seconds
Started Jul 29 05:06:30 PM PDT 24
Finished Jul 29 05:06:37 PM PDT 24
Peak memory 233508 kb
Host smart-71ff4439-7897-4396-85e3-f75620ad6cbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015005688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.2015005688
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.2362942823
Short name T908
Test name
Test status
Simulation time 967602853 ps
CPU time 3.5 seconds
Started Jul 29 05:06:30 PM PDT 24
Finished Jul 29 05:06:34 PM PDT 24
Peak memory 223668 kb
Host smart-f857ec85-1b3b-4ff5-a10e-c531ad28c742
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2362942823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.2362942823
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.1017589863
Short name T870
Test name
Test status
Simulation time 587152318 ps
CPU time 7.77 seconds
Started Jul 29 05:06:28 PM PDT 24
Finished Jul 29 05:06:36 PM PDT 24
Peak memory 223184 kb
Host smart-1b1da703-4161-4ee6-a830-b317f91a41c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017589863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.1017589863
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.3135562404
Short name T505
Test name
Test status
Simulation time 626247547 ps
CPU time 9.08 seconds
Started Jul 29 05:06:29 PM PDT 24
Finished Jul 29 05:06:39 PM PDT 24
Peak memory 217224 kb
Host smart-6f2afb17-335d-46e0-98fc-4744b54d9572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135562404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.3135562404
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.358190088
Short name T342
Test name
Test status
Simulation time 1052217407 ps
CPU time 3.75 seconds
Started Jul 29 05:06:31 PM PDT 24
Finished Jul 29 05:06:35 PM PDT 24
Peak memory 216996 kb
Host smart-4b18edb5-d6c9-4ea0-aabf-8b73116fbe44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358190088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.358190088
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.2257654348
Short name T847
Test name
Test status
Simulation time 13200992 ps
CPU time 0.78 seconds
Started Jul 29 05:06:31 PM PDT 24
Finished Jul 29 05:06:32 PM PDT 24
Peak memory 206552 kb
Host smart-2992243a-814f-4eaa-8a80-cb382e399bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257654348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.2257654348
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.3640224184
Short name T68
Test name
Test status
Simulation time 597826555 ps
CPU time 0.77 seconds
Started Jul 29 05:06:35 PM PDT 24
Finished Jul 29 05:06:36 PM PDT 24
Peak memory 206632 kb
Host smart-7a02de91-bec5-4938-8425-f98047fcba7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640224184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.3640224184
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.3427365923
Short name T111
Test name
Test status
Simulation time 362410890 ps
CPU time 3.01 seconds
Started Jul 29 05:06:32 PM PDT 24
Finished Jul 29 05:06:35 PM PDT 24
Peak memory 233352 kb
Host smart-ec954cbb-3a5c-4a1c-8cc1-7182fa02893a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427365923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.3427365923
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.2519715948
Short name T448
Test name
Test status
Simulation time 34399980 ps
CPU time 0.72 seconds
Started Jul 29 05:06:40 PM PDT 24
Finished Jul 29 05:06:41 PM PDT 24
Peak memory 205932 kb
Host smart-386d2341-bbce-4dc0-822f-2a7b117385ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519715948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
2519715948
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.2744237641
Short name T827
Test name
Test status
Simulation time 115037801 ps
CPU time 2.05 seconds
Started Jul 29 05:06:37 PM PDT 24
Finished Jul 29 05:06:39 PM PDT 24
Peak memory 225232 kb
Host smart-5603290b-8a15-4cf7-9b33-0f6a18078656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744237641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.2744237641
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.220709540
Short name T344
Test name
Test status
Simulation time 14569287 ps
CPU time 0.82 seconds
Started Jul 29 05:06:39 PM PDT 24
Finished Jul 29 05:06:40 PM PDT 24
Peak memory 205988 kb
Host smart-11d5ba8c-1a1c-4112-9206-ce225261a0c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220709540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.220709540
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.3775893846
Short name T425
Test name
Test status
Simulation time 5553274171 ps
CPU time 24.33 seconds
Started Jul 29 05:06:37 PM PDT 24
Finished Jul 29 05:07:01 PM PDT 24
Peak memory 253248 kb
Host smart-ddf27f1b-8296-48d1-8bf2-db75bfd79dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775893846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.3775893846
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.3041340723
Short name T38
Test name
Test status
Simulation time 2420649553 ps
CPU time 63.44 seconds
Started Jul 29 05:06:39 PM PDT 24
Finished Jul 29 05:07:42 PM PDT 24
Peak memory 248864 kb
Host smart-1d817c30-0eab-4135-961e-8c017b7206d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041340723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.3041340723
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.559139411
Short name T577
Test name
Test status
Simulation time 4216991811 ps
CPU time 54.1 seconds
Started Jul 29 05:06:41 PM PDT 24
Finished Jul 29 05:07:35 PM PDT 24
Peak memory 240924 kb
Host smart-abb5b169-d51d-4cd7-8f39-f3a525e58c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559139411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idle
.559139411
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.3799938433
Short name T300
Test name
Test status
Simulation time 216576954 ps
CPU time 7.1 seconds
Started Jul 29 05:06:47 PM PDT 24
Finished Jul 29 05:06:54 PM PDT 24
Peak memory 236840 kb
Host smart-dd2cdff1-f97b-4d98-9ecd-9e1e503010c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799938433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.3799938433
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.1024949150
Short name T446
Test name
Test status
Simulation time 32784899712 ps
CPU time 41.95 seconds
Started Jul 29 05:06:45 PM PDT 24
Finished Jul 29 05:07:27 PM PDT 24
Peak memory 249952 kb
Host smart-8242407e-ba70-4cd3-a27c-5e8eb4732834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024949150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmd
s.1024949150
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/37.spi_device_intercept.3399782145
Short name T601
Test name
Test status
Simulation time 119162468 ps
CPU time 3.11 seconds
Started Jul 29 05:06:39 PM PDT 24
Finished Jul 29 05:06:42 PM PDT 24
Peak memory 233480 kb
Host smart-ce72efe2-ce9a-4466-b8cb-301fd9fa5279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399782145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.3399782145
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.1073879643
Short name T662
Test name
Test status
Simulation time 124948593 ps
CPU time 2.23 seconds
Started Jul 29 05:06:39 PM PDT 24
Finished Jul 29 05:06:41 PM PDT 24
Peak memory 233020 kb
Host smart-d2ae75c6-3159-43c1-8df2-610ef0ec38b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073879643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.1073879643
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.1519134148
Short name T816
Test name
Test status
Simulation time 2688808700 ps
CPU time 3.52 seconds
Started Jul 29 05:06:36 PM PDT 24
Finished Jul 29 05:06:40 PM PDT 24
Peak memory 225204 kb
Host smart-ead599d4-d116-4936-8638-6ce5fd00e678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519134148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.1519134148
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.2815322192
Short name T899
Test name
Test status
Simulation time 5406067281 ps
CPU time 6.22 seconds
Started Jul 29 05:06:40 PM PDT 24
Finished Jul 29 05:06:46 PM PDT 24
Peak memory 225248 kb
Host smart-f221d73b-0ee6-4859-a4ee-ceb9c39aa593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815322192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.2815322192
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.600010299
Short name T343
Test name
Test status
Simulation time 986451067 ps
CPU time 12.44 seconds
Started Jul 29 05:06:38 PM PDT 24
Finished Jul 29 05:06:50 PM PDT 24
Peak memory 222132 kb
Host smart-357caa69-2d0a-451f-b65f-01bb93d46ad0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=600010299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dire
ct.600010299
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.2999892126
Short name T598
Test name
Test status
Simulation time 974076768 ps
CPU time 11.6 seconds
Started Jul 29 05:06:38 PM PDT 24
Finished Jul 29 05:06:50 PM PDT 24
Peak memory 216992 kb
Host smart-b7d1a2ff-59ed-4f0c-99cb-378d0434a09a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999892126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.2999892126
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.3628000025
Short name T363
Test name
Test status
Simulation time 1673998977 ps
CPU time 4.98 seconds
Started Jul 29 05:06:45 PM PDT 24
Finished Jul 29 05:06:50 PM PDT 24
Peak memory 217020 kb
Host smart-8c797a99-0c5e-4780-96f7-f5e5269b0930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628000025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.3628000025
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.1747234053
Short name T367
Test name
Test status
Simulation time 149447264 ps
CPU time 5.45 seconds
Started Jul 29 05:06:38 PM PDT 24
Finished Jul 29 05:06:44 PM PDT 24
Peak memory 216868 kb
Host smart-3c9ad81d-cf38-4473-8efb-56f6358d5af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747234053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.1747234053
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.2327617950
Short name T969
Test name
Test status
Simulation time 36283122 ps
CPU time 0.75 seconds
Started Jul 29 05:06:41 PM PDT 24
Finished Jul 29 05:06:42 PM PDT 24
Peak memory 206556 kb
Host smart-47849c0a-3358-47a0-a48e-7ed8f287d9ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327617950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.2327617950
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.2350553797
Short name T842
Test name
Test status
Simulation time 388558528 ps
CPU time 8.55 seconds
Started Jul 29 05:06:38 PM PDT 24
Finished Jul 29 05:06:46 PM PDT 24
Peak memory 233412 kb
Host smart-072acfee-4c69-4503-b2a7-cde3d07d5be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350553797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.2350553797
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.946163157
Short name T982
Test name
Test status
Simulation time 38796553 ps
CPU time 0.72 seconds
Started Jul 29 05:06:51 PM PDT 24
Finished Jul 29 05:06:52 PM PDT 24
Peak memory 206224 kb
Host smart-9f37e4f8-4406-4f4b-a41e-d31f2f64d4d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946163157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.946163157
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.1013602277
Short name T112
Test name
Test status
Simulation time 2087370779 ps
CPU time 3.68 seconds
Started Jul 29 05:06:44 PM PDT 24
Finished Jul 29 05:06:48 PM PDT 24
Peak memory 225192 kb
Host smart-fe3c8eb8-488b-4897-b80e-a9df46ca5f62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013602277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.1013602277
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.783441107
Short name T621
Test name
Test status
Simulation time 78750159 ps
CPU time 0.74 seconds
Started Jul 29 05:06:38 PM PDT 24
Finished Jul 29 05:06:39 PM PDT 24
Peak memory 207324 kb
Host smart-887fbfcb-979e-4669-9d34-2d98e024807a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783441107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.783441107
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.2393683223
Short name T467
Test name
Test status
Simulation time 948796981 ps
CPU time 12.26 seconds
Started Jul 29 05:06:44 PM PDT 24
Finished Jul 29 05:06:56 PM PDT 24
Peak memory 225272 kb
Host smart-853c442d-5f8a-4955-8ab6-b187ae6b304d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393683223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.2393683223
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.1490946667
Short name T138
Test name
Test status
Simulation time 8777609696 ps
CPU time 42.86 seconds
Started Jul 29 05:06:52 PM PDT 24
Finished Jul 29 05:07:35 PM PDT 24
Peak memory 251016 kb
Host smart-4a87ad2a-ef91-4632-a0f5-23834d628072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490946667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.1490946667
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.1728305763
Short name T709
Test name
Test status
Simulation time 32022363227 ps
CPU time 261.43 seconds
Started Jul 29 05:06:42 PM PDT 24
Finished Jul 29 05:11:04 PM PDT 24
Peak memory 249760 kb
Host smart-019b825c-5ca9-4e9e-9545-21e2e793759f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728305763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.1728305763
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.2496730902
Short name T833
Test name
Test status
Simulation time 145365120 ps
CPU time 3.17 seconds
Started Jul 29 05:06:52 PM PDT 24
Finished Jul 29 05:06:55 PM PDT 24
Peak memory 233424 kb
Host smart-7d50fd1e-a4e9-4e72-8207-add8cde49823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496730902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.2496730902
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.4194528198
Short name T544
Test name
Test status
Simulation time 5483599299 ps
CPU time 31.88 seconds
Started Jul 29 05:06:52 PM PDT 24
Finished Jul 29 05:07:24 PM PDT 24
Peak memory 253612 kb
Host smart-dd1eda90-7bf5-4d0f-8057-62fe9b842da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194528198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmd
s.4194528198
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/38.spi_device_intercept.3753082858
Short name T901
Test name
Test status
Simulation time 2973720553 ps
CPU time 29.01 seconds
Started Jul 29 05:06:45 PM PDT 24
Finished Jul 29 05:07:14 PM PDT 24
Peak memory 225264 kb
Host smart-42b1cf99-3c02-42a8-b541-4c8af8d44f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753082858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.3753082858
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.1090066954
Short name T753
Test name
Test status
Simulation time 8431978235 ps
CPU time 24.88 seconds
Started Jul 29 05:06:45 PM PDT 24
Finished Jul 29 05:07:10 PM PDT 24
Peak memory 241744 kb
Host smart-e48b154b-de35-4904-9c0f-c8e88e823e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090066954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.1090066954
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.233867450
Short name T287
Test name
Test status
Simulation time 36323242906 ps
CPU time 11.59 seconds
Started Jul 29 05:06:52 PM PDT 24
Finished Jul 29 05:07:04 PM PDT 24
Peak memory 233556 kb
Host smart-a3a9084a-655c-40b9-ad82-c3ba26c7110f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233867450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swap
.233867450
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.2323797676
Short name T260
Test name
Test status
Simulation time 2922626003 ps
CPU time 10.12 seconds
Started Jul 29 05:06:43 PM PDT 24
Finished Jul 29 05:06:54 PM PDT 24
Peak memory 225292 kb
Host smart-d5bfdc2a-3b16-455b-916a-0668c32554ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323797676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.2323797676
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.1947819970
Short name T597
Test name
Test status
Simulation time 89675152 ps
CPU time 3.91 seconds
Started Jul 29 05:06:43 PM PDT 24
Finished Jul 29 05:06:47 PM PDT 24
Peak memory 220692 kb
Host smart-21647efe-1c18-47f3-ad7e-dc6ee59c4011
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1947819970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.1947819970
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.2519544295
Short name T774
Test name
Test status
Simulation time 11610998292 ps
CPU time 103.08 seconds
Started Jul 29 05:06:43 PM PDT 24
Finished Jul 29 05:08:26 PM PDT 24
Peak memory 266864 kb
Host smart-16f6f6f5-b294-47c5-a219-8aa1db7b8465
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519544295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.2519544295
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.728830811
Short name T443
Test name
Test status
Simulation time 4163905250 ps
CPU time 20.44 seconds
Started Jul 29 05:06:46 PM PDT 24
Finished Jul 29 05:07:06 PM PDT 24
Peak memory 217388 kb
Host smart-3009bd2d-c7f3-487e-86ef-a1f2e26246de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728830811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.728830811
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.378779672
Short name T629
Test name
Test status
Simulation time 5674951095 ps
CPU time 5.48 seconds
Started Jul 29 05:06:38 PM PDT 24
Finished Jul 29 05:06:44 PM PDT 24
Peak memory 217048 kb
Host smart-476dfcfb-49a8-4efb-9937-ae8cd72edfa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378779672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.378779672
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.2931081054
Short name T478
Test name
Test status
Simulation time 10579864 ps
CPU time 0.7 seconds
Started Jul 29 05:06:44 PM PDT 24
Finished Jul 29 05:06:45 PM PDT 24
Peak memory 206032 kb
Host smart-0db977f9-73b0-47eb-a8db-33cff8a2ad00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931081054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.2931081054
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.2120139949
Short name T884
Test name
Test status
Simulation time 23313793 ps
CPU time 0.75 seconds
Started Jul 29 05:06:42 PM PDT 24
Finished Jul 29 05:06:43 PM PDT 24
Peak memory 206616 kb
Host smart-077fd988-1d60-49aa-aed3-fe2d0c643a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120139949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.2120139949
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.1841444647
Short name T924
Test name
Test status
Simulation time 308687108 ps
CPU time 3.25 seconds
Started Jul 29 05:06:52 PM PDT 24
Finished Jul 29 05:06:55 PM PDT 24
Peak memory 225320 kb
Host smart-9d4ce5b0-1b14-42dd-a04d-93c472991b6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841444647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.1841444647
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.2272165257
Short name T764
Test name
Test status
Simulation time 45191490 ps
CPU time 0.75 seconds
Started Jul 29 05:06:51 PM PDT 24
Finished Jul 29 05:06:52 PM PDT 24
Peak memory 206216 kb
Host smart-07337088-e89c-4770-a45b-313f65879092
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272165257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
2272165257
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.3444961014
Short name T808
Test name
Test status
Simulation time 2239057706 ps
CPU time 24.23 seconds
Started Jul 29 05:06:50 PM PDT 24
Finished Jul 29 05:07:14 PM PDT 24
Peak memory 233396 kb
Host smart-a4e57748-3d26-4639-ae5a-f18b8bc0a737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444961014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.3444961014
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.2247919266
Short name T468
Test name
Test status
Simulation time 90595124 ps
CPU time 0.79 seconds
Started Jul 29 05:06:51 PM PDT 24
Finished Jul 29 05:06:52 PM PDT 24
Peak memory 207384 kb
Host smart-94a455c0-c43d-4e78-bd8d-998d11daf4c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247919266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.2247919266
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.2820697720
Short name T69
Test name
Test status
Simulation time 17461374837 ps
CPU time 154.05 seconds
Started Jul 29 05:06:51 PM PDT 24
Finished Jul 29 05:09:25 PM PDT 24
Peak memory 250136 kb
Host smart-420a1ec5-6a51-4b9d-8097-d28319268753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820697720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.2820697720
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.132491294
Short name T58
Test name
Test status
Simulation time 27732414639 ps
CPU time 118.72 seconds
Started Jul 29 05:06:51 PM PDT 24
Finished Jul 29 05:08:50 PM PDT 24
Peak memory 258168 kb
Host smart-be5d1ca9-f918-4f7f-b8a3-a1003344cf7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132491294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.132491294
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.2187777701
Short name T463
Test name
Test status
Simulation time 2105738706 ps
CPU time 27.63 seconds
Started Jul 29 05:06:51 PM PDT 24
Finished Jul 29 05:07:19 PM PDT 24
Peak memory 218436 kb
Host smart-b0a7cc6c-d9cb-4357-9fbb-180a4120601b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187777701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.2187777701
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.136902329
Short name T809
Test name
Test status
Simulation time 1573861093 ps
CPU time 12.93 seconds
Started Jul 29 05:06:49 PM PDT 24
Finished Jul 29 05:07:02 PM PDT 24
Peak memory 236896 kb
Host smart-164654e8-0c2a-471f-a060-d105fbefc41a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136902329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.136902329
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.2181435441
Short name T746
Test name
Test status
Simulation time 37565875932 ps
CPU time 255.76 seconds
Started Jul 29 05:06:50 PM PDT 24
Finished Jul 29 05:11:06 PM PDT 24
Peak memory 249768 kb
Host smart-ea828b36-7315-4c25-a38c-6ce215a8db41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181435441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmd
s.2181435441
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/39.spi_device_intercept.1012492572
Short name T721
Test name
Test status
Simulation time 140402684 ps
CPU time 2.63 seconds
Started Jul 29 05:06:51 PM PDT 24
Finished Jul 29 05:06:54 PM PDT 24
Peak memory 227880 kb
Host smart-ca17d7ee-8f92-4595-84cf-45293930a6a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012492572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.1012492572
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.3848087313
Short name T230
Test name
Test status
Simulation time 130615568 ps
CPU time 3.54 seconds
Started Jul 29 05:06:49 PM PDT 24
Finished Jul 29 05:06:53 PM PDT 24
Peak memory 225264 kb
Host smart-1ee2424e-304d-4bbe-a354-4c4e5f08420d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848087313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.3848087313
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.1175112339
Short name T883
Test name
Test status
Simulation time 291873225 ps
CPU time 2.37 seconds
Started Jul 29 05:06:50 PM PDT 24
Finished Jul 29 05:06:52 PM PDT 24
Peak memory 224404 kb
Host smart-e0ae62b7-94bf-4edb-b9d6-7d6fcdb5325b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175112339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.1175112339
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.1862434955
Short name T912
Test name
Test status
Simulation time 7071178368 ps
CPU time 7.03 seconds
Started Jul 29 05:06:51 PM PDT 24
Finished Jul 29 05:06:58 PM PDT 24
Peak memory 241536 kb
Host smart-c255a031-fbd2-40e8-ab92-2fe0e07d822f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862434955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.1862434955
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.2464343813
Short name T345
Test name
Test status
Simulation time 93271462 ps
CPU time 4.05 seconds
Started Jul 29 05:06:50 PM PDT 24
Finished Jul 29 05:06:55 PM PDT 24
Peak memory 221068 kb
Host smart-769a4939-0f4f-47a5-9d84-0f22a9f0f64e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2464343813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.2464343813
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.4188249604
Short name T617
Test name
Test status
Simulation time 23217489760 ps
CPU time 262.42 seconds
Started Jul 29 05:06:51 PM PDT 24
Finished Jul 29 05:11:14 PM PDT 24
Peak memory 252592 kb
Host smart-9b410c7c-d446-412b-8391-354de1185896
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188249604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.4188249604
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.557826371
Short name T498
Test name
Test status
Simulation time 939295895 ps
CPU time 14.65 seconds
Started Jul 29 05:06:50 PM PDT 24
Finished Jul 29 05:07:05 PM PDT 24
Peak memory 217232 kb
Host smart-8cad2cb4-83df-46eb-82d3-ae8445564bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557826371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.557826371
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.83310726
Short name T789
Test name
Test status
Simulation time 5009790328 ps
CPU time 9.33 seconds
Started Jul 29 05:06:49 PM PDT 24
Finished Jul 29 05:06:58 PM PDT 24
Peak memory 217060 kb
Host smart-7fdf869a-5337-40ff-9a8e-8470c6578e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83310726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.83310726
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.3779160237
Short name T821
Test name
Test status
Simulation time 178383498 ps
CPU time 2.79 seconds
Started Jul 29 05:06:50 PM PDT 24
Finished Jul 29 05:06:53 PM PDT 24
Peak memory 217000 kb
Host smart-437bbb33-07f4-4ec2-9146-4874eb26d0da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779160237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.3779160237
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.2902846075
Short name T874
Test name
Test status
Simulation time 37401021 ps
CPU time 0.91 seconds
Started Jul 29 05:06:54 PM PDT 24
Finished Jul 29 05:06:55 PM PDT 24
Peak memory 206516 kb
Host smart-9096c45e-a655-4a48-be64-24ca02a72772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902846075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.2902846075
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.3705926099
Short name T889
Test name
Test status
Simulation time 4575611830 ps
CPU time 21.55 seconds
Started Jul 29 05:06:51 PM PDT 24
Finished Jul 29 05:07:13 PM PDT 24
Peak memory 233584 kb
Host smart-1c8ca1cd-1a10-4211-b1ff-79e0a69a5c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705926099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.3705926099
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.1734091505
Short name T453
Test name
Test status
Simulation time 42005150 ps
CPU time 0.75 seconds
Started Jul 29 05:03:37 PM PDT 24
Finished Jul 29 05:03:38 PM PDT 24
Peak memory 205860 kb
Host smart-e4ec2805-bd98-4ab6-bfd6-29ad99116c2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734091505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.1
734091505
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.4240539377
Short name T235
Test name
Test status
Simulation time 6653869022 ps
CPU time 15.74 seconds
Started Jul 29 05:03:38 PM PDT 24
Finished Jul 29 05:03:53 PM PDT 24
Peak memory 233380 kb
Host smart-b75a9417-175f-4998-835e-e2104a8e3170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240539377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.4240539377
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.15537815
Short name T898
Test name
Test status
Simulation time 13183734 ps
CPU time 0.72 seconds
Started Jul 29 05:03:37 PM PDT 24
Finished Jul 29 05:03:38 PM PDT 24
Peak memory 205928 kb
Host smart-aa69042d-a809-435c-8cf8-199830bbd842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15537815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.15537815
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.960139967
Short name T292
Test name
Test status
Simulation time 1750124707 ps
CPU time 18.27 seconds
Started Jul 29 05:03:42 PM PDT 24
Finished Jul 29 05:04:01 PM PDT 24
Peak memory 225296 kb
Host smart-da2c99c9-108c-42e0-a775-e1f0f4f78fcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960139967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.960139967
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.1286323576
Short name T878
Test name
Test status
Simulation time 8873524516 ps
CPU time 95.76 seconds
Started Jul 29 05:03:34 PM PDT 24
Finished Jul 29 05:05:10 PM PDT 24
Peak memory 252568 kb
Host smart-b402a715-8b89-4d91-8dec-34824c07312f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286323576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.1286323576
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.648341851
Short name T653
Test name
Test status
Simulation time 23249225153 ps
CPU time 314.81 seconds
Started Jul 29 05:03:37 PM PDT 24
Finished Jul 29 05:08:52 PM PDT 24
Peak memory 266516 kb
Host smart-723d3e59-29d9-4dc3-8fdb-37a7e763aaa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648341851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle.
648341851
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.3605036748
Short name T752
Test name
Test status
Simulation time 189343413 ps
CPU time 3.53 seconds
Started Jul 29 05:03:39 PM PDT 24
Finished Jul 29 05:03:43 PM PDT 24
Peak memory 233512 kb
Host smart-6d04bda3-e85c-4709-a6fa-9744499860e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605036748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.3605036748
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.2093472748
Short name T910
Test name
Test status
Simulation time 40937295 ps
CPU time 0.76 seconds
Started Jul 29 05:03:38 PM PDT 24
Finished Jul 29 05:03:39 PM PDT 24
Peak memory 216356 kb
Host smart-4f8da766-818e-4024-b50b-0ea1c913099c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093472748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds
.2093472748
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/4.spi_device_intercept.4248856839
Short name T743
Test name
Test status
Simulation time 231249111 ps
CPU time 3.98 seconds
Started Jul 29 05:03:39 PM PDT 24
Finished Jul 29 05:03:43 PM PDT 24
Peak memory 225236 kb
Host smart-74660872-dc82-4178-b916-5e5afb1ee84c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248856839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.4248856839
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.1521166898
Short name T481
Test name
Test status
Simulation time 576238452 ps
CPU time 3.4 seconds
Started Jul 29 05:03:43 PM PDT 24
Finished Jul 29 05:03:46 PM PDT 24
Peak memory 225248 kb
Host smart-9f01d9a3-4223-42d1-bede-935d2408bab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521166898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.1521166898
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.1307404523
Short name T894
Test name
Test status
Simulation time 27095381 ps
CPU time 1.14 seconds
Started Jul 29 05:03:40 PM PDT 24
Finished Jul 29 05:03:41 PM PDT 24
Peak memory 217196 kb
Host smart-1ba5ec23-527a-4923-a75f-8ee655192499
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307404523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.spi_device_mem_parity.1307404523
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.3060155761
Short name T190
Test name
Test status
Simulation time 8395550117 ps
CPU time 27.07 seconds
Started Jul 29 05:03:39 PM PDT 24
Finished Jul 29 05:04:06 PM PDT 24
Peak memory 233532 kb
Host smart-558ee23c-65e1-4abb-bba3-cf8c2dea2d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060155761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.3060155761
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.3186979390
Short name T493
Test name
Test status
Simulation time 7878575795 ps
CPU time 9.08 seconds
Started Jul 29 05:03:37 PM PDT 24
Finished Jul 29 05:03:47 PM PDT 24
Peak memory 225228 kb
Host smart-7b55a932-5746-4bb6-9600-bbf56e2523c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186979390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.3186979390
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.3958457180
Short name T146
Test name
Test status
Simulation time 4727026366 ps
CPU time 10.83 seconds
Started Jul 29 05:03:36 PM PDT 24
Finished Jul 29 05:03:47 PM PDT 24
Peak memory 220712 kb
Host smart-ca933dc6-66ff-4377-a87b-463ac0993ad2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3958457180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.3958457180
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.849760463
Short name T75
Test name
Test status
Simulation time 39300327 ps
CPU time 0.97 seconds
Started Jul 29 05:03:41 PM PDT 24
Finished Jul 29 05:03:42 PM PDT 24
Peak memory 235592 kb
Host smart-41e4f3a0-e3b2-4c37-9a22-305b3ba650f9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849760463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.849760463
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.1939930861
Short name T582
Test name
Test status
Simulation time 41825001 ps
CPU time 0.94 seconds
Started Jul 29 05:03:47 PM PDT 24
Finished Jul 29 05:03:48 PM PDT 24
Peak memory 207116 kb
Host smart-9dc97a15-5ee9-4327-bd91-c7a29cdc400d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939930861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.1939930861
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.758844667
Short name T561
Test name
Test status
Simulation time 486956000 ps
CPU time 5.26 seconds
Started Jul 29 05:03:35 PM PDT 24
Finished Jul 29 05:03:40 PM PDT 24
Peak memory 216940 kb
Host smart-17645682-76fc-4f7e-9735-ec1097694624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758844667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.758844667
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.790221065
Short name T326
Test name
Test status
Simulation time 4260872155 ps
CPU time 6.14 seconds
Started Jul 29 05:03:37 PM PDT 24
Finished Jul 29 05:03:44 PM PDT 24
Peak memory 217164 kb
Host smart-a40bb2ba-8531-4a1c-9d68-4ee4b0a2dcb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790221065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.790221065
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.2304429321
Short name T985
Test name
Test status
Simulation time 19084088 ps
CPU time 0.99 seconds
Started Jul 29 05:03:36 PM PDT 24
Finished Jul 29 05:03:37 PM PDT 24
Peak memory 207772 kb
Host smart-2dd5a416-2632-4ed3-bacd-2b4669cbd0a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304429321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.2304429321
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.393857260
Short name T8
Test name
Test status
Simulation time 29777944 ps
CPU time 0.86 seconds
Started Jul 29 05:03:42 PM PDT 24
Finished Jul 29 05:03:43 PM PDT 24
Peak memory 206576 kb
Host smart-55fd6b6a-9d47-4d84-b7fd-65fb82e9e686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393857260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.393857260
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.701346607
Short name T374
Test name
Test status
Simulation time 96710761 ps
CPU time 2.41 seconds
Started Jul 29 05:03:47 PM PDT 24
Finished Jul 29 05:03:49 PM PDT 24
Peak memory 225276 kb
Host smart-8108bfa7-8e23-43c5-b3fb-394e74857571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701346607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.701346607
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.2715208204
Short name T750
Test name
Test status
Simulation time 13069528 ps
CPU time 0.72 seconds
Started Jul 29 05:06:57 PM PDT 24
Finished Jul 29 05:06:58 PM PDT 24
Peak memory 206224 kb
Host smart-ec788a5a-fe0f-49e9-bba7-c7daf9ff9aef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715208204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
2715208204
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.3308172359
Short name T558
Test name
Test status
Simulation time 1982881143 ps
CPU time 22.52 seconds
Started Jul 29 05:06:56 PM PDT 24
Finished Jul 29 05:07:18 PM PDT 24
Peak memory 233440 kb
Host smart-59ab2946-e5bc-4054-ae73-8afe46ad3491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308172359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.3308172359
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.1791232667
Short name T459
Test name
Test status
Simulation time 44354165 ps
CPU time 0.79 seconds
Started Jul 29 05:06:50 PM PDT 24
Finished Jul 29 05:06:51 PM PDT 24
Peak memory 206288 kb
Host smart-c2baba84-5858-4da8-ab55-c15053cd72e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791232667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.1791232667
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.291643745
Short name T280
Test name
Test status
Simulation time 323136773692 ps
CPU time 575.95 seconds
Started Jul 29 05:06:56 PM PDT 24
Finished Jul 29 05:16:32 PM PDT 24
Peak memory 265848 kb
Host smart-f3ccaff9-8476-42ab-8fbe-bd5e45de8d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291643745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.291643745
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.1770503603
Short name T994
Test name
Test status
Simulation time 15859408464 ps
CPU time 21.95 seconds
Started Jul 29 05:06:58 PM PDT 24
Finished Jul 29 05:07:20 PM PDT 24
Peak memory 218236 kb
Host smart-3829f676-9031-4a7f-93d0-0393115f56c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770503603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.1770503603
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.213205158
Short name T64
Test name
Test status
Simulation time 4363166152 ps
CPU time 39.88 seconds
Started Jul 29 05:06:57 PM PDT 24
Finished Jul 29 05:07:37 PM PDT 24
Peak memory 241692 kb
Host smart-eeaa0e9a-d5b3-4c36-a19d-51d403f9d693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213205158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idle
.213205158
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.890500063
Short name T840
Test name
Test status
Simulation time 157382865 ps
CPU time 5.03 seconds
Started Jul 29 05:06:56 PM PDT 24
Finished Jul 29 05:07:01 PM PDT 24
Peak memory 233348 kb
Host smart-9a1578ec-c94a-4ceb-b32d-99ae9f3850e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890500063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.890500063
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.1070943267
Short name T295
Test name
Test status
Simulation time 58828356407 ps
CPU time 242.36 seconds
Started Jul 29 05:06:56 PM PDT 24
Finished Jul 29 05:10:59 PM PDT 24
Peak memory 262632 kb
Host smart-bd29f8c5-bdd8-4658-8491-5dce051402cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070943267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmd
s.1070943267
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/40.spi_device_intercept.3225137887
Short name T670
Test name
Test status
Simulation time 7093825765 ps
CPU time 6.57 seconds
Started Jul 29 05:06:58 PM PDT 24
Finished Jul 29 05:07:05 PM PDT 24
Peak memory 225352 kb
Host smart-3e9ee271-837f-4b07-b440-f223f07bf28f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225137887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.3225137887
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.3501958864
Short name T475
Test name
Test status
Simulation time 3815691131 ps
CPU time 41.5 seconds
Started Jul 29 05:06:57 PM PDT 24
Finished Jul 29 05:07:38 PM PDT 24
Peak memory 225400 kb
Host smart-ffcb6000-d89d-48ba-9be0-36ba9fa24aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501958864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.3501958864
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.1757013129
Short name T251
Test name
Test status
Simulation time 863437934 ps
CPU time 5.02 seconds
Started Jul 29 05:06:56 PM PDT 24
Finished Jul 29 05:07:01 PM PDT 24
Peak memory 233372 kb
Host smart-e332f826-29c8-4649-ae13-cf54b1749e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757013129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.1757013129
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.2033586406
Short name T364
Test name
Test status
Simulation time 311620379 ps
CPU time 2.04 seconds
Started Jul 29 05:06:57 PM PDT 24
Finished Jul 29 05:06:59 PM PDT 24
Peak memory 224456 kb
Host smart-b46ae717-8238-4dfa-ba98-7134708d55c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033586406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.2033586406
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.2199513802
Short name T829
Test name
Test status
Simulation time 141115722 ps
CPU time 4.15 seconds
Started Jul 29 05:06:57 PM PDT 24
Finished Jul 29 05:07:01 PM PDT 24
Peak memory 223588 kb
Host smart-51213991-a972-4318-a7d9-4afee4c95f0f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2199513802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.2199513802
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.10756748
Short name T310
Test name
Test status
Simulation time 5569422996 ps
CPU time 26.85 seconds
Started Jul 29 05:06:56 PM PDT 24
Finished Jul 29 05:07:23 PM PDT 24
Peak memory 217004 kb
Host smart-db6e0978-a1a4-47a1-b33a-711ee94845b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10756748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.10756748
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.3823630092
Short name T535
Test name
Test status
Simulation time 6276184197 ps
CPU time 20.86 seconds
Started Jul 29 05:06:56 PM PDT 24
Finished Jul 29 05:07:17 PM PDT 24
Peak memory 217000 kb
Host smart-696f1d09-0a9b-445a-a453-5ea2e17bb9f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823630092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.3823630092
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.2333301103
Short name T844
Test name
Test status
Simulation time 64762557 ps
CPU time 0.89 seconds
Started Jul 29 05:06:57 PM PDT 24
Finished Jul 29 05:06:58 PM PDT 24
Peak memory 208416 kb
Host smart-b5661c88-6a0d-41a0-9153-d7090a001624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333301103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.2333301103
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.1264511195
Short name T400
Test name
Test status
Simulation time 70957319 ps
CPU time 0.91 seconds
Started Jul 29 05:06:58 PM PDT 24
Finished Jul 29 05:06:59 PM PDT 24
Peak memory 206580 kb
Host smart-811fdfc4-d380-461d-82b3-0344da886929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264511195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.1264511195
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.24937383
Short name T888
Test name
Test status
Simulation time 5845278659 ps
CPU time 14.6 seconds
Started Jul 29 05:06:56 PM PDT 24
Finished Jul 29 05:07:11 PM PDT 24
Peak memory 239392 kb
Host smart-a438c17a-a89e-4c55-9654-7e100deba9e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24937383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.24937383
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.326437353
Short name T413
Test name
Test status
Simulation time 15757000 ps
CPU time 0.73 seconds
Started Jul 29 05:07:05 PM PDT 24
Finished Jul 29 05:07:07 PM PDT 24
Peak memory 205848 kb
Host smart-31c9f6ec-10e6-4e40-89e5-305ffae63f57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326437353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.326437353
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.3660855600
Short name T919
Test name
Test status
Simulation time 110040803 ps
CPU time 2.62 seconds
Started Jul 29 05:07:01 PM PDT 24
Finished Jul 29 05:07:04 PM PDT 24
Peak memory 233040 kb
Host smart-cb444268-bfba-4d54-9163-df9fdef784bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660855600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.3660855600
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.2832950405
Short name T580
Test name
Test status
Simulation time 88467854 ps
CPU time 0.79 seconds
Started Jul 29 05:07:03 PM PDT 24
Finished Jul 29 05:07:04 PM PDT 24
Peak memory 205912 kb
Host smart-0297e8be-f05c-4c8b-bbc0-db6e281d3e98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832950405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.2832950405
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.3788060713
Short name T86
Test name
Test status
Simulation time 5797361436 ps
CPU time 80.83 seconds
Started Jul 29 05:07:03 PM PDT 24
Finished Jul 29 05:08:24 PM PDT 24
Peak memory 253836 kb
Host smart-a9b1f240-3bea-44da-a501-3cb21689be90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788060713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.3788060713
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.1251727889
Short name T376
Test name
Test status
Simulation time 4197900167 ps
CPU time 66.57 seconds
Started Jul 29 05:07:01 PM PDT 24
Finished Jul 29 05:08:08 PM PDT 24
Peak memory 251444 kb
Host smart-dc482d9f-c533-4845-a6b3-0d57563a5d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251727889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.1251727889
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.219059093
Short name T1012
Test name
Test status
Simulation time 84475128320 ps
CPU time 274.68 seconds
Started Jul 29 05:07:05 PM PDT 24
Finished Jul 29 05:11:39 PM PDT 24
Peak memory 249868 kb
Host smart-c12dd546-35a5-4e8d-acb5-07636ef83856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219059093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idle
.219059093
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.3380525953
Short name T813
Test name
Test status
Simulation time 371992232 ps
CPU time 5.73 seconds
Started Jul 29 05:07:07 PM PDT 24
Finished Jul 29 05:07:13 PM PDT 24
Peak memory 235312 kb
Host smart-0cea3e0a-c370-466f-9468-8b553dd04a4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380525953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.3380525953
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_intercept.267981853
Short name T362
Test name
Test status
Simulation time 377385210 ps
CPU time 6.01 seconds
Started Jul 29 05:07:03 PM PDT 24
Finished Jul 29 05:07:09 PM PDT 24
Peak memory 225148 kb
Host smart-859e2145-3a53-427c-92f8-ccf710127bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267981853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.267981853
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.1371651526
Short name T882
Test name
Test status
Simulation time 649419033 ps
CPU time 15.04 seconds
Started Jul 29 05:07:02 PM PDT 24
Finished Jul 29 05:07:17 PM PDT 24
Peak memory 233400 kb
Host smart-390b5861-dcc9-44bd-8aa2-fca7cd1387b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371651526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.1371651526
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.3088746078
Short name T261
Test name
Test status
Simulation time 38705644439 ps
CPU time 23.47 seconds
Started Jul 29 05:07:02 PM PDT 24
Finished Jul 29 05:07:26 PM PDT 24
Peak memory 225328 kb
Host smart-aee22424-4662-4f30-8e83-e60e87450760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088746078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.3088746078
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.840366670
Short name T259
Test name
Test status
Simulation time 7499923315 ps
CPU time 6.73 seconds
Started Jul 29 05:07:01 PM PDT 24
Finished Jul 29 05:07:08 PM PDT 24
Peak memory 225296 kb
Host smart-15951503-1d45-4cc3-b5c4-67eb82736c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840366670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.840366670
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.42054553
Short name T998
Test name
Test status
Simulation time 1903333569 ps
CPU time 6.39 seconds
Started Jul 29 05:07:02 PM PDT 24
Finished Jul 29 05:07:08 PM PDT 24
Peak memory 223580 kb
Host smart-69286299-1d89-4ae0-9d47-c0803d35fbf8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=42054553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_direc
t.42054553
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.1158767687
Short name T710
Test name
Test status
Simulation time 1420591048 ps
CPU time 18.83 seconds
Started Jul 29 05:07:03 PM PDT 24
Finished Jul 29 05:07:22 PM PDT 24
Peak memory 217244 kb
Host smart-e9ad5d1e-8528-448b-a4e6-2ebe2cf043e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158767687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.1158767687
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.3683980897
Short name T358
Test name
Test status
Simulation time 7644847413 ps
CPU time 8.03 seconds
Started Jul 29 05:07:01 PM PDT 24
Finished Jul 29 05:07:10 PM PDT 24
Peak memory 217104 kb
Host smart-06da068a-8c54-46d0-9b4a-6ef47bb625d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683980897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.3683980897
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.1863101428
Short name T732
Test name
Test status
Simulation time 171285240 ps
CPU time 1.16 seconds
Started Jul 29 05:07:03 PM PDT 24
Finished Jul 29 05:07:05 PM PDT 24
Peak memory 216704 kb
Host smart-774de31b-21c8-4295-961b-a3a12afc353b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863101428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.1863101428
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.3161068718
Short name T37
Test name
Test status
Simulation time 85401041 ps
CPU time 0.88 seconds
Started Jul 29 05:07:02 PM PDT 24
Finished Jul 29 05:07:03 PM PDT 24
Peak memory 206620 kb
Host smart-9f2e47bc-aa17-40db-bf49-7d1cec70c646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161068718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.3161068718
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.3955672872
Short name T511
Test name
Test status
Simulation time 199195284 ps
CPU time 2.83 seconds
Started Jul 29 05:07:04 PM PDT 24
Finished Jul 29 05:07:07 PM PDT 24
Peak memory 225268 kb
Host smart-4f7012cc-0324-4e1f-a625-2d41db987d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955672872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.3955672872
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.3590317295
Short name T361
Test name
Test status
Simulation time 31429457 ps
CPU time 0.76 seconds
Started Jul 29 05:07:08 PM PDT 24
Finished Jul 29 05:07:09 PM PDT 24
Peak memory 205856 kb
Host smart-5f07f186-5887-43ee-9bd2-6a0a626c9a1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590317295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
3590317295
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.3657278559
Short name T959
Test name
Test status
Simulation time 1225750072 ps
CPU time 5.87 seconds
Started Jul 29 05:07:09 PM PDT 24
Finished Jul 29 05:07:15 PM PDT 24
Peak memory 225264 kb
Host smart-7f749f7b-3fc2-4809-a268-5f6a01bc7ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657278559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.3657278559
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.3132650231
Short name T726
Test name
Test status
Simulation time 27849027 ps
CPU time 0.83 seconds
Started Jul 29 05:07:11 PM PDT 24
Finished Jul 29 05:07:12 PM PDT 24
Peak memory 207000 kb
Host smart-d0159694-3e13-49e6-919b-41294b8c4541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132650231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.3132650231
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.2476040408
Short name T408
Test name
Test status
Simulation time 32586740441 ps
CPU time 97.48 seconds
Started Jul 29 05:07:07 PM PDT 24
Finished Jul 29 05:08:45 PM PDT 24
Peak memory 265284 kb
Host smart-ec8b15ad-cb03-40ba-be9c-8206b9348b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476040408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.2476040408
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.2096028995
Short name T986
Test name
Test status
Simulation time 62799324321 ps
CPU time 166.15 seconds
Started Jul 29 05:07:12 PM PDT 24
Finished Jul 29 05:09:59 PM PDT 24
Peak memory 249888 kb
Host smart-5457e67e-f15e-4217-91ab-6236529c10eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096028995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.2096028995
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.1587727263
Short name T747
Test name
Test status
Simulation time 36694371581 ps
CPU time 100.73 seconds
Started Jul 29 05:07:07 PM PDT 24
Finished Jul 29 05:08:48 PM PDT 24
Peak memory 252336 kb
Host smart-d347a9bc-7450-43e9-8cb6-c05b3ac27f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587727263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.1587727263
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.3484414948
Short name T967
Test name
Test status
Simulation time 175155495 ps
CPU time 6.29 seconds
Started Jul 29 05:07:08 PM PDT 24
Finished Jul 29 05:07:15 PM PDT 24
Peak memory 233400 kb
Host smart-72489dec-0444-4f09-9690-c3d0c55532b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484414948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.3484414948
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_intercept.3059494821
Short name T423
Test name
Test status
Simulation time 5359417539 ps
CPU time 19.78 seconds
Started Jul 29 05:07:11 PM PDT 24
Finished Jul 29 05:07:31 PM PDT 24
Peak memory 233544 kb
Host smart-081ec15c-e4c3-4ef8-81f8-8346bc54130c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059494821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.3059494821
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.387233725
Short name T519
Test name
Test status
Simulation time 1243509657 ps
CPU time 9.22 seconds
Started Jul 29 05:07:10 PM PDT 24
Finished Jul 29 05:07:19 PM PDT 24
Peak memory 239988 kb
Host smart-4b30874a-e402-4649-86f4-57b09d01321c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387233725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.387233725
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.1481355705
Short name T256
Test name
Test status
Simulation time 642830640 ps
CPU time 2.98 seconds
Started Jul 29 05:07:08 PM PDT 24
Finished Jul 29 05:07:11 PM PDT 24
Peak memory 233416 kb
Host smart-a86cd864-f773-4e6b-8f49-a54de3e30d43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481355705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.1481355705
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.1714139833
Short name T386
Test name
Test status
Simulation time 16947746848 ps
CPU time 19.98 seconds
Started Jul 29 05:07:08 PM PDT 24
Finished Jul 29 05:07:28 PM PDT 24
Peak memory 225256 kb
Host smart-00820b4b-5a86-40b8-9352-bb44021c5ed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714139833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.1714139833
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.1902373641
Short name T510
Test name
Test status
Simulation time 151846304 ps
CPU time 4.56 seconds
Started Jul 29 05:07:11 PM PDT 24
Finished Jul 29 05:07:16 PM PDT 24
Peak memory 223676 kb
Host smart-688507e5-c2fb-4f18-b64c-aa8ac378448d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1902373641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.1902373641
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.3991856973
Short name T21
Test name
Test status
Simulation time 3453295359 ps
CPU time 89.01 seconds
Started Jul 29 05:07:08 PM PDT 24
Finished Jul 29 05:08:37 PM PDT 24
Peak memory 255344 kb
Host smart-4f39f12f-0d6f-4410-9d3a-89149c3a668b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991856973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.3991856973
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.1295113297
Short name T602
Test name
Test status
Simulation time 4589887222 ps
CPU time 26.95 seconds
Started Jul 29 05:07:08 PM PDT 24
Finished Jul 29 05:07:36 PM PDT 24
Peak memory 216988 kb
Host smart-5058739f-8e55-4fce-93e8-7ae023c277ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295113297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.1295113297
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.1804399646
Short name T477
Test name
Test status
Simulation time 97793509269 ps
CPU time 23.66 seconds
Started Jul 29 05:07:12 PM PDT 24
Finished Jul 29 05:07:36 PM PDT 24
Peak memory 216968 kb
Host smart-37fde659-3284-4cd1-8d67-e3c80604ffca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804399646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.1804399646
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.3832850020
Short name T863
Test name
Test status
Simulation time 59143429 ps
CPU time 1.73 seconds
Started Jul 29 05:07:08 PM PDT 24
Finished Jul 29 05:07:09 PM PDT 24
Peak memory 216984 kb
Host smart-065208cf-9865-40cf-8a3f-e90da0fbe8e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832850020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.3832850020
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.2974558290
Short name T805
Test name
Test status
Simulation time 15932802 ps
CPU time 0.75 seconds
Started Jul 29 05:07:07 PM PDT 24
Finished Jul 29 05:07:08 PM PDT 24
Peak memory 206596 kb
Host smart-2374d202-5945-4bfc-94a5-88b9f89d57aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974558290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.2974558290
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.2561309529
Short name T244
Test name
Test status
Simulation time 8092274092 ps
CPU time 7.59 seconds
Started Jul 29 05:07:08 PM PDT 24
Finished Jul 29 05:07:16 PM PDT 24
Peak memory 240872 kb
Host smart-f1241d7f-a76e-47d6-9dc6-01fa634c91d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561309529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.2561309529
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.2987746883
Short name T492
Test name
Test status
Simulation time 48735901 ps
CPU time 0.7 seconds
Started Jul 29 05:07:14 PM PDT 24
Finished Jul 29 05:07:15 PM PDT 24
Peak memory 205780 kb
Host smart-d8bf60c1-c2cc-48dc-a540-0f5da50d14b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987746883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
2987746883
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.413196374
Short name T627
Test name
Test status
Simulation time 2745977696 ps
CPU time 13.22 seconds
Started Jul 29 05:07:12 PM PDT 24
Finished Jul 29 05:07:26 PM PDT 24
Peak memory 233372 kb
Host smart-19005375-d268-408a-ae4d-c924a451d044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413196374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.413196374
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.1807311154
Short name T375
Test name
Test status
Simulation time 15347789 ps
CPU time 0.75 seconds
Started Jul 29 05:07:08 PM PDT 24
Finished Jul 29 05:07:09 PM PDT 24
Peak memory 206252 kb
Host smart-ac30b048-aa6c-4d71-9f1d-4465d1aa4702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807311154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.1807311154
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.3091160831
Short name T934
Test name
Test status
Simulation time 81752992334 ps
CPU time 57.06 seconds
Started Jul 29 05:07:15 PM PDT 24
Finished Jul 29 05:08:12 PM PDT 24
Peak memory 257348 kb
Host smart-d06233bb-5643-4551-bdb1-da07568f9595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091160831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.3091160831
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.3730437404
Short name T141
Test name
Test status
Simulation time 40658670506 ps
CPU time 413.89 seconds
Started Jul 29 05:07:15 PM PDT 24
Finished Jul 29 05:14:09 PM PDT 24
Peak memory 258184 kb
Host smart-b4700c97-fc44-409e-879d-f46640fb57a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730437404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.3730437404
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.1833422607
Short name T594
Test name
Test status
Simulation time 12307309703 ps
CPU time 70.95 seconds
Started Jul 29 05:07:16 PM PDT 24
Finished Jul 29 05:08:27 PM PDT 24
Peak memory 249856 kb
Host smart-c220b0ec-61ac-457a-8bd3-71fbdb60c682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833422607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.1833422607
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.504897956
Short name T297
Test name
Test status
Simulation time 6774739233 ps
CPU time 43.01 seconds
Started Jul 29 05:07:12 PM PDT 24
Finished Jul 29 05:07:55 PM PDT 24
Peak memory 240268 kb
Host smart-da37c18a-2944-4510-8dde-dc00815dfb51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504897956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.504897956
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_intercept.1753535559
Short name T494
Test name
Test status
Simulation time 1099140506 ps
CPU time 3.87 seconds
Started Jul 29 05:07:08 PM PDT 24
Finished Jul 29 05:07:12 PM PDT 24
Peak memory 233488 kb
Host smart-a1a0f07a-fe4a-410e-be85-df442177baa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753535559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.1753535559
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.2125850365
Short name T759
Test name
Test status
Simulation time 2364321173 ps
CPU time 12.54 seconds
Started Jul 29 05:07:08 PM PDT 24
Finished Jul 29 05:07:21 PM PDT 24
Peak memory 233372 kb
Host smart-bb25d868-af2f-431b-a290-e093a729ee5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125850365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.2125850365
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.1112666170
Short name T538
Test name
Test status
Simulation time 3416155539 ps
CPU time 5.46 seconds
Started Jul 29 05:07:09 PM PDT 24
Finished Jul 29 05:07:15 PM PDT 24
Peak memory 233480 kb
Host smart-90390aa0-69ab-4fac-95f8-ebd367826a29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112666170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.1112666170
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.3583395885
Short name T529
Test name
Test status
Simulation time 11347435415 ps
CPU time 19.64 seconds
Started Jul 29 05:07:09 PM PDT 24
Finished Jul 29 05:07:29 PM PDT 24
Peak memory 225332 kb
Host smart-157cb09e-3178-4c77-8351-53ce62d0210f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583395885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.3583395885
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.1332225188
Short name T576
Test name
Test status
Simulation time 588853841 ps
CPU time 5.54 seconds
Started Jul 29 05:07:14 PM PDT 24
Finished Jul 29 05:07:20 PM PDT 24
Peak memory 222712 kb
Host smart-7e393307-7727-48ed-b089-5b4088566b8b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1332225188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.1332225188
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.2070944185
Short name T371
Test name
Test status
Simulation time 24386156372 ps
CPU time 257.76 seconds
Started Jul 29 05:07:13 PM PDT 24
Finished Jul 29 05:11:31 PM PDT 24
Peak memory 251536 kb
Host smart-ee6e499a-7508-492f-8900-53de7c8bdb9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070944185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.2070944185
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.137373889
Short name T391
Test name
Test status
Simulation time 2605467949 ps
CPU time 16.71 seconds
Started Jul 29 05:07:12 PM PDT 24
Finished Jul 29 05:07:29 PM PDT 24
Peak memory 216944 kb
Host smart-a1a031d9-512d-4452-873d-43b187b4d4f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137373889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.137373889
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.2802074987
Short name T738
Test name
Test status
Simulation time 1830583557 ps
CPU time 5.78 seconds
Started Jul 29 05:07:10 PM PDT 24
Finished Jul 29 05:07:16 PM PDT 24
Peak memory 216912 kb
Host smart-6a0ffec9-016e-464e-9e12-2c125209b398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802074987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.2802074987
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.525068169
Short name T996
Test name
Test status
Simulation time 17079263 ps
CPU time 0.99 seconds
Started Jul 29 05:07:09 PM PDT 24
Finished Jul 29 05:07:10 PM PDT 24
Peak memory 207584 kb
Host smart-6c1f623f-6bce-4925-9221-c046f8f359bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525068169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.525068169
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.2259795930
Short name T507
Test name
Test status
Simulation time 30866634 ps
CPU time 0.84 seconds
Started Jul 29 05:07:08 PM PDT 24
Finished Jul 29 05:07:09 PM PDT 24
Peak memory 207528 kb
Host smart-e61565a7-a8ff-478c-a5a7-5ec6fb17fdeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259795930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.2259795930
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.2613452909
Short name T137
Test name
Test status
Simulation time 21452711682 ps
CPU time 17.29 seconds
Started Jul 29 05:07:09 PM PDT 24
Finished Jul 29 05:07:27 PM PDT 24
Peak memory 233476 kb
Host smart-3f197836-3e87-48e2-97bc-867ad1b28786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613452909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.2613452909
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.2305313221
Short name T687
Test name
Test status
Simulation time 15706388 ps
CPU time 0.74 seconds
Started Jul 29 05:07:22 PM PDT 24
Finished Jul 29 05:07:24 PM PDT 24
Peak memory 205876 kb
Host smart-9f296855-6e8d-4946-a79c-ef2f11932da8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305313221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
2305313221
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.3931785697
Short name T263
Test name
Test status
Simulation time 47878430 ps
CPU time 2.85 seconds
Started Jul 29 05:07:15 PM PDT 24
Finished Jul 29 05:07:18 PM PDT 24
Peak memory 233344 kb
Host smart-492c5fa1-0f04-410f-aa70-a9550db46e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931785697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.3931785697
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.2636842571
Short name T915
Test name
Test status
Simulation time 29615671 ps
CPU time 0.79 seconds
Started Jul 29 05:07:13 PM PDT 24
Finished Jul 29 05:07:14 PM PDT 24
Peak memory 206952 kb
Host smart-60b63f3a-2409-4e49-9587-0e14fcb71f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636842571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.2636842571
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.2170293397
Short name T539
Test name
Test status
Simulation time 164995448015 ps
CPU time 142.03 seconds
Started Jul 29 05:07:15 PM PDT 24
Finished Jul 29 05:09:37 PM PDT 24
Peak memory 249844 kb
Host smart-406fcf83-2303-40f8-ab4b-07b5213a486e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170293397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.2170293397
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.2397905789
Short name T866
Test name
Test status
Simulation time 389218256578 ps
CPU time 606.36 seconds
Started Jul 29 05:07:15 PM PDT 24
Finished Jul 29 05:17:21 PM PDT 24
Peak memory 274536 kb
Host smart-101f06b1-c76a-4a36-b36a-17c5eb6c61a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397905789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.2397905789
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.1743468494
Short name T340
Test name
Test status
Simulation time 671717313 ps
CPU time 3.28 seconds
Started Jul 29 05:07:15 PM PDT 24
Finished Jul 29 05:07:18 PM PDT 24
Peak memory 225136 kb
Host smart-11626467-f4d9-4ffb-b27a-7310c34d7ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743468494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.1743468494
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.1247983645
Short name T660
Test name
Test status
Simulation time 3660267480 ps
CPU time 26.04 seconds
Started Jul 29 05:07:14 PM PDT 24
Finished Jul 29 05:07:40 PM PDT 24
Peak memory 240968 kb
Host smart-03f1c663-cfd4-4c2a-82ca-37df32c594bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247983645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmd
s.1247983645
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/44.spi_device_intercept.1616785912
Short name T634
Test name
Test status
Simulation time 115782768 ps
CPU time 2.65 seconds
Started Jul 29 05:07:15 PM PDT 24
Finished Jul 29 05:07:18 PM PDT 24
Peak memory 233024 kb
Host smart-319611c3-d823-4236-991f-e7b743c71da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616785912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.1616785912
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.3429720064
Short name T316
Test name
Test status
Simulation time 29161257073 ps
CPU time 88.42 seconds
Started Jul 29 05:07:16 PM PDT 24
Finished Jul 29 05:08:44 PM PDT 24
Peak memory 249952 kb
Host smart-4e29d094-627f-4741-99f6-f4a9886cd8fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429720064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.3429720064
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.2440941433
Short name T335
Test name
Test status
Simulation time 6516756613 ps
CPU time 18 seconds
Started Jul 29 05:07:15 PM PDT 24
Finished Jul 29 05:07:33 PM PDT 24
Peak memory 233552 kb
Host smart-1aee1dbc-07d0-44b8-8ae0-f1291ce15a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440941433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.2440941433
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.3919722316
Short name T66
Test name
Test status
Simulation time 518060766 ps
CPU time 5.1 seconds
Started Jul 29 05:07:14 PM PDT 24
Finished Jul 29 05:07:19 PM PDT 24
Peak memory 228992 kb
Host smart-45676483-d0ab-455e-a0a5-5c2c51a66d66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919722316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.3919722316
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.3433281972
Short name T94
Test name
Test status
Simulation time 1000663414 ps
CPU time 5.15 seconds
Started Jul 29 05:07:14 PM PDT 24
Finished Jul 29 05:07:20 PM PDT 24
Peak memory 220840 kb
Host smart-ec43e2a9-3a7a-4ef0-abb4-3df88fcbb063
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3433281972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.3433281972
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.2628791707
Short name T1010
Test name
Test status
Simulation time 7277407690 ps
CPU time 35.23 seconds
Started Jul 29 05:07:21 PM PDT 24
Finished Jul 29 05:07:56 PM PDT 24
Peak memory 225396 kb
Host smart-964b230a-911b-4aaa-8e44-ab41864e3312
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628791707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.2628791707
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.1097550066
Short name T989
Test name
Test status
Simulation time 1825907297 ps
CPU time 29.12 seconds
Started Jul 29 05:07:15 PM PDT 24
Finished Jul 29 05:07:45 PM PDT 24
Peak memory 216984 kb
Host smart-751dd22a-c613-491d-b1c8-ac87a8aeb7bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097550066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.1097550066
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.721728904
Short name T858
Test name
Test status
Simulation time 1519917326 ps
CPU time 6.42 seconds
Started Jul 29 05:07:14 PM PDT 24
Finished Jul 29 05:07:21 PM PDT 24
Peak memory 216940 kb
Host smart-5eefeef6-9212-4c89-a842-1354a495c8dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721728904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.721728904
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.1180897686
Short name T318
Test name
Test status
Simulation time 62664018 ps
CPU time 1.1 seconds
Started Jul 29 05:07:16 PM PDT 24
Finished Jul 29 05:07:17 PM PDT 24
Peak memory 207808 kb
Host smart-38f71c79-e9ad-455b-a271-26b909df60b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180897686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.1180897686
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.2579578634
Short name T914
Test name
Test status
Simulation time 59130741 ps
CPU time 0.71 seconds
Started Jul 29 05:07:17 PM PDT 24
Finished Jul 29 05:07:18 PM PDT 24
Peak memory 206600 kb
Host smart-4baede11-0f1c-41d4-ade9-0c241600604b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579578634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.2579578634
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.2145068000
Short name T570
Test name
Test status
Simulation time 1470699610 ps
CPU time 2.94 seconds
Started Jul 29 05:07:15 PM PDT 24
Finished Jul 29 05:07:18 PM PDT 24
Peak memory 233388 kb
Host smart-6c543871-f864-48b9-a79a-a3d4e70b74ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145068000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.2145068000
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.1904417083
Short name T555
Test name
Test status
Simulation time 28302379 ps
CPU time 0.7 seconds
Started Jul 29 05:07:29 PM PDT 24
Finished Jul 29 05:07:30 PM PDT 24
Peak memory 205248 kb
Host smart-e3e2f7ec-81c6-4b09-927f-af88cafc9999
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904417083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
1904417083
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.4257367242
Short name T713
Test name
Test status
Simulation time 1411521575 ps
CPU time 5.17 seconds
Started Jul 29 05:07:21 PM PDT 24
Finished Jul 29 05:07:26 PM PDT 24
Peak memory 233352 kb
Host smart-c0360847-2171-4a77-9b6d-8019e8cd67e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257367242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.4257367242
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.3345483459
Short name T406
Test name
Test status
Simulation time 46321832 ps
CPU time 0.83 seconds
Started Jul 29 05:07:21 PM PDT 24
Finished Jul 29 05:07:22 PM PDT 24
Peak memory 207388 kb
Host smart-25419905-08c8-4fa1-807e-dda8b4adfe1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345483459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.3345483459
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.2316174837
Short name T87
Test name
Test status
Simulation time 61446790142 ps
CPU time 123.86 seconds
Started Jul 29 05:07:21 PM PDT 24
Finished Jul 29 05:09:25 PM PDT 24
Peak memory 267064 kb
Host smart-ecc5b5eb-c8dc-452e-8bd5-7e1924839568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316174837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.2316174837
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.1782417659
Short name T140
Test name
Test status
Simulation time 8434480484 ps
CPU time 24.48 seconds
Started Jul 29 05:07:22 PM PDT 24
Finished Jul 29 05:07:46 PM PDT 24
Peak memory 233624 kb
Host smart-eea6dc94-1fc0-4780-aa25-0ea05bfdec1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782417659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.1782417659
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.2794764246
Short name T150
Test name
Test status
Simulation time 575889043 ps
CPU time 7.01 seconds
Started Jul 29 05:07:20 PM PDT 24
Finished Jul 29 05:07:27 PM PDT 24
Peak memory 249296 kb
Host smart-bf9cb8ae-16b1-4f6b-9569-0045cae55880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794764246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.2794764246
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_intercept.3291998277
Short name T689
Test name
Test status
Simulation time 107788438 ps
CPU time 2.07 seconds
Started Jul 29 05:07:27 PM PDT 24
Finished Jul 29 05:07:29 PM PDT 24
Peak memory 225208 kb
Host smart-ffe497f9-304d-49b6-a48c-b0fdf5e76c85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291998277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.3291998277
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.2282861363
Short name T210
Test name
Test status
Simulation time 37287512989 ps
CPU time 45.26 seconds
Started Jul 29 05:07:20 PM PDT 24
Finished Jul 29 05:08:06 PM PDT 24
Peak memory 225308 kb
Host smart-4e0d4d23-99a0-4065-9804-d6b867b176d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282861363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.2282861363
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.179200195
Short name T254
Test name
Test status
Simulation time 4263165156 ps
CPU time 14.66 seconds
Started Jul 29 05:07:22 PM PDT 24
Finished Jul 29 05:07:37 PM PDT 24
Peak memory 225336 kb
Host smart-dd1a9eef-dcb7-4459-9544-3035157a13dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179200195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swap
.179200195
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.3913979075
Short name T209
Test name
Test status
Simulation time 3176713605 ps
CPU time 4.42 seconds
Started Jul 29 05:07:20 PM PDT 24
Finished Jul 29 05:07:25 PM PDT 24
Peak memory 225224 kb
Host smart-851c7d35-5b3b-4c6b-b394-9fa3ea711efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913979075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.3913979075
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.3039960528
Short name T958
Test name
Test status
Simulation time 2558405240 ps
CPU time 14.04 seconds
Started Jul 29 05:07:23 PM PDT 24
Finished Jul 29 05:07:37 PM PDT 24
Peak memory 219572 kb
Host smart-7cc06b53-6d82-4bae-acdf-bfb5b9e9b2fa
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3039960528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.3039960528
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.3235250347
Short name T573
Test name
Test status
Simulation time 5623931755 ps
CPU time 38.92 seconds
Started Jul 29 05:07:20 PM PDT 24
Finished Jul 29 05:07:59 PM PDT 24
Peak memory 250000 kb
Host smart-d98709dd-b3f2-4370-ac9d-7a4777ed0c3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235250347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.3235250347
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.1496889041
Short name T714
Test name
Test status
Simulation time 5007950770 ps
CPU time 12.05 seconds
Started Jul 29 05:07:22 PM PDT 24
Finished Jul 29 05:07:34 PM PDT 24
Peak memory 217132 kb
Host smart-4760646b-d912-4045-86f0-e67a5a8572f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496889041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.1496889041
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.4100600343
Short name T491
Test name
Test status
Simulation time 2403638490 ps
CPU time 7.46 seconds
Started Jul 29 05:07:21 PM PDT 24
Finished Jul 29 05:07:29 PM PDT 24
Peak memory 217056 kb
Host smart-1b95a93e-4376-47f1-8fce-01b6c169eaac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100600343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.4100600343
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.3018468052
Short name T590
Test name
Test status
Simulation time 77606328 ps
CPU time 0.85 seconds
Started Jul 29 05:07:23 PM PDT 24
Finished Jul 29 05:07:24 PM PDT 24
Peak memory 206656 kb
Host smart-9eff0ce5-ccb1-4877-9db2-0ea53a0fbb04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018468052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.3018468052
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.1458670693
Short name T964
Test name
Test status
Simulation time 66512399 ps
CPU time 0.9 seconds
Started Jul 29 05:07:29 PM PDT 24
Finished Jul 29 05:07:30 PM PDT 24
Peak memory 207588 kb
Host smart-ffcce9b2-741c-4b3d-8f6a-676417d14eb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458670693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.1458670693
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.1271577022
Short name T207
Test name
Test status
Simulation time 1780818323 ps
CPU time 5.36 seconds
Started Jul 29 05:07:21 PM PDT 24
Finished Jul 29 05:07:26 PM PDT 24
Peak memory 225264 kb
Host smart-c0c1815e-0871-4c01-9420-c5e5c621056b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271577022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.1271577022
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.419136907
Short name T365
Test name
Test status
Simulation time 20069735 ps
CPU time 0.73 seconds
Started Jul 29 05:07:31 PM PDT 24
Finished Jul 29 05:07:32 PM PDT 24
Peak memory 205292 kb
Host smart-c059a7dd-dd73-4f77-b8ec-c05a7bbbe42c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419136907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.419136907
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.295842777
Short name T248
Test name
Test status
Simulation time 59857959 ps
CPU time 2.31 seconds
Started Jul 29 05:07:30 PM PDT 24
Finished Jul 29 05:07:32 PM PDT 24
Peak memory 233512 kb
Host smart-2bbb1cd2-826a-4bb1-bfeb-f11f6a9219db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295842777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.295842777
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.2795423791
Short name T744
Test name
Test status
Simulation time 13577870 ps
CPU time 0.76 seconds
Started Jul 29 05:07:29 PM PDT 24
Finished Jul 29 05:07:29 PM PDT 24
Peak memory 207360 kb
Host smart-3a5da62f-ca9e-4e66-a1eb-2b75e28a647b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795423791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.2795423791
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.2948836796
Short name T708
Test name
Test status
Simulation time 729428658 ps
CPU time 13.89 seconds
Started Jul 29 05:07:30 PM PDT 24
Finished Jul 29 05:07:44 PM PDT 24
Peak memory 236472 kb
Host smart-06ab46d2-4707-4461-afb4-c491380c5214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948836796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.2948836796
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.1848343861
Short name T853
Test name
Test status
Simulation time 11607065750 ps
CPU time 129.84 seconds
Started Jul 29 05:07:29 PM PDT 24
Finished Jul 29 05:09:39 PM PDT 24
Peak memory 249952 kb
Host smart-3f67f91b-29d2-4189-bf44-349e5939bf0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848343861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.1848343861
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.3864311873
Short name T220
Test name
Test status
Simulation time 4324291854 ps
CPU time 19.28 seconds
Started Jul 29 05:07:29 PM PDT 24
Finished Jul 29 05:07:49 PM PDT 24
Peak memory 241676 kb
Host smart-b359f14a-a55c-435d-b1b7-3341eb43fb87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864311873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.3864311873
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.4052518720
Short name T151
Test name
Test status
Simulation time 413862727 ps
CPU time 3.68 seconds
Started Jul 29 05:07:29 PM PDT 24
Finished Jul 29 05:07:33 PM PDT 24
Peak memory 225200 kb
Host smart-e0bb5e44-93d1-4bef-adae-a41ba03aa12f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052518720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.4052518720
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.2355886836
Short name T719
Test name
Test status
Simulation time 58132991 ps
CPU time 0.74 seconds
Started Jul 29 05:07:30 PM PDT 24
Finished Jul 29 05:07:31 PM PDT 24
Peak memory 216468 kb
Host smart-3dfbb05f-3679-41d1-aab8-6e17ba123bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355886836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmd
s.2355886836
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_intercept.2244344248
Short name T488
Test name
Test status
Simulation time 2920933592 ps
CPU time 10.7 seconds
Started Jul 29 05:07:31 PM PDT 24
Finished Jul 29 05:07:42 PM PDT 24
Peak memory 225304 kb
Host smart-6afbf6d5-6bc3-453c-a90b-247eb2aedae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244344248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.2244344248
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.2009167103
Short name T26
Test name
Test status
Simulation time 1584229585 ps
CPU time 5.72 seconds
Started Jul 29 05:07:30 PM PDT 24
Finished Jul 29 05:07:36 PM PDT 24
Peak memory 233528 kb
Host smart-c0eb2594-be22-4ac9-8abc-ce0ab5e18dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009167103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.2009167103
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.428128868
Short name T861
Test name
Test status
Simulation time 288247603 ps
CPU time 2.98 seconds
Started Jul 29 05:07:29 PM PDT 24
Finished Jul 29 05:07:33 PM PDT 24
Peak memory 233444 kb
Host smart-5bf330ba-973e-44fc-bd5a-fdb9c90e8575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428128868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swap
.428128868
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.1333907501
Short name T651
Test name
Test status
Simulation time 6530982026 ps
CPU time 9.11 seconds
Started Jul 29 05:07:31 PM PDT 24
Finished Jul 29 05:07:40 PM PDT 24
Peak memory 233504 kb
Host smart-6eb5767a-7236-4c1c-a602-3fb5bf10051a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333907501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.1333907501
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.757032523
Short name T676
Test name
Test status
Simulation time 419277684 ps
CPU time 3.39 seconds
Started Jul 29 05:07:31 PM PDT 24
Finished Jul 29 05:07:35 PM PDT 24
Peak memory 220860 kb
Host smart-cc14262c-c6d5-4b94-8650-89bffa42ee30
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=757032523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dire
ct.757032523
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.1616934727
Short name T161
Test name
Test status
Simulation time 50046531 ps
CPU time 0.96 seconds
Started Jul 29 05:07:30 PM PDT 24
Finished Jul 29 05:07:31 PM PDT 24
Peak memory 206100 kb
Host smart-e7d3c259-6457-4dee-aa39-004393cc50b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616934727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.1616934727
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.3984426004
Short name T820
Test name
Test status
Simulation time 5721432862 ps
CPU time 26.63 seconds
Started Jul 29 05:07:30 PM PDT 24
Finished Jul 29 05:07:56 PM PDT 24
Peak memory 217112 kb
Host smart-ba9900bb-9670-4585-b7c0-38979b094ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984426004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.3984426004
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.1544854024
Short name T749
Test name
Test status
Simulation time 1409921176 ps
CPU time 4.52 seconds
Started Jul 29 05:07:30 PM PDT 24
Finished Jul 29 05:07:34 PM PDT 24
Peak memory 216860 kb
Host smart-76849890-a5e1-4e2c-bc10-2894cbfa76f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544854024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.1544854024
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.2802966106
Short name T578
Test name
Test status
Simulation time 567981295 ps
CPU time 6.43 seconds
Started Jul 29 05:07:28 PM PDT 24
Finished Jul 29 05:07:35 PM PDT 24
Peak memory 216956 kb
Host smart-f9c52bb8-5103-4dc2-8095-c62e14a126f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802966106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.2802966106
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.2421038330
Short name T925
Test name
Test status
Simulation time 48516088 ps
CPU time 0.86 seconds
Started Jul 29 05:07:29 PM PDT 24
Finished Jul 29 05:07:30 PM PDT 24
Peak memory 206608 kb
Host smart-b50aee8b-8cd4-4698-8228-a4d651b55a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421038330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.2421038330
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.3203103096
Short name T586
Test name
Test status
Simulation time 1110611398 ps
CPU time 3.12 seconds
Started Jul 29 05:07:31 PM PDT 24
Finished Jul 29 05:07:34 PM PDT 24
Peak memory 225416 kb
Host smart-bcf00227-e07f-4cf3-bb7c-f58b0528c30d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203103096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.3203103096
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.3316673309
Short name T454
Test name
Test status
Simulation time 16890962 ps
CPU time 0.66 seconds
Started Jul 29 05:07:36 PM PDT 24
Finished Jul 29 05:07:37 PM PDT 24
Peak memory 205864 kb
Host smart-8d436bae-571d-4351-9365-73f5c2cdb23d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316673309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
3316673309
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.56420631
Short name T14
Test name
Test status
Simulation time 1274694009 ps
CPU time 9.57 seconds
Started Jul 29 05:07:36 PM PDT 24
Finished Jul 29 05:07:45 PM PDT 24
Peak memory 225232 kb
Host smart-0d47ea3a-f0a3-400b-bc8c-42e7b38c1df2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56420631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.56420631
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.2407083675
Short name T639
Test name
Test status
Simulation time 39274265 ps
CPU time 0.81 seconds
Started Jul 29 05:07:29 PM PDT 24
Finished Jul 29 05:07:30 PM PDT 24
Peak memory 206968 kb
Host smart-ad22d537-c48e-48a1-8ef3-ca616a6a025f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407083675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.2407083675
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.3907278672
Short name T663
Test name
Test status
Simulation time 3782744610 ps
CPU time 52.55 seconds
Started Jul 29 05:07:36 PM PDT 24
Finished Jul 29 05:08:29 PM PDT 24
Peak memory 250084 kb
Host smart-c27a1524-c6fb-40ba-9bec-434676dc4663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907278672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.3907278672
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.3380573472
Short name T238
Test name
Test status
Simulation time 27950364695 ps
CPU time 312.92 seconds
Started Jul 29 05:07:37 PM PDT 24
Finished Jul 29 05:12:50 PM PDT 24
Peak memory 255944 kb
Host smart-04bee85c-8840-46af-97e7-bdcad2c29fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380573472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.3380573472
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.3376368142
Short name T560
Test name
Test status
Simulation time 26698598020 ps
CPU time 108.69 seconds
Started Jul 29 05:08:07 PM PDT 24
Finished Jul 29 05:09:56 PM PDT 24
Peak memory 258080 kb
Host smart-94f21308-290d-4a6c-9e79-f5c151702682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376368142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.3376368142
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.887053730
Short name T298
Test name
Test status
Simulation time 702470218 ps
CPU time 7.6 seconds
Started Jul 29 05:07:36 PM PDT 24
Finished Jul 29 05:07:44 PM PDT 24
Peak memory 225296 kb
Host smart-536f1c52-b26a-4480-831b-37c56281d49b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887053730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.887053730
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.2184779340
Short name T46
Test name
Test status
Simulation time 60031599934 ps
CPU time 107.54 seconds
Started Jul 29 05:07:38 PM PDT 24
Finished Jul 29 05:09:26 PM PDT 24
Peak memory 241712 kb
Host smart-3f630490-d2bc-42be-bece-25b0209b64a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184779340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmd
s.2184779340
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_intercept.798539854
Short name T226
Test name
Test status
Simulation time 1143998371 ps
CPU time 6.29 seconds
Started Jul 29 05:07:38 PM PDT 24
Finished Jul 29 05:07:45 PM PDT 24
Peak memory 233464 kb
Host smart-d6b23093-fe72-40f4-88fd-be1e6197e5ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798539854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.798539854
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.4277800952
Short name T887
Test name
Test status
Simulation time 745827222 ps
CPU time 6.8 seconds
Started Jul 29 05:07:38 PM PDT 24
Finished Jul 29 05:07:45 PM PDT 24
Peak memory 233464 kb
Host smart-f4af807d-6b88-4473-8b59-2fe1726e315e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277800952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.4277800952
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.3798257264
Short name T736
Test name
Test status
Simulation time 379389405 ps
CPU time 4.33 seconds
Started Jul 29 05:07:38 PM PDT 24
Finished Jul 29 05:07:43 PM PDT 24
Peak memory 233480 kb
Host smart-af10ee9e-9b31-452a-b7e6-889668c8a059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798257264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.3798257264
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.4119964904
Short name T501
Test name
Test status
Simulation time 1559673905 ps
CPU time 5.34 seconds
Started Jul 29 05:07:34 PM PDT 24
Finished Jul 29 05:07:40 PM PDT 24
Peak memory 233360 kb
Host smart-3222422f-6390-46cb-b373-b81f2bb53c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119964904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.4119964904
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.1150814400
Short name T403
Test name
Test status
Simulation time 6805214434 ps
CPU time 17.56 seconds
Started Jul 29 05:07:34 PM PDT 24
Finished Jul 29 05:07:52 PM PDT 24
Peak memory 220780 kb
Host smart-715d73e1-0466-40a1-9101-944b4a25ed0e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1150814400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.1150814400
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.2648221826
Short name T581
Test name
Test status
Simulation time 53555521 ps
CPU time 1.1 seconds
Started Jul 29 05:07:36 PM PDT 24
Finished Jul 29 05:07:37 PM PDT 24
Peak memory 207452 kb
Host smart-a84ce4c1-f2d6-43dc-8aa3-a079b8c86030
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648221826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.2648221826
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.773630385
Short name T1013
Test name
Test status
Simulation time 814791596 ps
CPU time 3.81 seconds
Started Jul 29 05:07:49 PM PDT 24
Finished Jul 29 05:07:53 PM PDT 24
Peak memory 217128 kb
Host smart-655a7866-b92a-4926-bdc5-f4d9cec9e52d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773630385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.773630385
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.214967428
Short name T449
Test name
Test status
Simulation time 37644304252 ps
CPU time 13.41 seconds
Started Jul 29 05:07:35 PM PDT 24
Finished Jul 29 05:07:48 PM PDT 24
Peak memory 218064 kb
Host smart-e6137e7e-b03d-4d5f-9ba0-dfd474d5c5ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214967428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.214967428
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.3929061200
Short name T607
Test name
Test status
Simulation time 46710088 ps
CPU time 1.42 seconds
Started Jul 29 05:07:36 PM PDT 24
Finished Jul 29 05:07:38 PM PDT 24
Peak memory 208996 kb
Host smart-6160c52f-280b-4c29-a389-6cb1947f1fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929061200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.3929061200
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.1515915974
Short name T436
Test name
Test status
Simulation time 58976067 ps
CPU time 0.9 seconds
Started Jul 29 05:07:31 PM PDT 24
Finished Jul 29 05:07:32 PM PDT 24
Peak memory 206600 kb
Host smart-15d13b73-2bb0-440a-aa9a-cf7bea36ffeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515915974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.1515915974
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.2207479238
Short name T893
Test name
Test status
Simulation time 484756434 ps
CPU time 5.08 seconds
Started Jul 29 05:07:37 PM PDT 24
Finished Jul 29 05:07:42 PM PDT 24
Peak memory 233432 kb
Host smart-f8cdd2fb-564d-4d91-be3b-e490c048a640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207479238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.2207479238
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.341369163
Short name T532
Test name
Test status
Simulation time 18975473 ps
CPU time 0.72 seconds
Started Jul 29 05:07:40 PM PDT 24
Finished Jul 29 05:07:41 PM PDT 24
Peak memory 205772 kb
Host smart-f2e0a37f-8042-4d0f-8c97-2621dcd64ccc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341369163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.341369163
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.3859315908
Short name T944
Test name
Test status
Simulation time 2240821795 ps
CPU time 12.39 seconds
Started Jul 29 05:07:38 PM PDT 24
Finished Jul 29 05:07:50 PM PDT 24
Peak memory 233512 kb
Host smart-957c1c19-d624-46a4-959b-5990d9bf3859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859315908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.3859315908
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.3796145092
Short name T512
Test name
Test status
Simulation time 109777825 ps
CPU time 0.79 seconds
Started Jul 29 05:07:35 PM PDT 24
Finished Jul 29 05:07:36 PM PDT 24
Peak memory 206968 kb
Host smart-2bd75297-23e4-4bf0-8c9d-e92cab773a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796145092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.3796145092
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.2254601912
Short name T929
Test name
Test status
Simulation time 65348036734 ps
CPU time 112.44 seconds
Started Jul 29 05:08:07 PM PDT 24
Finished Jul 29 05:10:00 PM PDT 24
Peak memory 236376 kb
Host smart-b3d53375-2649-4f16-a201-3f3914638c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254601912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.2254601912
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.500907987
Short name T291
Test name
Test status
Simulation time 55642863705 ps
CPU time 176.36 seconds
Started Jul 29 05:07:54 PM PDT 24
Finished Jul 29 05:10:50 PM PDT 24
Peak memory 274268 kb
Host smart-f0b6a1c0-27c6-4725-ae94-1dc92001c16d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500907987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.500907987
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.125160366
Short name T252
Test name
Test status
Simulation time 58727170502 ps
CPU time 152.46 seconds
Started Jul 29 05:08:07 PM PDT 24
Finished Jul 29 05:10:40 PM PDT 24
Peak memory 250920 kb
Host smart-6f94b773-edcb-4d15-bd5c-ea9d0366f73c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125160366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idle
.125160366
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.2308802268
Short name T773
Test name
Test status
Simulation time 4409840955 ps
CPU time 7.3 seconds
Started Jul 29 05:08:07 PM PDT 24
Finished Jul 29 05:08:15 PM PDT 24
Peak memory 236564 kb
Host smart-51dd4aff-ae5d-4e55-9051-ed8c2ff0a197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308802268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.2308802268
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.2804914207
Short name T278
Test name
Test status
Simulation time 21264876940 ps
CPU time 150.39 seconds
Started Jul 29 05:07:53 PM PDT 24
Finished Jul 29 05:10:23 PM PDT 24
Peak memory 263192 kb
Host smart-9eee4ffc-b288-4991-96d2-80071d34ad63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804914207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmd
s.2804914207
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/48.spi_device_intercept.296611087
Short name T776
Test name
Test status
Simulation time 761715358 ps
CPU time 3.63 seconds
Started Jul 29 05:08:07 PM PDT 24
Finished Jul 29 05:08:11 PM PDT 24
Peak memory 233416 kb
Host smart-ead46030-ec88-43fe-8a6c-574130006e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296611087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.296611087
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.1978425486
Short name T360
Test name
Test status
Simulation time 5062399491 ps
CPU time 24.19 seconds
Started Jul 29 05:07:37 PM PDT 24
Finished Jul 29 05:08:01 PM PDT 24
Peak memory 241332 kb
Host smart-e3dbaba2-37db-4b78-876f-b6634cc60f04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978425486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.1978425486
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.1226852053
Short name T704
Test name
Test status
Simulation time 2166486288 ps
CPU time 3.62 seconds
Started Jul 29 05:07:37 PM PDT 24
Finished Jul 29 05:07:41 PM PDT 24
Peak memory 225288 kb
Host smart-4ea8a327-7c44-4ca8-89f8-890fbbf623c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226852053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.1226852053
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.1308199178
Short name T236
Test name
Test status
Simulation time 780393923 ps
CPU time 3.22 seconds
Started Jul 29 05:07:36 PM PDT 24
Finished Jul 29 05:07:39 PM PDT 24
Peak memory 233480 kb
Host smart-60b6294a-e42b-4cf4-9125-62bfbc46f083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308199178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.1308199178
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.2648988679
Short name T148
Test name
Test status
Simulation time 1186085077 ps
CPU time 10.72 seconds
Started Jul 29 05:07:46 PM PDT 24
Finished Jul 29 05:07:56 PM PDT 24
Peak memory 223576 kb
Host smart-c2a242d1-f154-4075-b715-7b82d3c13325
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2648988679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.2648988679
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.2599277251
Short name T926
Test name
Test status
Simulation time 10404125738 ps
CPU time 187.74 seconds
Started Jul 29 05:07:46 PM PDT 24
Finished Jul 29 05:10:54 PM PDT 24
Peak memory 282704 kb
Host smart-136847af-a42d-4c63-be22-b857d1b8d65a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599277251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.2599277251
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.143043689
Short name T803
Test name
Test status
Simulation time 2207423622 ps
CPU time 11.11 seconds
Started Jul 29 05:07:34 PM PDT 24
Finished Jul 29 05:07:45 PM PDT 24
Peak memory 217112 kb
Host smart-46154ba9-83ed-4836-8686-f54645a03603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143043689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.143043689
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.3662925672
Short name T466
Test name
Test status
Simulation time 3481065914 ps
CPU time 6.8 seconds
Started Jul 29 05:07:34 PM PDT 24
Finished Jul 29 05:07:41 PM PDT 24
Peak memory 217032 kb
Host smart-9e5d9bf4-c5d2-42b7-9e1e-c593b815a7ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662925672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.3662925672
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.3319713304
Short name T684
Test name
Test status
Simulation time 487582225 ps
CPU time 3.26 seconds
Started Jul 29 05:07:35 PM PDT 24
Finished Jul 29 05:07:38 PM PDT 24
Peak memory 217000 kb
Host smart-ff1505fe-898f-4351-a7a2-2ba833205bae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319713304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.3319713304
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.3095270036
Short name T661
Test name
Test status
Simulation time 50085847 ps
CPU time 0.72 seconds
Started Jul 29 05:08:07 PM PDT 24
Finished Jul 29 05:08:08 PM PDT 24
Peak memory 206504 kb
Host smart-5de96100-010d-474b-b566-a1d3d180b98f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095270036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.3095270036
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.4090801539
Short name T420
Test name
Test status
Simulation time 362904831 ps
CPU time 2.84 seconds
Started Jul 29 05:07:36 PM PDT 24
Finished Jul 29 05:07:39 PM PDT 24
Peak memory 225228 kb
Host smart-bc82721d-47c5-4324-81eb-e479efb37590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090801539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.4090801539
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.3367259925
Short name T845
Test name
Test status
Simulation time 120267084 ps
CPU time 0.7 seconds
Started Jul 29 05:07:55 PM PDT 24
Finished Jul 29 05:07:56 PM PDT 24
Peak memory 205876 kb
Host smart-684d9e1a-a04f-4f34-b12b-ac00a7487af2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367259925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
3367259925
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.61966907
Short name T928
Test name
Test status
Simulation time 462124703 ps
CPU time 2.5 seconds
Started Jul 29 05:07:46 PM PDT 24
Finished Jul 29 05:07:48 PM PDT 24
Peak memory 225072 kb
Host smart-57dd0045-fe9a-40f0-9ba1-13f9e91ce551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61966907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.61966907
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.3526088817
Short name T336
Test name
Test status
Simulation time 35901869 ps
CPU time 0.83 seconds
Started Jul 29 05:07:44 PM PDT 24
Finished Jul 29 05:07:45 PM PDT 24
Peak memory 206984 kb
Host smart-2fc1f37d-7ad4-4cbb-ab5e-e4dbee06b007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526088817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.3526088817
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.2737147159
Short name T201
Test name
Test status
Simulation time 10836965795 ps
CPU time 85.17 seconds
Started Jul 29 05:07:56 PM PDT 24
Finished Jul 29 05:09:21 PM PDT 24
Peak memory 241076 kb
Host smart-95bd15a7-96f2-4618-9849-cf5f760ba1a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737147159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.2737147159
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.4144460133
Short name T33
Test name
Test status
Simulation time 14287458187 ps
CPU time 128.07 seconds
Started Jul 29 05:07:55 PM PDT 24
Finished Jul 29 05:10:03 PM PDT 24
Peak memory 258052 kb
Host smart-504964ce-a1a6-4baa-87e5-b4b18ade56ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144460133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.4144460133
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.2389443046
Short name T184
Test name
Test status
Simulation time 18245639471 ps
CPU time 152.86 seconds
Started Jul 29 05:07:56 PM PDT 24
Finished Jul 29 05:10:29 PM PDT 24
Peak memory 250596 kb
Host smart-da1fd280-e444-4854-9066-0b59e6f58d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389443046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.2389443046
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.4141330836
Short name T862
Test name
Test status
Simulation time 515579864 ps
CPU time 9.43 seconds
Started Jul 29 05:07:49 PM PDT 24
Finished Jul 29 05:07:59 PM PDT 24
Peak memory 249860 kb
Host smart-4ace2750-0e59-4ea4-b16c-258ac6467c1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141330836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.4141330836
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.2311076105
Short name T279
Test name
Test status
Simulation time 6155591823 ps
CPU time 108.08 seconds
Started Jul 29 05:07:47 PM PDT 24
Finished Jul 29 05:09:36 PM PDT 24
Peak memory 254672 kb
Host smart-a6118e8e-bde4-42a1-9607-54a445d119aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311076105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmd
s.2311076105
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/49.spi_device_intercept.2886899632
Short name T246
Test name
Test status
Simulation time 2201193512 ps
CPU time 25.59 seconds
Started Jul 29 05:07:46 PM PDT 24
Finished Jul 29 05:08:12 PM PDT 24
Peak memory 225392 kb
Host smart-54475e48-2e7c-4548-8e5f-dd3da86a3e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886899632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.2886899632
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.1229597472
Short name T939
Test name
Test status
Simulation time 362884251 ps
CPU time 9.71 seconds
Started Jul 29 05:07:46 PM PDT 24
Finished Jul 29 05:07:56 PM PDT 24
Peak memory 240820 kb
Host smart-fba6c2ae-ee95-40f2-99c3-0c68c5c33567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229597472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.1229597472
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.3517330380
Short name T707
Test name
Test status
Simulation time 9876553322 ps
CPU time 7.19 seconds
Started Jul 29 05:07:46 PM PDT 24
Finished Jul 29 05:07:53 PM PDT 24
Peak memory 233452 kb
Host smart-d7c5f55d-25de-4d62-b94f-5b61be824f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517330380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.3517330380
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.2525884432
Short name T966
Test name
Test status
Simulation time 1110051332 ps
CPU time 5.83 seconds
Started Jul 29 05:07:47 PM PDT 24
Finished Jul 29 05:07:53 PM PDT 24
Peak memory 239708 kb
Host smart-ffa160d6-3894-4d77-be94-63490d00e221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525884432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.2525884432
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.3933767641
Short name T792
Test name
Test status
Simulation time 7364773519 ps
CPU time 21.75 seconds
Started Jul 29 05:07:46 PM PDT 24
Finished Jul 29 05:08:08 PM PDT 24
Peak memory 222772 kb
Host smart-fbc72fa0-af80-4d48-80e7-0f1522bbc617
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3933767641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.3933767641
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.76611896
Short name T163
Test name
Test status
Simulation time 118089035 ps
CPU time 0.95 seconds
Started Jul 29 05:07:53 PM PDT 24
Finished Jul 29 05:07:54 PM PDT 24
Peak memory 207312 kb
Host smart-86055bc4-aea4-44cb-a1e0-05c9277d4fcc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76611896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stress
_all.76611896
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.1735907279
Short name T965
Test name
Test status
Simulation time 193519886 ps
CPU time 2.47 seconds
Started Jul 29 05:07:49 PM PDT 24
Finished Jul 29 05:07:51 PM PDT 24
Peak memory 218540 kb
Host smart-c2f02b65-30cc-45ad-a2fb-33aa214e17e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735907279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.1735907279
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.3867096656
Short name T31
Test name
Test status
Simulation time 3040193439 ps
CPU time 8.44 seconds
Started Jul 29 05:07:46 PM PDT 24
Finished Jul 29 05:07:54 PM PDT 24
Peak memory 217220 kb
Host smart-5b5dd34f-ee8f-432f-86ec-155eb326871f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867096656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.3867096656
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.4119880421
Short name T330
Test name
Test status
Simulation time 965791701 ps
CPU time 3.62 seconds
Started Jul 29 05:07:51 PM PDT 24
Finished Jul 29 05:07:55 PM PDT 24
Peak memory 216928 kb
Host smart-0ebfb295-9167-4209-bfd4-b7c8824f3f49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119880421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.4119880421
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.3118150142
Short name T636
Test name
Test status
Simulation time 29616900 ps
CPU time 0.85 seconds
Started Jul 29 05:07:46 PM PDT 24
Finished Jul 29 05:07:47 PM PDT 24
Peak memory 206556 kb
Host smart-1c24ae1b-a5b7-4d1c-a444-c1d7789bce05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118150142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.3118150142
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.3972187741
Short name T445
Test name
Test status
Simulation time 299328861 ps
CPU time 3.12 seconds
Started Jul 29 05:07:47 PM PDT 24
Finished Jul 29 05:07:50 PM PDT 24
Peak memory 233472 kb
Host smart-e9bcc6d4-7086-4f17-b6ec-e108e5b1ba8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972187741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.3972187741
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.2631650129
Short name T461
Test name
Test status
Simulation time 12325462 ps
CPU time 0.76 seconds
Started Jul 29 05:03:39 PM PDT 24
Finished Jul 29 05:03:40 PM PDT 24
Peak memory 205300 kb
Host smart-7a605ecd-7b2b-4825-972b-90a15fb98d0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631650129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.2
631650129
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.1173774919
Short name T725
Test name
Test status
Simulation time 148940280 ps
CPU time 4.26 seconds
Started Jul 29 05:03:36 PM PDT 24
Finished Jul 29 05:03:40 PM PDT 24
Peak memory 225180 kb
Host smart-b8b03dd8-054d-4e24-a034-7acccda31ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173774919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.1173774919
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.1653122835
Short name T542
Test name
Test status
Simulation time 30714962 ps
CPU time 0.81 seconds
Started Jul 29 05:03:35 PM PDT 24
Finished Jul 29 05:03:36 PM PDT 24
Peak memory 206288 kb
Host smart-033df7b2-ffa0-42e1-b085-0779750c837b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653122835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.1653122835
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.737236844
Short name T55
Test name
Test status
Simulation time 180278119405 ps
CPU time 312.18 seconds
Started Jul 29 05:03:47 PM PDT 24
Finished Jul 29 05:08:59 PM PDT 24
Peak memory 253680 kb
Host smart-38952a66-3077-4e0e-8228-7e9510fa0ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737236844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.737236844
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.3584241198
Short name T59
Test name
Test status
Simulation time 8809301226 ps
CPU time 120.15 seconds
Started Jul 29 05:03:47 PM PDT 24
Finished Jul 29 05:05:48 PM PDT 24
Peak memory 270896 kb
Host smart-cefdb1de-c1b2-4144-afb8-3788178a0c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584241198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.3584241198
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.2683929471
Short name T646
Test name
Test status
Simulation time 1461087382 ps
CPU time 10.95 seconds
Started Jul 29 05:03:47 PM PDT 24
Finished Jul 29 05:03:59 PM PDT 24
Peak memory 234836 kb
Host smart-af9415bc-ad71-4352-a5bb-354d96844141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683929471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.2683929471
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.1753361904
Short name T618
Test name
Test status
Simulation time 649249729 ps
CPU time 14.69 seconds
Started Jul 29 05:03:46 PM PDT 24
Finished Jul 29 05:04:01 PM PDT 24
Peak memory 249892 kb
Host smart-eeda5e9e-5e1d-4515-aa58-ea306d359a65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753361904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds
.1753361904
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/5.spi_device_intercept.1403773438
Short name T541
Test name
Test status
Simulation time 3451942295 ps
CPU time 11.38 seconds
Started Jul 29 05:03:38 PM PDT 24
Finished Jul 29 05:03:50 PM PDT 24
Peak memory 225292 kb
Host smart-e4fd5eb6-9e23-479f-b7d5-c092125fe884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403773438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.1403773438
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.1356116785
Short name T589
Test name
Test status
Simulation time 51160778488 ps
CPU time 25.98 seconds
Started Jul 29 05:03:37 PM PDT 24
Finished Jul 29 05:04:03 PM PDT 24
Peak memory 233364 kb
Host smart-9150c829-295d-4d20-b63e-43fe1ef45ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356116785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.1356116785
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.902378971
Short name T346
Test name
Test status
Simulation time 119673032 ps
CPU time 1.05 seconds
Started Jul 29 05:03:38 PM PDT 24
Finished Jul 29 05:03:39 PM PDT 24
Peak memory 217156 kb
Host smart-6c9b74d4-c3de-4b80-8d60-4593843e6202
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902378971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.spi_device_mem_parity.902378971
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.1911067636
Short name T783
Test name
Test status
Simulation time 41825241 ps
CPU time 2.35 seconds
Started Jul 29 05:03:39 PM PDT 24
Finished Jul 29 05:03:41 PM PDT 24
Peak memory 233480 kb
Host smart-205ea0ae-dcf3-4f0f-a852-24d89a9c5e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911067636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.1911067636
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.2477806919
Short name T977
Test name
Test status
Simulation time 345992374 ps
CPU time 6.52 seconds
Started Jul 29 05:03:38 PM PDT 24
Finished Jul 29 05:03:45 PM PDT 24
Peak memory 240412 kb
Host smart-bb8861d9-2769-4d47-a10d-6887447eca25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477806919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.2477806919
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.4169252136
Short name T800
Test name
Test status
Simulation time 1209503599 ps
CPU time 16.36 seconds
Started Jul 29 05:03:42 PM PDT 24
Finished Jul 29 05:03:59 PM PDT 24
Peak memory 220900 kb
Host smart-8cf4bbf0-cbcb-4dc3-9a43-64ce6481d438
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4169252136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.4169252136
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.4124028535
Short name T212
Test name
Test status
Simulation time 91454452852 ps
CPU time 158.83 seconds
Started Jul 29 05:03:37 PM PDT 24
Finished Jul 29 05:06:15 PM PDT 24
Peak memory 258124 kb
Host smart-8aeec189-3c8e-4f47-a245-0c843e648334
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124028535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.4124028535
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.650106779
Short name T671
Test name
Test status
Simulation time 592906588 ps
CPU time 7.41 seconds
Started Jul 29 05:03:37 PM PDT 24
Finished Jul 29 05:03:44 PM PDT 24
Peak memory 217228 kb
Host smart-bea91e8c-0a13-4439-a74c-d393231188f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650106779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.650106779
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.3392995188
Short name T798
Test name
Test status
Simulation time 80047114161 ps
CPU time 19.18 seconds
Started Jul 29 05:03:37 PM PDT 24
Finished Jul 29 05:03:56 PM PDT 24
Peak memory 217036 kb
Host smart-70a3f841-b2a3-415a-851b-719502ebd6e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392995188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.3392995188
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.955080602
Short name T452
Test name
Test status
Simulation time 161356782 ps
CPU time 1.56 seconds
Started Jul 29 05:03:37 PM PDT 24
Finished Jul 29 05:03:38 PM PDT 24
Peak memory 216992 kb
Host smart-2c797c3d-ec90-4e66-b78a-5ee920f13f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955080602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.955080602
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.2557503254
Short name T638
Test name
Test status
Simulation time 82173850 ps
CPU time 0.97 seconds
Started Jul 29 05:03:41 PM PDT 24
Finished Jul 29 05:03:42 PM PDT 24
Peak memory 207608 kb
Host smart-05cc5eec-863e-48ff-b31b-fe97be68a33b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557503254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.2557503254
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.3198764128
Short name T691
Test name
Test status
Simulation time 3299828454 ps
CPU time 8.84 seconds
Started Jul 29 05:03:38 PM PDT 24
Finished Jul 29 05:03:47 PM PDT 24
Peak memory 225236 kb
Host smart-e1191f04-f50e-48f2-9891-7d9002fb4df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198764128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.3198764128
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.205341414
Short name T828
Test name
Test status
Simulation time 34375968 ps
CPU time 0.73 seconds
Started Jul 29 05:03:44 PM PDT 24
Finished Jul 29 05:03:45 PM PDT 24
Peak memory 205292 kb
Host smart-82c9107e-aa70-49d7-bca9-5ddf85009772
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205341414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.205341414
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.2934769981
Short name T642
Test name
Test status
Simulation time 208907730 ps
CPU time 2.96 seconds
Started Jul 29 05:03:43 PM PDT 24
Finished Jul 29 05:03:46 PM PDT 24
Peak memory 233464 kb
Host smart-bced1e0b-1b9c-4453-964f-900ec8f757d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934769981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.2934769981
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.3964025115
Short name T341
Test name
Test status
Simulation time 32323021 ps
CPU time 0.77 seconds
Started Jul 29 05:03:43 PM PDT 24
Finished Jul 29 05:03:44 PM PDT 24
Peak memory 206276 kb
Host smart-242f0614-9e2d-4cca-b15d-3c6df79963e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964025115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.3964025115
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.3113185890
Short name T215
Test name
Test status
Simulation time 20321670115 ps
CPU time 139.25 seconds
Started Jul 29 05:03:42 PM PDT 24
Finished Jul 29 05:06:02 PM PDT 24
Peak memory 250112 kb
Host smart-feb308ee-a19e-44e4-bc8e-79868261e356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113185890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.3113185890
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.1047830708
Short name T916
Test name
Test status
Simulation time 27042578029 ps
CPU time 120.97 seconds
Started Jul 29 05:03:44 PM PDT 24
Finished Jul 29 05:05:45 PM PDT 24
Peak memory 252484 kb
Host smart-a55ff1a4-daeb-42f4-877f-1b571cc14336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047830708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.1047830708
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.4236424012
Short name T415
Test name
Test status
Simulation time 1649811360 ps
CPU time 32.17 seconds
Started Jul 29 05:03:45 PM PDT 24
Finished Jul 29 05:04:17 PM PDT 24
Peak memory 249892 kb
Host smart-818662ab-7ae1-4c38-8861-95d083f8b537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236424012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.4236424012
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.4196027418
Short name T50
Test name
Test status
Simulation time 434418372 ps
CPU time 6.68 seconds
Started Jul 29 05:03:53 PM PDT 24
Finished Jul 29 05:04:00 PM PDT 24
Peak memory 233508 kb
Host smart-00ecc734-fbcb-41a1-8aa4-1c7071074574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196027418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.4196027418
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_intercept.1534238856
Short name T513
Test name
Test status
Simulation time 339070674 ps
CPU time 4.26 seconds
Started Jul 29 05:03:43 PM PDT 24
Finished Jul 29 05:03:48 PM PDT 24
Peak memory 225280 kb
Host smart-99e0d1ce-7c6a-4ace-b9f4-6a656fd5c1dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534238856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.1534238856
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.494408198
Short name T80
Test name
Test status
Simulation time 3513155301 ps
CPU time 16.76 seconds
Started Jul 29 05:03:46 PM PDT 24
Finished Jul 29 05:04:03 PM PDT 24
Peak memory 233580 kb
Host smart-cef7c351-d43b-40d9-8d88-2a6c8a2a7d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494408198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.494408198
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.3692766211
Short name T685
Test name
Test status
Simulation time 18604428 ps
CPU time 1.06 seconds
Started Jul 29 05:03:46 PM PDT 24
Finished Jul 29 05:03:47 PM PDT 24
Peak memory 217196 kb
Host smart-532c9cef-700c-4ea9-aa75-69516920d4ec
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692766211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.spi_device_mem_parity.3692766211
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.2138997571
Short name T502
Test name
Test status
Simulation time 845252752 ps
CPU time 5.16 seconds
Started Jul 29 05:03:43 PM PDT 24
Finished Jul 29 05:03:48 PM PDT 24
Peak memory 241520 kb
Host smart-6ac47860-db95-4247-880e-3213751d86d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138997571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.2138997571
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.3205448266
Short name T424
Test name
Test status
Simulation time 3581355765 ps
CPU time 4.75 seconds
Started Jul 29 05:03:43 PM PDT 24
Finished Jul 29 05:03:47 PM PDT 24
Peak memory 225244 kb
Host smart-76ecaf8e-cf99-4f4f-9db0-e98c409bcb11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205448266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.3205448266
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.810649205
Short name T379
Test name
Test status
Simulation time 205783702 ps
CPU time 3.29 seconds
Started Jul 29 05:03:43 PM PDT 24
Finished Jul 29 05:03:46 PM PDT 24
Peak memory 219012 kb
Host smart-ad7da678-36f0-4a11-af30-cd147903d0d3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=810649205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_direc
t.810649205
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.796807359
Short name T182
Test name
Test status
Simulation time 7510598044 ps
CPU time 108.78 seconds
Started Jul 29 05:03:44 PM PDT 24
Finished Jul 29 05:05:33 PM PDT 24
Peak memory 257472 kb
Host smart-a0c37f10-bebb-4e22-8c95-f4963f94a2ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796807359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stress
_all.796807359
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.944572853
Short name T311
Test name
Test status
Simulation time 1695790269 ps
CPU time 21.4 seconds
Started Jul 29 05:03:43 PM PDT 24
Finished Jul 29 05:04:04 PM PDT 24
Peak memory 217260 kb
Host smart-85a043e0-3e6b-494c-8166-790e1855d131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944572853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.944572853
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.1966861640
Short name T447
Test name
Test status
Simulation time 38293837181 ps
CPU time 17.55 seconds
Started Jul 29 05:03:44 PM PDT 24
Finished Jul 29 05:04:01 PM PDT 24
Peak memory 217036 kb
Host smart-2d9a1fc5-074f-4362-a403-a19dadeb2533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966861640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.1966861640
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.3643453786
Short name T933
Test name
Test status
Simulation time 98427520 ps
CPU time 1.14 seconds
Started Jul 29 05:03:44 PM PDT 24
Finished Jul 29 05:03:46 PM PDT 24
Peak memory 208068 kb
Host smart-4aa27fe5-fe5d-4a57-bbfc-f46894c4c405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643453786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.3643453786
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.3352512570
Short name T464
Test name
Test status
Simulation time 103010237 ps
CPU time 0.88 seconds
Started Jul 29 05:03:44 PM PDT 24
Finished Jul 29 05:03:45 PM PDT 24
Peak memory 206620 kb
Host smart-d73340b2-217a-45b0-be08-01ae51faa9bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352512570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.3352512570
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.441073562
Short name T223
Test name
Test status
Simulation time 9525912839 ps
CPU time 9.54 seconds
Started Jul 29 05:03:42 PM PDT 24
Finished Jul 29 05:03:51 PM PDT 24
Peak memory 225200 kb
Host smart-75061379-3c13-4e8a-8a7c-163cd641b0af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441073562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.441073562
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.1102503711
Short name T838
Test name
Test status
Simulation time 28126014 ps
CPU time 0.75 seconds
Started Jul 29 05:03:49 PM PDT 24
Finished Jul 29 05:03:50 PM PDT 24
Peak memory 205316 kb
Host smart-a0dcf2e2-d3cb-4a8d-b902-001eab37cbac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102503711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.1
102503711
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.734820979
Short name T859
Test name
Test status
Simulation time 2270274511 ps
CPU time 4.42 seconds
Started Jul 29 05:03:56 PM PDT 24
Finished Jul 29 05:04:00 PM PDT 24
Peak memory 225316 kb
Host smart-01e63e92-7b47-4bbd-aad9-bff63adf2cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734820979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.734820979
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.3065255162
Short name T355
Test name
Test status
Simulation time 15707320 ps
CPU time 0.78 seconds
Started Jul 29 05:03:43 PM PDT 24
Finished Jul 29 05:03:44 PM PDT 24
Peak memory 206028 kb
Host smart-2c0039e6-3b34-4abd-a8ca-db2fcf2f65b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065255162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.3065255162
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.695819407
Short name T284
Test name
Test status
Simulation time 15428433842 ps
CPU time 161.04 seconds
Started Jul 29 05:03:56 PM PDT 24
Finished Jul 29 05:06:37 PM PDT 24
Peak memory 256484 kb
Host smart-c39471c3-1168-4bc7-bf7f-0df8cafcaf89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695819407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.695819407
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.3772452381
Short name T213
Test name
Test status
Simulation time 75399722329 ps
CPU time 595.89 seconds
Started Jul 29 05:03:49 PM PDT 24
Finished Jul 29 05:13:45 PM PDT 24
Peak memory 271968 kb
Host smart-991fe5bf-a3b7-4087-8799-e3846bdabe94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772452381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.3772452381
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.645467451
Short name T1009
Test name
Test status
Simulation time 36332367622 ps
CPU time 86.48 seconds
Started Jul 29 05:03:50 PM PDT 24
Finished Jul 29 05:05:16 PM PDT 24
Peak memory 236348 kb
Host smart-d6a9a880-ebe5-4721-941c-4c591dac0e98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645467451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle.
645467451
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.3258714811
Short name T554
Test name
Test status
Simulation time 170337945 ps
CPU time 4.48 seconds
Started Jul 29 05:03:55 PM PDT 24
Finished Jul 29 05:04:00 PM PDT 24
Peak memory 241036 kb
Host smart-da4c2c9d-8c92-4a4d-9b7e-1f2dce3ea191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258714811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.3258714811
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.2173597325
Short name T881
Test name
Test status
Simulation time 23522774276 ps
CPU time 107.08 seconds
Started Jul 29 05:03:52 PM PDT 24
Finished Jul 29 05:05:39 PM PDT 24
Peak memory 273428 kb
Host smart-5032cc56-cc73-4a11-8643-35114b158454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173597325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds
.2173597325
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_intercept.3293608207
Short name T204
Test name
Test status
Simulation time 10762998055 ps
CPU time 18.26 seconds
Started Jul 29 05:03:50 PM PDT 24
Finished Jul 29 05:04:09 PM PDT 24
Peak memory 233476 kb
Host smart-6a10b6de-4d2a-4cdb-b322-39d3166aebe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293608207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.3293608207
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.3011240216
Short name T801
Test name
Test status
Simulation time 2862600030 ps
CPU time 27.63 seconds
Started Jul 29 05:03:50 PM PDT 24
Finished Jul 29 05:04:17 PM PDT 24
Peak memory 233444 kb
Host smart-c1b3a2f1-8742-4545-a81d-c1bba1d1abe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011240216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.3011240216
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.2444233130
Short name T368
Test name
Test status
Simulation time 30229619 ps
CPU time 1.02 seconds
Started Jul 29 05:03:43 PM PDT 24
Finished Jul 29 05:03:44 PM PDT 24
Peak memory 218408 kb
Host smart-280d4c53-994a-4119-ba33-bed1c1197f03
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444233130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.spi_device_mem_parity.2444233130
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.1450285480
Short name T255
Test name
Test status
Simulation time 101533127 ps
CPU time 3.02 seconds
Started Jul 29 05:03:51 PM PDT 24
Finished Jul 29 05:03:54 PM PDT 24
Peak memory 233344 kb
Host smart-def38cb6-bff4-4c9c-9aa3-7b8a46709607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450285480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.1450285480
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.1836490033
Short name T266
Test name
Test status
Simulation time 398420722 ps
CPU time 2.86 seconds
Started Jul 29 05:03:54 PM PDT 24
Finished Jul 29 05:03:57 PM PDT 24
Peak memory 233456 kb
Host smart-62f2998c-0d4b-4c29-af58-1239cfa627f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836490033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.1836490033
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.3340914503
Short name T1019
Test name
Test status
Simulation time 756718216 ps
CPU time 9.51 seconds
Started Jul 29 05:03:55 PM PDT 24
Finished Jul 29 05:04:05 PM PDT 24
Peak memory 221136 kb
Host smart-b46f2d46-47b1-46eb-9af8-5c1bc3ae93b7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3340914503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.3340914503
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.2582062235
Short name T159
Test name
Test status
Simulation time 139956178524 ps
CPU time 123.99 seconds
Started Jul 29 05:03:51 PM PDT 24
Finished Jul 29 05:05:55 PM PDT 24
Peak memory 263772 kb
Host smart-b6cc22b2-94a0-4713-9bcf-ed3b0be42763
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582062235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.2582062235
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.1215873413
Short name T489
Test name
Test status
Simulation time 3662722926 ps
CPU time 25.58 seconds
Started Jul 29 05:03:44 PM PDT 24
Finished Jul 29 05:04:10 PM PDT 24
Peak memory 217000 kb
Host smart-7ecf852f-70c6-4a7d-9fdc-8b8dd02f0afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215873413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.1215873413
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.3174028160
Short name T917
Test name
Test status
Simulation time 7710545773 ps
CPU time 21.91 seconds
Started Jul 29 05:03:43 PM PDT 24
Finished Jul 29 05:04:05 PM PDT 24
Peak memory 217100 kb
Host smart-16bddb6f-0f65-43e1-acf7-c84e3e12af43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174028160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.3174028160
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.3398372194
Short name T430
Test name
Test status
Simulation time 256257580 ps
CPU time 1.38 seconds
Started Jul 29 05:03:50 PM PDT 24
Finished Jul 29 05:03:51 PM PDT 24
Peak memory 216932 kb
Host smart-23edfa03-b675-4b92-98a4-18209386f8b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398372194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.3398372194
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.905626513
Short name T370
Test name
Test status
Simulation time 91184984 ps
CPU time 0.81 seconds
Started Jul 29 05:03:54 PM PDT 24
Finished Jul 29 05:03:55 PM PDT 24
Peak memory 206572 kb
Host smart-a9ecfa83-80e7-48cd-8286-348c8115a6a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905626513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.905626513
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.1680570146
Short name T867
Test name
Test status
Simulation time 6887942596 ps
CPU time 16.69 seconds
Started Jul 29 05:03:49 PM PDT 24
Finished Jul 29 05:04:06 PM PDT 24
Peak memory 233496 kb
Host smart-ba4c8c35-8d0b-4e95-be32-fdfceb294ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680570146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.1680570146
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.1106646216
Short name T615
Test name
Test status
Simulation time 44354872 ps
CPU time 0.69 seconds
Started Jul 29 05:03:52 PM PDT 24
Finished Jul 29 05:03:53 PM PDT 24
Peak memory 205852 kb
Host smart-81522dcd-c33b-4d0a-8564-d992730dc108
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106646216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.1
106646216
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.3691039942
Short name T240
Test name
Test status
Simulation time 2682439654 ps
CPU time 8.86 seconds
Started Jul 29 05:03:55 PM PDT 24
Finished Jul 29 05:04:04 PM PDT 24
Peak memory 233360 kb
Host smart-090849f1-9e88-4dea-bb24-35b59ffa05d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691039942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.3691039942
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.3875879112
Short name T667
Test name
Test status
Simulation time 69491346 ps
CPU time 0.75 seconds
Started Jul 29 05:03:52 PM PDT 24
Finished Jul 29 05:03:53 PM PDT 24
Peak memory 206432 kb
Host smart-fdd76bb9-ee8a-470f-aad6-bd744a2e8f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875879112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.3875879112
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.934566156
Short name T885
Test name
Test status
Simulation time 210944955304 ps
CPU time 336.27 seconds
Started Jul 29 05:03:57 PM PDT 24
Finished Jul 29 05:09:34 PM PDT 24
Peak memory 257996 kb
Host smart-32be312b-2925-42b1-91b5-95d79bdf8e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934566156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.934566156
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.3508952796
Short name T60
Test name
Test status
Simulation time 16851348853 ps
CPU time 202.79 seconds
Started Jul 29 05:03:55 PM PDT 24
Finished Jul 29 05:07:17 PM PDT 24
Peak memory 255808 kb
Host smart-7d461f96-aadd-44a6-bd99-2b998c473e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508952796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.3508952796
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.1774519971
Short name T44
Test name
Test status
Simulation time 60201116216 ps
CPU time 131.29 seconds
Started Jul 29 05:03:57 PM PDT 24
Finished Jul 29 05:06:09 PM PDT 24
Peak memory 250252 kb
Host smart-cc683222-928b-4f78-90af-154a546159ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774519971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.1774519971
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.3242535306
Short name T516
Test name
Test status
Simulation time 1059799600 ps
CPU time 14.65 seconds
Started Jul 29 05:03:56 PM PDT 24
Finished Jul 29 05:04:11 PM PDT 24
Peak memory 225260 kb
Host smart-ea018eed-3ab5-4576-b408-2fd03048cdf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242535306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.3242535306
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.1613907915
Short name T180
Test name
Test status
Simulation time 20851162300 ps
CPU time 143.58 seconds
Started Jul 29 05:03:56 PM PDT 24
Finished Jul 29 05:06:20 PM PDT 24
Peak memory 274072 kb
Host smart-454d32c3-1cd6-4924-b0fa-569df7b6bfc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613907915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds
.1613907915
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/8.spi_device_intercept.1180201681
Short name T483
Test name
Test status
Simulation time 3402300744 ps
CPU time 13.96 seconds
Started Jul 29 05:03:56 PM PDT 24
Finished Jul 29 05:04:10 PM PDT 24
Peak memory 233480 kb
Host smart-7782d262-778c-48f4-b012-2168cde39e98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180201681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.1180201681
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.394849544
Short name T956
Test name
Test status
Simulation time 217383309 ps
CPU time 2.31 seconds
Started Jul 29 05:03:53 PM PDT 24
Finished Jul 29 05:03:55 PM PDT 24
Peak memory 223736 kb
Host smart-c90320a0-a1e0-4421-88c1-9bef7104b994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394849544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.394849544
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.2343383937
Short name T585
Test name
Test status
Simulation time 22103308 ps
CPU time 1.11 seconds
Started Jul 29 05:03:50 PM PDT 24
Finished Jul 29 05:03:51 PM PDT 24
Peak memory 217168 kb
Host smart-4c983454-25df-43fe-9738-2bcdb2f5bba7
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343383937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.spi_device_mem_parity.2343383937
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.1508741187
Short name T487
Test name
Test status
Simulation time 7285186006 ps
CPU time 28.91 seconds
Started Jul 29 05:03:55 PM PDT 24
Finished Jul 29 05:04:24 PM PDT 24
Peak memory 233508 kb
Host smart-7a372bf9-7ee8-4083-a0bc-9b92e5dd80e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508741187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.1508741187
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.439189374
Short name T450
Test name
Test status
Simulation time 2579736216 ps
CPU time 8.65 seconds
Started Jul 29 05:03:53 PM PDT 24
Finished Jul 29 05:04:01 PM PDT 24
Peak memory 225516 kb
Host smart-4eaf1909-cddb-4f99-b2a9-7f76bb5ea755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439189374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.439189374
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.1411105326
Short name T47
Test name
Test status
Simulation time 173199349 ps
CPU time 4.46 seconds
Started Jul 29 05:03:57 PM PDT 24
Finished Jul 29 05:04:02 PM PDT 24
Peak memory 223200 kb
Host smart-87648b39-091e-4b4c-98a9-4975113a7af4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1411105326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.1411105326
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.799507748
Short name T162
Test name
Test status
Simulation time 42124802617 ps
CPU time 430.29 seconds
Started Jul 29 05:03:59 PM PDT 24
Finished Jul 29 05:11:09 PM PDT 24
Peak memory 273380 kb
Host smart-e6fb8eaf-c158-4599-a6e6-311fdc08800e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799507748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stress
_all.799507748
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.3575683498
Short name T949
Test name
Test status
Simulation time 5214540684 ps
CPU time 27.15 seconds
Started Jul 29 05:03:50 PM PDT 24
Finished Jul 29 05:04:17 PM PDT 24
Peak memory 217012 kb
Host smart-f72162ec-cb9c-4d9e-804c-f4e58594b792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575683498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.3575683498
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.1405303630
Short name T525
Test name
Test status
Simulation time 115126377 ps
CPU time 1.21 seconds
Started Jul 29 05:03:49 PM PDT 24
Finished Jul 29 05:03:51 PM PDT 24
Peak memory 208340 kb
Host smart-4b3da250-9b3a-4d75-85ca-2ad5088f6e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405303630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.1405303630
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.3711062001
Short name T322
Test name
Test status
Simulation time 10674260 ps
CPU time 0.7 seconds
Started Jul 29 05:03:59 PM PDT 24
Finished Jul 29 05:03:59 PM PDT 24
Peak memory 206048 kb
Host smart-43b3d809-da0f-40ab-8602-8f864d74b85a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711062001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.3711062001
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.3816724430
Short name T628
Test name
Test status
Simulation time 154086956 ps
CPU time 0.81 seconds
Started Jul 29 05:03:52 PM PDT 24
Finished Jul 29 05:03:53 PM PDT 24
Peak memory 206628 kb
Host smart-9f96ce36-fff9-46a5-9a88-c35ebd84f5f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816724430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.3816724430
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.2926776977
Short name T604
Test name
Test status
Simulation time 1899671006 ps
CPU time 10.14 seconds
Started Jul 29 05:03:57 PM PDT 24
Finished Jul 29 05:04:08 PM PDT 24
Peak memory 249396 kb
Host smart-496c0c59-44a7-4c1d-9c37-be1f453922c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926776977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.2926776977
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.1583779081
Short name T73
Test name
Test status
Simulation time 39745241 ps
CPU time 0.74 seconds
Started Jul 29 05:04:04 PM PDT 24
Finished Jul 29 05:04:05 PM PDT 24
Peak memory 206188 kb
Host smart-df2900f5-86c2-426c-a06f-3daf55473439
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583779081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.1
583779081
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.1744428377
Short name T462
Test name
Test status
Simulation time 671280733 ps
CPU time 2.03 seconds
Started Jul 29 05:04:03 PM PDT 24
Finished Jul 29 05:04:05 PM PDT 24
Peak memory 224712 kb
Host smart-5c04065c-c544-470c-8559-24602f1196af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744428377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.1744428377
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.4100572916
Short name T550
Test name
Test status
Simulation time 18539293 ps
CPU time 0.81 seconds
Started Jul 29 05:03:53 PM PDT 24
Finished Jul 29 05:03:54 PM PDT 24
Peak memory 207072 kb
Host smart-52a82145-b0d5-4dd5-ab42-9f2c3da4c786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100572916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.4100572916
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.3170606998
Short name T434
Test name
Test status
Simulation time 11218958213 ps
CPU time 27.35 seconds
Started Jul 29 05:04:00 PM PDT 24
Finished Jul 29 05:04:27 PM PDT 24
Peak memory 225264 kb
Host smart-39e163f8-9391-4523-bd16-0d939905aba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170606998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.3170606998
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.15510722
Short name T144
Test name
Test status
Simulation time 500590499265 ps
CPU time 352.46 seconds
Started Jul 29 05:04:01 PM PDT 24
Finished Jul 29 05:09:53 PM PDT 24
Peak memory 265640 kb
Host smart-0e44c799-1476-4337-90e7-a068a7e99882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15510722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.15510722
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.3142108724
Short name T836
Test name
Test status
Simulation time 146139033437 ps
CPU time 351.66 seconds
Started Jul 29 05:04:02 PM PDT 24
Finished Jul 29 05:09:54 PM PDT 24
Peak memory 265272 kb
Host smart-e9ac9d0b-d798-4447-a682-5a3ae0ef3eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142108724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.3142108724
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.1292504060
Short name T299
Test name
Test status
Simulation time 1016344861 ps
CPU time 8.09 seconds
Started Jul 29 05:04:03 PM PDT 24
Finished Jul 29 05:04:11 PM PDT 24
Peak memory 231800 kb
Host smart-bc0b9bfa-68a2-48d9-b57f-db5531fc108a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292504060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.1292504060
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.1533861419
Short name T286
Test name
Test status
Simulation time 36211831952 ps
CPU time 104.91 seconds
Started Jul 29 05:04:02 PM PDT 24
Finished Jul 29 05:05:47 PM PDT 24
Peak memory 254032 kb
Host smart-83a76077-638b-41f7-9948-b202145d0c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533861419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds
.1533861419
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_intercept.3991529418
Short name T385
Test name
Test status
Simulation time 195758373 ps
CPU time 2.85 seconds
Started Jul 29 05:04:03 PM PDT 24
Finished Jul 29 05:04:06 PM PDT 24
Peak memory 233444 kb
Host smart-17b177d4-7a80-473f-bf6f-9dc87ac9345e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991529418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.3991529418
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.2430688013
Short name T231
Test name
Test status
Simulation time 18283787402 ps
CPU time 168.31 seconds
Started Jul 29 05:03:59 PM PDT 24
Finished Jul 29 05:06:47 PM PDT 24
Peak memory 254564 kb
Host smart-1a92cd1b-3689-4489-bd51-e259bd3e6341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430688013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.2430688013
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.1080111065
Short name T824
Test name
Test status
Simulation time 57878687 ps
CPU time 1.04 seconds
Started Jul 29 05:03:54 PM PDT 24
Finished Jul 29 05:03:56 PM PDT 24
Peak memory 218336 kb
Host smart-f48f301f-3a2b-4bd6-972b-185a16acf5a4
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080111065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.spi_device_mem_parity.1080111065
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.2514627792
Short name T264
Test name
Test status
Simulation time 7101688103 ps
CPU time 22.44 seconds
Started Jul 29 05:04:04 PM PDT 24
Finished Jul 29 05:04:26 PM PDT 24
Peak memory 230372 kb
Host smart-02268792-cf82-4c4c-a06b-2516284490e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514627792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.2514627792
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.1696076336
Short name T267
Test name
Test status
Simulation time 6238222297 ps
CPU time 19.95 seconds
Started Jul 29 05:04:00 PM PDT 24
Finished Jul 29 05:04:20 PM PDT 24
Peak memory 233448 kb
Host smart-c46b9850-f869-45d1-bcfc-add6e2e27e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696076336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.1696076336
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.3528054366
Short name T995
Test name
Test status
Simulation time 3793432842 ps
CPU time 9.85 seconds
Started Jul 29 05:04:02 PM PDT 24
Finished Jul 29 05:04:12 PM PDT 24
Peak memory 219656 kb
Host smart-4663b625-30da-4764-b612-2944ca35d75a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3528054366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.3528054366
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.2814314798
Short name T632
Test name
Test status
Simulation time 195477895 ps
CPU time 1.19 seconds
Started Jul 29 05:04:01 PM PDT 24
Finished Jul 29 05:04:02 PM PDT 24
Peak memory 207696 kb
Host smart-57292c36-a76b-4fee-871c-1f2a8d81ffd5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814314798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.2814314798
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.3486476173
Short name T688
Test name
Test status
Simulation time 2543293347 ps
CPU time 22.03 seconds
Started Jul 29 05:03:59 PM PDT 24
Finished Jul 29 05:04:21 PM PDT 24
Peak memory 217052 kb
Host smart-882f2561-1849-43b2-8f2b-ed602029d4f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486476173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.3486476173
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.1349518094
Short name T32
Test name
Test status
Simulation time 6436555435 ps
CPU time 11.25 seconds
Started Jul 29 05:03:53 PM PDT 24
Finished Jul 29 05:04:04 PM PDT 24
Peak memory 217016 kb
Host smart-cf0b6f66-6529-4cee-a68f-bff3f4baf88e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349518094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.1349518094
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.144688596
Short name T565
Test name
Test status
Simulation time 60282117 ps
CPU time 0.87 seconds
Started Jul 29 05:03:56 PM PDT 24
Finished Jul 29 05:03:57 PM PDT 24
Peak memory 206564 kb
Host smart-b21794f8-ec29-42af-86c6-eec530870805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144688596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.144688596
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.3278990252
Short name T918
Test name
Test status
Simulation time 77942815 ps
CPU time 0.84 seconds
Started Jul 29 05:03:53 PM PDT 24
Finished Jul 29 05:03:54 PM PDT 24
Peak memory 206456 kb
Host smart-70589f50-3c40-473f-a7d5-dc365d3947aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278990252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.3278990252
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.1799426319
Short name T232
Test name
Test status
Simulation time 235243030 ps
CPU time 3.28 seconds
Started Jul 29 05:04:00 PM PDT 24
Finished Jul 29 05:04:03 PM PDT 24
Peak memory 233476 kb
Host smart-ae50d284-0cc6-4280-a589-8a59150f47d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799426319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.1799426319
Directory /workspace/9.spi_device_upload/latest
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