Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2288285	1			T1	35		T2	10244		T3	68
all_values[1]	2288285	1			T1	35		T2	10244		T3	68
all_values[2]	2288285	1			T1	35		T2	10244		T3	68
all_values[3]	2288285	1			T1	35		T2	10244		T3	68
all_values[4]	2288285	1			T1	35		T2	10244		T3	68
all_values[5]	2288285	1			T1	35		T2	10244		T3	68
all_values[6]	2288285	1			T1	35		T2	10244		T3	68
all_values[7]	2288285	1			T1	35		T2	10244		T3	68

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17743849

1

T1

280

T2

81952

T3

544

auto[1]

562431

1

T11

99

T74

190

T15

46

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18284462

1

T1

280

T2

81952

T3

544

auto[1]

21818

1

T5

1

T11

282

T28

159

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2213881	1			T1	35		T2	10244		T3	68
all_values[0]	auto[0]	auto[1]	9863	1			T5	1		T11	86		T28	91
all_values[0]	auto[1]	auto[0]	63856	1			T11	5		T74	15		T15	4
all_values[0]	auto[1]	auto[1]	685	1			T11	4		T74	8		T16	2
all_values[1]	auto[0]	auto[0]	2233833	1			T1	35		T2	10244		T3	68
all_values[1]	auto[0]	auto[1]	6512	1			T11	84		T28	45		T74	3
all_values[1]	auto[1]	auto[0]	47606	1			T11	10		T74	17		T15	3
all_values[1]	auto[1]	auto[1]	334	1			T11	1		T74	10		T15	2
all_values[2]	auto[0]	auto[0]	2210943	1			T1	35		T2	10244		T3	68
all_values[2]	auto[0]	auto[1]	2145	1			T11	40		T28	23		T74	9
all_values[2]	auto[1]	auto[0]	74970	1			T11	9		T74	16		T15	9
all_values[2]	auto[1]	auto[1]	227	1			T11	5		T74	6		T16	4
all_values[3]	auto[0]	auto[0]	2219294	1			T1	35		T2	10244		T3	68
all_values[3]	auto[0]	auto[1]	198	1			T11	9		T74	6		T15	3
all_values[3]	auto[1]	auto[0]	68564	1			T11	7		T74	13		T15	1
all_values[3]	auto[1]	auto[1]	229	1			T11	6		T74	12		T15	1
all_values[4]	auto[0]	auto[0]	2215589	1			T1	35		T2	10244		T3	68
all_values[4]	auto[0]	auto[1]	197	1			T11	5		T74	13		T15	2
all_values[4]	auto[1]	auto[0]	72265	1			T11	4		T74	12		T15	7
all_values[4]	auto[1]	auto[1]	234	1			T11	8		T74	7		T16	3
all_values[5]	auto[0]	auto[0]	2227512	1			T1	35		T2	10244		T3	68
all_values[5]	auto[0]	auto[1]	180	1			T11	4		T74	9		T16	1
all_values[5]	auto[1]	auto[0]	60384	1			T11	9		T74	15		T15	3
all_values[5]	auto[1]	auto[1]	209	1			T11	8		T74	8		T15	3
all_values[6]	auto[0]	auto[0]	2152632	1			T1	35		T2	10244		T3	68
all_values[6]	auto[0]	auto[1]	202	1			T11	6		T74	9		T15	4
all_values[6]	auto[1]	auto[0]	135241	1			T11	4		T74	13		T15	4
all_values[6]	auto[1]	auto[1]	210	1			T11	7		T74	14		T15	1
all_values[7]	auto[0]	auto[0]	2250649	1			T1	35		T2	10244		T3	68
all_values[7]	auto[0]	auto[1]	219	1			T11	4		T74	7		T15	1
all_values[7]	auto[1]	auto[0]	37243	1			T11	7		T74	22		T15	5
all_values[7]	auto[1]	auto[1]	174	1			T11	5		T74	2		T15	3