Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	35199	1			T1	2		T2	76		T3	6
auto[SpiFlashAddrCfg]	7496	1			T1	2		T2	50		T5	12
auto[SpiFlashAddr3b]	9245	1			T2	51		T3	4		T5	19
auto[SpiFlashAddr4b]	7384	1			T1	2		T2	43		T5	12

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33827

1

T1

6

T2

118

T3

10

auto[1]

25497

1

T2

102

T5

216

T11

202

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31422

1

T1

6

T2

110

T3

6

auto[1]

27902

1

T2

110

T3

4

T5

126

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	39770	1			T1	2		T2	98		T3	6
values[1]	1102	1			T2	6		T11	16		T12	2
values[2]	1428	1			T2	12		T5	6		T11	15
values[3]	1392	1			T2	6		T5	5		T11	16
values[4]	1448	1			T2	6		T5	1		T11	17
values[5]	1521	1			T2	13		T5	3		T11	15
values[6]	1468	1			T2	11		T5	2		T11	9
values[7]	1484	1			T2	3		T3	2		T5	2
values[8]	9711	1			T1	4		T2	65		T3	2

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29251

1

T1

6

T2

220

T3

10

auto[1]

30073

1

T5

264

T11

188

T27

200

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

56083

1

T1

6

T2

208

T3

10

write

3241

1

T2

12

T5

2

T11

19

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

18880

1

T1

2

T2

109

T3

6

valids[0x1]

40444

1

T1

4

T2

111

T3

4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1534	1			T2	13		T5	6		T11	19
internal_process_ops[0x5a]	1532	1			T2	8		T11	20		T12	4
internal_process_ops[0x05]	21488	1			T1	2		T2	6		T5	186
internal_process_ops[0x35]	1549	1			T2	9		T3	2		T5	7
internal_process_ops[0x15]	1582	1			T2	9		T5	2		T11	7
internal_process_ops[0x03]	1043	1			T2	5		T11	11		T27	3
internal_process_ops[0x0b]	1049	1			T2	10		T11	13		T12	2
internal_process_ops[0x3b]	1077	1			T2	7		T5	1		T11	7
internal_process_ops[0x6b]	1014	1			T2	6		T5	3		T11	9
internal_process_ops[0xbb]	979	1			T2	5		T5	1		T11	6
internal_process_ops[0xeb]	990	1			T1	2		T2	14		T11	6

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

57748

1

T1

6

T2

212

T3

10

auto[1]

1576

1

T2

8

T5

1

T11

12

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

57028

1

T1

6

T2

213

T3

10

auto[1]

2296

1

T2

7

T5

9

T11

13

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9417

1

T1

2

T2

48

T3

6

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6227

1

T2

26

T11

36

T48

6

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1997

1

T1

2

T2

26

T11

22

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1789

1

T2

21

T11

16

T48

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2489

1

T2

12

T3

4

T11

19

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2085

1

T2

32

T11

21

T12

8

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1960

1

T1

2

T2

27

T11

16

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1705

1

T2

16

T11

29

T12

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

101

1

T25

2

T44

1

T50

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

92

1

T2

1

T11

1

T45

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

86

1

T2

1

T50

4

T45

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

84

1

T44

2

T50

1

T52

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

134

1

T2

1

T42

2

T50

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

93

1

T2

1

T44

1

T50

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

95

1

T44

2

T50

1

T108

4

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

97

1

T2

1

T11

1

T12

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

121

1

T2

2

T41

2

T46

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

106

1

T11

1

T50

1

T45

3

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

87

1

T11

2

T43

1

T50

3

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

90

1

T2

5

T44

1

T50

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

103

1

T11

1

T43

3

T45

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

119

1

T43

2

T44

2

T50

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

91

1

T43

2

T44

1

T45

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

83

1

T11

1

T48

2

T49

6

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

11336

1

T5

28

T11

58

T27

62

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7432

1

T5

193

T11

39

T27

22

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1452

1

T5

3

T11

10

T27

19

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1453

1

T5

9

T11

14

T27

16

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1905

1

T5

11

T11

15

T27

20

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1915

1

T5

7

T11

22

T27

17

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1604

1

T5

4

T11

4

T27

15

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1317

1

T5

7

T11

14

T27

12

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

95

1

T57

3

T90

1

T17

4

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

103

1

T11

1

T28

2

T101

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

123

1

T11

1

T27

2

T90

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

103

1

T27

1

T28

3

T57

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

88

1

T11

1

T27

1

T90

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

83

1

T11

2

T27

3

T90

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

89

1

T11

2

T27

1

T17

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

126

1

T27

1

T28

4

T56

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

139

1

T5

1

T27

2

T28

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

98

1

T17

1

T184

5

T32

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

104

1

T27

2

T28

1

T18

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

106

1

T11

4

T27

1

T28

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

99

1

T28

1

T90

2

T17

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

93

1

T5

1

T11

1

T27

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

110

1

T28

2

T56

3

T17

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

100

1

T27

2

T28

1

T17

7

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3580	1			T2	34		T3	2		T9	2
auto[0]	values[0]	valids[0x1]	14876	1			T1	2		T2	64		T3	4
auto[0]	values[1]	valids[0x1]	556	1			T2	6		T11	11		T12	2
auto[0]	values[2]	valids[0x0]	483	1			T2	10		T11	4		T43	4
auto[0]	values[2]	valids[0x1]	268	1			T2	2		T11	7		T47	2
auto[0]	values[3]	valids[0x0]	486	1			T2	1		T11	7		T107	2
auto[0]	values[3]	valids[0x1]	289	1			T2	5		T25	4		T44	7
auto[0]	values[4]	valids[0x0]	530	1			T2	5		T11	2		T44	6
auto[0]	values[4]	valids[0x1]	286	1			T2	1		T11	4		T43	1
auto[0]	values[5]	valids[0x0]	569	1			T2	9		T11	7		T25	2
auto[0]	values[5]	valids[0x1]	300	1			T2	4		T11	2		T44	4
auto[0]	values[6]	valids[0x0]	555	1			T2	9		T11	5		T12	2
auto[0]	values[6]	valids[0x1]	328	1			T2	2		T11	2		T107	4
auto[0]	values[7]	valids[0x0]	562	1			T2	3		T3	2		T11	4
auto[0]	values[7]	valids[0x1]	264	1			T11	5		T25	4		T44	2
auto[0]	values[8]	valids[0x0]	3342	1			T1	2		T2	38		T3	2
auto[0]	values[8]	valids[0x1]	1977	1			T1	2		T2	27		T11	22
auto[1]	values[0]	valids[0x0]	3999	1			T5	25		T11	26		T27	49
auto[1]	values[0]	valids[0x1]	17315	1			T5	208		T11	94		T27	62
auto[1]	values[1]	valids[0x1]	546	1			T11	5		T27	11		T28	8
auto[1]	values[2]	valids[0x0]	391	1			T5	5		T27	2		T28	5
auto[1]	values[2]	valids[0x1]	286	1			T5	1		T11	4		T27	7
auto[1]	values[3]	valids[0x0]	384	1			T5	4		T11	3		T27	4
auto[1]	values[3]	valids[0x1]	233	1			T5	1		T11	6		T28	3
auto[1]	values[4]	valids[0x0]	369	1			T11	11		T27	5		T56	1
auto[1]	values[4]	valids[0x1]	263	1			T5	1		T27	2		T28	1
auto[1]	values[5]	valids[0x0]	370	1			T5	3		T11	4		T27	5
auto[1]	values[5]	valids[0x1]	282	1			T11	2		T27	1		T28	6
auto[1]	values[6]	valids[0x0]	334	1			T5	2		T27	5		T28	1
auto[1]	values[6]	valids[0x1]	251	1			T11	2		T28	4		T57	1
auto[1]	values[7]	valids[0x0]	352	1			T5	2		T27	4		T28	1
auto[1]	values[7]	valids[0x1]	306	1			T11	3		T27	2		T28	1
auto[1]	values[8]	valids[0x0]	2574	1			T5	11		T11	12		T27	24
auto[1]	values[8]	valids[0x1]	1818	1			T5	1		T11	16		T27	17