Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3445377

1

T1

257

T2

19451

T3

3959

auto[1]

31744

1

T2

26

T5

184

T11

70

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1114850

1

T1

1

T2

488

T3

1

auto[1]

2362271

1

T1

256

T2

18989

T3

3958

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	669710	1			T1	257		T2	32		T3	3959
auto[524288:1048575]	375483	1			T2	64		T5	625		T11	2162
auto[1048576:1572863]	363741	1			T2	7896		T5	9		T9	7
auto[1572864:2097151]	440460	1			T2	1593		T5	480		T11	2082
auto[2097152:2621439]	377083	1			T2	40		T5	644		T9	50
auto[2621440:3145727]	364859	1			T2	5155		T5	914		T11	522
auto[3145728:3670015]	430680	1			T2	1685		T5	2785		T9	1
auto[3670016:4194303]	455105	1			T2	3012		T5	64		T9	101

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2397992

1

T1

257

T2

19472

T3

3959

auto[1]

1079129

1

T2

5

T5

5

T9

189

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3056804

1

T1

257

T2

19162

T3

3959

auto[1]

420317

1

T2

315

T5

258

T11

2926

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	198588	1			T1	1		T2	22		T3	1
auto[0]	auto[0]	auto[0:524287]	auto[1]	407640	1			T1	256		T2	5		T3	3958
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	141187	1			T2	51		T5	8		T11	2
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	192264	1			T2	8		T5	541		T11	1902
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	113642	1			T2	70		T5	4		T9	7
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	215908	1			T2	7824		T5	1		T11	6379
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	144288	1			T2	74		T5	1		T11	3
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	240039	1			T2	1507		T5	188		T11	518
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	102835	1			T2	37		T5	1		T9	50
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	215228	1			T5	643		T11	521		T107	1
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	101965	1			T2	54		T5	2		T11	10
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	207477	1			T2	4819		T5	898		T11	512
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	156816	1			T2	41		T9	1		T11	8
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	207432	1			T2	1620		T5	2785		T11	3427
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	145238	1			T2	56		T5	6		T9	101
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	241760	1			T2	2948		T5	1		T11	2824
auto[0]	auto[1]	auto[0:524287]	auto[0]	1010	1			T2	5		T11	1		T14	6
auto[0]	auto[1]	auto[0:524287]	auto[1]	58081	1			T11	1063		T57	114		T90	256
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	592	1			T11	2		T27	5		T28	1
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	37187	1			T11	256		T44	769		T50	2785
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	667	1			T2	2		T11	3		T27	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	30107	1			T11	36		T91	257		T20	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	794	1			T2	5		T5	2		T27	2
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	51893	1			T5	256		T11	1561		T28	1713
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	934	1			T11	1		T14	2		T27	17
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	54631	1			T28	1		T17	718		T91	256
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	724	1			T2	21		T14	3		T27	8
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	51875	1			T2	258		T44	2961		T90	8
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	856	1			T2	16		T11	2		T27	10
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	60749	1			T27	3		T28	1		T57	512
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	900	1			T2	8		T11	1		T14	339
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	62070	1			T57	129		T90	1703		T101	256
auto[1]	auto[0]	auto[0:524287]	auto[0]	422	1			T11	3		T28	2		T42	2
auto[1]	auto[0]	auto[0:524287]	auto[1]	2756	1			T11	12		T28	22		T42	16
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	370	1			T2	5		T5	4		T27	7
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	3248	1			T5	72		T27	55		T28	6
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	497	1			T5	1		T11	2		T27	3
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2499	1			T5	3		T11	8		T28	4
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	392	1			T2	7		T5	1		T27	14
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	2380	1			T5	32		T27	1		T28	3
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	321	1			T2	3		T11	1		T27	11
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2378	1			T11	5		T27	3		T44	51
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	346	1			T2	3		T5	2		T27	5
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	1939	1			T5	12		T28	1		T44	10
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	418	1			T2	8		T11	1		T28	2
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	2812	1			T56	161		T90	106		T17	7
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	384	1			T5	1		T11	6		T28	2
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	3335	1			T5	56		T11	32		T28	10
auto[1]	auto[1]	auto[0:524287]	auto[0]	95	1			T101	1		T18	1		T21	2
auto[1]	auto[1]	auto[0:524287]	auto[1]	1118	1			T101	4		T18	1		T21	4
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	86	1			T44	1		T17	2		T21	3
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	549	1			T44	7		T17	57		T21	20
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	62	1			T91	1		T20	1		T217	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	359	1			T91	14		T20	6		T217	18
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	52	1			T17	2		T91	1		T244	2
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	622	1			T17	57		T91	22		T244	10
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	92	1			T27	4		T28	1		T21	3
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	664	1			T28	2		T21	77		T184	11
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	78	1			T108	6		T202	1		T227	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	455	1			T202	9		T227	15		T194	146
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	88	1			T28	1		T91	4		T21	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	1509	1			T28	1		T91	55		T21	3
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	111	1			T57	1		T45	3		T91	2
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	1307	1			T57	27		T91	3		T245	24

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1954995	1			T1	257		T2	19136		T3	3959
auto[0]	auto[0]	auto[1]	1077312	1			T5	4		T9	189		T13	213
auto[0]	auto[1]	auto[0]	411942	1			T2	315		T5	258		T11	2926
auto[0]	auto[1]	auto[1]	1128	1			T14	8		T44	1		T91	5
auto[1]	auto[0]	auto[0]	23938	1			T2	21		T5	183		T11	70
auto[1]	auto[0]	auto[1]	559	1			T2	5		T5	1		T27	6
auto[1]	auto[1]	auto[0]	7117	1			T27	3		T28	5		T57	27
auto[1]	auto[1]	auto[1]	130	1			T27	1		T57	1		T17	2