Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2288285	1			T1	35		T2	10244		T3	68
all_pins[1]	2288285	1			T1	35		T2	10244		T3	68
all_pins[2]	2288285	1			T1	35		T2	10244		T3	68
all_pins[3]	2288285	1			T1	35		T2	10244		T3	68
all_pins[4]	2288285	1			T1	35		T2	10244		T3	68
all_pins[5]	2288285	1			T1	35		T2	10244		T3	68
all_pins[6]	2288285	1			T1	35		T2	10244		T3	68
all_pins[7]	2288285	1			T1	35		T2	10244		T3	68

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	18168655	1			T1	280		T2	81952		T3	544
values[0x1]	137625	1			T11	44		T74	67		T15	10
transitions[0x0=>0x1]	136546	1			T11	33		T74	50		T15	9
transitions[0x1=>0x0]	136557	1			T11	33		T74	50		T15	9

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2287550	1			T1	35		T2	10244		T3	68
all_pins[0]	values[0x1]	735	1			T11	4		T74	8		T16	2
all_pins[0]	transitions[0x0=>0x1]	659	1			T11	4		T74	5		T16	2
all_pins[0]	transitions[0x1=>0x0]	273	1			T11	1		T74	7		T15	2
all_pins[1]	values[0x0]	2287936	1			T1	35		T2	10244		T3	68
all_pins[1]	values[0x1]	349	1			T11	1		T74	10		T15	2
all_pins[1]	transitions[0x0=>0x1]	277	1			T74	9		T15	2		T16	2
all_pins[1]	transitions[0x1=>0x0]	160	1			T11	4		T74	5		T16	4
all_pins[2]	values[0x0]	2288053	1			T1	35		T2	10244		T3	68
all_pins[2]	values[0x1]	232	1			T11	5		T74	6		T16	4
all_pins[2]	transitions[0x0=>0x1]	146	1			T11	3		T74	3		T16	1
all_pins[2]	transitions[0x1=>0x0]	143	1			T11	4		T74	9		T15	1
all_pins[3]	values[0x0]	2288056	1			T1	35		T2	10244		T3	68
all_pins[3]	values[0x1]	229	1			T11	6		T74	12		T15	1
all_pins[3]	transitions[0x0=>0x1]	167	1			T11	4		T74	9		T15	1
all_pins[3]	transitions[0x1=>0x0]	172	1			T11	6		T74	4		T16	1
all_pins[4]	values[0x0]	2288051	1			T1	35		T2	10244		T3	68
all_pins[4]	values[0x1]	234	1			T11	8		T74	7		T16	3
all_pins[4]	transitions[0x0=>0x1]	178	1			T11	5		T74	4		T16	1
all_pins[4]	transitions[0x1=>0x0]	802	1			T11	5		T74	5		T15	3
all_pins[5]	values[0x0]	2287427	1			T1	35		T2	10244		T3	68
all_pins[5]	values[0x1]	858	1			T11	8		T74	8		T15	3
all_pins[5]	transitions[0x0=>0x1]	224	1			T11	8		T74	4		T15	3
all_pins[5]	transitions[0x1=>0x0]	134180	1			T11	7		T74	10		T15	1
all_pins[6]	values[0x0]	2153471	1			T1	35		T2	10244		T3	68
all_pins[6]	values[0x1]	134814	1			T11	7		T74	14		T15	1
all_pins[6]	transitions[0x0=>0x1]	134771	1			T11	4		T74	14		T17	1
all_pins[6]	transitions[0x1=>0x0]	131	1			T11	2		T74	2		T15	2
all_pins[7]	values[0x0]	2288111	1			T1	35		T2	10244		T3	68
all_pins[7]	values[0x1]	174	1			T11	5		T74	2		T15	3
all_pins[7]	transitions[0x0=>0x1]	124	1			T11	5		T74	2		T15	3
all_pins[7]	transitions[0x1=>0x0]	696	1			T11	4		T74	8		T16	1