Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16732

1

T1

6

T2

118

T3

10

auto[1]

12519

1

T2

102

T11

106

T12

12

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3251	1			T2	40		T9	2		T11	20
values[1]	4097	1			T11	44		T44	131		T50	20
values[2]	3752	1			T2	40		T11	46		T130	4
values[3]	3151	1			T1	6		T2	20		T11	29
values[4]	3335	1			T2	80		T12	12		T14	8
values[5]	3704	1			T2	20		T11	20		T42	24
values[6]	4264	1			T2	20		T11	23		T44	20
values[7]	3697	1			T3	10		T11	20		T246	6

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3535	1			T2	20		T11	73		T42	24
values[1]	3612	1			T11	46		T130	4		T44	40
values[2]	3075	1			T2	40		T9	2		T41	14
values[3]	3665	1			T2	60		T3	10		T12	12
values[4]	3435	1			T2	20		T107	10		T44	55
values[5]	4183	1			T11	20		T43	40		T44	51
values[6]	3651	1			T2	60		T11	20		T49	16
values[7]	4095	1			T1	6		T2	20		T11	43

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	222	1			T2	11		T11	8		T44	10
auto[0]	values[0]	values[1]	239	1			T210	16		T148	4		T93	12
auto[0]	values[0]	values[2]	114	1			T9	2		T217	10		T247	12
auto[0]	values[0]	values[3]	138	1			T2	9		T222	8		T248	15
auto[0]	values[0]	values[4]	364	1			T44	28		T91	8		T21	11
auto[0]	values[0]	values[5]	179	1			T20	10		T32	5		T249	12
auto[0]	values[0]	values[6]	186	1			T202	9		T93	16		T94	23
auto[0]	values[0]	values[7]	390	1			T91	91		T217	10		T250	6
auto[0]	values[1]	values[0]	186	1			T11	14		T62	12		T20	9
auto[0]	values[1]	values[1]	174	1			T19	9		T228	6		T206	16
auto[0]	values[1]	values[2]	204	1			T208	9		T205	15		T93	15
auto[0]	values[1]	values[3]	290	1			T44	14		T251	12		T252	16
auto[0]	values[1]	values[4]	228	1			T21	26		T253	14		T84	14
auto[0]	values[1]	values[5]	446	1			T20	9		T207	37		T202	21
auto[0]	values[1]	values[6]	343	1			T11	6		T44	14		T195	14
auto[0]	values[1]	values[7]	469	1			T50	13		T91	10		T21	14
auto[0]	values[2]	values[0]	217	1			T91	20		T210	9		T208	9
auto[0]	values[2]	values[1]	288	1			T11	10		T130	4		T44	8
auto[0]	values[2]	values[2]	189	1			T91	14		T210	12		T206	18
auto[0]	values[2]	values[3]	215	1			T50	18		T207	13		T202	11
auto[0]	values[2]	values[4]	309	1			T50	25		T45	8		T212	11
auto[0]	values[2]	values[5]	217	1			T45	9		T21	15		T210	14
auto[0]	values[2]	values[6]	239	1			T2	14		T44	30		T254	31
auto[0]	values[2]	values[7]	470	1			T2	8		T11	16		T91	37
auto[0]	values[3]	values[0]	184	1			T11	11		T255	10		T212	9
auto[0]	values[3]	values[1]	341	1			T92	30		T237	43		T93	14
auto[0]	values[3]	values[2]	179	1			T41	14		T256	6		T93	16
auto[0]	values[3]	values[3]	224	1			T2	12		T25	18		T45	8
auto[0]	values[3]	values[4]	187	1			T44	9		T202	82		T210	14
auto[0]	values[3]	values[5]	189	1			T44	13		T209	6		T21	11
auto[0]	values[3]	values[6]	169	1			T84	11		T92	9		T257	15
auto[0]	values[3]	values[7]	340	1			T1	6		T44	10		T50	12
auto[0]	values[4]	values[0]	256	1			T45	23		T21	14		T212	17
auto[0]	values[4]	values[1]	110	1			T44	10		T235	12		T20	13
auto[0]	values[4]	values[2]	320	1			T47	16		T46	20		T50	51
auto[0]	values[4]	values[3]	373	1			T2	13		T14	8		T21	8
auto[0]	values[4]	values[4]	151	1			T2	8		T107	10		T92	9
auto[0]	values[4]	values[5]	334	1			T44	13		T258	12		T153	8
auto[0]	values[4]	values[6]	241	1			T2	20		T108	12		T92	15
auto[0]	values[4]	values[7]	178	1			T259	14		T210	13		T222	53
auto[0]	values[5]	values[0]	371	1			T42	24		T44	12		T21	6
auto[0]	values[5]	values[1]	125	1			T11	13		T50	4		T226	20
auto[0]	values[5]	values[2]	184	1			T2	11		T260	14		T206	12
auto[0]	values[5]	values[3]	328	1			T19	11		T178	2		T223	11
auto[0]	values[5]	values[4]	199	1			T50	40		T91	15		T21	12
auto[0]	values[5]	values[5]	365	1			T43	9		T196	6		T45	15
auto[0]	values[5]	values[6]	267	1			T108	15		T20	25		T217	26
auto[0]	values[5]	values[7]	193	1			T44	15		T45	21		T108	11
auto[0]	values[6]	values[0]	262	1			T50	10		T228	15		T212	14
auto[0]	values[6]	values[1]	371	1			T242	6		T207	16		T202	12
auto[0]	values[6]	values[2]	409	1			T2	12		T44	7		T19	20
auto[0]	values[6]	values[3]	270	1			T45	25		T212	11		T222	39
auto[0]	values[6]	values[4]	328	1			T45	11		T32	33		T84	13
auto[0]	values[6]	values[5]	213	1			T21	15		T84	26		T223	9
auto[0]	values[6]	values[6]	316	1			T50	13		T91	12		T206	10
auto[0]	values[6]	values[7]	114	1			T11	9		T50	11		T19	13
auto[0]	values[7]	values[0]	281	1			T45	13		T261	4		T84	17
auto[0]	values[7]	values[1]	495	1			T45	14		T59	8		T108	12
auto[0]	values[7]	values[2]	116	1			T230	14		T108	10		T262	6
auto[0]	values[7]	values[3]	269	1			T3	10		T246	6		T207	32
auto[0]	values[7]	values[4]	229	1			T91	8		T94	8		T263	16
auto[0]	values[7]	values[5]	385	1			T11	9		T43	14		T19	9
auto[0]	values[7]	values[6]	190	1			T212	14		T92	13		T170	12
auto[0]	values[7]	values[7]	360	1			T216	86		T91	13		T195	11
auto[1]	values[0]	values[0]	142	1			T2	9		T11	12		T44	10
auto[1]	values[0]	values[1]	135	1			T210	4		T93	8		T264	8
auto[1]	values[0]	values[2]	73	1			T217	11		T264	3		T265	48
auto[1]	values[0]	values[3]	79	1			T2	11		T222	12		T266	16
auto[1]	values[0]	values[4]	258	1			T44	7		T91	95		T21	9
auto[1]	values[0]	values[5]	292	1			T20	50		T32	15		T249	16
auto[1]	values[0]	values[6]	159	1			T267	12		T202	13		T93	6
auto[1]	values[0]	values[7]	281	1			T91	8		T217	43		T248	7
auto[1]	values[1]	values[0]	216	1			T11	10		T62	8		T20	11
auto[1]	values[1]	values[1]	206	1			T19	11		T228	14		T206	14
auto[1]	values[1]	values[2]	107	1			T51	20		T208	11		T205	19
auto[1]	values[1]	values[3]	200	1			T44	14		T143	5		T93	29
auto[1]	values[1]	values[4]	219	1			T21	27		T84	6		T170	22
auto[1]	values[1]	values[5]	353	1			T20	11		T207	21		T202	8
auto[1]	values[1]	values[6]	345	1			T11	14		T44	89		T195	6
auto[1]	values[1]	values[7]	111	1			T50	7		T91	10		T21	8
auto[1]	values[2]	values[0]	184	1			T91	67		T210	11		T208	11
auto[1]	values[2]	values[1]	186	1			T11	16		T44	12		T202	42
auto[1]	values[2]	values[2]	247	1			T91	24		T268	2		T269	18
auto[1]	values[2]	values[3]	278	1			T50	22		T207	7		T202	38
auto[1]	values[2]	values[4]	165	1			T50	21		T45	12		T212	9
auto[1]	values[2]	values[5]	247	1			T45	11		T21	5		T210	6
auto[1]	values[2]	values[6]	156	1			T2	6		T44	7		T249	18
auto[1]	values[2]	values[7]	145	1			T2	12		T11	4		T91	6
auto[1]	values[3]	values[0]	135	1			T11	18		T212	14		T200	9
auto[1]	values[3]	values[1]	234	1			T92	5		T237	7		T93	9
auto[1]	values[3]	values[2]	124	1			T93	6		T270	15		T271	8
auto[1]	values[3]	values[3]	117	1			T2	8		T272	4		T45	12
auto[1]	values[3]	values[4]	52	1			T44	11		T202	7		T210	6
auto[1]	values[3]	values[5]	140	1			T44	7		T21	17		T212	6
auto[1]	values[3]	values[6]	248	1			T84	9		T92	21		T257	5
auto[1]	values[3]	values[7]	288	1			T44	10		T50	8		T52	14
auto[1]	values[4]	values[0]	194	1			T45	17		T21	12		T212	9
auto[1]	values[4]	values[1]	75	1			T44	10		T20	7		T212	8
auto[1]	values[4]	values[2]	200	1			T50	9		T238	20		T45	6
auto[1]	values[4]	values[3]	362	1			T2	7		T12	12		T21	16
auto[1]	values[4]	values[4]	93	1			T2	12		T92	11		T249	12
auto[1]	values[4]	values[5]	196	1			T44	18		T153	12		T270	8
auto[1]	values[4]	values[6]	122	1			T2	20		T108	8		T92	5
auto[1]	values[4]	values[7]	130	1			T210	7		T222	6		T208	14
auto[1]	values[5]	values[0]	338	1			T44	8		T21	14		T217	5
auto[1]	values[5]	values[1]	149	1			T11	7		T50	36		T92	23
auto[1]	values[5]	values[2]	177	1			T2	9		T260	30		T206	9
auto[1]	values[5]	values[3]	156	1			T19	9		T223	12		T153	6
auto[1]	values[5]	values[4]	161	1			T50	6		T91	5		T21	15
auto[1]	values[5]	values[5]	255	1			T43	11		T45	5		T21	59
auto[1]	values[5]	values[6]	252	1			T108	5		T20	82		T217	13
auto[1]	values[5]	values[7]	184	1			T44	66		T45	19		T108	9
auto[1]	values[6]	values[0]	270	1			T50	69		T228	5		T212	6
auto[1]	values[6]	values[1]	273	1			T273	6		T207	7		T202	17
auto[1]	values[6]	values[2]	365	1			T2	8		T44	13		T19	8
auto[1]	values[6]	values[3]	246	1			T45	15		T212	12		T222	11
auto[1]	values[6]	values[4]	216	1			T45	9		T32	20		T84	7
auto[1]	values[6]	values[5]	184	1			T21	6		T84	14		T223	11
auto[1]	values[6]	values[6]	275	1			T50	31		T91	17		T206	10
auto[1]	values[6]	values[7]	152	1			T11	14		T50	11		T19	7
auto[1]	values[7]	values[0]	77	1			T45	7		T84	3		T154	7
auto[1]	values[7]	values[1]	211	1			T45	6		T108	8		T20	10
auto[1]	values[7]	values[2]	67	1			T108	10		T205	10		T93	7
auto[1]	values[7]	values[3]	120	1			T207	12		T153	3		T205	27
auto[1]	values[7]	values[4]	276	1			T91	13		T94	119		T274	10
auto[1]	values[7]	values[5]	188	1			T11	11		T43	6		T19	15
auto[1]	values[7]	values[6]	143	1			T49	16		T212	6		T92	7
auto[1]	values[7]	values[7]	290	1			T48	14		T91	7		T195	9