Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	451	1			T11	2		T44	9		T50	3
auto[ReadAddrCrossIntoMailbox]	249	1			T2	1		T11	2		T44	7
auto[ReadAddrCrossOutOfMailbox]	299	1			T2	3		T11	5		T44	8
auto[ReadAddrCrossAllMailbox]	226	1			T2	4		T11	3		T44	3
auto[ReadAddrOutsideMailbox]	3359	1			T1	2		T2	39		T11	31

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2256

1

T1

1

T2

26

T11

16

auto[1]

2328

1

T1

1

T2

21

T11

27

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	789	1			T2	5		T11	11		T47	2
read_ops[0x0b]	777	1			T2	10		T11	8		T12	2
read_ops[0x3b]	803	1			T2	7		T11	7		T25	2
read_ops[0x6b]	752	1			T2	6		T11	8		T107	2
read_ops[0xbb]	747	1			T2	5		T11	5		T41	2
read_ops[0xeb]	716	1			T1	2		T2	14		T11	4

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	46	1			T11	1		T44	3		T45	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	36	1			T44	2		T202	1		T206	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	22	1			T45	1		T21	2		T223	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	14	1			T44	2		T50	1		T210	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	21	1			T45	1		T203	1		T225	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	27	1			T11	1		T44	3		T91	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	20	1			T2	2		T32	1		T170	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	20	1			T19	1		T228	1		T212	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	302	1			T2	2		T11	2		T47	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	281	1			T2	1		T11	7		T47	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	33	1			T210	1		T32	2		T84	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	31	1			T44	1		T202	1		T84	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	19	1			T50	1		T260	1		T84	2
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	22	1			T44	2		T212	1		T210	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	31	1			T44	1		T50	2		T45	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	29	1			T11	1		T62	1		T207	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	35	1			T44	1		T45	1		T108	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	18	1			T11	1		T84	1		T93	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	288	1			T2	7		T11	1		T12	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	271	1			T2	3		T11	5		T12	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	38	1			T44	1		T108	2		T21	4
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	35	1			T50	2		T45	1		T217	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	23	1			T2	1		T44	1		T50	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	23	1			T11	1		T50	2		T45	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	32	1			T2	1		T11	1		T91	2
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	30	1			T91	3		T228	2		T84	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	19	1			T11	2		T275	1		T203	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	20	1			T2	1		T44	1		T275	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	265	1			T2	2		T11	3		T25	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	318	1			T2	2		T25	1		T47	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	46	1			T44	1		T45	1		T217	2
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	36	1			T44	1		T108	1		T21	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	20	1			T44	1		T50	2		T207	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	22	1			T45	1		T21	1		T84	2
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	27	1			T11	2		T44	1		T275	2
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	20	1			T45	1		T275	2		T210	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T275	1		T208	1		T93	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	14	1			T19	1		T91	1		T275	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	272	1			T2	3		T11	2		T107	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	277	1			T2	3		T11	4		T107	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	35	1			T11	1		T50	1		T20	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	32	1			T91	1		T228	1		T276	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	24	1			T50	1		T45	1		T230	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	18	1			T44	1		T50	1		T230	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	15	1			T44	1		T210	1		T92	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	19	1			T50	1		T45	1		T84	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T50	1		T275	2		T260	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	27	1			T45	2		T275	2		T207	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	272	1			T2	2		T41	1		T44	3
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	289	1			T2	3		T11	4		T41	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	44	1			T91	1		T20	1		T229	3
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	39	1			T19	1		T91	1		T229	3
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	22	1			T11	1		T62	1		T91	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	20	1			T45	1		T212	1		T210	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	21	1			T44	1		T20	1		T212	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	27	1			T2	2		T44	1		T210	2
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	5	1			T84	1		T92	1		T277	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	14	1			T2	1		T44	1		T210	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	225	1			T1	1		T2	6		T12	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	299	1			T1	1		T2	5		T11	3