Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3395	1			T11	43		T130	4		T44	35
values[1]	3134	1			T2	20		T11	44		T50	20
values[2]	3254	1			T2	40		T9	2		T12	12
values[3]	3683	1			T2	80		T11	46		T44	59
values[4]	4164	1			T11	20		T41	14		T49	16
values[5]	3446	1			T1	6		T11	20		T14	8
values[6]	4071	1			T2	60		T3	10		T25	18
values[7]	4104	1			T2	20		T11	29		T42	24

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3254	1			T1	6		T2	40		T11	20
values[1]	3358	1			T2	40		T3	10		T11	47
values[2]	3703	1			T11	55		T41	14		T272	4
values[3]	3695	1			T2	20		T11	40		T42	24
values[4]	3636	1			T2	40		T11	20		T50	127
values[5]	3959	1			T2	20		T11	20		T44	223
values[6]	3772	1			T9	2		T107	10		T46	20
values[7]	3874	1			T2	60		T43	40		T44	20

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28487

1

T1

6

T2

212

T3

10

auto[1]

764

1

T2

8

T11

4

T12

2

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	205	1			T92	24		T211	20		T154	20
auto[0]	values[0]	values[1]	403	1			T11	22		T130	4		T21	28
auto[0]	values[0]	values[2]	427	1			T273	6		T108	20		T210	38
auto[0]	values[0]	values[3]	551	1			T50	45		T19	27		T91	43
auto[0]	values[0]	values[4]	371	1			T11	20		T21	25		T170	58
auto[0]	values[0]	values[5]	469	1			T44	35		T45	18		T91	21
auto[0]	values[0]	values[6]	484	1			T21	23		T228	28		T92	54
auto[0]	values[0]	values[7]	391	1			T50	20		T235	12		T238	20
auto[0]	values[1]	values[0]	408	1			T212	20		T143	20		T93	21
auto[0]	values[1]	values[1]	509	1			T11	23		T254	31		T278	2
auto[0]	values[1]	values[2]	542	1			T50	20		T217	47		T212	20
auto[0]	values[1]	values[3]	434	1			T20	19		T268	2		T217	19
auto[0]	values[1]	values[4]	362	1			T253	14		T212	21		T207	20
auto[0]	values[1]	values[5]	302	1			T2	20		T11	20		T279	2
auto[0]	values[1]	values[6]	349	1			T45	19		T52	12		T32	20
auto[0]	values[1]	values[7]	156	1			T45	20		T91	19		T82	6
auto[0]	values[2]	values[0]	385	1			T19	24		T21	32		T217	38
auto[0]	values[2]	values[1]	287	1			T12	10		T92	28		T93	22
auto[0]	values[2]	values[2]	402	1			T272	4		T51	16		T45	19
auto[0]	values[2]	values[3]	351	1			T91	96		T20	35		T280	10
auto[0]	values[2]	values[4]	500	1			T2	19		T45	40		T198	20
auto[0]	values[2]	values[5]	453	1			T44	36		T50	39		T92	17
auto[0]	values[2]	values[6]	362	1			T9	2		T217	51		T212	20
auto[0]	values[2]	values[7]	407	1			T2	20		T108	18		T207	23
auto[0]	values[3]	values[0]	293	1			T2	40		T212	20		T210	20
auto[0]	values[3]	values[1]	347	1			T45	20		T210	19		T84	19
auto[0]	values[3]	values[2]	561	1			T11	25		T21	20		T32	25
auto[0]	values[3]	values[3]	438	1			T11	20		T44	30		T93	20
auto[0]	values[3]	values[4]	241	1			T2	18		T59	8		T91	55
auto[0]	values[3]	values[5]	661	1			T44	28		T21	20		T228	20
auto[0]	values[3]	values[6]	483	1			T21	19		T202	49		T84	40
auto[0]	values[3]	values[7]	567	1			T2	18		T20	20		T21	21
auto[0]	values[4]	values[0]	368	1			T50	19		T21	20		T202	29
auto[0]	values[4]	values[1]	364	1			T44	81		T209	6		T20	27
auto[0]	values[4]	values[2]	533	1			T41	14		T91	102		T20	70
auto[0]	values[4]	values[3]	504	1			T11	20		T45	19		T62	20
auto[0]	values[4]	values[4]	513	1			T50	79		T247	12		T207	44
auto[0]	values[4]	values[5]	556	1			T44	122		T226	20		T91	20
auto[0]	values[4]	values[6]	757	1			T49	10		T45	18		T222	66
auto[0]	values[4]	values[7]	449	1			T19	19		T210	16		T32	20
auto[0]	values[5]	values[0]	451	1			T1	6		T11	20		T47	16
auto[0]	values[5]	values[1]	236	1			T14	8		T48	12		T108	19
auto[0]	values[5]	values[2]	270	1			T261	4		T281	24		T252	16
auto[0]	values[5]	values[3]	557	1			T246	6		T44	19		T50	18
auto[0]	values[5]	values[4]	581	1			T50	26		T21	64		T210	19
auto[0]	values[5]	values[5]	458	1			T91	58		T20	132		T228	25
auto[0]	values[5]	values[6]	437	1			T108	17		T212	43		T282	6
auto[0]	values[5]	values[7]	354	1			T43	38		T202	28		T222	49
auto[0]	values[6]	values[0]	478	1			T25	18		T50	18		T19	17
auto[0]	values[6]	values[1]	375	1			T2	20		T3	10		T91	36
auto[0]	values[6]	values[2]	529	1			T269	18		T283	2		T208	18
auto[0]	values[6]	values[3]	497	1			T2	18		T44	39		T207	20
auto[0]	values[6]	values[4]	393	1			T50	21		T228	20		T210	20
auto[0]	values[6]	values[5]	405	1			T19	20		T92	20		T208	20
auto[0]	values[6]	values[6]	478	1			T107	10		T44	20		T45	20
auto[0]	values[6]	values[7]	815	1			T2	19		T50	43		T196	6
auto[0]	values[7]	values[0]	581	1			T44	20		T230	14		T91	32
auto[0]	values[7]	values[1]	733	1			T2	20		T44	20		T45	19
auto[0]	values[7]	values[2]	342	1			T11	28		T259	14		T91	20
auto[0]	values[7]	values[3]	251	1			T42	24		T237	47		T203	51
auto[0]	values[7]	values[4]	574	1			T45	20		T91	29		T92	147
auto[0]	values[7]	values[5]	583	1			T50	59		T202	111		T210	20
auto[0]	values[7]	values[6]	331	1			T46	20		T108	40		T202	20
auto[0]	values[7]	values[7]	633	1			T44	18		T178	2		T91	67
auto[1]	values[0]	values[0]	6	1			T92	2		T274	2		T284	2
auto[1]	values[0]	values[1]	15	1			T11	1		T257	1		T285	2
auto[1]	values[0]	values[2]	10	1			T210	2		T32	2		T200	1
auto[1]	values[0]	values[3]	7	1			T50	1		T19	1		T32	2
auto[1]	values[0]	values[4]	18	1			T21	2		T170	2		T153	3
auto[1]	values[0]	values[5]	14	1			T45	2		T222	1		T94	6
auto[1]	values[0]	values[6]	15	1			T21	1		T205	1		T58	3
auto[1]	values[0]	values[7]	9	1			T270	2		T243	3		T286	1
auto[1]	values[1]	values[0]	14	1			T143	1		T93	1		T58	1
auto[1]	values[1]	values[1]	16	1			T11	1		T212	1		T203	2
auto[1]	values[1]	values[2]	11	1			T84	1		T170	3		T154	2
auto[1]	values[1]	values[3]	19	1			T20	1		T217	2		T198	1
auto[1]	values[1]	values[4]	5	1			T143	1		T243	1		T218	1
auto[1]	values[1]	values[5]	2	1			T287	1		T288	1		-	-
auto[1]	values[1]	values[6]	3	1			T45	1		T52	2		-	-
auto[1]	values[1]	values[7]	2	1			T91	1		T289	1		-	-
auto[1]	values[2]	values[0]	11	1			T21	1		T217	1		T92	1
auto[1]	values[2]	values[1]	16	1			T12	2		T92	2		T93	1
auto[1]	values[2]	values[2]	16	1			T51	4		T45	1		T108	1
auto[1]	values[2]	values[3]	12	1			T91	3		T20	3		T202	2
auto[1]	values[2]	values[4]	18	1			T2	1		T274	6		T156	2
auto[1]	values[2]	values[5]	8	1			T44	1		T50	1		T92	3
auto[1]	values[2]	values[6]	8	1			T217	2		T212	1		T170	2
auto[1]	values[2]	values[7]	18	1			T108	2		T249	1		T93	3
auto[1]	values[3]	values[0]	9	1			T205	5		T200	1		T264	1
auto[1]	values[3]	values[1]	8	1			T210	1		T84	1		T94	1
auto[1]	values[3]	values[2]	16	1			T11	1		T21	1		T32	2
auto[1]	values[3]	values[3]	5	1			T44	1		T270	3		T289	1
auto[1]	values[3]	values[4]	10	1			T2	2		T91	2		T285	1
auto[1]	values[3]	values[5]	12	1			T198	1		T232	3		T290	1
auto[1]	values[3]	values[6]	17	1			T21	3		T93	1		T200	5
auto[1]	values[3]	values[7]	15	1			T2	2		T260	2		T291	2
auto[1]	values[4]	values[0]	16	1			T50	1		T85	4		T175	5
auto[1]	values[4]	values[1]	9	1			T20	2		T248	1		T292	2
auto[1]	values[4]	values[2]	10	1			T91	1		T20	1		T84	1
auto[1]	values[4]	values[3]	19	1			T45	1		T210	4		T203	4
auto[1]	values[4]	values[4]	15	1			T243	3		T285	4		T293	2
auto[1]	values[4]	values[5]	10	1			T44	1		T243	1		T218	1
auto[1]	values[4]	values[6]	27	1			T49	6		T45	2		T222	2
auto[1]	values[4]	values[7]	14	1			T19	1		T210	4		T294	3
auto[1]	values[5]	values[0]	6	1			T202	1		T289	3		T286	1
auto[1]	values[5]	values[1]	10	1			T48	2		T108	1		T84	1
auto[1]	values[5]	values[2]	14	1			T295	2		T154	1		T248	2
auto[1]	values[5]	values[3]	21	1			T44	1		T50	2		T207	2
auto[1]	values[5]	values[4]	17	1			T21	2		T210	1		T170	2
auto[1]	values[5]	values[5]	8	1			T20	1		T228	1		T94	1
auto[1]	values[5]	values[6]	12	1			T108	3		T296	2		T297	1
auto[1]	values[5]	values[7]	14	1			T43	2		T202	1		T222	1
auto[1]	values[6]	values[0]	16	1			T50	2		T19	3		T195	4
auto[1]	values[6]	values[1]	10	1			T91	2		T206	2		T153	3
auto[1]	values[6]	values[2]	14	1			T208	2		T237	3		T170	2
auto[1]	values[6]	values[3]	22	1			T2	2		T44	1		T143	2
auto[1]	values[6]	values[4]	6	1			T50	1		T92	1		T292	3
auto[1]	values[6]	values[5]	9	1			T153	2		T211	2		T264	1
auto[1]	values[6]	values[6]	7	1			T264	1		T293	2		T292	2
auto[1]	values[6]	values[7]	17	1			T2	1		T50	1		T205	3
auto[1]	values[7]	values[0]	7	1			T94	1		T214	1		T264	1
auto[1]	values[7]	values[1]	20	1			T45	1		T212	1		T222	4
auto[1]	values[7]	values[2]	6	1			T11	1		T212	1		T270	1
auto[1]	values[7]	values[3]	7	1			T237	3		T270	1		T214	2
auto[1]	values[7]	values[4]	12	1			T92	2		T298	3		T299	2
auto[1]	values[7]	values[5]	9	1			T50	1		T203	1		T173	2
auto[1]	values[7]	values[6]	2	1			T271	1		T297	1		-	-
auto[1]	values[7]	values[7]	13	1			T44	2		T202	3		T32	3