Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	874	1			T11	24		T74	34		T15	11
all_values[1]	874	1			T11	24		T74	34		T15	11
all_values[2]	874	1			T11	24		T74	34		T15	11
all_values[3]	874	1			T11	24		T74	34		T15	11
all_values[4]	874	1			T11	24		T74	34		T15	11
all_values[5]	874	1			T11	24		T74	34		T15	11
all_values[6]	874	1			T11	24		T74	34		T15	11
all_values[7]	874	1			T11	24		T74	34		T15	11

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3639

1

T11

108

T74

114

T15

52

auto[1]

3353

1

T11

84

T74

158

T15

36

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2744

1

T11

75

T74

108

T15

48

auto[1]

4248

1

T11

117

T74

164

T15

40

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3959

1

T11

108

T74

155

T15

59

auto[1]

3033

1

T11

84

T74

117

T15

29

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	167	1			T11	6		T74	6		T15	4
all_values[0]	auto[0]	auto[0]	auto[1]	98	1			T11	2		T74	2		T16	3
all_values[0]	auto[0]	auto[1]	auto[0]	159	1			T11	5		T74	10		T15	3
all_values[0]	auto[0]	auto[1]	auto[1]	79	1			T11	2		T74	6		T15	1
all_values[0]	auto[1]	auto[0]	auto[1]	199	1			T11	7		T74	4		T15	3
all_values[0]	auto[1]	auto[1]	auto[1]	172	1			T11	2		T74	6		T16	5
all_values[1]	auto[0]	auto[0]	auto[0]	164	1			T11	7		T74	7		T15	1
all_values[1]	auto[0]	auto[0]	auto[1]	89	1			T74	3		T15	1		T16	3
all_values[1]	auto[0]	auto[1]	auto[0]	140	1			T11	6		T74	9		T15	1
all_values[1]	auto[0]	auto[1]	auto[1]	95	1			T11	1		T74	4		T15	3
all_values[1]	auto[1]	auto[0]	auto[1]	227	1			T11	9		T74	2		T15	5
all_values[1]	auto[1]	auto[1]	auto[1]	159	1			T11	1		T74	9		T16	1
all_values[2]	auto[0]	auto[0]	auto[0]	182	1			T11	6		T74	5		T15	4
all_values[2]	auto[0]	auto[0]	auto[1]	77	1			T11	2		T74	1		T16	1
all_values[2]	auto[0]	auto[1]	auto[0]	147	1			T11	4		T74	8		T15	4
all_values[2]	auto[0]	auto[1]	auto[1]	92	1			T11	1		T74	5		T15	1
all_values[2]	auto[1]	auto[0]	auto[1]	194	1			T11	3		T74	11		T15	1
all_values[2]	auto[1]	auto[1]	auto[1]	182	1			T11	8		T74	4		T15	1
all_values[3]	auto[0]	auto[0]	auto[0]	174	1			T11	1		T74	6		T15	5
all_values[3]	auto[0]	auto[0]	auto[1]	84	1			T11	3		T74	2		T15	1
all_values[3]	auto[0]	auto[1]	auto[0]	148	1			T11	4		T74	6		T15	1
all_values[3]	auto[0]	auto[1]	auto[1]	86	1			T11	4		T74	3		T16	2
all_values[3]	auto[1]	auto[0]	auto[1]	199	1			T11	8		T74	8		T15	4
all_values[3]	auto[1]	auto[1]	auto[1]	183	1			T11	4		T74	9		T16	3
all_values[4]	auto[0]	auto[0]	auto[0]	162	1			T11	4		T74	4		T15	4
all_values[4]	auto[0]	auto[0]	auto[1]	78	1			T11	3		T74	5		T16	2
all_values[4]	auto[0]	auto[1]	auto[0]	153	1			T11	1		T74	6		T15	4
all_values[4]	auto[0]	auto[1]	auto[1]	103	1			T11	6		T74	3		T16	1
all_values[4]	auto[1]	auto[0]	auto[1]	191	1			T11	6		T74	9		T15	1
all_values[4]	auto[1]	auto[1]	auto[1]	187	1			T11	4		T74	7		T15	2
all_values[5]	auto[0]	auto[0]	auto[0]	236	1			T11	6		T74	8		T15	5
all_values[5]	auto[0]	auto[1]	auto[0]	249	1			T11	6		T74	9		T15	3
all_values[5]	auto[1]	auto[0]	auto[1]	197	1			T11	5		T74	6		T17	1
all_values[5]	auto[1]	auto[1]	auto[1]	192	1			T11	7		T74	11		T15	3
all_values[6]	auto[0]	auto[0]	auto[0]	186	1			T11	6		T74	2		T15	1
all_values[6]	auto[0]	auto[0]	auto[1]	70	1			T11	3		T74	2		T15	2
all_values[6]	auto[0]	auto[1]	auto[0]	141	1			T11	1		T74	3		T15	3
all_values[6]	auto[0]	auto[1]	auto[1]	86	1			T11	1		T74	7		T17	1
all_values[6]	auto[1]	auto[0]	auto[1]	198	1			T11	7		T74	6		T15	4
all_values[6]	auto[1]	auto[1]	auto[1]	193	1			T11	6		T74	14		T15	1
all_values[7]	auto[0]	auto[0]	auto[0]	177	1			T11	7		T74	6		T15	4
all_values[7]	auto[0]	auto[0]	auto[1]	97	1			T11	2		T74	3		T16	2
all_values[7]	auto[0]	auto[1]	auto[0]	159	1			T11	5		T74	13		T15	1
all_values[7]	auto[0]	auto[1]	auto[1]	81	1			T11	3		T74	1		T15	2
all_values[7]	auto[1]	auto[0]	auto[1]	193	1			T11	5		T74	6		T15	2
all_values[7]	auto[1]	auto[1]	auto[1]	167	1			T11	2		T74	5		T15	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal