Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1861

1

T5

1

T6

15

T7

4

auto[1]

1857

1

T6

17

T7

1

T8

10

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1824

1

T5

1

T7

5

T8

7

auto[1]

1894

1

T6

32

T8

8

T11

8

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3014

1

T6

32

T8

14

T11

24

auto[1]

704

1

T5

1

T7

5

T8

1

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	727	1			T6	7		T11	7		T23	3
valid[1]	762	1			T5	1		T6	6		T7	2
valid[2]	766	1			T6	7		T8	5		T11	2
valid[3]	754	1			T6	8		T7	2		T8	2
valid[4]	709	1			T6	4		T7	1		T8	3

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	104	1			T11	4		T28	1		T38	1
auto[0]	auto[0]	valid[0]	auto[1]	186	1			T6	2		T23	1		T24	2
auto[0]	auto[0]	valid[1]	auto[0]	123	1			T8	3		T11	2		T28	2
auto[0]	auto[0]	valid[1]	auto[1]	183	1			T6	3		T8	1		T23	2
auto[0]	auto[0]	valid[2]	auto[0]	123	1			T38	2		T55	1		T100	1
auto[0]	auto[0]	valid[2]	auto[1]	187	1			T6	4		T23	1		T30	1
auto[0]	auto[0]	valid[3]	auto[0]	117	1			T11	2		T28	1		T38	2
auto[0]	auto[0]	valid[3]	auto[1]	194	1			T6	4		T11	2		T30	1
auto[0]	auto[0]	valid[4]	auto[0]	111	1			T8	1		T11	3		T38	1
auto[0]	auto[0]	valid[4]	auto[1]	187	1			T6	2		T23	2		T30	2
auto[0]	auto[1]	valid[0]	auto[0]	103	1			T11	1		T31	1		T38	2
auto[0]	auto[1]	valid[0]	auto[1]	199	1			T6	5		T11	1		T23	2
auto[0]	auto[1]	valid[1]	auto[0]	108	1			T11	1		T28	1		T31	1
auto[0]	auto[1]	valid[1]	auto[1]	197	1			T6	3		T8	1		T11	1
auto[0]	auto[1]	valid[2]	auto[0]	113	1			T317	1		T90	1		T100	2
auto[0]	auto[1]	valid[2]	auto[1]	203	1			T6	3		T8	5		T11	1
auto[0]	auto[1]	valid[3]	auto[0]	120	1			T8	1		T11	3		T28	2
auto[0]	auto[1]	valid[3]	auto[1]	190	1			T6	4		T8	1		T11	1
auto[0]	auto[1]	valid[4]	auto[0]	98	1			T8	1		T28	1		T31	1
auto[0]	auto[1]	valid[4]	auto[1]	168	1			T6	2		T11	2		T24	1
auto[1]	auto[0]	valid[0]	auto[0]	63	1			T101	1		T17	1		T18	1
auto[1]	auto[0]	valid[1]	auto[0]	78	1			T5	1		T7	1		T11	2
auto[1]	auto[0]	valid[2]	auto[0]	68	1			T11	1		T31	1		T44	1
auto[1]	auto[0]	valid[3]	auto[0]	65	1			T7	2		T11	1		T28	1
auto[1]	auto[0]	valid[4]	auto[0]	72	1			T7	1		T31	1		T38	1
auto[1]	auto[1]	valid[0]	auto[0]	72	1			T11	1		T28	1		T38	1
auto[1]	auto[1]	valid[1]	auto[0]	73	1			T7	1		T31	1		T44	1
auto[1]	auto[1]	valid[2]	auto[0]	72	1			T38	1		T44	1		T101	1
auto[1]	auto[1]	valid[3]	auto[0]	68	1			T11	2		T101	2		T62	1
auto[1]	auto[1]	valid[4]	auto[0]	73	1			T8	1		T28	1		T100	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal