Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

46895

1

T5

30

T7

258

T8

317

auto[1]

18159

1

T5

12

T6

315

T8

76

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

47932

1

T5

28

T6

315

T7

169

auto[1]

17122

1

T5

14

T7

89

T8

115

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	33743	1			T5	16		T6	167		T7	126
others[1]	5457	1			T5	6		T6	29		T7	24
others[2]	5376	1			T5	6		T6	27		T7	28
others[3]	6095	1			T5	4		T6	32		T7	26
interest[1]	3563	1			T5	2		T6	12		T7	19
interest[4]	22246	1			T5	13		T6	117		T7	75
interest[64]	10820	1			T5	8		T6	48		T7	35

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	15446	1			T5	9		T7	81		T8	98
auto[0]	auto[0]	others[1]	2539	1			T5	2		T7	18		T8	13
auto[0]	auto[0]	others[2]	2449	1			T7	18		T8	16		T11	22
auto[0]	auto[0]	others[3]	2776	1			T5	1		T7	16		T8	24
auto[0]	auto[0]	interest[1]	1646	1			T7	14		T8	16		T11	26
auto[0]	auto[0]	interest[4]	10100	1			T5	8		T7	45		T8	60
auto[0]	auto[0]	interest[64]	4917	1			T5	4		T7	22		T8	35
auto[0]	auto[1]	others[0]	9504	1			T5	5		T6	167		T8	38
auto[0]	auto[1]	others[1]	1441	1			T5	1		T6	29		T8	5
auto[0]	auto[1]	others[2]	1544	1			T5	2		T6	27		T8	5
auto[0]	auto[1]	others[3]	1722	1			T5	1		T6	32		T8	11
auto[0]	auto[1]	interest[1]	970	1			T5	1		T6	12		T8	6
auto[0]	auto[1]	interest[4]	6345	1			T5	4		T6	117		T8	25
auto[0]	auto[1]	interest[64]	2978	1			T5	2		T6	48		T8	11
auto[1]	auto[0]	others[0]	8793	1			T5	2		T7	45		T8	55
auto[1]	auto[0]	others[1]	1477	1			T5	3		T7	6		T8	15
auto[1]	auto[0]	others[2]	1383	1			T5	4		T7	10		T8	5
auto[1]	auto[0]	others[3]	1597	1			T5	2		T7	10		T8	14
auto[1]	auto[0]	interest[1]	947	1			T5	1		T7	5		T8	8
auto[1]	auto[0]	interest[4]	5801	1			T5	1		T7	30		T8	46
auto[1]	auto[0]	interest[64]	2925	1			T5	2		T7	13		T8	18

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal